1/*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 *    Rob Clark <robclark@freedesktop.org>
25 */
26
27#include "pipe/p_state.h"
28#include "util/u_memory.h"
29#include "util/u_prim.h"
30#include "util/u_string.h"
31
32#include "freedreno_resource.h"
33#include "freedreno_state.h"
34
35#include "fd5_context.h"
36#include "fd5_draw.h"
37#include "fd5_emit.h"
38#include "fd5_format.h"
39#include "fd5_program.h"
40#include "fd5_zsa.h"
41
42static void
43draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
44          struct fd5_emit *emit, unsigned index_offset) assert_dt
45{
46   const struct pipe_draw_info *info = emit->info;
47   enum pc_di_primtype primtype = ctx->screen->primtypes[info->mode];
48
49   fd5_emit_state(ctx, ring, emit);
50
51   if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE))
52      fd5_emit_vertex_bufs(ring, emit);
53
54   OUT_PKT4(ring, REG_A5XX_VFD_INDEX_OFFSET, 2);
55   OUT_RING(ring, info->index_size ? emit->draw->index_bias
56                                   : emit->draw->start); /* VFD_INDEX_OFFSET */
57   OUT_RING(ring, info->start_instance); /* VFD_INSTANCE_START_OFFSET */
58
59   OUT_PKT4(ring, REG_A5XX_PC_RESTART_INDEX, 1);
60   OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
61                     info->restart_index
62                                          : 0xffffffff);
63
64   fd5_emit_render_cntl(ctx, false, emit->binning_pass);
65   fd5_draw_emit(ctx->batch, ring, primtype,
66                 emit->binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY, info,
67                 emit->indirect, emit->draw, index_offset);
68}
69
70static bool
71fd5_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
72             unsigned drawid_offset,
73             const struct pipe_draw_indirect_info *indirect,
74             const struct pipe_draw_start_count_bias *draw,
75             unsigned index_offset) in_dt
76{
77   struct fd5_emit emit = {
78      .debug = &ctx->debug,
79      .vtx = &ctx->vtx,
80      .info = info,
81      .drawid_offset = drawid_offset,
82      .indirect = indirect,
83      .draw = draw,
84      .key = {
85         .vs = ctx->prog.vs,
86         .fs = ctx->prog.fs,
87         .key = {
88            .rasterflat = ctx->rasterizer->flatshade,
89         },
90         .clip_plane_enable = ctx->rasterizer->clip_plane_enable,
91      },
92      .rasterflat = ctx->rasterizer->flatshade,
93      .sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
94      .sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,
95   };
96
97   ir3_fixup_shader_state(&ctx->base, &emit.key.key);
98
99   unsigned dirty = ctx->dirty;
100
101   emit.prog = fd5_program_state(
102      ir3_cache_lookup(ctx->shader_cache, &emit.key, &ctx->debug));
103
104   /* bail if compile failed: */
105   if (!emit.prog)
106      return false;
107
108   const struct ir3_shader_variant *vp = fd5_emit_get_vp(&emit);
109   const struct ir3_shader_variant *fp = fd5_emit_get_fp(&emit);
110
111   ir3_update_max_tf_vtx(ctx, vp);
112
113   /* do regular pass first: */
114
115   if (unlikely(ctx->stats_users > 0)) {
116      ctx->stats.vs_regs += ir3_shader_halfregs(vp);
117      ctx->stats.fs_regs += ir3_shader_halfregs(fp);
118   }
119
120   /* figure out whether we need to disable LRZ write for binning
121    * pass using draw pass's fp:
122    */
123   emit.no_lrz_write = fp->writes_pos || fp->no_earlyz || fp->has_kill;
124
125   emit.binning_pass = false;
126   emit.dirty = dirty;
127
128   draw_impl(ctx, ctx->batch->draw, &emit, index_offset);
129
130   /* and now binning pass: */
131   emit.binning_pass = true;
132   emit.dirty = dirty & ~(FD_DIRTY_BLEND);
133   emit.vs = NULL; /* we changed key so need to refetch vp */
134   emit.fs = NULL;
135   draw_impl(ctx, ctx->batch->binning, &emit, index_offset);
136
137   if (emit.streamout_mask) {
138      struct fd_ringbuffer *ring = ctx->batch->draw;
139
140      for (unsigned i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
141         if (emit.streamout_mask & (1 << i)) {
142            fd5_event_write(ctx->batch, ring, FLUSH_SO_0 + i, false);
143         }
144      }
145   }
146
147   fd_context_all_clean(ctx);
148
149   return true;
150}
151
152static bool
153is_z32(enum pipe_format format)
154{
155   switch (format) {
156   case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
157   case PIPE_FORMAT_Z32_UNORM:
158   case PIPE_FORMAT_Z32_FLOAT:
159      return true;
160   default:
161      return false;
162   }
163}
164
165static void
166fd5_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
167{
168   struct fd_ringbuffer *ring;
169   uint32_t clear = util_pack_z(PIPE_FORMAT_Z16_UNORM, depth);
170
171   ring = fd_batch_get_prologue(batch);
172
173   OUT_WFI5(ring);
174
175   OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1);
176   OUT_RING(ring, 0x10000000);
177
178   OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
179   OUT_RING(ring, 0x20fffff);
180
181   OUT_PKT4(ring, REG_A5XX_GRAS_SU_CNTL, 1);
182   OUT_RING(ring,
183            A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(0.0f) |
184               A5XX_GRAS_SU_CNTL_LINE_MODE(zsbuf->b.b.nr_samples  > 1 ?
185                                           RECTANGULAR : BRESENHAM));
186
187   OUT_PKT4(ring, REG_A5XX_GRAS_CNTL, 1);
188   OUT_RING(ring, 0x00000000);
189
190   OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1);
191   OUT_RING(ring, 0x00000181);
192
193   OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
194   OUT_RING(ring, 0x00000000);
195
196   OUT_PKT4(ring, REG_A5XX_RB_MRT_BUF_INFO(0), 5);
197   OUT_RING(ring, A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(RB5_R16_UNORM) |
198                     A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(TILE5_LINEAR) |
199                     A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(WZYX));
200   OUT_RING(ring, A5XX_RB_MRT_PITCH(zsbuf->lrz_pitch * 2));
201   OUT_RING(ring, A5XX_RB_MRT_ARRAY_PITCH(fd_bo_size(zsbuf->lrz)));
202   OUT_RELOC(ring, zsbuf->lrz, 0x1000, 0, 0);
203
204   OUT_PKT4(ring, REG_A5XX_RB_RENDER_CNTL, 1);
205   OUT_RING(ring, 0x00000000);
206
207   OUT_PKT4(ring, REG_A5XX_RB_DEST_MSAA_CNTL, 1);
208   OUT_RING(ring, A5XX_RB_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE));
209
210   OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
211   OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(BLIT_MRT0));
212
213   OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
214   OUT_RING(ring, A5XX_RB_CLEAR_CNTL_FAST_CLEAR | A5XX_RB_CLEAR_CNTL_MASK(0xf));
215
216   OUT_PKT4(ring, REG_A5XX_RB_CLEAR_COLOR_DW0, 1);
217   OUT_RING(ring, clear); /* RB_CLEAR_COLOR_DW0 */
218
219   OUT_PKT4(ring, REG_A5XX_VSC_RESOLVE_CNTL, 2);
220   OUT_RING(ring, A5XX_VSC_RESOLVE_CNTL_X(zsbuf->lrz_width) |
221                     A5XX_VSC_RESOLVE_CNTL_Y(zsbuf->lrz_height));
222   OUT_RING(ring, 0x00000000); // XXX UNKNOWN_0CDE
223
224   OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
225   OUT_RING(ring, A5XX_RB_CNTL_BYPASS);
226
227   OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_1, 2);
228   OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_1_X(0) | A5XX_RB_RESOLVE_CNTL_1_Y(0));
229   OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_2_X(zsbuf->lrz_width - 1) |
230                     A5XX_RB_RESOLVE_CNTL_2_Y(zsbuf->lrz_height - 1));
231
232   fd5_emit_blit(batch, ring);
233}
234
235static bool
236fd5_clear(struct fd_context *ctx, unsigned buffers,
237          const union pipe_color_union *color, double depth,
238          unsigned stencil) assert_dt
239{
240   struct fd_ringbuffer *ring = ctx->batch->draw;
241   struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
242
243   if ((buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) &&
244       is_z32(pfb->zsbuf->format))
245      return false;
246
247   fd5_emit_render_cntl(ctx, true, false);
248
249   if (buffers & PIPE_CLEAR_COLOR) {
250      for (int i = 0; i < pfb->nr_cbufs; i++) {
251         union util_color uc = {0};
252
253         if (!pfb->cbufs[i])
254            continue;
255
256         if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
257            continue;
258
259         enum pipe_format pfmt = pfb->cbufs[i]->format;
260
261         // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
262         union pipe_color_union swapped;
263         switch (fd5_pipe2swap(pfmt)) {
264         case WZYX:
265            swapped.ui[0] = color->ui[0];
266            swapped.ui[1] = color->ui[1];
267            swapped.ui[2] = color->ui[2];
268            swapped.ui[3] = color->ui[3];
269            break;
270         case WXYZ:
271            swapped.ui[2] = color->ui[0];
272            swapped.ui[1] = color->ui[1];
273            swapped.ui[0] = color->ui[2];
274            swapped.ui[3] = color->ui[3];
275            break;
276         case ZYXW:
277            swapped.ui[3] = color->ui[0];
278            swapped.ui[0] = color->ui[1];
279            swapped.ui[1] = color->ui[2];
280            swapped.ui[2] = color->ui[3];
281            break;
282         case XYZW:
283            swapped.ui[3] = color->ui[0];
284            swapped.ui[2] = color->ui[1];
285            swapped.ui[1] = color->ui[2];
286            swapped.ui[0] = color->ui[3];
287            break;
288         }
289
290         util_pack_color_union(pfmt, &uc, &swapped);
291
292         OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
293         OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(BLIT_MRT0 + i));
294
295         OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
296         OUT_RING(ring,
297                  A5XX_RB_CLEAR_CNTL_FAST_CLEAR | A5XX_RB_CLEAR_CNTL_MASK(0xf));
298
299         OUT_PKT4(ring, REG_A5XX_RB_CLEAR_COLOR_DW0, 4);
300         OUT_RING(ring, uc.ui[0]); /* RB_CLEAR_COLOR_DW0 */
301         OUT_RING(ring, uc.ui[1]); /* RB_CLEAR_COLOR_DW1 */
302         OUT_RING(ring, uc.ui[2]); /* RB_CLEAR_COLOR_DW2 */
303         OUT_RING(ring, uc.ui[3]); /* RB_CLEAR_COLOR_DW3 */
304
305         fd5_emit_blit(ctx->batch, ring);
306      }
307   }
308
309   if (pfb->zsbuf && (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL))) {
310      uint32_t clear = util_pack_z_stencil(pfb->zsbuf->format, depth, stencil);
311      uint32_t mask = 0;
312
313      if (buffers & PIPE_CLEAR_DEPTH)
314         mask |= 0x1;
315
316      if (buffers & PIPE_CLEAR_STENCIL)
317         mask |= 0x2;
318
319      OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
320      OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(BLIT_ZS));
321
322      OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
323      OUT_RING(ring,
324               A5XX_RB_CLEAR_CNTL_FAST_CLEAR | A5XX_RB_CLEAR_CNTL_MASK(mask));
325
326      OUT_PKT4(ring, REG_A5XX_RB_CLEAR_COLOR_DW0, 1);
327      OUT_RING(ring, clear); /* RB_CLEAR_COLOR_DW0 */
328
329      fd5_emit_blit(ctx->batch, ring);
330
331      if (pfb->zsbuf && (buffers & PIPE_CLEAR_DEPTH)) {
332         struct fd_resource *zsbuf = fd_resource(pfb->zsbuf->texture);
333         if (zsbuf->lrz) {
334            zsbuf->lrz_valid = true;
335            fd5_clear_lrz(ctx->batch, zsbuf, depth);
336         }
337      }
338   }
339
340   /* disable fast clear to not interfere w/ gmem->mem, etc.. */
341   OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
342   OUT_RING(ring, 0x00000000); /* RB_CLEAR_CNTL */
343
344   return true;
345}
346
347void
348fd5_draw_init(struct pipe_context *pctx) disable_thread_safety_analysis
349{
350   struct fd_context *ctx = fd_context(pctx);
351   ctx->draw_vbo = fd5_draw_vbo;
352   ctx->clear = fd5_clear;
353}
354