1/*
2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 *    Rob Clark <robclark@freedesktop.org>
25 */
26
27#include "pipe/p_state.h"
28#include "util/u_memory.h"
29#include "util/u_prim.h"
30#include "util/u_string.h"
31
32#include "freedreno_resource.h"
33#include "freedreno_state.h"
34
35#include "fd4_context.h"
36#include "fd4_draw.h"
37#include "fd4_emit.h"
38#include "fd4_format.h"
39#include "fd4_program.h"
40#include "fd4_zsa.h"
41
42static void
43draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
44          struct fd4_emit *emit, unsigned index_offset) assert_dt
45{
46   const struct pipe_draw_info *info = emit->info;
47   enum pc_di_primtype primtype = ctx->screen->primtypes[info->mode];
48
49   fd4_emit_state(ctx, ring, emit);
50
51   if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE))
52      fd4_emit_vertex_bufs(ring, emit);
53
54   OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
55   OUT_RING(ring, info->index_size ? emit->draw->index_bias
56                                   : emit->draw->start); /* VFD_INDEX_OFFSET */
57   OUT_RING(ring, info->start_instance);                 /* ??? UNKNOWN_2209 */
58
59   OUT_PKT0(ring, REG_A4XX_PC_RESTART_INDEX, 1);
60   OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
61                     info->restart_index
62                                          : 0xffffffff);
63
64   /* points + psize -> spritelist: */
65   if (ctx->rasterizer->point_size_per_vertex &&
66       fd4_emit_get_vp(emit)->writes_psize && (info->mode == PIPE_PRIM_POINTS))
67      primtype = DI_PT_POINTLIST_PSIZE;
68
69   fd4_draw_emit(ctx->batch, ring, primtype,
70                 emit->binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY, info,
71                 emit->indirect, emit->draw, index_offset);
72}
73
74static bool
75fd4_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
76             unsigned drawid_offset,
77             const struct pipe_draw_indirect_info *indirect,
78             const struct pipe_draw_start_count_bias *draw,
79             unsigned index_offset) in_dt
80{
81   struct fd4_context *fd4_ctx = fd4_context(ctx);
82   struct fd4_emit emit = {
83      .debug = &ctx->debug,
84      .vtx = &ctx->vtx,
85      .info = info,
86      .drawid_offset = drawid_offset,
87      .indirect = indirect,
88      .draw = draw,
89      .key = {
90         .vs = ctx->prog.vs,
91         .fs = ctx->prog.fs,
92         .key = {
93            .rasterflat = ctx->rasterizer->flatshade,
94            .ucp_enables = ctx->rasterizer->clip_plane_enable,
95            .has_per_samp = fd4_ctx->fastc_srgb || fd4_ctx->vastc_srgb,
96            .vastc_srgb = fd4_ctx->vastc_srgb,
97            .fastc_srgb = fd4_ctx->fastc_srgb,
98         },
99      },
100      .rasterflat = ctx->rasterizer->flatshade,
101      .sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
102      .sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,
103   };
104
105   /* Check if we actually need the tg4 workarounds */
106   if (ir3_get_shader_info(emit.key.vs)->uses_texture_gather) {
107      emit.key.key.has_per_samp = true;
108      memcpy(emit.key.key.vsampler_swizzles, fd4_ctx->vsampler_swizzles,
109            sizeof(emit.key.key.vsampler_swizzles));
110   }
111   if (ir3_get_shader_info(emit.key.fs)->uses_texture_gather) {
112      emit.key.key.has_per_samp = true;
113      memcpy(emit.key.key.fsampler_swizzles, fd4_ctx->fsampler_swizzles,
114            sizeof(emit.key.key.fsampler_swizzles));
115   }
116
117   if (info->mode != PIPE_PRIM_MAX && !indirect && !info->primitive_restart &&
118       !u_trim_pipe_prim(info->mode, (unsigned *)&draw->count))
119      return false;
120
121   ir3_fixup_shader_state(&ctx->base, &emit.key.key);
122
123   enum fd_dirty_3d_state dirty = ctx->dirty;
124
125   emit.prog = fd4_program_state(
126      ir3_cache_lookup(ctx->shader_cache, &emit.key, &ctx->debug));
127
128   /* bail if compile failed: */
129   if (!emit.prog)
130      return false;
131
132   const struct ir3_shader_variant *vp = fd4_emit_get_vp(&emit);
133   const struct ir3_shader_variant *fp = fd4_emit_get_fp(&emit);
134
135   ir3_update_max_tf_vtx(ctx, vp);
136
137   /* do regular pass first: */
138
139   if (unlikely(ctx->stats_users > 0)) {
140      ctx->stats.vs_regs += ir3_shader_halfregs(vp);
141      ctx->stats.fs_regs += ir3_shader_halfregs(fp);
142   }
143
144   emit.binning_pass = false;
145   emit.dirty = dirty;
146
147   struct fd_ringbuffer *ring = ctx->batch->draw;
148
149   if (ctx->rasterizer->rasterizer_discard) {
150      fd_wfi(ctx->batch, ring);
151      OUT_PKT3(ring, CP_REG_RMW, 3);
152      OUT_RING(ring, REG_A4XX_RB_RENDER_CONTROL);
153      OUT_RING(ring, ~A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE);
154      OUT_RING(ring, A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE);
155   }
156
157   draw_impl(ctx, ctx->batch->draw, &emit, index_offset);
158
159   if (ctx->rasterizer->rasterizer_discard) {
160      fd_wfi(ctx->batch, ring);
161      OUT_PKT3(ring, CP_REG_RMW, 3);
162      OUT_RING(ring, REG_A4XX_RB_RENDER_CONTROL);
163      OUT_RING(ring, ~A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE);
164      OUT_RING(ring, 0);
165   }
166
167   /* and now binning pass: */
168   emit.binning_pass = true;
169   emit.dirty = dirty & ~(FD_DIRTY_BLEND);
170   emit.vs = NULL; /* we changed key so need to refetch vs */
171   emit.fs = NULL;
172   draw_impl(ctx, ctx->batch->binning, &emit, index_offset);
173
174   fd_context_all_clean(ctx);
175
176   return true;
177}
178
179void
180fd4_draw_init(struct pipe_context *pctx) disable_thread_safety_analysis
181{
182   struct fd_context *ctx = fd_context(pctx);
183   ctx->draw_vbo = fd4_draw_vbo;
184}
185