1/*
2 * Copyright (C) 2021 Ilia Mirkin <imirkin@alum.mit.edu>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 *    Ilia Mirkin <imirkin@alum.mit.edu>
25 */
26
27#include "pipe/p_state.h"
28
29#include "freedreno_resource.h"
30
31#include "fd4_compute.h"
32#include "fd4_context.h"
33#include "fd4_emit.h"
34
35/* maybe move to fd4_program? */
36static void
37cs_program_emit(struct fd_ringbuffer *ring, struct ir3_shader_variant *v)
38{
39   const struct ir3_info *i = &v->info;
40   enum a3xx_threadsize thrsz = i->double_threadsize ? FOUR_QUADS : TWO_QUADS;
41   unsigned instrlen = v->instrlen;
42
43   /* XXX verify that this is the case on a4xx */
44   /* if shader is more than 32*16 instructions, don't preload it.  Similar
45    * to the combined restriction of 64*16 for VS+FS
46    */
47   if (instrlen > 32)
48      instrlen = 0;
49
50   OUT_PKT0(ring, REG_A4XX_SP_SP_CTRL_REG, 1);
51   OUT_RING(ring, 0x00860010); /* SP_SP_CTRL_REG */
52
53   OUT_PKT0(ring, REG_A4XX_HLSQ_CONTROL_0_REG, 1);
54   OUT_RING(ring, A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(TWO_QUADS) |
55                     A4XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT |
56                     0x000001a0 /* XXX */);
57
58   OUT_PKT0(ring, REG_A4XX_SP_CS_CTRL_REG0, 1);
59   OUT_RING(ring, A4XX_SP_CS_CTRL_REG0_THREADSIZE(thrsz) |
60                     A4XX_SP_CS_CTRL_REG0_SUPERTHREADMODE |
61                     A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(i->max_half_reg + 1) |
62                     A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(i->max_reg + 1));
63
64   OUT_PKT0(ring, REG_A4XX_HLSQ_UPDATE_CONTROL, 1);
65   OUT_RING(ring, 0x00000038); /* HLSQ_UPDATE_CONTROL */
66
67   OUT_PKT0(ring, REG_A4XX_HLSQ_CS_CONTROL_REG, 1);
68   OUT_RING(ring, A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET(0) |
69                     A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET(0) |
70                     A4XX_HLSQ_CS_CONTROL_REG_ENABLED |
71                     A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH(1) |
72                     COND(v->has_ssbo, A4XX_HLSQ_CS_CONTROL_REG_SSBO_ENABLE) |
73                     A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH(v->constlen / 4));
74
75   uint32_t driver_param_base = v->const_state->offsets.driver_param * 4;
76   uint32_t local_invocation_id, work_group_id, local_group_size_id,
77      num_wg_id, work_dim_id, unused_id;
78   local_invocation_id =
79      ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
80   work_group_id = driver_param_base + IR3_DP_WORKGROUP_ID_X;
81   num_wg_id = driver_param_base + IR3_DP_NUM_WORK_GROUPS_X;
82   local_group_size_id = driver_param_base + IR3_DP_LOCAL_GROUP_SIZE_X;
83   work_dim_id = driver_param_base + IR3_DP_WORK_DIM;
84   /* NOTE: At some point we'll want to use this, it's probably WGOFFSETCONSTID */
85   unused_id = driver_param_base + IR3_DP_BASE_GROUP_X;
86
87   OUT_PKT0(ring, REG_A4XX_HLSQ_CL_CONTROL_0, 2);
88   OUT_RING(ring, A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID(work_group_id) |
89                     A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID(work_dim_id) |
90                     A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID(local_invocation_id));
91   OUT_RING(ring, A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID(unused_id) |
92                     A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID(local_group_size_id));
93
94   OUT_PKT0(ring, REG_A4XX_HLSQ_CL_KERNEL_CONST, 1);
95   OUT_RING(ring, A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID(unused_id) |
96                     A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID(num_wg_id));
97
98   OUT_PKT0(ring, REG_A4XX_HLSQ_CL_WG_OFFSET, 1);
99   OUT_RING(ring, A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID(unused_id));
100
101   OUT_PKT0(ring, REG_A4XX_HLSQ_MODE_CONTROL, 1);
102   OUT_RING(ring, 0x00000003); /* HLSQ_MODE_CONTROL */
103
104   OUT_PKT0(ring, REG_A4XX_HLSQ_UPDATE_CONTROL, 1);
105   OUT_RING(ring, 0x00000000); /* HLSQ_UPDATE_CONTROL */
106
107   OUT_PKT0(ring, REG_A4XX_SP_CS_OBJ_START, 1);
108   OUT_RELOC(ring, v->bo, 0, 0, 0); /* SP_CS_OBJ_START */
109
110   OUT_PKT0(ring, REG_A4XX_SP_CS_LENGTH_REG, 1);
111   OUT_RING(ring, v->instrlen);
112
113   if (instrlen > 0)
114      fd4_emit_shader(ring, v);
115}
116
117static void
118fd4_launch_grid(struct fd_context *ctx,
119                const struct pipe_grid_info *info) assert_dt
120{
121   struct fd4_context *fd4_ctx = fd4_context(ctx);
122   struct ir3_shader_key key = {
123      .has_per_samp = fd4_ctx->castc_srgb,
124      .fastc_srgb = fd4_ctx->castc_srgb,
125   };
126   struct ir3_shader *shader = ir3_get_shader(ctx->compute);
127   struct ir3_shader_variant *v;
128   struct fd_ringbuffer *ring = ctx->batch->draw;
129   unsigned nglobal = 0;
130
131   if (ir3_get_shader_info(ctx->compute)->uses_texture_gather) {
132      key.has_per_samp = true;
133      memcpy(key.fsampler_swizzles, fd4_ctx->csampler_swizzles,
134             sizeof(key.fsampler_swizzles));
135   }
136
137   v = ir3_shader_variant(shader, key, false, &ctx->debug);
138   if (!v)
139      return;
140
141   if (ctx->dirty_shader[PIPE_SHADER_COMPUTE] & FD_DIRTY_SHADER_PROG)
142      cs_program_emit(ring, v);
143
144   fd4_emit_cs_state(ctx, ring, v);
145   fd4_emit_cs_consts(v, ring, ctx, info);
146
147   u_foreach_bit (i, ctx->global_bindings.enabled_mask)
148      nglobal++;
149
150   if (nglobal > 0) {
151      /* global resources don't otherwise get an OUT_RELOC(), since
152       * the raw ptr address is emitted ir ir3_emit_cs_consts().
153       * So to make the kernel aware that these buffers are referenced
154       * by the batch, emit dummy reloc's as part of a no-op packet
155       * payload:
156       */
157      OUT_PKT3(ring, CP_NOP, 2 * nglobal);
158      u_foreach_bit (i, ctx->global_bindings.enabled_mask) {
159         struct pipe_resource *prsc = ctx->global_bindings.buf[i];
160         OUT_RELOC(ring, fd_resource(prsc)->bo, 0, 0, 0);
161      }
162   }
163
164   const unsigned *local_size =
165      info->block; // v->shader->nir->info->workgroup_size;
166   const unsigned *num_groups = info->grid;
167   /* for some reason, mesa/st doesn't set info->work_dim, so just assume 3: */
168   const unsigned work_dim = info->work_dim ? info->work_dim : 3;
169   OUT_PKT0(ring, REG_A4XX_HLSQ_CL_NDRANGE_0, 7);
170   OUT_RING(ring, A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM(work_dim) |
171                     A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX(local_size[0] - 1) |
172                     A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY(local_size[1] - 1) |
173                     A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ(local_size[2] - 1));
174   OUT_RING(ring,
175            A4XX_HLSQ_CL_NDRANGE_1_SIZE_X(local_size[0] * num_groups[0]));
176   OUT_RING(ring, 0); /* HLSQ_CL_NDRANGE_2_GLOBALOFF_X */
177   OUT_RING(ring,
178            A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y(local_size[1] * num_groups[1]));
179   OUT_RING(ring, 0); /* HLSQ_CL_NDRANGE_4_GLOBALOFF_Y */
180   OUT_RING(ring,
181            A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z(local_size[2] * num_groups[2]));
182   OUT_RING(ring, 0); /* HLSQ_CL_NDRANGE_6_GLOBALOFF_Z */
183
184   if (info->indirect) {
185      struct fd_resource *rsc = fd_resource(info->indirect);
186
187      fd_event_write(ctx->batch, ring, CACHE_FLUSH);
188      fd_wfi(ctx->batch, ring);
189
190      OUT_PKT3(ring, CP_EXEC_CS_INDIRECT, 3);
191      OUT_RING(ring, 0x00000000);
192      OUT_RELOC(ring, rsc->bo, info->indirect_offset, 0, 0);
193      OUT_RING(ring,
194               A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(local_size[0] - 1) |
195                  A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(local_size[1] - 1) |
196                  A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(local_size[2] - 1));
197   } else {
198      OUT_PKT3(ring, CP_EXEC_CS, 4);
199      OUT_RING(ring, 0x00000000);
200      OUT_RING(ring, CP_EXEC_CS_1_NGROUPS_X(info->grid[0]));
201      OUT_RING(ring, CP_EXEC_CS_2_NGROUPS_Y(info->grid[1]));
202      OUT_RING(ring, CP_EXEC_CS_3_NGROUPS_Z(info->grid[2]));
203   }
204}
205
206void
207fd4_compute_init(struct pipe_context *pctx) disable_thread_safety_analysis
208{
209   struct fd_context *ctx = fd_context(pctx);
210   ctx->launch_grid = fd4_launch_grid;
211   pctx->create_compute_state = ir3_shader_compute_state_create;
212   pctx->delete_compute_state = ir3_shader_state_delete;
213}
214