1/*
2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 *    Rob Clark <robclark@freedesktop.org>
25 */
26
27#include "freedreno_batch.h"
28#include "freedreno_context.h"
29#include "freedreno_query_hw.h"
30#include "freedreno_util.h"
31
32#include "fd3_format.h"
33#include "fd3_query.h"
34
35struct fd_rb_samp_ctrs {
36   uint64_t ctr[16];
37};
38
39/*
40 * Occlusion Query:
41 *
42 * OCCLUSION_COUNTER and OCCLUSION_PREDICATE differ only in how they
43 * interpret results
44 */
45
46static struct fd_hw_sample *
47occlusion_get_sample(struct fd_batch *batch, struct fd_ringbuffer *ring)
48{
49   struct fd_hw_sample *samp =
50      fd_hw_sample_init(batch, sizeof(struct fd_rb_samp_ctrs));
51
52   /* Set RB_SAMPLE_COUNT_ADDR to samp->offset plus value of
53    * HW_QUERY_BASE_REG register:
54    */
55   OUT_PKT3(ring, CP_SET_CONSTANT, 3);
56   OUT_RING(ring, CP_REG(REG_A3XX_RB_SAMPLE_COUNT_ADDR) | 0x80000000);
57   OUT_RING(ring, HW_QUERY_BASE_REG);
58   OUT_RING(ring, samp->offset);
59
60   OUT_PKT0(ring, REG_A3XX_RB_SAMPLE_COUNT_CONTROL, 1);
61   OUT_RING(ring, A3XX_RB_SAMPLE_COUNT_CONTROL_COPY);
62
63   OUT_PKT3(ring, CP_DRAW_INDX, 3);
64   OUT_RING(ring, 0x00000000);
65   OUT_RING(ring, DRAW(DI_PT_POINTLIST_PSIZE, DI_SRC_SEL_AUTO_INDEX,
66                       INDEX_SIZE_IGN, USE_VISIBILITY, 0));
67   OUT_RING(ring, 0); /* NumIndices */
68
69   fd_event_write(batch, ring, ZPASS_DONE);
70
71   OUT_PKT0(ring, REG_A3XX_RBBM_PERFCTR_CTL, 1);
72   OUT_RING(ring, A3XX_RBBM_PERFCTR_CTL_ENABLE);
73
74   OUT_PKT0(ring, REG_A3XX_VBIF_PERF_CNT_EN, 1);
75   OUT_RING(ring, A3XX_VBIF_PERF_CNT_EN_CNT0 | A3XX_VBIF_PERF_CNT_EN_CNT1 |
76                     A3XX_VBIF_PERF_CNT_EN_PWRCNT0 |
77                     A3XX_VBIF_PERF_CNT_EN_PWRCNT1 |
78                     A3XX_VBIF_PERF_CNT_EN_PWRCNT2);
79
80   return samp;
81}
82
83static uint64_t
84count_samples(const struct fd_rb_samp_ctrs *start,
85              const struct fd_rb_samp_ctrs *end)
86{
87   uint64_t n = 0;
88   unsigned i;
89
90   /* not quite sure what all of these are, possibly different
91    * counters for each MRT render target:
92    */
93   for (i = 0; i < 16; i += 4)
94      n += end->ctr[i] - start->ctr[i];
95
96   return n;
97}
98
99static void
100occlusion_counter_accumulate_result(struct fd_context *ctx, const void *start,
101                                    const void *end,
102                                    union pipe_query_result *result)
103{
104   uint64_t n = count_samples(start, end);
105   result->u64 += n;
106}
107
108static void
109occlusion_predicate_accumulate_result(struct fd_context *ctx, const void *start,
110                                      const void *end,
111                                      union pipe_query_result *result)
112{
113   uint64_t n = count_samples(start, end);
114   result->b |= (n > 0);
115}
116
117static const struct fd_hw_sample_provider occlusion_counter = {
118   .query_type = PIPE_QUERY_OCCLUSION_COUNTER,
119   .get_sample = occlusion_get_sample,
120   .accumulate_result = occlusion_counter_accumulate_result,
121};
122
123static const struct fd_hw_sample_provider occlusion_predicate = {
124   .query_type = PIPE_QUERY_OCCLUSION_PREDICATE,
125   .get_sample = occlusion_get_sample,
126   .accumulate_result = occlusion_predicate_accumulate_result,
127};
128
129static const struct fd_hw_sample_provider occlusion_predicate_conservative = {
130   .query_type = PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE,
131   .get_sample = occlusion_get_sample,
132   .accumulate_result = occlusion_predicate_accumulate_result,
133};
134
135void
136fd3_query_context_init(struct pipe_context *pctx) disable_thread_safety_analysis
137{
138   struct fd_context *ctx = fd_context(pctx);
139
140   ctx->create_query = fd_hw_create_query;
141   ctx->query_prepare = fd_hw_query_prepare;
142   ctx->query_prepare_tile = fd_hw_query_prepare_tile;
143   ctx->query_update_batch = fd_hw_query_update_batch;
144
145   fd_hw_query_register_provider(pctx, &occlusion_counter);
146   fd_hw_query_register_provider(pctx, &occlusion_predicate);
147   fd_hw_query_register_provider(pctx, &occlusion_predicate_conservative);
148}
149