1/* 2 * Copyright (C) 2012-2013 Rob Clark <robclark@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Rob Clark <robclark@freedesktop.org> 25 */ 26 27#include "pipe/p_state.h" 28#include "util/u_helpers.h" 29#include "util/u_memory.h" 30#include "util/u_string.h" 31 32#include "freedreno_resource.h" 33 34#include "fd2_blend.h" 35#include "fd2_context.h" 36#include "fd2_emit.h" 37#include "fd2_program.h" 38#include "fd2_rasterizer.h" 39#include "fd2_texture.h" 40#include "fd2_util.h" 41#include "fd2_zsa.h" 42 43/* NOTE: just define the position for const regs statically.. the blob 44 * driver doesn't seem to change these dynamically, and I can't really 45 * think of a good reason to so.. 46 */ 47#define VS_CONST_BASE 0x20 48#define PS_CONST_BASE 0x120 49 50static void 51emit_constants(struct fd_ringbuffer *ring, uint32_t base, 52 struct fd_constbuf_stateobj *constbuf, 53 struct fd2_shader_stateobj *shader) 54{ 55 uint32_t enabled_mask = constbuf->enabled_mask; 56 uint32_t start_base = base; 57 unsigned i; 58 59 /* emit user constants: */ 60 while (enabled_mask) { 61 unsigned index = ffs(enabled_mask) - 1; 62 struct pipe_constant_buffer *cb = &constbuf->cb[index]; 63 unsigned size = align(cb->buffer_size, 4) / 4; /* size in dwords */ 64 65 // I expect that size should be a multiple of vec4's: 66 assert(size == align(size, 4)); 67 68 /* hmm, sometimes we still seem to end up with consts bound, 69 * even if shader isn't using them, which ends up overwriting 70 * const reg's used for immediates.. this is a hack to work 71 * around that: 72 */ 73 if (shader && ((base - start_base) >= (shader->first_immediate * 4))) 74 break; 75 76 const uint32_t *dwords; 77 78 if (cb->user_buffer) { 79 dwords = cb->user_buffer; 80 } else { 81 struct fd_resource *rsc = fd_resource(cb->buffer); 82 dwords = fd_bo_map(rsc->bo); 83 } 84 85 dwords = (uint32_t *)(((uint8_t *)dwords) + cb->buffer_offset); 86 87 OUT_PKT3(ring, CP_SET_CONSTANT, size + 1); 88 OUT_RING(ring, base); 89 for (i = 0; i < size; i++) 90 OUT_RING(ring, *(dwords++)); 91 92 base += size; 93 enabled_mask &= ~(1 << index); 94 } 95 96 /* emit shader immediates: */ 97 if (shader) { 98 for (i = 0; i < shader->num_immediates; i++) { 99 OUT_PKT3(ring, CP_SET_CONSTANT, 5); 100 OUT_RING(ring, start_base + (4 * (shader->first_immediate + i))); 101 OUT_RING(ring, shader->immediates[i].val[0]); 102 OUT_RING(ring, shader->immediates[i].val[1]); 103 OUT_RING(ring, shader->immediates[i].val[2]); 104 OUT_RING(ring, shader->immediates[i].val[3]); 105 base += 4; 106 } 107 } 108} 109 110typedef uint32_t texmask; 111 112static texmask 113emit_texture(struct fd_ringbuffer *ring, struct fd_context *ctx, 114 struct fd_texture_stateobj *tex, unsigned samp_id, texmask emitted) 115{ 116 unsigned const_idx = fd2_get_const_idx(ctx, tex, samp_id); 117 static const struct fd2_sampler_stateobj dummy_sampler = {}; 118 static const struct fd2_pipe_sampler_view dummy_view = {}; 119 const struct fd2_sampler_stateobj *sampler; 120 const struct fd2_pipe_sampler_view *view; 121 struct fd_resource *rsc; 122 123 if (emitted & (1 << const_idx)) 124 return 0; 125 126 sampler = tex->samplers[samp_id] 127 ? fd2_sampler_stateobj(tex->samplers[samp_id]) 128 : &dummy_sampler; 129 view = tex->textures[samp_id] ? fd2_pipe_sampler_view(tex->textures[samp_id]) 130 : &dummy_view; 131 132 rsc = view->base.texture ? fd_resource(view->base.texture) : NULL; 133 134 OUT_PKT3(ring, CP_SET_CONSTANT, 7); 135 OUT_RING(ring, 0x00010000 + (0x6 * const_idx)); 136 137 OUT_RING(ring, sampler->tex0 | view->tex0); 138 if (rsc) 139 OUT_RELOC(ring, rsc->bo, fd_resource_offset(rsc, 0, 0), view->tex1, 0); 140 else 141 OUT_RING(ring, 0); 142 143 OUT_RING(ring, view->tex2); 144 OUT_RING(ring, sampler->tex3 | view->tex3); 145 OUT_RING(ring, sampler->tex4 | view->tex4); 146 147 if (rsc && rsc->b.b.last_level) 148 OUT_RELOC(ring, rsc->bo, fd_resource_offset(rsc, 1, 0), view->tex5, 0); 149 else 150 OUT_RING(ring, view->tex5); 151 152 return (1 << const_idx); 153} 154 155static void 156emit_textures(struct fd_ringbuffer *ring, struct fd_context *ctx) 157{ 158 struct fd_texture_stateobj *fragtex = &ctx->tex[PIPE_SHADER_FRAGMENT]; 159 struct fd_texture_stateobj *verttex = &ctx->tex[PIPE_SHADER_VERTEX]; 160 texmask emitted = 0; 161 unsigned i; 162 163 for (i = 0; i < verttex->num_samplers; i++) 164 if (verttex->samplers[i]) 165 emitted |= emit_texture(ring, ctx, verttex, i, emitted); 166 167 for (i = 0; i < fragtex->num_samplers; i++) 168 if (fragtex->samplers[i]) 169 emitted |= emit_texture(ring, ctx, fragtex, i, emitted); 170} 171 172void 173fd2_emit_vertex_bufs(struct fd_ringbuffer *ring, uint32_t val, 174 struct fd2_vertex_buf *vbufs, uint32_t n) 175{ 176 unsigned i; 177 178 OUT_PKT3(ring, CP_SET_CONSTANT, 1 + (2 * n)); 179 OUT_RING(ring, (0x1 << 16) | (val & 0xffff)); 180 for (i = 0; i < n; i++) { 181 struct fd_resource *rsc = fd_resource(vbufs[i].prsc); 182 OUT_RELOC(ring, rsc->bo, vbufs[i].offset, 3, 0); 183 OUT_RING(ring, vbufs[i].size); 184 } 185} 186 187void 188fd2_emit_state_binning(struct fd_context *ctx, 189 const enum fd_dirty_3d_state dirty) 190{ 191 struct fd2_blend_stateobj *blend = fd2_blend_stateobj(ctx->blend); 192 struct fd_ringbuffer *ring = ctx->batch->binning; 193 194 /* subset of fd2_emit_state needed for hw binning on a20x */ 195 196 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_VTXSTATE)) 197 fd2_program_emit(ctx, ring, &ctx->prog); 198 199 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_CONST)) { 200 emit_constants(ring, VS_CONST_BASE * 4, 201 &ctx->constbuf[PIPE_SHADER_VERTEX], 202 (dirty & FD_DIRTY_PROG) ? ctx->prog.vs : NULL); 203 } 204 205 if (dirty & FD_DIRTY_VIEWPORT) { 206 OUT_PKT3(ring, CP_SET_CONSTANT, 9); 207 OUT_RING(ring, 0x00000184); 208 OUT_RING(ring, fui(ctx->viewport.translate[0])); 209 OUT_RING(ring, fui(ctx->viewport.translate[1])); 210 OUT_RING(ring, fui(ctx->viewport.translate[2])); 211 OUT_RING(ring, fui(0.0f)); 212 OUT_RING(ring, fui(ctx->viewport.scale[0])); 213 OUT_RING(ring, fui(ctx->viewport.scale[1])); 214 OUT_RING(ring, fui(ctx->viewport.scale[2])); 215 OUT_RING(ring, fui(0.0f)); 216 } 217 218 /* not sure why this is needed */ 219 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_FRAMEBUFFER)) { 220 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 221 OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_CONTROL)); 222 OUT_RING(ring, blend->rb_blendcontrol); 223 224 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 225 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_MASK)); 226 OUT_RING(ring, blend->rb_colormask); 227 } 228 229 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 230 OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_SC_MODE_CNTL)); 231 OUT_RING(ring, A2XX_PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE); 232} 233 234void 235fd2_emit_state(struct fd_context *ctx, const enum fd_dirty_3d_state dirty) 236{ 237 struct fd2_blend_stateobj *blend = fd2_blend_stateobj(ctx->blend); 238 struct fd2_zsa_stateobj *zsa = fd2_zsa_stateobj(ctx->zsa); 239 struct fd2_shader_stateobj *fs = ctx->prog.fs; 240 struct fd_ringbuffer *ring = ctx->batch->draw; 241 242 /* NOTE: we probably want to eventually refactor this so each state 243 * object handles emitting it's own state.. although the mapping of 244 * state to registers is not always orthogonal, sometimes a single 245 * register contains bitfields coming from multiple state objects, 246 * so not sure the best way to deal with that yet. 247 */ 248 249 if (dirty & FD_DIRTY_SAMPLE_MASK) { 250 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 251 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK)); 252 OUT_RING(ring, ctx->sample_mask); 253 } 254 255 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF | FD_DIRTY_PROG)) { 256 struct pipe_stencil_ref *sr = &ctx->stencil_ref; 257 uint32_t val = zsa->rb_depthcontrol; 258 259 if (fs->has_kill) 260 val &= ~A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE; 261 262 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 263 OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL)); 264 OUT_RING(ring, val); 265 266 OUT_PKT3(ring, CP_SET_CONSTANT, 4); 267 OUT_RING(ring, CP_REG(REG_A2XX_RB_STENCILREFMASK_BF)); 268 OUT_RING(ring, zsa->rb_stencilrefmask_bf | 269 A2XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[1])); 270 OUT_RING(ring, zsa->rb_stencilrefmask | 271 A2XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0])); 272 OUT_RING(ring, zsa->rb_alpha_ref); 273 } 274 275 if (ctx->rasterizer && dirty & FD_DIRTY_RASTERIZER) { 276 struct fd2_rasterizer_stateobj *rasterizer = 277 fd2_rasterizer_stateobj(ctx->rasterizer); 278 OUT_PKT3(ring, CP_SET_CONSTANT, 3); 279 OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL)); 280 OUT_RING(ring, rasterizer->pa_cl_clip_cntl); 281 OUT_RING(ring, rasterizer->pa_su_sc_mode_cntl | 282 A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE); 283 284 OUT_PKT3(ring, CP_SET_CONSTANT, 5); 285 OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_POINT_SIZE)); 286 OUT_RING(ring, rasterizer->pa_su_point_size); 287 OUT_RING(ring, rasterizer->pa_su_point_minmax); 288 OUT_RING(ring, rasterizer->pa_su_line_cntl); 289 OUT_RING(ring, rasterizer->pa_sc_line_stipple); 290 291 OUT_PKT3(ring, CP_SET_CONSTANT, 6); 292 OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_VTX_CNTL)); 293 OUT_RING(ring, rasterizer->pa_su_vtx_cntl); 294 OUT_RING(ring, fui(1.0f)); /* PA_CL_GB_VERT_CLIP_ADJ */ 295 OUT_RING(ring, fui(1.0f)); /* PA_CL_GB_VERT_DISC_ADJ */ 296 OUT_RING(ring, fui(1.0f)); /* PA_CL_GB_HORZ_CLIP_ADJ */ 297 OUT_RING(ring, fui(1.0f)); /* PA_CL_GB_HORZ_DISC_ADJ */ 298 299 if (rasterizer->base.offset_tri) { 300 /* TODO: why multiply scale by 2 ? without it deqp test fails 301 * deqp/piglit tests aren't very precise 302 */ 303 OUT_PKT3(ring, CP_SET_CONSTANT, 5); 304 OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE)); 305 OUT_RING(ring, 306 fui(rasterizer->base.offset_scale * 2.0f)); /* FRONT_SCALE */ 307 OUT_RING(ring, fui(rasterizer->base.offset_units)); /* FRONT_OFFSET */ 308 OUT_RING(ring, 309 fui(rasterizer->base.offset_scale * 2.0f)); /* BACK_SCALE */ 310 OUT_RING(ring, fui(rasterizer->base.offset_units)); /* BACK_OFFSET */ 311 } 312 } 313 314 /* NOTE: scissor enabled bit is part of rasterizer state: */ 315 if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER)) { 316 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx); 317 318 OUT_PKT3(ring, CP_SET_CONSTANT, 3); 319 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL)); 320 OUT_RING(ring, xy2d(scissor->minx, /* PA_SC_WINDOW_SCISSOR_TL */ 321 scissor->miny)); 322 OUT_RING(ring, xy2d(scissor->maxx, /* PA_SC_WINDOW_SCISSOR_BR */ 323 scissor->maxy)); 324 325 ctx->batch->max_scissor.minx = 326 MIN2(ctx->batch->max_scissor.minx, scissor->minx); 327 ctx->batch->max_scissor.miny = 328 MIN2(ctx->batch->max_scissor.miny, scissor->miny); 329 ctx->batch->max_scissor.maxx = 330 MAX2(ctx->batch->max_scissor.maxx, scissor->maxx); 331 ctx->batch->max_scissor.maxy = 332 MAX2(ctx->batch->max_scissor.maxy, scissor->maxy); 333 } 334 335 if (dirty & FD_DIRTY_VIEWPORT) { 336 OUT_PKT3(ring, CP_SET_CONSTANT, 7); 337 OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VPORT_XSCALE)); 338 OUT_RING(ring, fui(ctx->viewport.scale[0])); /* PA_CL_VPORT_XSCALE */ 339 OUT_RING(ring, fui(ctx->viewport.translate[0])); /* PA_CL_VPORT_XOFFSET */ 340 OUT_RING(ring, fui(ctx->viewport.scale[1])); /* PA_CL_VPORT_YSCALE */ 341 OUT_RING(ring, fui(ctx->viewport.translate[1])); /* PA_CL_VPORT_YOFFSET */ 342 OUT_RING(ring, fui(ctx->viewport.scale[2])); /* PA_CL_VPORT_ZSCALE */ 343 OUT_RING(ring, fui(ctx->viewport.translate[2])); /* PA_CL_VPORT_ZOFFSET */ 344 345 /* set viewport in C65/C66, for a20x hw binning and fragcoord.z */ 346 OUT_PKT3(ring, CP_SET_CONSTANT, 9); 347 OUT_RING(ring, 0x00000184); 348 349 OUT_RING(ring, fui(ctx->viewport.translate[0])); 350 OUT_RING(ring, fui(ctx->viewport.translate[1])); 351 OUT_RING(ring, fui(ctx->viewport.translate[2])); 352 OUT_RING(ring, fui(0.0f)); 353 354 OUT_RING(ring, fui(ctx->viewport.scale[0])); 355 OUT_RING(ring, fui(ctx->viewport.scale[1])); 356 OUT_RING(ring, fui(ctx->viewport.scale[2])); 357 OUT_RING(ring, fui(0.0f)); 358 } 359 360 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_VTXSTATE | FD_DIRTY_TEXSTATE)) 361 fd2_program_emit(ctx, ring, &ctx->prog); 362 363 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_CONST)) { 364 emit_constants(ring, VS_CONST_BASE * 4, 365 &ctx->constbuf[PIPE_SHADER_VERTEX], 366 (dirty & FD_DIRTY_PROG) ? ctx->prog.vs : NULL); 367 emit_constants(ring, PS_CONST_BASE * 4, 368 &ctx->constbuf[PIPE_SHADER_FRAGMENT], 369 (dirty & FD_DIRTY_PROG) ? ctx->prog.fs : NULL); 370 } 371 372 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_ZSA)) { 373 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 374 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLORCONTROL)); 375 OUT_RING(ring, zsa->rb_colorcontrol | blend->rb_colorcontrol); 376 } 377 378 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_FRAMEBUFFER)) { 379 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 380 OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_CONTROL)); 381 OUT_RING(ring, blend->rb_blendcontrol); 382 383 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 384 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_MASK)); 385 OUT_RING(ring, blend->rb_colormask); 386 } 387 388 if (dirty & FD_DIRTY_BLEND_COLOR) { 389 OUT_PKT3(ring, CP_SET_CONSTANT, 5); 390 OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_RED)); 391 OUT_RING(ring, float_to_ubyte(ctx->blend_color.color[0])); 392 OUT_RING(ring, float_to_ubyte(ctx->blend_color.color[1])); 393 OUT_RING(ring, float_to_ubyte(ctx->blend_color.color[2])); 394 OUT_RING(ring, float_to_ubyte(ctx->blend_color.color[3])); 395 } 396 397 if (dirty & (FD_DIRTY_TEX | FD_DIRTY_PROG)) 398 emit_textures(ring, ctx); 399} 400 401/* emit per-context initialization: 402 */ 403void 404fd2_emit_restore(struct fd_context *ctx, struct fd_ringbuffer *ring) 405{ 406 if (is_a20x(ctx->screen)) { 407 OUT_PKT0(ring, REG_A2XX_RB_BC_CONTROL, 1); 408 OUT_RING(ring, A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(3) | 409 A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP | 410 A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE | 411 A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(8) | 412 A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(3)); 413 414 /* not sure why this is required */ 415 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 416 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_VIZ_QUERY)); 417 OUT_RING(ring, A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID(16)); 418 419 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 420 OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL)); 421 OUT_RING(ring, 0x00000002); 422 423 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 424 OUT_RING(ring, CP_REG(REG_A2XX_VGT_OUT_DEALLOC_CNTL)); 425 OUT_RING(ring, 0x00000002); 426 } else { 427 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 428 OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL)); 429 OUT_RING(ring, 0x0000003b); 430 } 431 432 /* enable perfcntrs */ 433 OUT_PKT0(ring, REG_A2XX_CP_PERFMON_CNTL, 1); 434 OUT_RING(ring, COND(FD_DBG(PERFC), 1)); 435 436 /* note: perfcntrs don't work without the PM_OVERRIDE bit */ 437 OUT_PKT0(ring, REG_A2XX_RBBM_PM_OVERRIDE1, 2); 438 OUT_RING(ring, 0xffffffff); 439 OUT_RING(ring, 0x00000fff); 440 441 OUT_PKT0(ring, REG_A2XX_TP0_CHICKEN, 1); 442 OUT_RING(ring, 0x00000002); 443 444 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1); 445 OUT_RING(ring, 0x00007fff); 446 447 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 448 OUT_RING(ring, CP_REG(REG_A2XX_SQ_VS_CONST)); 449 OUT_RING(ring, A2XX_SQ_VS_CONST_BASE(VS_CONST_BASE) | 450 A2XX_SQ_VS_CONST_SIZE(0x100)); 451 452 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 453 OUT_RING(ring, CP_REG(REG_A2XX_SQ_PS_CONST)); 454 OUT_RING(ring, 455 A2XX_SQ_PS_CONST_BASE(PS_CONST_BASE) | A2XX_SQ_PS_CONST_SIZE(0xe0)); 456 457 OUT_PKT3(ring, CP_SET_CONSTANT, 3); 458 OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX)); 459 OUT_RING(ring, 0xffffffff); /* VGT_MAX_VTX_INDX */ 460 OUT_RING(ring, 0x00000000); /* VGT_MIN_VTX_INDX */ 461 462 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 463 OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET)); 464 OUT_RING(ring, 0x00000000); 465 466 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 467 OUT_RING(ring, CP_REG(REG_A2XX_SQ_CONTEXT_MISC)); 468 OUT_RING(ring, A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(CENTERS_ONLY)); 469 470 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 471 OUT_RING(ring, CP_REG(REG_A2XX_SQ_INTERPOLATOR_CNTL)); 472 OUT_RING(ring, 0xffffffff); 473 474 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 475 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_CONFIG)); 476 OUT_RING(ring, 0x00000000); 477 478 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 479 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_LINE_CNTL)); 480 OUT_RING(ring, 0x00000000); 481 482 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 483 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET)); 484 OUT_RING(ring, 0x00000000); 485 486 // XXX we change this dynamically for draw/clear.. vs gmem<->mem.. 487 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 488 OUT_RING(ring, CP_REG(REG_A2XX_RB_MODECONTROL)); 489 OUT_RING(ring, A2XX_RB_MODECONTROL_EDRAM_MODE(COLOR_DEPTH)); 490 491 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 492 OUT_RING(ring, CP_REG(REG_A2XX_RB_SAMPLE_POS)); 493 OUT_RING(ring, 0x88888888); 494 495 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 496 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_DEST_MASK)); 497 OUT_RING(ring, 0xffffffff); 498 499 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 500 OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_DEST_INFO)); 501 OUT_RING(ring, A2XX_RB_COPY_DEST_INFO_FORMAT(COLORX_4_4_4_4) | 502 A2XX_RB_COPY_DEST_INFO_WRITE_RED | 503 A2XX_RB_COPY_DEST_INFO_WRITE_GREEN | 504 A2XX_RB_COPY_DEST_INFO_WRITE_BLUE | 505 A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA); 506 507 OUT_PKT3(ring, CP_SET_CONSTANT, 3); 508 OUT_RING(ring, CP_REG(REG_A2XX_SQ_WRAPPING_0)); 509 OUT_RING(ring, 0x00000000); /* SQ_WRAPPING_0 */ 510 OUT_RING(ring, 0x00000000); /* SQ_WRAPPING_1 */ 511 512 OUT_PKT3(ring, CP_SET_DRAW_INIT_FLAGS, 1); 513 OUT_RING(ring, 0x00000000); 514 515 OUT_PKT3(ring, CP_WAIT_REG_EQ, 4); 516 OUT_RING(ring, 0x000005d0); 517 OUT_RING(ring, 0x00000000); 518 OUT_RING(ring, 0x5f601000); 519 OUT_RING(ring, 0x00000001); 520 521 OUT_PKT0(ring, REG_A2XX_SQ_INST_STORE_MANAGMENT, 1); 522 OUT_RING(ring, 0x00000180); 523 524 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1); 525 OUT_RING(ring, 0x00000300); 526 527 OUT_PKT3(ring, CP_SET_SHADER_BASES, 1); 528 OUT_RING(ring, 0x80000180); 529 530 /* not sure what this form of CP_SET_CONSTANT is.. */ 531 OUT_PKT3(ring, CP_SET_CONSTANT, 13); 532 OUT_RING(ring, 0x00000000); 533 OUT_RING(ring, 0x00000000); 534 OUT_RING(ring, 0x00000000); 535 OUT_RING(ring, 0x00000000); 536 OUT_RING(ring, 0x00000000); 537 OUT_RING(ring, 0x469c4000); 538 OUT_RING(ring, 0x3f800000); 539 OUT_RING(ring, 0x3f000000); 540 OUT_RING(ring, 0x00000000); 541 OUT_RING(ring, 0x40000000); 542 OUT_RING(ring, 0x3f400000); 543 OUT_RING(ring, 0x3ec00000); 544 OUT_RING(ring, 0x3e800000); 545 546 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 547 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_MASK)); 548 OUT_RING(ring, 549 A2XX_RB_COLOR_MASK_WRITE_RED | A2XX_RB_COLOR_MASK_WRITE_GREEN | 550 A2XX_RB_COLOR_MASK_WRITE_BLUE | A2XX_RB_COLOR_MASK_WRITE_ALPHA); 551 552 OUT_PKT3(ring, CP_SET_CONSTANT, 5); 553 OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_RED)); 554 OUT_RING(ring, 0x00000000); /* RB_BLEND_RED */ 555 OUT_RING(ring, 0x00000000); /* RB_BLEND_GREEN */ 556 OUT_RING(ring, 0x00000000); /* RB_BLEND_BLUE */ 557 OUT_RING(ring, 0x000000ff); /* RB_BLEND_ALPHA */ 558 559 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 560 OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VTE_CNTL)); 561 OUT_RING(ring, A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT | 562 A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA | 563 A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA | 564 A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA | 565 A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA | 566 A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA | 567 A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA); 568} 569 570void 571fd2_emit_init_screen(struct pipe_screen *pscreen) 572{ 573 struct fd_screen *screen = fd_screen(pscreen); 574 screen->emit_ib = fd2_emit_ib; 575} 576 577void 578fd2_emit_init(struct pipe_context *pctx) 579{ 580} 581