1/* 2 * Copyright (c) 2012-2015 Etnaviv Project 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Wladimir J. van der Laan <laanwj@gmail.com> 25 * Christian Gmeiner <christian.gmeiner@gmail.com> 26 */ 27 28#include "etnaviv_screen.h" 29 30#include "hw/common.xml.h" 31 32#include "etnaviv_compiler.h" 33#include "etnaviv_context.h" 34#include "etnaviv_debug.h" 35#include "etnaviv_fence.h" 36#include "etnaviv_format.h" 37#include "etnaviv_query.h" 38#include "etnaviv_resource.h" 39#include "etnaviv_translate.h" 40 41#include "util/hash_table.h" 42#include "util/os_time.h" 43#include "util/u_math.h" 44#include "util/u_memory.h" 45#include "util/u_screen.h" 46#include "util/u_string.h" 47 48#include "frontend/drm_driver.h" 49 50#include "drm-uapi/drm_fourcc.h" 51 52#define ETNA_DRM_VERSION_FENCE_FD ETNA_DRM_VERSION(1, 1) 53#define ETNA_DRM_VERSION_PERFMON ETNA_DRM_VERSION(1, 2) 54 55static const struct debug_named_value etna_debug_options[] = { 56 {"dbg_msgs", ETNA_DBG_MSGS, "Print debug messages"}, 57 {"drm_msgs", ETNA_DRM_MSGS, "Print drm messages"}, 58 {"frame_msgs", ETNA_DBG_FRAME_MSGS, "Print frame messages"}, 59 {"resource_msgs", ETNA_DBG_RESOURCE_MSGS, "Print resource messages"}, 60 {"compiler_msgs", ETNA_DBG_COMPILER_MSGS, "Print compiler messages"}, 61 {"linker_msgs", ETNA_DBG_LINKER_MSGS, "Print linker messages"}, 62 {"dump_shaders", ETNA_DBG_DUMP_SHADERS, "Dump shaders"}, 63 {"no_ts", ETNA_DBG_NO_TS, "Disable TS"}, 64 {"no_autodisable", ETNA_DBG_NO_AUTODISABLE, "Disable autodisable"}, 65 {"no_supertile", ETNA_DBG_NO_SUPERTILE, "Disable supertiles"}, 66 {"no_early_z", ETNA_DBG_NO_EARLY_Z, "Disable early z"}, 67 {"cflush_all", ETNA_DBG_CFLUSH_ALL, "Flush every cache before state update"}, 68 {"msaa2x", ETNA_DBG_MSAA_2X, "Force 2x msaa"}, 69 {"msaa4x", ETNA_DBG_MSAA_4X, "Force 4x msaa"}, 70 {"flush_all", ETNA_DBG_FLUSH_ALL, "Flush after every rendered primitive"}, 71 {"zero", ETNA_DBG_ZERO, "Zero all resources after allocation"}, 72 {"draw_stall", ETNA_DBG_DRAW_STALL, "Stall FE/PE after each rendered primitive"}, 73 {"shaderdb", ETNA_DBG_SHADERDB, "Enable shaderdb output"}, 74 {"no_singlebuffer",ETNA_DBG_NO_SINGLEBUF, "Disable single buffer feature"}, 75 {"deqp", ETNA_DBG_DEQP, "Hacks to run dEQP GLES3 tests"}, /* needs MESA_GLES_VERSION_OVERRIDE=3.0 */ 76 {"nocache", ETNA_DBG_NOCACHE, "Disable shader cache"}, 77 {"no_linear_pe", ETNA_DBG_NO_LINEAR_PE, "Disable linear PE"}, 78 DEBUG_NAMED_VALUE_END 79}; 80 81DEBUG_GET_ONCE_FLAGS_OPTION(etna_mesa_debug, "ETNA_MESA_DEBUG", etna_debug_options, 0) 82int etna_mesa_debug = 0; 83 84static void 85etna_screen_destroy(struct pipe_screen *pscreen) 86{ 87 struct etna_screen *screen = etna_screen(pscreen); 88 89 if (screen->dummy_desc_reloc.bo) 90 etna_bo_del(screen->dummy_desc_reloc.bo); 91 92 if (screen->dummy_rt_reloc.bo) 93 etna_bo_del(screen->dummy_rt_reloc.bo); 94 95 if (screen->perfmon) 96 etna_perfmon_del(screen->perfmon); 97 98 etna_shader_screen_fini(pscreen); 99 100 if (screen->pipe) 101 etna_pipe_del(screen->pipe); 102 103 if (screen->gpu) 104 etna_gpu_del(screen->gpu); 105 106 if (screen->ro) 107 screen->ro->destroy(screen->ro); 108 109 if (screen->dev) 110 etna_device_del(screen->dev); 111 112 FREE(screen); 113} 114 115static const char * 116etna_screen_get_name(struct pipe_screen *pscreen) 117{ 118 struct etna_screen *priv = etna_screen(pscreen); 119 static char buffer[128]; 120 121 snprintf(buffer, sizeof(buffer), "Vivante GC%x rev %04x", priv->model, 122 priv->revision); 123 124 return buffer; 125} 126 127static const char * 128etna_screen_get_vendor(struct pipe_screen *pscreen) 129{ 130 return "etnaviv"; 131} 132 133static const char * 134etna_screen_get_device_vendor(struct pipe_screen *pscreen) 135{ 136 return "Vivante"; 137} 138 139static int 140etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) 141{ 142 struct etna_screen *screen = etna_screen(pscreen); 143 144 switch (param) { 145 /* Supported features (boolean caps). */ 146 case PIPE_CAP_POINT_SPRITE: 147 case PIPE_CAP_BLEND_EQUATION_SEPARATE: 148 case PIPE_CAP_FS_COORD_ORIGIN_UPPER_LEFT: 149 case PIPE_CAP_FS_COORD_PIXEL_CENTER_HALF_INTEGER: 150 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD: 151 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES: 152 case PIPE_CAP_TEXTURE_BARRIER: 153 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: 154 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: 155 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: 156 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: 157 case PIPE_CAP_TGSI_TEXCOORD: 158 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: 159 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS: 160 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: 161 case PIPE_CAP_STRING_MARKER: 162 case PIPE_CAP_FRONTEND_NOOP: 163 return 1; 164 case PIPE_CAP_NATIVE_FENCE_FD: 165 return screen->drm_version >= ETNA_DRM_VERSION_FENCE_FD; 166 case PIPE_CAP_FS_POSITION_IS_SYSVAL: 167 case PIPE_CAP_FS_FACE_IS_INTEGER_SYSVAL: /* note: not integer */ 168 return 1; 169 case PIPE_CAP_FS_POINT_IS_SYSVAL: 170 return 0; 171 172 /* Memory */ 173 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: 174 return 256; 175 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: 176 return 4096; 177 178 case PIPE_CAP_NPOT_TEXTURES: 179 return true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1, 180 NON_POWER_OF_TWO); */ 181 182 case PIPE_CAP_ANISOTROPIC_FILTER: 183 case PIPE_CAP_TEXTURE_SWIZZLE: 184 case PIPE_CAP_PRIMITIVE_RESTART: 185 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX: 186 return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); 187 188 case PIPE_CAP_ALPHA_TEST: 189 return !VIV_FEATURE(screen, chipMinorFeatures7, PE_NO_ALPHA_TEST); 190 191 /* Unsupported features. */ 192 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: 193 case PIPE_CAP_TEXRECT: 194 return 0; 195 196 /* Stream output. */ 197 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: 198 return DBG_ENABLED(ETNA_DBG_DEQP) ? 4 : 0; 199 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: 200 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: 201 return 0; 202 203 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE: 204 return 128; 205 case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET: 206 return 255; 207 case PIPE_CAP_MAX_VERTEX_BUFFERS: 208 return screen->specs.stream_count; 209 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: 210 return VIV_FEATURE(screen, chipMinorFeatures4, HALTI2); 211 212 213 /* Texturing. */ 214 case PIPE_CAP_TEXTURE_SHADOW_MAP: 215 return 1; 216 case PIPE_CAP_MAX_TEXTURE_2D_SIZE: 217 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: /* TODO: verify */ 218 return screen->specs.max_texture_size; 219 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 220 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: 221 { 222 int log2_max_tex_size = util_last_bit(screen->specs.max_texture_size); 223 assert(log2_max_tex_size > 0); 224 return log2_max_tex_size; 225 } 226 227 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET: 228 case PIPE_CAP_MIN_TEXEL_OFFSET: 229 return -8; 230 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET: 231 case PIPE_CAP_MAX_TEXEL_OFFSET: 232 return 7; 233 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: 234 return screen->specs.seamless_cube_map; 235 236 /* Queries. */ 237 case PIPE_CAP_OCCLUSION_QUERY: 238 return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); 239 240 /* Preferences */ 241 case PIPE_CAP_TEXTURE_TRANSFER_MODES: 242 return 0; 243 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET: { 244 /* etnaviv is being run on systems as small as 256MB total RAM so 245 * we need to provide a sane value for such a device. Limit the 246 * memory budget to min(~3% of pyhiscal memory, 64MB). 247 * 248 * a simple divison by 32 provides the numbers we want. 249 * 256MB / 32 = 8MB 250 * 2048MB / 32 = 64MB 251 */ 252 uint64_t system_memory; 253 254 if (!os_get_total_physical_memory(&system_memory)) 255 system_memory = (uint64_t)4096 << 20; 256 257 return MIN2(system_memory / 32, 64 * 1024 * 1024); 258 } 259 260 case PIPE_CAP_MAX_VARYINGS: 261 return screen->specs.max_varyings; 262 263 case PIPE_CAP_SUPPORTED_PRIM_MODES: 264 case PIPE_CAP_SUPPORTED_PRIM_MODES_WITH_RESTART: { 265 /* Generate the bitmask of supported draw primitives. */ 266 uint32_t modes = 1 << PIPE_PRIM_POINTS | 267 1 << PIPE_PRIM_LINES | 268 1 << PIPE_PRIM_LINE_STRIP | 269 1 << PIPE_PRIM_TRIANGLES | 270 1 << PIPE_PRIM_TRIANGLE_FAN; 271 272 /* TODO: The bug relates only to indexed draws, but here we signal 273 * that there is no support for triangle strips at all. This should 274 * be refined. 275 */ 276 if (VIV_FEATURE(screen, chipMinorFeatures2, BUG_FIXES8)) 277 modes |= 1 << PIPE_PRIM_TRIANGLE_STRIP; 278 279 if (VIV_FEATURE(screen, chipMinorFeatures2, LINE_LOOP)) 280 modes |= 1 << PIPE_PRIM_LINE_LOOP; 281 282 return modes; 283 } 284 285 case PIPE_CAP_PCI_GROUP: 286 case PIPE_CAP_PCI_BUS: 287 case PIPE_CAP_PCI_DEVICE: 288 case PIPE_CAP_PCI_FUNCTION: 289 return 0; 290 case PIPE_CAP_ACCELERATED: 291 return 1; 292 case PIPE_CAP_VIDEO_MEMORY: 293 return 0; 294 case PIPE_CAP_UMA: 295 return 1; 296 default: 297 return u_pipe_screen_get_param_defaults(pscreen, param); 298 } 299} 300 301static float 302etna_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param) 303{ 304 struct etna_screen *screen = etna_screen(pscreen); 305 306 switch (param) { 307 case PIPE_CAPF_MIN_LINE_WIDTH: 308 case PIPE_CAPF_MIN_LINE_WIDTH_AA: 309 case PIPE_CAPF_MIN_POINT_SIZE: 310 case PIPE_CAPF_MIN_POINT_SIZE_AA: 311 return 1; 312 case PIPE_CAPF_POINT_SIZE_GRANULARITY: 313 case PIPE_CAPF_LINE_WIDTH_GRANULARITY: 314 return 0.1; 315 case PIPE_CAPF_MAX_LINE_WIDTH: 316 case PIPE_CAPF_MAX_LINE_WIDTH_AA: 317 case PIPE_CAPF_MAX_POINT_SIZE: 318 case PIPE_CAPF_MAX_POINT_SIZE_AA: 319 return 8192.0f; 320 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: 321 return 16.0f; 322 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: 323 return util_last_bit(screen->specs.max_texture_size); 324 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE: 325 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE: 326 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY: 327 return 0.0f; 328 } 329 330 debug_printf("unknown paramf %d", param); 331 return 0; 332} 333 334static int 335etna_screen_get_shader_param(struct pipe_screen *pscreen, 336 enum pipe_shader_type shader, 337 enum pipe_shader_cap param) 338{ 339 struct etna_screen *screen = etna_screen(pscreen); 340 bool ubo_enable = screen->specs.halti >= 2; 341 342 if (DBG_ENABLED(ETNA_DBG_DEQP)) 343 ubo_enable = true; 344 345 switch (shader) { 346 case PIPE_SHADER_FRAGMENT: 347 case PIPE_SHADER_VERTEX: 348 break; 349 case PIPE_SHADER_COMPUTE: 350 case PIPE_SHADER_GEOMETRY: 351 case PIPE_SHADER_TESS_CTRL: 352 case PIPE_SHADER_TESS_EVAL: 353 return 0; 354 default: 355 DBG("unknown shader type %d", shader); 356 return 0; 357 } 358 359 switch (param) { 360 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 361 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 362 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 363 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 364 return ETNA_MAX_TOKENS; 365 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 366 return ETNA_MAX_DEPTH; /* XXX */ 367 case PIPE_SHADER_CAP_MAX_INPUTS: 368 /* Maximum number of inputs for the vertex shader is the number 369 * of vertex elements - each element defines one vertex shader 370 * input register. For the fragment shader, this is the number 371 * of varyings. */ 372 return shader == PIPE_SHADER_FRAGMENT ? screen->specs.max_varyings 373 : screen->specs.vertex_max_elements; 374 case PIPE_SHADER_CAP_MAX_OUTPUTS: 375 return 16; /* see VIVS_VS_OUTPUT */ 376 case PIPE_SHADER_CAP_MAX_TEMPS: 377 return 64; /* Max native temporaries. */ 378 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 379 return ubo_enable ? ETNA_MAX_CONST_BUF : 1; 380 case PIPE_SHADER_CAP_CONT_SUPPORTED: 381 return 1; 382 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 383 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 384 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 385 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 386 return 1; 387 case PIPE_SHADER_CAP_SUBROUTINES: 388 return 0; 389 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: 390 return VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG); 391 case PIPE_SHADER_CAP_INT64_ATOMICS: 392 case PIPE_SHADER_CAP_FP16: 393 case PIPE_SHADER_CAP_FP16_DERIVATIVES: 394 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS: 395 case PIPE_SHADER_CAP_INT16: 396 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS: 397 return 0; 398 case PIPE_SHADER_CAP_INTEGERS: 399 return screen->specs.halti >= 2; 400 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: 401 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: 402 return shader == PIPE_SHADER_FRAGMENT 403 ? screen->specs.fragment_sampler_count 404 : screen->specs.vertex_sampler_count; 405 case PIPE_SHADER_CAP_PREFERRED_IR: 406 return PIPE_SHADER_IR_NIR; 407 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE: 408 if (ubo_enable) 409 return 16384; /* 16384 so state tracker enables UBOs */ 410 return shader == PIPE_SHADER_FRAGMENT 411 ? screen->specs.max_ps_uniforms * sizeof(float[4]) 412 : screen->specs.max_vs_uniforms * sizeof(float[4]); 413 case PIPE_SHADER_CAP_DROUND_SUPPORTED: 414 case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED: 415 case PIPE_SHADER_CAP_LDEXP_SUPPORTED: 416 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: 417 return false; 418 case PIPE_SHADER_CAP_SUPPORTED_IRS: 419 return (1 << PIPE_SHADER_IR_TGSI) | 420 (1 << PIPE_SHADER_IR_NIR); 421 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: 422 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: 423 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: 424 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: 425 return 0; 426 } 427 428 debug_printf("unknown shader param %d", param); 429 return 0; 430} 431 432static uint64_t 433etna_screen_get_timestamp(struct pipe_screen *pscreen) 434{ 435 return os_time_get_nano(); 436} 437 438static bool 439gpu_supports_texture_target(struct etna_screen *screen, 440 enum pipe_texture_target target) 441{ 442 if (target == PIPE_TEXTURE_CUBE_ARRAY) 443 return false; 444 445 /* pre-halti has no array/3D */ 446 if (screen->specs.halti < 0 && 447 (target == PIPE_TEXTURE_1D_ARRAY || 448 target == PIPE_TEXTURE_2D_ARRAY || 449 target == PIPE_TEXTURE_3D)) 450 return false; 451 452 return true; 453} 454 455static bool 456gpu_supports_texture_format(struct etna_screen *screen, uint32_t fmt, 457 enum pipe_format format) 458{ 459 bool supported = true; 460 461 if (fmt == TEXTURE_FORMAT_ETC1) 462 supported = VIV_FEATURE(screen, chipFeatures, ETC1_TEXTURE_COMPRESSION); 463 464 if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5) 465 supported = VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION); 466 467 if (util_format_is_srgb(format)) 468 supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); 469 470 if (fmt & EXT_FORMAT) 471 supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); 472 473 if (fmt & ASTC_FORMAT) { 474 supported = screen->specs.tex_astc; 475 } 476 477 if (util_format_is_snorm(format)) 478 supported = VIV_FEATURE(screen, chipMinorFeatures2, HALTI1); 479 480 if (format != PIPE_FORMAT_S8_UINT_Z24_UNORM && 481 (util_format_is_pure_integer(format) || util_format_is_float(format))) 482 supported = VIV_FEATURE(screen, chipMinorFeatures4, HALTI2); 483 484 485 if (!supported) 486 return false; 487 488 if (texture_format_needs_swiz(format)) 489 return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); 490 491 return true; 492} 493 494static bool 495gpu_supports_render_format(struct etna_screen *screen, enum pipe_format format, 496 unsigned sample_count) 497{ 498 const uint32_t fmt = translate_pe_format(format); 499 500 if (fmt == ETNA_NO_MATCH) 501 return false; 502 503 /* MSAA is broken */ 504 if (sample_count > 1) 505 return false; 506 507 if (format == PIPE_FORMAT_R8_UNORM) 508 return VIV_FEATURE(screen, chipMinorFeatures5, HALTI5); 509 510 /* figure out 8bpp RS clear to enable these formats */ 511 if (format == PIPE_FORMAT_R8_SINT || format == PIPE_FORMAT_R8_UINT) 512 return VIV_FEATURE(screen, chipMinorFeatures5, HALTI5); 513 514 if (util_format_is_srgb(format)) 515 return VIV_FEATURE(screen, chipMinorFeatures5, HALTI3); 516 517 if (util_format_is_pure_integer(format) || util_format_is_float(format)) 518 return VIV_FEATURE(screen, chipMinorFeatures4, HALTI2); 519 520 if (format == PIPE_FORMAT_R8G8_UNORM) 521 return VIV_FEATURE(screen, chipMinorFeatures4, HALTI2); 522 523 /* any other extended format is HALTI0 (only R10G10B10A2?) */ 524 if (fmt >= PE_FORMAT_R16F) 525 return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); 526 527 return true; 528} 529 530static bool 531gpu_supports_vertex_format(struct etna_screen *screen, enum pipe_format format) 532{ 533 if (translate_vertex_format_type(format) == ETNA_NO_MATCH) 534 return false; 535 536 if (util_format_is_pure_integer(format)) 537 return VIV_FEATURE(screen, chipMinorFeatures4, HALTI2); 538 539 return true; 540} 541 542static bool 543etna_screen_is_format_supported(struct pipe_screen *pscreen, 544 enum pipe_format format, 545 enum pipe_texture_target target, 546 unsigned sample_count, 547 unsigned storage_sample_count, 548 unsigned usage) 549{ 550 struct etna_screen *screen = etna_screen(pscreen); 551 unsigned allowed = 0; 552 553 if (!gpu_supports_texture_target(screen, target)) 554 return false; 555 556 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count)) 557 return false; 558 559 if (usage & PIPE_BIND_RENDER_TARGET) { 560 if (gpu_supports_render_format(screen, format, sample_count)) 561 allowed |= PIPE_BIND_RENDER_TARGET; 562 } 563 564 if (usage & PIPE_BIND_DEPTH_STENCIL) { 565 if (translate_depth_format(format) != ETNA_NO_MATCH) 566 allowed |= PIPE_BIND_DEPTH_STENCIL; 567 } 568 569 if (usage & PIPE_BIND_SAMPLER_VIEW) { 570 uint32_t fmt = translate_texture_format(format); 571 572 if (!gpu_supports_texture_format(screen, fmt, format)) 573 fmt = ETNA_NO_MATCH; 574 575 if (sample_count < 2 && fmt != ETNA_NO_MATCH) 576 allowed |= PIPE_BIND_SAMPLER_VIEW; 577 } 578 579 if (usage & PIPE_BIND_VERTEX_BUFFER) { 580 if (gpu_supports_vertex_format(screen, format)) 581 allowed |= PIPE_BIND_VERTEX_BUFFER; 582 } 583 584 if (usage & PIPE_BIND_INDEX_BUFFER) { 585 /* must be supported index format */ 586 if (format == PIPE_FORMAT_R8_UINT || format == PIPE_FORMAT_R16_UINT || 587 (format == PIPE_FORMAT_R32_UINT && 588 VIV_FEATURE(screen, chipFeatures, 32_BIT_INDICES))) { 589 allowed |= PIPE_BIND_INDEX_BUFFER; 590 } 591 } 592 593 /* Always allowed */ 594 allowed |= 595 usage & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED); 596 597 if (usage != allowed) { 598 DBG("not supported: format=%s, target=%d, sample_count=%d, " 599 "usage=%x, allowed=%x", 600 util_format_name(format), target, sample_count, usage, allowed); 601 } 602 603 return usage == allowed; 604} 605 606const uint64_t supported_modifiers[] = { 607 DRM_FORMAT_MOD_LINEAR, 608 DRM_FORMAT_MOD_VIVANTE_TILED, 609 DRM_FORMAT_MOD_VIVANTE_SUPER_TILED, 610 DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED, 611 DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED, 612}; 613 614static bool modifier_num_supported(struct pipe_screen *pscreen, int num) 615{ 616 struct etna_screen *screen = etna_screen(pscreen); 617 618 /* don't advertise split tiled formats on single pipe/buffer GPUs */ 619 if ((screen->specs.pixel_pipes == 1 || screen->specs.single_buffer) && 620 num >= 3) 621 return false; 622 623 return true; 624} 625 626static void 627etna_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen, 628 enum pipe_format format, int max, 629 uint64_t *modifiers, 630 unsigned int *external_only, int *count) 631{ 632 int i, num_modifiers = 0; 633 634 if (max > ARRAY_SIZE(supported_modifiers)) 635 max = ARRAY_SIZE(supported_modifiers); 636 637 if (!max) { 638 modifiers = NULL; 639 max = ARRAY_SIZE(supported_modifiers); 640 } 641 642 for (i = 0; num_modifiers < max; i++) { 643 if (!modifier_num_supported(pscreen, i)) 644 break; 645 646 if (modifiers) 647 modifiers[num_modifiers] = supported_modifiers[i]; 648 if (external_only) 649 external_only[num_modifiers] = util_format_is_yuv(format) ? 1 : 0; 650 num_modifiers++; 651 } 652 653 *count = num_modifiers; 654} 655 656static bool 657etna_screen_is_dmabuf_modifier_supported(struct pipe_screen *pscreen, 658 uint64_t modifier, 659 enum pipe_format format, 660 bool *external_only) 661{ 662 int i; 663 664 for (i = 0; i < ARRAY_SIZE(supported_modifiers); i++) { 665 if (!modifier_num_supported(pscreen, i)) 666 break; 667 668 if (modifier == supported_modifiers[i]) { 669 if (external_only) 670 *external_only = util_format_is_yuv(format) ? 1 : 0; 671 672 return true; 673 } 674 } 675 676 return false; 677} 678 679static void 680etna_determine_uniform_limits(struct etna_screen *screen) 681{ 682 /* values for the non unified case are taken from 683 * gcmCONFIGUREUNIFORMS in the Vivante kernel driver file 684 * drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h. 685 */ 686 if (screen->model == chipModel_GC2000 && 687 (screen->revision == 0x5118 || screen->revision == 0x5140)) { 688 screen->specs.max_vs_uniforms = 256; 689 screen->specs.max_ps_uniforms = 64; 690 } else if (screen->specs.num_constants == 320) { 691 screen->specs.max_vs_uniforms = 256; 692 screen->specs.max_ps_uniforms = 64; 693 } else if (screen->specs.num_constants > 256 && 694 screen->model == chipModel_GC1000) { 695 /* All GC1000 series chips can only support 64 uniforms for ps on non-unified const mode. */ 696 screen->specs.max_vs_uniforms = 256; 697 screen->specs.max_ps_uniforms = 64; 698 } else if (screen->specs.num_constants > 256) { 699 screen->specs.max_vs_uniforms = 256; 700 screen->specs.max_ps_uniforms = 256; 701 } else if (screen->specs.num_constants == 256) { 702 screen->specs.max_vs_uniforms = 256; 703 screen->specs.max_ps_uniforms = 256; 704 } else { 705 screen->specs.max_vs_uniforms = 168; 706 screen->specs.max_ps_uniforms = 64; 707 } 708} 709 710static void 711etna_determine_sampler_limits(struct etna_screen *screen) 712{ 713 /* vertex and fragment samplers live in one address space */ 714 if (screen->specs.halti >= 1) { 715 screen->specs.vertex_sampler_offset = 16; 716 screen->specs.fragment_sampler_count = 16; 717 screen->specs.vertex_sampler_count = 16; 718 } else { 719 screen->specs.vertex_sampler_offset = 8; 720 screen->specs.fragment_sampler_count = 8; 721 screen->specs.vertex_sampler_count = 4; 722 } 723 724 if (screen->model == 0x400) 725 screen->specs.vertex_sampler_count = 0; 726} 727 728static bool 729etna_get_specs(struct etna_screen *screen) 730{ 731 uint64_t val; 732 uint32_t instruction_count; 733 734 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_INSTRUCTION_COUNT, &val)) { 735 DBG("could not get ETNA_GPU_INSTRUCTION_COUNT"); 736 goto fail; 737 } 738 instruction_count = val; 739 740 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE, 741 &val)) { 742 DBG("could not get ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE"); 743 goto fail; 744 } 745 screen->specs.vertex_output_buffer_size = val; 746 747 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_CACHE_SIZE, &val)) { 748 DBG("could not get ETNA_GPU_VERTEX_CACHE_SIZE"); 749 goto fail; 750 } 751 screen->specs.vertex_cache_size = val; 752 753 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_SHADER_CORE_COUNT, &val)) { 754 DBG("could not get ETNA_GPU_SHADER_CORE_COUNT"); 755 goto fail; 756 } 757 screen->specs.shader_core_count = val; 758 759 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_STREAM_COUNT, &val)) { 760 DBG("could not get ETNA_GPU_STREAM_COUNT"); 761 goto fail; 762 } 763 screen->specs.stream_count = val; 764 765 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REGISTER_MAX, &val)) { 766 DBG("could not get ETNA_GPU_REGISTER_MAX"); 767 goto fail; 768 } 769 screen->specs.max_registers = val; 770 771 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_PIXEL_PIPES, &val)) { 772 DBG("could not get ETNA_GPU_PIXEL_PIPES"); 773 goto fail; 774 } 775 screen->specs.pixel_pipes = val; 776 777 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_CONSTANTS, &val)) { 778 DBG("could not get %s", "ETNA_GPU_NUM_CONSTANTS"); 779 goto fail; 780 } 781 if (val == 0) { 782 fprintf(stderr, "Warning: zero num constants (update kernel?)\n"); 783 val = 168; 784 } 785 screen->specs.num_constants = val; 786 787 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_VARYINGS, &val)) { 788 DBG("could not get ETNA_GPU_NUM_VARYINGS"); 789 goto fail; 790 } 791 screen->specs.max_varyings = MAX2(val, ETNA_NUM_VARYINGS); 792 793 /* Figure out gross GPU architecture. See rnndb/common.xml for a specific 794 * description of the differences. */ 795 if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI5)) 796 screen->specs.halti = 5; /* New GC7000/GC8x00 */ 797 else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI4)) 798 screen->specs.halti = 4; /* Old GC7000/GC7400 */ 799 else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI3)) 800 screen->specs.halti = 3; /* None? */ 801 else if (VIV_FEATURE(screen, chipMinorFeatures4, HALTI2)) 802 screen->specs.halti = 2; /* GC2500/GC3000/GC5000/GC6400 */ 803 else if (VIV_FEATURE(screen, chipMinorFeatures2, HALTI1)) 804 screen->specs.halti = 1; /* GC900/GC4000/GC7000UL */ 805 else if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) 806 screen->specs.halti = 0; /* GC880/GC2000/GC7000TM */ 807 else 808 screen->specs.halti = -1; /* GC7000nanolite / pre-GC2000 except GC880 */ 809 if (screen->specs.halti >= 0) 810 DBG("etnaviv: GPU arch: HALTI%d", screen->specs.halti); 811 else 812 DBG("etnaviv: GPU arch: pre-HALTI"); 813 814 screen->specs.can_supertile = 815 VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED); 816 screen->specs.bits_per_tile = 817 !VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) || 818 VIV_FEATURE(screen, chipMinorFeatures6, CACHE128B256BPERLINE) ? 4 : 2; 819 820 screen->specs.ts_clear_value = 821 VIV_FEATURE(screen, chipMinorFeatures10, DEC400) ? 0xffffffff : 822 screen->specs.bits_per_tile == 4 ? 0x11111111 : 0x55555555; 823 824 screen->specs.vs_need_z_div = 825 screen->model < 0x1000 && screen->model != 0x880; 826 screen->specs.has_sin_cos_sqrt = 827 VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG); 828 screen->specs.has_sign_floor_ceil = 829 VIV_FEATURE(screen, chipMinorFeatures0, HAS_SIGN_FLOOR_CEIL); 830 screen->specs.has_shader_range_registers = 831 screen->model >= 0x1000 || screen->model == 0x880; 832 screen->specs.npot_tex_any_wrap = 833 VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO); 834 screen->specs.has_new_transcendentals = 835 VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS); 836 screen->specs.has_halti2_instructions = 837 VIV_FEATURE(screen, chipMinorFeatures4, HALTI2); 838 screen->specs.has_no_oneconst_limit = 839 VIV_FEATURE(screen, chipMinorFeatures8, SH_NO_ONECONST_LIMIT); 840 screen->specs.v4_compression = 841 VIV_FEATURE(screen, chipMinorFeatures6, V4_COMPRESSION); 842 screen->specs.seamless_cube_map = 843 (screen->model != 0x880) && /* Seamless cubemap is broken on GC880? */ 844 VIV_FEATURE(screen, chipMinorFeatures2, SEAMLESS_CUBE_MAP); 845 846 if (screen->specs.halti >= 5) { 847 /* GC7000 - this core must load shaders from memory. */ 848 screen->specs.vs_offset = 0; 849 screen->specs.ps_offset = 0; 850 screen->specs.max_instructions = 0; /* Do not program shaders manually */ 851 screen->specs.has_icache = true; 852 } else if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) { 853 /* GC3000 - this core is capable of loading shaders from 854 * memory. It can also run shaders from registers, as a fallback, but 855 * "max_instructions" does not have the correct value. It has place for 856 * 2*256 instructions just like GC2000, but the offsets are slightly 857 * different. 858 */ 859 screen->specs.vs_offset = 0xC000; 860 /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses 861 * this mirror for writing PS instructions, probably safest to do the 862 * same. 863 */ 864 screen->specs.ps_offset = 0x8000 + 0x1000; 865 screen->specs.max_instructions = 256; /* maximum number instructions for non-icache use */ 866 screen->specs.has_icache = true; 867 } else { 868 if (instruction_count > 256) { /* unified instruction memory? */ 869 screen->specs.vs_offset = 0xC000; 870 screen->specs.ps_offset = 0xD000; /* like vivante driver */ 871 screen->specs.max_instructions = 256; 872 } else { 873 screen->specs.vs_offset = 0x4000; 874 screen->specs.ps_offset = 0x6000; 875 screen->specs.max_instructions = instruction_count; 876 } 877 screen->specs.has_icache = false; 878 } 879 880 if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) { 881 screen->specs.vertex_max_elements = 16; 882 } else { 883 /* Etna_viv documentation seems confused over the correct value 884 * here so choose the lower to be safe: HALTI0 says 16 i.s.o. 885 * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */ 886 screen->specs.vertex_max_elements = 10; 887 } 888 889 etna_determine_uniform_limits(screen); 890 etna_determine_sampler_limits(screen); 891 892 if (screen->specs.halti >= 5) { 893 screen->specs.has_unified_uniforms = true; 894 screen->specs.vs_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS_MIRROR(0); 895 screen->specs.ps_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS(screen->specs.max_vs_uniforms*4); 896 } else if (screen->specs.halti >= 1) { 897 /* unified uniform memory on GC3000 - HALTI1 feature bit is just a guess 898 */ 899 screen->specs.has_unified_uniforms = true; 900 screen->specs.vs_uniforms_offset = VIVS_SH_UNIFORMS(0); 901 /* hardcode PS uniforms to start after end of VS uniforms - 902 * for more flexibility this offset could be variable based on the 903 * shader. 904 */ 905 screen->specs.ps_uniforms_offset = VIVS_SH_UNIFORMS(screen->specs.max_vs_uniforms*4); 906 } else { 907 screen->specs.has_unified_uniforms = false; 908 screen->specs.vs_uniforms_offset = VIVS_VS_UNIFORMS(0); 909 screen->specs.ps_uniforms_offset = VIVS_PS_UNIFORMS(0); 910 } 911 912 screen->specs.max_texture_size = 913 VIV_FEATURE(screen, chipMinorFeatures0, TEXTURE_8K) ? 8192 : 2048; 914 screen->specs.max_rendertarget_size = 915 VIV_FEATURE(screen, chipMinorFeatures0, RENDERTARGET_8K) ? 8192 : 2048; 916 917 screen->specs.single_buffer = VIV_FEATURE(screen, chipMinorFeatures4, SINGLE_BUFFER); 918 if (screen->specs.single_buffer) 919 DBG("etnaviv: Single buffer mode enabled with %d pixel pipes", screen->specs.pixel_pipes); 920 921 screen->specs.tex_astc = VIV_FEATURE(screen, chipMinorFeatures4, TEXTURE_ASTC) && 922 !VIV_FEATURE(screen, chipMinorFeatures6, NO_ASTC); 923 924 screen->specs.use_blt = VIV_FEATURE(screen, chipMinorFeatures5, BLT_ENGINE); 925 926 /* Only allow fast clear with MC2.0, as the TS unit bypasses the memory 927 * offset on MC1.0 and we have no way to fixup the address. 928 */ 929 if (!VIV_FEATURE(screen, chipMinorFeatures0, MC20)) 930 screen->features[viv_chipFeatures] &= ~chipFeatures_FAST_CLEAR; 931 932 return true; 933 934fail: 935 return false; 936} 937 938struct etna_bo * 939etna_screen_bo_from_handle(struct pipe_screen *pscreen, 940 struct winsys_handle *whandle) 941{ 942 struct etna_screen *screen = etna_screen(pscreen); 943 struct etna_bo *bo; 944 945 if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) { 946 bo = etna_bo_from_name(screen->dev, whandle->handle); 947 } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) { 948 bo = etna_bo_from_dmabuf(screen->dev, whandle->handle); 949 } else { 950 DBG("Attempt to import unsupported handle type %d", whandle->type); 951 return NULL; 952 } 953 954 if (!bo) { 955 DBG("ref name 0x%08x failed", whandle->handle); 956 return NULL; 957 } 958 959 return bo; 960} 961 962static const void * 963etna_get_compiler_options(struct pipe_screen *pscreen, 964 enum pipe_shader_ir ir, unsigned shader) 965{ 966 return etna_compiler_get_options(etna_screen(pscreen)->compiler); 967} 968 969static struct disk_cache * 970etna_get_disk_shader_cache(struct pipe_screen *pscreen) 971{ 972 struct etna_screen *screen = etna_screen(pscreen); 973 struct etna_compiler *compiler = screen->compiler; 974 975 return compiler->disk_cache; 976} 977 978struct pipe_screen * 979etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu, 980 struct renderonly *ro) 981{ 982 struct etna_screen *screen = CALLOC_STRUCT(etna_screen); 983 struct pipe_screen *pscreen; 984 uint64_t val; 985 986 if (!screen) 987 return NULL; 988 989 pscreen = &screen->base; 990 screen->dev = dev; 991 screen->gpu = gpu; 992 screen->ro = ro; 993 screen->refcnt = 1; 994 995 screen->drm_version = etnaviv_device_version(screen->dev); 996 etna_mesa_debug = debug_get_option_etna_mesa_debug(); 997 998 /* Disable autodisable for correct rendering with TS */ 999 etna_mesa_debug |= ETNA_DBG_NO_AUTODISABLE; 1000 1001 screen->pipe = etna_pipe_new(gpu, ETNA_PIPE_3D); 1002 if (!screen->pipe) { 1003 DBG("could not create 3d pipe"); 1004 goto fail; 1005 } 1006 1007 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_MODEL, &val)) { 1008 DBG("could not get ETNA_GPU_MODEL"); 1009 goto fail; 1010 } 1011 screen->model = val; 1012 1013 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REVISION, &val)) { 1014 DBG("could not get ETNA_GPU_REVISION"); 1015 goto fail; 1016 } 1017 screen->revision = val; 1018 1019 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_0, &val)) { 1020 DBG("could not get ETNA_GPU_FEATURES_0"); 1021 goto fail; 1022 } 1023 screen->features[0] = val; 1024 1025 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_1, &val)) { 1026 DBG("could not get ETNA_GPU_FEATURES_1"); 1027 goto fail; 1028 } 1029 screen->features[1] = val; 1030 1031 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_2, &val)) { 1032 DBG("could not get ETNA_GPU_FEATURES_2"); 1033 goto fail; 1034 } 1035 screen->features[2] = val; 1036 1037 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_3, &val)) { 1038 DBG("could not get ETNA_GPU_FEATURES_3"); 1039 goto fail; 1040 } 1041 screen->features[3] = val; 1042 1043 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_4, &val)) { 1044 DBG("could not get ETNA_GPU_FEATURES_4"); 1045 goto fail; 1046 } 1047 screen->features[4] = val; 1048 1049 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_5, &val)) { 1050 DBG("could not get ETNA_GPU_FEATURES_5"); 1051 goto fail; 1052 } 1053 screen->features[5] = val; 1054 1055 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_6, &val)) { 1056 DBG("could not get ETNA_GPU_FEATURES_6"); 1057 goto fail; 1058 } 1059 screen->features[6] = val; 1060 1061 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_7, &val)) { 1062 DBG("could not get ETNA_GPU_FEATURES_7"); 1063 goto fail; 1064 } 1065 screen->features[7] = val; 1066 1067 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_8, &val)) { 1068 DBG("could not get ETNA_GPU_FEATURES_8"); 1069 goto fail; 1070 } 1071 screen->features[8] = val; 1072 1073 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_9, &val)) { 1074 DBG("could not get ETNA_GPU_FEATURES_9"); 1075 goto fail; 1076 } 1077 screen->features[9] = val; 1078 1079 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_10, &val)) { 1080 DBG("could not get ETNA_GPU_FEATURES_10"); 1081 goto fail; 1082 } 1083 screen->features[10] = val; 1084 1085 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_11, &val)) { 1086 DBG("could not get ETNA_GPU_FEATURES_11"); 1087 goto fail; 1088 } 1089 screen->features[11] = val; 1090 1091 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_12, &val)) { 1092 DBG("could not get ETNA_GPU_FEATURES_12"); 1093 goto fail; 1094 } 1095 screen->features[12] = val; 1096 1097 if (!etna_get_specs(screen)) 1098 goto fail; 1099 1100 if (screen->specs.halti >= 5 && !etnaviv_device_softpin_capable(dev)) { 1101 DBG("halti5 requires softpin"); 1102 goto fail; 1103 } 1104 1105 /* apply debug options that disable individual features */ 1106 if (DBG_ENABLED(ETNA_DBG_NO_EARLY_Z)) 1107 screen->features[viv_chipFeatures] |= chipFeatures_NO_EARLY_Z; 1108 if (DBG_ENABLED(ETNA_DBG_NO_TS)) 1109 screen->features[viv_chipFeatures] &= ~chipFeatures_FAST_CLEAR; 1110 if (DBG_ENABLED(ETNA_DBG_NO_AUTODISABLE)) 1111 screen->features[viv_chipMinorFeatures1] &= ~chipMinorFeatures1_AUTO_DISABLE; 1112 if (DBG_ENABLED(ETNA_DBG_NO_SUPERTILE)) 1113 screen->specs.can_supertile = 0; 1114 if (DBG_ENABLED(ETNA_DBG_NO_SINGLEBUF)) 1115 screen->specs.single_buffer = 0; 1116 if (DBG_ENABLED(ETNA_DBG_NO_LINEAR_PE)) 1117 screen->features[viv_chipMinorFeatures2] &= ~chipMinorFeatures2_LINEAR_PE; 1118 1119 pscreen->destroy = etna_screen_destroy; 1120 pscreen->get_param = etna_screen_get_param; 1121 pscreen->get_paramf = etna_screen_get_paramf; 1122 pscreen->get_shader_param = etna_screen_get_shader_param; 1123 pscreen->get_compiler_options = etna_get_compiler_options; 1124 pscreen->get_disk_shader_cache = etna_get_disk_shader_cache; 1125 1126 pscreen->get_name = etna_screen_get_name; 1127 pscreen->get_vendor = etna_screen_get_vendor; 1128 pscreen->get_device_vendor = etna_screen_get_device_vendor; 1129 1130 pscreen->get_timestamp = etna_screen_get_timestamp; 1131 pscreen->context_create = etna_context_create; 1132 pscreen->is_format_supported = etna_screen_is_format_supported; 1133 pscreen->query_dmabuf_modifiers = etna_screen_query_dmabuf_modifiers; 1134 pscreen->is_dmabuf_modifier_supported = etna_screen_is_dmabuf_modifier_supported; 1135 1136 if (!etna_shader_screen_init(pscreen)) 1137 goto fail; 1138 1139 etna_fence_screen_init(pscreen); 1140 etna_query_screen_init(pscreen); 1141 etna_resource_screen_init(pscreen); 1142 1143 util_dynarray_init(&screen->supported_pm_queries, NULL); 1144 slab_create_parent(&screen->transfer_pool, sizeof(struct etna_transfer), 16); 1145 1146 if (screen->drm_version >= ETNA_DRM_VERSION_PERFMON) 1147 etna_pm_query_setup(screen); 1148 1149 1150 /* create dummy RT buffer, used when rendering with no color buffer */ 1151 screen->dummy_rt_reloc.bo = etna_bo_new(screen->dev, 64 * 64 * 4, 1152 DRM_ETNA_GEM_CACHE_WC); 1153 if (!screen->dummy_rt_reloc.bo) 1154 goto fail; 1155 1156 screen->dummy_rt_reloc.offset = 0; 1157 screen->dummy_rt_reloc.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE; 1158 1159 if (screen->specs.halti >= 5) { 1160 void *buf; 1161 1162 /* create an empty dummy texture descriptor */ 1163 screen->dummy_desc_reloc.bo = etna_bo_new(screen->dev, 0x100, 1164 DRM_ETNA_GEM_CACHE_WC); 1165 if (!screen->dummy_desc_reloc.bo) 1166 goto fail; 1167 1168 buf = etna_bo_map(screen->dummy_desc_reloc.bo); 1169 etna_bo_cpu_prep(screen->dummy_desc_reloc.bo, DRM_ETNA_PREP_WRITE); 1170 memset(buf, 0, 0x100); 1171 etna_bo_cpu_fini(screen->dummy_desc_reloc.bo); 1172 screen->dummy_desc_reloc.offset = 0; 1173 screen->dummy_desc_reloc.flags = ETNA_RELOC_READ; 1174 } 1175 1176 return pscreen; 1177 1178fail: 1179 etna_screen_destroy(pscreen); 1180 return NULL; 1181} 1182