1/*
2 * Copyright (c) 2012-2015 Etnaviv Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef H_ETNA_INTERNAL
25#define H_ETNA_INTERNAL
26
27#include <assert.h>
28#include <stdbool.h>
29#include <stdint.h>
30
31#include "hw/common.xml.h"
32#include "hw/common_3d.xml.h"
33#include "hw/state.xml.h"
34#include "hw/state_3d.xml.h"
35
36#include "drm/etnaviv_drmif.h"
37
38#define ETNA_NUM_INPUTS (16)
39#define ETNA_NUM_VARYINGS 16
40#define ETNA_NUM_LOD (14)
41#define ETNA_NUM_LAYERS (6)
42#define ETNA_MAX_UNIFORMS (256)
43#define ETNA_MAX_CONST_BUF 16
44#define ETNA_MAX_PIXELPIPES 2
45
46/* All RS operations must have width%16 = 0 */
47#define ETNA_RS_WIDTH_MASK (16 - 1)
48/* RS tiled operations must have height%4 = 0 */
49#define ETNA_RS_HEIGHT_MASK (3)
50/* PE render targets must be aligned to 64 bytes */
51#define ETNA_PE_ALIGNMENT (64)
52
53/* These demarcate the margin (fixp16) between the computed sizes and the
54  value sent to the chip. These have been set to the numbers used by the
55  Vivante driver on gc2000. They used to be -1 for scissor right and bottom. I
56  am not sure whether older hardware was relying on these or they were just a
57  guess. But if so, these need to be moved to the _specs structure.
58*/
59#define ETNA_SE_SCISSOR_MARGIN_RIGHT (0x1119)
60#define ETNA_SE_SCISSOR_MARGIN_BOTTOM (0x1111)
61#define ETNA_SE_CLIP_MARGIN_RIGHT (0xffff)
62#define ETNA_SE_CLIP_MARGIN_BOTTOM (0xffff)
63
64/* GPU chip 3D specs */
65struct etna_specs {
66   /* HALTI (gross architecture) level. -1 for pre-HALTI. */
67   int halti : 8;
68   /* supports SUPERTILE (64x64) tiling? */
69   unsigned can_supertile : 1;
70   /* needs z=(z+w)/2, for older GCxxx */
71   unsigned vs_need_z_div : 1;
72   /* supports trigonometric instructions */
73   unsigned has_sin_cos_sqrt : 1;
74   /* has SIGN/FLOOR/CEIL instructions */
75   unsigned has_sign_floor_ceil : 1;
76   /* can use VS_RANGE, PS_RANGE registers*/
77   unsigned has_shader_range_registers : 1;
78   /* has the new sin/cos/log functions */
79   unsigned has_new_transcendentals : 1;
80   /* has the new dp2/dpX_norm instructions, among others */
81   unsigned has_halti2_instructions : 1;
82   /* has no limit on the number of constant sources per instruction */
83   unsigned has_no_oneconst_limit : 1;
84   /* has V4_COMPRESSION */
85   unsigned v4_compression : 1;
86   /* supports single-buffer rendering with multiple pixel pipes */
87   unsigned single_buffer : 1;
88   /* has unified uniforms memory */
89   unsigned has_unified_uniforms : 1;
90   /* can load shader instructions from memory */
91   unsigned has_icache : 1;
92   /* ASTC texture support (and has associated states) */
93   unsigned tex_astc : 1;
94   /* has BLT engine instead of RS */
95   unsigned use_blt : 1;
96   /* can use any kind of wrapping mode on npot textures */
97   unsigned npot_tex_any_wrap : 1;
98   /* supports seamless cube map */
99   unsigned seamless_cube_map : 1;
100   /* number of bits per TS tile */
101   unsigned bits_per_tile;
102   /* clear value for TS (dependent on bits_per_tile) */
103   uint32_t ts_clear_value;
104   /* base of vertex texture units */
105   unsigned vertex_sampler_offset;
106   /* number of fragment sampler units */
107   unsigned fragment_sampler_count;
108   /* number of vertex sampler units */
109   unsigned vertex_sampler_count;
110   /* size of vertex shader output buffer */
111   unsigned vertex_output_buffer_size;
112   /* maximum number of vertex element configurations */
113   unsigned vertex_max_elements;
114   /* size of a cached vertex (?) */
115   unsigned vertex_cache_size;
116   /* number of shader cores */
117   unsigned shader_core_count;
118   /* number of vertex streams */
119   unsigned stream_count;
120   /* vertex shader memory address*/
121   uint32_t vs_offset;
122   /* pixel shader memory address*/
123   uint32_t ps_offset;
124   /* vertex shader uniforms address*/
125   uint32_t vs_uniforms_offset;
126   /* pixel shader uniforms address*/
127   uint32_t ps_uniforms_offset;
128   /* vertex/fragment shader max instructions */
129   uint32_t max_instructions;
130   /* maximum number of varyings */
131   unsigned max_varyings;
132   /* maximum number of registers */
133   unsigned max_registers;
134   /* maximum vertex uniforms */
135   unsigned max_vs_uniforms;
136   /* maximum pixel uniforms */
137   unsigned max_ps_uniforms;
138   /* maximum texture size */
139   unsigned max_texture_size;
140   /* maximum texture size */
141   unsigned max_rendertarget_size;
142   /* available pixel pipes */
143   unsigned pixel_pipes;
144   /* number of constants */
145   unsigned num_constants;
146};
147
148/* Compiled Gallium state. All the different compiled state atoms are woven
149 * together and uploaded only when it is necessary to synchronize the state,
150 * for example before rendering. */
151
152/* Compiled pipe_blend_color */
153struct compiled_blend_color {
154   float color[4];
155   uint32_t PE_ALPHA_BLEND_COLOR;
156   uint32_t PE_ALPHA_COLOR_EXT0;
157   uint32_t PE_ALPHA_COLOR_EXT1;
158};
159
160/* Compiled pipe_stencil_ref */
161struct compiled_stencil_ref {
162   uint32_t PE_STENCIL_CONFIG[2];
163   uint32_t PE_STENCIL_CONFIG_EXT[2];
164};
165
166/* Compiled pipe_viewport_state */
167struct compiled_viewport_state {
168   uint32_t PA_VIEWPORT_SCALE_X;
169   uint32_t PA_VIEWPORT_SCALE_Y;
170   uint32_t PA_VIEWPORT_SCALE_Z;
171   uint32_t PA_VIEWPORT_OFFSET_X;
172   uint32_t PA_VIEWPORT_OFFSET_Y;
173   uint32_t PA_VIEWPORT_OFFSET_Z;
174   uint32_t SE_SCISSOR_LEFT;
175   uint32_t SE_SCISSOR_TOP;
176   uint32_t SE_SCISSOR_RIGHT;
177   uint32_t SE_SCISSOR_BOTTOM;
178   uint32_t PE_DEPTH_NEAR;
179   uint32_t PE_DEPTH_FAR;
180};
181
182/* Compiled pipe_framebuffer_state */
183struct compiled_framebuffer_state {
184   uint32_t GL_MULTI_SAMPLE_CONFIG;
185   uint32_t PE_COLOR_FORMAT;
186   uint32_t PE_DEPTH_CONFIG;
187   struct etna_reloc PE_DEPTH_ADDR;
188   struct etna_reloc PE_PIPE_DEPTH_ADDR[ETNA_MAX_PIXELPIPES];
189   uint32_t PE_DEPTH_STRIDE;
190   uint32_t PE_HDEPTH_CONTROL;
191   uint32_t PE_DEPTH_NORMALIZE;
192   struct etna_reloc PE_COLOR_ADDR;
193   struct etna_reloc PE_PIPE_COLOR_ADDR[ETNA_MAX_PIXELPIPES];
194   uint32_t PE_COLOR_STRIDE;
195   uint32_t PE_MEM_CONFIG;
196   uint32_t RA_MULTISAMPLE_UNK00E04;
197   uint32_t RA_MULTISAMPLE_UNK00E10[VIVS_RA_MULTISAMPLE_UNK00E10__LEN];
198   uint32_t RA_CENTROID_TABLE[VIVS_RA_CENTROID_TABLE__LEN];
199   uint32_t TS_MEM_CONFIG;
200   uint32_t TS_DEPTH_CLEAR_VALUE;
201   struct etna_reloc TS_DEPTH_STATUS_BASE;
202   struct etna_reloc TS_DEPTH_SURFACE_BASE;
203   uint32_t TS_COLOR_CLEAR_VALUE;
204   uint32_t TS_COLOR_CLEAR_VALUE_EXT;
205   struct etna_reloc TS_COLOR_STATUS_BASE;
206   struct etna_reloc TS_COLOR_SURFACE_BASE;
207   uint32_t PE_LOGIC_OP;
208   uint32_t PS_CONTROL;
209   uint32_t PS_CONTROL_EXT;
210   bool msaa_mode; /* adds input (and possible temp) to PS */
211};
212
213/* Compiled context->create_vertex_elements_state */
214struct compiled_vertex_elements_state {
215   unsigned num_elements;
216   uint32_t FE_VERTEX_ELEMENT_CONFIG[VIVS_FE_VERTEX_ELEMENT_CONFIG__LEN];
217   uint32_t NFE_GENERIC_ATTRIB_CONFIG0[VIVS_NFE_GENERIC_ATTRIB__LEN];
218   uint32_t NFE_GENERIC_ATTRIB_SCALE[VIVS_NFE_GENERIC_ATTRIB__LEN];
219   uint32_t NFE_GENERIC_ATTRIB_CONFIG1[VIVS_NFE_GENERIC_ATTRIB__LEN];
220   unsigned num_buffers;
221   uint32_t NFE_VERTEX_STREAMS_VERTEX_DIVISOR[VIVS_NFE_VERTEX_STREAMS__LEN];
222};
223
224/* Compiled context->set_vertex_buffer result */
225struct compiled_set_vertex_buffer {
226   uint32_t FE_VERTEX_STREAM_CONTROL;
227   struct etna_reloc FE_VERTEX_STREAM_BASE_ADDR;
228};
229
230/* Compiled linked VS+PS shader state */
231struct compiled_shader_state {
232   uint32_t RA_CONTROL;
233   uint32_t PA_ATTRIBUTE_ELEMENT_COUNT;
234   uint32_t PA_CONFIG;
235   uint32_t PA_SHADER_ATTRIBUTES[VIVS_PA_SHADER_ATTRIBUTES__LEN];
236   uint32_t VS_END_PC;
237   uint32_t VS_OUTPUT_COUNT; /* number of outputs if point size per vertex disabled */
238   uint32_t VS_OUTPUT_COUNT_PSIZE; /* number of outputs of point size per vertex enabled */
239   uint32_t VS_INPUT_COUNT;
240   uint32_t VS_TEMP_REGISTER_CONTROL;
241   uint32_t VS_OUTPUT[4];
242   uint32_t VS_INPUT[4];
243   uint32_t VS_LOAD_BALANCING;
244   uint32_t VS_START_PC;
245   uint32_t PS_END_PC;
246   uint32_t PS_OUTPUT_REG;
247   uint32_t PS_INPUT_COUNT;
248   uint32_t PS_INPUT_COUNT_MSAA; /* Adds an input */
249   uint32_t PS_TEMP_REGISTER_CONTROL;
250   uint32_t PS_TEMP_REGISTER_CONTROL_MSAA; /* Adds a temporary if needed to make space for extra input */
251   uint32_t PS_START_PC;
252   uint32_t GL_VARYING_TOTAL_COMPONENTS;
253   uint32_t GL_VARYING_NUM_COMPONENTS[2];
254   uint32_t GL_VARYING_COMPONENT_USE[2];
255   uint32_t GL_HALTI5_SH_SPECIALS;
256   uint32_t FE_HALTI5_ID_CONFIG;
257   unsigned vs_inst_mem_size;
258   unsigned ps_inst_mem_size;
259   uint32_t *VS_INST_MEM;
260   uint32_t *PS_INST_MEM;
261   struct etna_reloc PS_INST_ADDR;
262   struct etna_reloc VS_INST_ADDR;
263   unsigned writes_z:1;
264   unsigned uses_discard:1;
265};
266
267/* Helpers to assist creating and setting bitarrays (eg, for varyings).
268 * field_size must be a power of two, and <= 32. */
269#define DEFINE_ETNA_BITARRAY(name, num, field_size) \
270   uint32_t name[(num) * (field_size) / 32]
271
272static inline void
273etna_bitarray_set(uint32_t *array, size_t array_size, size_t field_size,
274                  size_t index, uint32_t value)
275{
276   size_t shift = (index * field_size) % 32;
277   size_t offset = (index * field_size) / 32;
278
279   assert(index < array_size * 32 / field_size);
280   assert(value < 1 << field_size);
281
282   array[offset] |= value << shift;
283}
284
285#define etna_bitarray_set(array, field_size, index, value) \
286   etna_bitarray_set((array), ARRAY_SIZE(array), field_size, index, value)
287
288#endif
289