1/* 2 * Copyright © 2019 Google LLC 3 * SPDX-License-Identifier: MIT 4 */ 5 6#include "tu_shader.h" 7 8#include "spirv/nir_spirv.h" 9#include "util/mesa-sha1.h" 10#include "nir/nir_xfb_info.h" 11#include "nir/nir_vulkan.h" 12#include "vk_util.h" 13 14#include "ir3/ir3_nir.h" 15 16#include "tu_device.h" 17#include "tu_descriptor_set.h" 18#include "tu_pipeline.h" 19 20nir_shader * 21tu_spirv_to_nir(struct tu_device *dev, 22 void *mem_ctx, 23 const VkPipelineShaderStageCreateInfo *stage_info, 24 gl_shader_stage stage) 25{ 26 /* TODO these are made-up */ 27 const struct spirv_to_nir_options spirv_options = { 28 .ubo_addr_format = nir_address_format_vec2_index_32bit_offset, 29 .ssbo_addr_format = nir_address_format_vec2_index_32bit_offset, 30 31 /* Accessed via stg/ldg */ 32 .phys_ssbo_addr_format = nir_address_format_64bit_global, 33 34 /* Accessed via the const register file */ 35 .push_const_addr_format = nir_address_format_logical, 36 37 /* Accessed via ldl/stl */ 38 .shared_addr_format = nir_address_format_32bit_offset, 39 40 /* Accessed via stg/ldg (not used with Vulkan?) */ 41 .global_addr_format = nir_address_format_64bit_global, 42 43 /* Use 16-bit math for RelaxedPrecision ALU ops */ 44 .mediump_16bit_alu = true, 45 46 /* ViewID is a sysval in geometry stages and an input in the FS */ 47 .view_index_is_input = stage == MESA_SHADER_FRAGMENT, 48 .caps = { 49 .transform_feedback = true, 50 .tessellation = true, 51 .draw_parameters = true, 52 .image_read_without_format = true, 53 .image_write_without_format = true, 54 .variable_pointers = true, 55 .stencil_export = true, 56 .multiview = true, 57 .shader_viewport_index_layer = true, 58 .geometry_streams = true, 59 .device_group = true, 60 .descriptor_indexing = true, 61 .descriptor_array_dynamic_indexing = true, 62 .descriptor_array_non_uniform_indexing = true, 63 .runtime_descriptor_array = true, 64 .float_controls = true, 65 .float16 = true, 66 .int16 = true, 67 .storage_16bit = dev->physical_device->info->a6xx.storage_16bit, 68 .demote_to_helper_invocation = true, 69 .vk_memory_model = true, 70 .vk_memory_model_device_scope = true, 71 .subgroup_basic = true, 72 .subgroup_ballot = true, 73 .subgroup_vote = true, 74 .subgroup_quad = true, 75 .subgroup_shuffle = true, 76 .subgroup_arithmetic = true, 77 .physical_storage_buffer_address = true, 78 }, 79 }; 80 81 const nir_shader_compiler_options *nir_options = 82 ir3_get_compiler_options(dev->compiler); 83 84 struct vk_shader_module *module = 85 vk_shader_module_from_handle(stage_info->module); 86 87 nir_shader *nir; 88 VkResult result = vk_shader_module_to_nir(&dev->vk, module, 89 stage, stage_info->pName, 90 stage_info->pSpecializationInfo, 91 &spirv_options, nir_options, 92 mem_ctx, &nir); 93 if (result != VK_SUCCESS) 94 return NULL; 95 96 if (unlikely(dev->physical_device->instance->debug_flags & TU_DEBUG_NIR)) { 97 fprintf(stderr, "translated nir:\n"); 98 nir_print_shader(nir, stderr); 99 } 100 101 const struct nir_lower_sysvals_to_varyings_options sysvals_to_varyings = { 102 .point_coord = true, 103 }; 104 NIR_PASS_V(nir, nir_lower_sysvals_to_varyings, &sysvals_to_varyings); 105 106 NIR_PASS_V(nir, nir_lower_global_vars_to_local); 107 NIR_PASS_V(nir, nir_split_var_copies); 108 NIR_PASS_V(nir, nir_lower_var_copies); 109 110 NIR_PASS_V(nir, nir_opt_copy_prop_vars); 111 NIR_PASS_V(nir, nir_opt_combine_stores, nir_var_all); 112 113 NIR_PASS_V(nir, nir_lower_is_helper_invocation); 114 115 NIR_PASS_V(nir, nir_lower_system_values); 116 117 NIR_PASS_V(nir, nir_lower_frexp); 118 119 ir3_optimize_loop(dev->compiler, nir); 120 121 NIR_PASS_V(nir, nir_opt_conditional_discard); 122 123 return nir; 124} 125 126static void 127lower_load_push_constant(struct tu_device *dev, 128 nir_builder *b, 129 nir_intrinsic_instr *instr, 130 struct tu_shader *shader, 131 const struct tu_pipeline_layout *layout) 132{ 133 uint32_t base = nir_intrinsic_base(instr); 134 assert(base % 4 == 0); 135 136 if (tu6_shared_constants_enable(layout, dev->compiler)) { 137 /* All stages share the same range. We could potentially add 138 * push_constant_offset to layout and apply it, but this is good for 139 * now. 140 */ 141 base += dev->compiler->shared_consts_base_offset * 4; 142 } else { 143 assert(base >= shader->push_consts.lo * 4); 144 base -= shader->push_consts.lo * 4; 145 } 146 147 nir_ssa_def *load = 148 nir_load_uniform(b, instr->num_components, 149 instr->dest.ssa.bit_size, 150 nir_ushr(b, instr->src[0].ssa, nir_imm_int(b, 2)), 151 .base = base); 152 153 nir_ssa_def_rewrite_uses(&instr->dest.ssa, load); 154 155 nir_instr_remove(&instr->instr); 156} 157 158static void 159lower_vulkan_resource_index(nir_builder *b, nir_intrinsic_instr *instr, 160 struct tu_shader *shader, 161 const struct tu_pipeline_layout *layout) 162{ 163 nir_ssa_def *vulkan_idx = instr->src[0].ssa; 164 165 unsigned set = nir_intrinsic_desc_set(instr); 166 unsigned binding = nir_intrinsic_binding(instr); 167 struct tu_descriptor_set_layout *set_layout = layout->set[set].layout; 168 struct tu_descriptor_set_binding_layout *binding_layout = 169 &set_layout->binding[binding]; 170 uint32_t base; 171 172 shader->active_desc_sets |= 1u << set; 173 174 switch (binding_layout->type) { 175 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC: 176 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC: 177 base = (layout->set[set].dynamic_offset_start + 178 binding_layout->dynamic_offset_offset) / (4 * A6XX_TEX_CONST_DWORDS); 179 set = MAX_SETS; 180 break; 181 default: 182 base = binding_layout->offset / (4 * A6XX_TEX_CONST_DWORDS); 183 break; 184 } 185 186 unsigned stride = binding_layout->size / (4 * A6XX_TEX_CONST_DWORDS); 187 assert(util_is_power_of_two_nonzero(stride)); 188 nir_ssa_def *shift = nir_imm_int(b, util_logbase2(stride)); 189 nir_ssa_def *def = nir_vec3(b, nir_imm_int(b, set), 190 nir_iadd(b, nir_imm_int(b, base), 191 nir_ishl(b, vulkan_idx, shift)), 192 shift); 193 194 nir_ssa_def_rewrite_uses(&instr->dest.ssa, def); 195 nir_instr_remove(&instr->instr); 196} 197 198static void 199lower_vulkan_resource_reindex(nir_builder *b, nir_intrinsic_instr *instr) 200{ 201 nir_ssa_def *old_index = instr->src[0].ssa; 202 nir_ssa_def *delta = instr->src[1].ssa; 203 nir_ssa_def *shift = nir_channel(b, old_index, 2); 204 205 nir_ssa_def *new_index = 206 nir_vec3(b, nir_channel(b, old_index, 0), 207 nir_iadd(b, nir_channel(b, old_index, 1), 208 nir_ishl(b, delta, shift)), 209 shift); 210 211 nir_ssa_def_rewrite_uses(&instr->dest.ssa, new_index); 212 nir_instr_remove(&instr->instr); 213} 214 215static void 216lower_load_vulkan_descriptor(nir_builder *b, nir_intrinsic_instr *intrin) 217{ 218 nir_ssa_def *old_index = intrin->src[0].ssa; 219 /* Loading the descriptor happens as part of the load/store instruction so 220 * this is a no-op. We just need to turn the shift into an offset of 0. 221 */ 222 nir_ssa_def *new_index = 223 nir_vec3(b, nir_channel(b, old_index, 0), 224 nir_channel(b, old_index, 1), 225 nir_imm_int(b, 0)); 226 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, new_index); 227 nir_instr_remove(&intrin->instr); 228} 229 230static void 231lower_ssbo_ubo_intrinsic(struct tu_device *dev, 232 nir_builder *b, nir_intrinsic_instr *intrin) 233{ 234 const nir_intrinsic_info *info = &nir_intrinsic_infos[intrin->intrinsic]; 235 236 /* The bindless base is part of the instruction, which means that part of 237 * the "pointer" has to be constant. We solve this in the same way the blob 238 * does, by generating a bunch of if-statements. In the usual case where 239 * the descriptor set is constant we can skip that, though). 240 */ 241 242 unsigned buffer_src; 243 if (intrin->intrinsic == nir_intrinsic_store_ssbo) { 244 /* This has the value first */ 245 buffer_src = 1; 246 } else { 247 buffer_src = 0; 248 } 249 250 nir_ssa_scalar scalar_idx = nir_ssa_scalar_resolved(intrin->src[buffer_src].ssa, 0); 251 nir_ssa_def *descriptor_idx = nir_channel(b, intrin->src[buffer_src].ssa, 1); 252 253 /* For isam, we need to use the appropriate descriptor if 16-bit storage is 254 * enabled. Descriptor 0 is the 16-bit one, descriptor 1 is the 32-bit one. 255 */ 256 if (dev->physical_device->info->a6xx.storage_16bit && 257 intrin->intrinsic == nir_intrinsic_load_ssbo && 258 (nir_intrinsic_access(intrin) & ACCESS_CAN_REORDER) && 259 intrin->dest.ssa.bit_size > 16) { 260 descriptor_idx = nir_iadd(b, descriptor_idx, nir_imm_int(b, 1)); 261 } 262 263 nir_ssa_def *results[MAX_SETS + 1] = { NULL }; 264 265 if (nir_ssa_scalar_is_const(scalar_idx)) { 266 nir_ssa_def *bindless = 267 nir_bindless_resource_ir3(b, 32, descriptor_idx, .desc_set = nir_ssa_scalar_as_uint(scalar_idx)); 268 nir_instr_rewrite_src_ssa(&intrin->instr, &intrin->src[buffer_src], bindless); 269 return; 270 } 271 272 nir_ssa_def *base_idx = nir_channel(b, scalar_idx.def, scalar_idx.comp); 273 for (unsigned i = 0; i < MAX_SETS + 1; i++) { 274 /* if (base_idx == i) { ... */ 275 nir_if *nif = nir_push_if(b, nir_ieq_imm(b, base_idx, i)); 276 277 nir_ssa_def *bindless = 278 nir_bindless_resource_ir3(b, 32, descriptor_idx, .desc_set = i); 279 280 nir_intrinsic_instr *copy = 281 nir_intrinsic_instr_create(b->shader, intrin->intrinsic); 282 283 copy->num_components = intrin->num_components; 284 285 for (unsigned src = 0; src < info->num_srcs; src++) { 286 if (src == buffer_src) 287 copy->src[src] = nir_src_for_ssa(bindless); 288 else 289 copy->src[src] = nir_src_for_ssa(intrin->src[src].ssa); 290 } 291 292 for (unsigned idx = 0; idx < info->num_indices; idx++) { 293 copy->const_index[idx] = intrin->const_index[idx]; 294 } 295 296 if (info->has_dest) { 297 nir_ssa_dest_init(©->instr, ©->dest, 298 intrin->dest.ssa.num_components, 299 intrin->dest.ssa.bit_size, 300 NULL); 301 results[i] = ©->dest.ssa; 302 } 303 304 nir_builder_instr_insert(b, ©->instr); 305 306 /* } else { ... */ 307 nir_push_else(b, nif); 308 } 309 310 nir_ssa_def *result = 311 nir_ssa_undef(b, intrin->dest.ssa.num_components, intrin->dest.ssa.bit_size); 312 for (int i = MAX_SETS; i >= 0; i--) { 313 nir_pop_if(b, NULL); 314 if (info->has_dest) 315 result = nir_if_phi(b, results[i], result); 316 } 317 318 if (info->has_dest) 319 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, result); 320 nir_instr_remove(&intrin->instr); 321} 322 323static nir_ssa_def * 324build_bindless(struct tu_device *dev, nir_builder *b, 325 nir_deref_instr *deref, bool is_sampler, 326 struct tu_shader *shader, 327 const struct tu_pipeline_layout *layout) 328{ 329 nir_variable *var = nir_deref_instr_get_variable(deref); 330 331 unsigned set = var->data.descriptor_set; 332 unsigned binding = var->data.binding; 333 const struct tu_descriptor_set_binding_layout *bind_layout = 334 &layout->set[set].layout->binding[binding]; 335 336 /* input attachments use non bindless workaround */ 337 if (bind_layout->type == VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT && 338 likely(!(dev->instance->debug_flags & TU_DEBUG_DYNAMIC))) { 339 const struct glsl_type *glsl_type = glsl_without_array(var->type); 340 uint32_t idx = var->data.index * 2; 341 342 BITSET_SET_RANGE_INSIDE_WORD(b->shader->info.textures_used, idx * 2, ((idx * 2) + (bind_layout->array_size * 2)) - 1); 343 344 /* D24S8 workaround: stencil of D24S8 will be sampled as uint */ 345 if (glsl_get_sampler_result_type(glsl_type) == GLSL_TYPE_UINT) 346 idx += 1; 347 348 if (deref->deref_type == nir_deref_type_var) 349 return nir_imm_int(b, idx); 350 351 nir_ssa_def *arr_index = nir_ssa_for_src(b, deref->arr.index, 1); 352 return nir_iadd(b, nir_imm_int(b, idx), 353 nir_imul_imm(b, arr_index, 2)); 354 } 355 356 shader->active_desc_sets |= 1u << set; 357 358 nir_ssa_def *desc_offset; 359 unsigned descriptor_stride; 360 unsigned offset = 0; 361 /* Samplers come second in combined image/sampler descriptors, see 362 * write_combined_image_sampler_descriptor(). 363 */ 364 if (is_sampler && bind_layout->type == 365 VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER) { 366 offset = 1; 367 } 368 desc_offset = 369 nir_imm_int(b, (bind_layout->offset / (4 * A6XX_TEX_CONST_DWORDS)) + 370 offset); 371 descriptor_stride = bind_layout->size / (4 * A6XX_TEX_CONST_DWORDS); 372 373 if (deref->deref_type != nir_deref_type_var) { 374 assert(deref->deref_type == nir_deref_type_array); 375 376 nir_ssa_def *arr_index = nir_ssa_for_src(b, deref->arr.index, 1); 377 desc_offset = nir_iadd(b, desc_offset, 378 nir_imul_imm(b, arr_index, descriptor_stride)); 379 } 380 381 return nir_bindless_resource_ir3(b, 32, desc_offset, .desc_set = set); 382} 383 384static void 385lower_image_deref(struct tu_device *dev, nir_builder *b, 386 nir_intrinsic_instr *instr, struct tu_shader *shader, 387 const struct tu_pipeline_layout *layout) 388{ 389 nir_deref_instr *deref = nir_src_as_deref(instr->src[0]); 390 nir_ssa_def *bindless = build_bindless(dev, b, deref, false, shader, layout); 391 nir_rewrite_image_intrinsic(instr, bindless, true); 392} 393 394static bool 395lower_intrinsic(nir_builder *b, nir_intrinsic_instr *instr, 396 struct tu_device *dev, 397 struct tu_shader *shader, 398 const struct tu_pipeline_layout *layout) 399{ 400 switch (instr->intrinsic) { 401 case nir_intrinsic_load_push_constant: 402 lower_load_push_constant(dev, b, instr, shader, layout); 403 return true; 404 405 case nir_intrinsic_load_vulkan_descriptor: 406 lower_load_vulkan_descriptor(b, instr); 407 return true; 408 409 case nir_intrinsic_vulkan_resource_index: 410 lower_vulkan_resource_index(b, instr, shader, layout); 411 return true; 412 case nir_intrinsic_vulkan_resource_reindex: 413 lower_vulkan_resource_reindex(b, instr); 414 return true; 415 416 case nir_intrinsic_load_ubo: 417 case nir_intrinsic_load_ssbo: 418 case nir_intrinsic_store_ssbo: 419 case nir_intrinsic_ssbo_atomic_add: 420 case nir_intrinsic_ssbo_atomic_imin: 421 case nir_intrinsic_ssbo_atomic_umin: 422 case nir_intrinsic_ssbo_atomic_imax: 423 case nir_intrinsic_ssbo_atomic_umax: 424 case nir_intrinsic_ssbo_atomic_and: 425 case nir_intrinsic_ssbo_atomic_or: 426 case nir_intrinsic_ssbo_atomic_xor: 427 case nir_intrinsic_ssbo_atomic_exchange: 428 case nir_intrinsic_ssbo_atomic_comp_swap: 429 case nir_intrinsic_ssbo_atomic_fadd: 430 case nir_intrinsic_ssbo_atomic_fmin: 431 case nir_intrinsic_ssbo_atomic_fmax: 432 case nir_intrinsic_ssbo_atomic_fcomp_swap: 433 case nir_intrinsic_get_ssbo_size: 434 lower_ssbo_ubo_intrinsic(dev, b, instr); 435 return true; 436 437 case nir_intrinsic_image_deref_load: 438 case nir_intrinsic_image_deref_store: 439 case nir_intrinsic_image_deref_atomic_add: 440 case nir_intrinsic_image_deref_atomic_imin: 441 case nir_intrinsic_image_deref_atomic_umin: 442 case nir_intrinsic_image_deref_atomic_imax: 443 case nir_intrinsic_image_deref_atomic_umax: 444 case nir_intrinsic_image_deref_atomic_and: 445 case nir_intrinsic_image_deref_atomic_or: 446 case nir_intrinsic_image_deref_atomic_xor: 447 case nir_intrinsic_image_deref_atomic_exchange: 448 case nir_intrinsic_image_deref_atomic_comp_swap: 449 case nir_intrinsic_image_deref_size: 450 case nir_intrinsic_image_deref_samples: 451 lower_image_deref(dev, b, instr, shader, layout); 452 return true; 453 454 default: 455 return false; 456 } 457} 458 459static void 460lower_tex_ycbcr(const struct tu_pipeline_layout *layout, 461 nir_builder *builder, 462 nir_tex_instr *tex) 463{ 464 int deref_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_deref); 465 assert(deref_src_idx >= 0); 466 nir_deref_instr *deref = nir_src_as_deref(tex->src[deref_src_idx].src); 467 468 nir_variable *var = nir_deref_instr_get_variable(deref); 469 const struct tu_descriptor_set_layout *set_layout = 470 layout->set[var->data.descriptor_set].layout; 471 const struct tu_descriptor_set_binding_layout *binding = 472 &set_layout->binding[var->data.binding]; 473 const struct tu_sampler_ycbcr_conversion *ycbcr_samplers = 474 tu_immutable_ycbcr_samplers(set_layout, binding); 475 476 if (!ycbcr_samplers) 477 return; 478 479 /* For the following instructions, we don't apply any change */ 480 if (tex->op == nir_texop_txs || 481 tex->op == nir_texop_query_levels || 482 tex->op == nir_texop_lod) 483 return; 484 485 assert(tex->texture_index == 0); 486 unsigned array_index = 0; 487 if (deref->deref_type != nir_deref_type_var) { 488 assert(deref->deref_type == nir_deref_type_array); 489 if (!nir_src_is_const(deref->arr.index)) 490 return; 491 array_index = nir_src_as_uint(deref->arr.index); 492 array_index = MIN2(array_index, binding->array_size - 1); 493 } 494 const struct tu_sampler_ycbcr_conversion *ycbcr_sampler = ycbcr_samplers + array_index; 495 496 if (ycbcr_sampler->ycbcr_model == VK_SAMPLER_YCBCR_MODEL_CONVERSION_RGB_IDENTITY) 497 return; 498 499 builder->cursor = nir_after_instr(&tex->instr); 500 501 uint8_t bits = vk_format_get_component_bits(ycbcr_sampler->format, 502 UTIL_FORMAT_COLORSPACE_RGB, 503 PIPE_SWIZZLE_X); 504 505 switch (ycbcr_sampler->format) { 506 case VK_FORMAT_G8B8G8R8_422_UNORM: 507 case VK_FORMAT_B8G8R8G8_422_UNORM: 508 case VK_FORMAT_G8_B8R8_2PLANE_420_UNORM: 509 case VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM: 510 /* util_format_get_component_bits doesn't return what we want */ 511 bits = 8; 512 break; 513 default: 514 break; 515 } 516 517 uint32_t bpcs[3] = {bits, bits, bits}; /* TODO: use right bpc for each channel ? */ 518 nir_ssa_def *result = nir_convert_ycbcr_to_rgb(builder, 519 ycbcr_sampler->ycbcr_model, 520 ycbcr_sampler->ycbcr_range, 521 &tex->dest.ssa, 522 bpcs); 523 nir_ssa_def_rewrite_uses_after(&tex->dest.ssa, result, 524 result->parent_instr); 525 526 builder->cursor = nir_before_instr(&tex->instr); 527} 528 529static bool 530lower_tex(nir_builder *b, nir_tex_instr *tex, struct tu_device *dev, 531 struct tu_shader *shader, const struct tu_pipeline_layout *layout) 532{ 533 lower_tex_ycbcr(layout, b, tex); 534 535 int sampler_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_deref); 536 if (sampler_src_idx >= 0) { 537 nir_deref_instr *deref = nir_src_as_deref(tex->src[sampler_src_idx].src); 538 nir_ssa_def *bindless = build_bindless(dev, b, deref, true, shader, layout); 539 nir_instr_rewrite_src(&tex->instr, &tex->src[sampler_src_idx].src, 540 nir_src_for_ssa(bindless)); 541 tex->src[sampler_src_idx].src_type = nir_tex_src_sampler_handle; 542 } 543 544 int tex_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_deref); 545 if (tex_src_idx >= 0) { 546 nir_deref_instr *deref = nir_src_as_deref(tex->src[tex_src_idx].src); 547 nir_ssa_def *bindless = build_bindless(dev, b, deref, false, shader, layout); 548 nir_instr_rewrite_src(&tex->instr, &tex->src[tex_src_idx].src, 549 nir_src_for_ssa(bindless)); 550 tex->src[tex_src_idx].src_type = nir_tex_src_texture_handle; 551 552 /* for the input attachment case: */ 553 if (bindless->parent_instr->type != nir_instr_type_intrinsic) 554 tex->src[tex_src_idx].src_type = nir_tex_src_texture_offset; 555 } 556 557 return true; 558} 559 560struct lower_instr_params { 561 struct tu_device *dev; 562 struct tu_shader *shader; 563 const struct tu_pipeline_layout *layout; 564}; 565 566static bool 567lower_instr(nir_builder *b, nir_instr *instr, void *cb_data) 568{ 569 struct lower_instr_params *params = cb_data; 570 b->cursor = nir_before_instr(instr); 571 switch (instr->type) { 572 case nir_instr_type_tex: 573 return lower_tex(b, nir_instr_as_tex(instr), params->dev, params->shader, params->layout); 574 case nir_instr_type_intrinsic: 575 return lower_intrinsic(b, nir_instr_as_intrinsic(instr), params->dev, params->shader, params->layout); 576 default: 577 return false; 578 } 579} 580 581/* Figure out the range of push constants that we're actually going to push to 582 * the shader, and tell the backend to reserve this range when pushing UBO 583 * constants. 584 */ 585 586static void 587gather_push_constants(nir_shader *shader, struct tu_shader *tu_shader) 588{ 589 uint32_t min = UINT32_MAX, max = 0; 590 nir_foreach_function(function, shader) { 591 if (!function->impl) 592 continue; 593 594 nir_foreach_block(block, function->impl) { 595 nir_foreach_instr_safe(instr, block) { 596 if (instr->type != nir_instr_type_intrinsic) 597 continue; 598 599 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); 600 if (intrin->intrinsic != nir_intrinsic_load_push_constant) 601 continue; 602 603 uint32_t base = nir_intrinsic_base(intrin); 604 uint32_t range = nir_intrinsic_range(intrin); 605 min = MIN2(min, base); 606 max = MAX2(max, base + range); 607 break; 608 } 609 } 610 } 611 612 if (min >= max) { 613 tu_shader->push_consts.lo = 0; 614 tu_shader->push_consts.dwords = 0; 615 return; 616 } 617 618 /* CP_LOAD_STATE OFFSET and NUM_UNIT for SHARED_CONSTS are in units of 619 * dwords while loading regular consts is in units of vec4's. 620 * So we unify the unit here as dwords for tu_push_constant_range, then 621 * we should consider correct unit when emitting. 622 * 623 * Note there's an alignment requirement of 16 dwords on OFFSET. Expand 624 * the range and change units accordingly. 625 */ 626 tu_shader->push_consts.lo = (min / 4) / 4 * 4; 627 tu_shader->push_consts.dwords = 628 align(max, 16) / 4 - tu_shader->push_consts.lo; 629} 630 631static bool 632tu_lower_io(nir_shader *shader, struct tu_device *dev, 633 struct tu_shader *tu_shader, 634 const struct tu_pipeline_layout *layout) 635{ 636 if (!tu6_shared_constants_enable(layout, dev->compiler)) 637 gather_push_constants(shader, tu_shader); 638 639 struct lower_instr_params params = { 640 .dev = dev, 641 .shader = tu_shader, 642 .layout = layout, 643 }; 644 645 bool progress = nir_shader_instructions_pass(shader, 646 lower_instr, 647 nir_metadata_none, 648 ¶ms); 649 650 /* Remove now-unused variables so that when we gather the shader info later 651 * they won't be counted. 652 */ 653 654 if (progress) 655 nir_opt_dce(shader); 656 657 progress |= 658 nir_remove_dead_variables(shader, 659 nir_var_uniform | nir_var_mem_ubo | nir_var_mem_ssbo, 660 NULL); 661 662 return progress; 663} 664 665static void 666shared_type_info(const struct glsl_type *type, unsigned *size, unsigned *align) 667{ 668 assert(glsl_type_is_vector_or_scalar(type)); 669 670 unsigned comp_size = 671 glsl_type_is_boolean(type) ? 4 : glsl_get_bit_size(type) / 8; 672 unsigned length = glsl_get_vector_elements(type); 673 *size = comp_size * length; 674 *align = comp_size; 675} 676 677static void 678tu_gather_xfb_info(nir_shader *nir, struct ir3_stream_output_info *info) 679{ 680 nir_shader_gather_xfb_info(nir); 681 682 if (!nir->xfb_info) 683 return; 684 685 nir_xfb_info *xfb = nir->xfb_info; 686 687 uint8_t output_map[VARYING_SLOT_TESS_MAX]; 688 memset(output_map, 0, sizeof(output_map)); 689 690 nir_foreach_shader_out_variable(var, nir) { 691 unsigned slots = 692 var->data.compact ? DIV_ROUND_UP(glsl_get_length(var->type), 4) 693 : glsl_count_attribute_slots(var->type, false); 694 for (unsigned i = 0; i < slots; i++) 695 output_map[var->data.location + i] = var->data.driver_location + i; 696 } 697 698 assert(xfb->output_count <= IR3_MAX_SO_OUTPUTS); 699 info->num_outputs = xfb->output_count; 700 701 for (int i = 0; i < IR3_MAX_SO_BUFFERS; i++) { 702 info->stride[i] = xfb->buffers[i].stride / 4; 703 info->buffer_to_stream[i] = xfb->buffer_to_stream[i]; 704 } 705 706 info->streams_written = xfb->streams_written; 707 708 for (int i = 0; i < xfb->output_count; i++) { 709 info->output[i].register_index = output_map[xfb->outputs[i].location]; 710 info->output[i].start_component = xfb->outputs[i].component_offset; 711 info->output[i].num_components = 712 util_bitcount(xfb->outputs[i].component_mask); 713 info->output[i].output_buffer = xfb->outputs[i].buffer; 714 info->output[i].dst_offset = xfb->outputs[i].offset / 4; 715 info->output[i].stream = xfb->buffer_to_stream[xfb->outputs[i].buffer]; 716 } 717} 718 719struct tu_shader * 720tu_shader_create(struct tu_device *dev, 721 nir_shader *nir, 722 const struct tu_shader_key *key, 723 struct tu_pipeline_layout *layout, 724 const VkAllocationCallbacks *alloc) 725{ 726 struct tu_shader *shader; 727 728 shader = vk_zalloc2( 729 &dev->vk.alloc, alloc, 730 sizeof(*shader), 731 8, VK_SYSTEM_ALLOCATION_SCOPE_COMMAND); 732 if (!shader) 733 return NULL; 734 735 NIR_PASS_V(nir, nir_opt_access, &(nir_opt_access_options) { 736 .is_vulkan = true, 737 .infer_non_readable = true, 738 }); 739 740 if (nir->info.stage == MESA_SHADER_FRAGMENT) { 741 NIR_PASS_V(nir, nir_lower_input_attachments, 742 &(nir_input_attachment_options) { 743 .use_fragcoord_sysval = true, 744 .use_layer_id_sysval = false, 745 /* When using multiview rendering, we must use 746 * gl_ViewIndex as the layer id to pass to the texture 747 * sampling function. gl_Layer doesn't work when 748 * multiview is enabled. 749 */ 750 .use_view_id_for_layer = key->multiview_mask != 0, 751 }); 752 } 753 754 /* This needs to happen before multiview lowering which rewrites store 755 * instructions of the position variable, so that we can just rewrite one 756 * store at the end instead of having to rewrite every store specified by 757 * the user. 758 */ 759 ir3_nir_lower_io_to_temporaries(nir); 760 761 if (nir->info.stage == MESA_SHADER_VERTEX && key->multiview_mask) { 762 tu_nir_lower_multiview(nir, key->multiview_mask, 763 &shader->multi_pos_output, dev); 764 } 765 766 if (nir->info.stage == MESA_SHADER_FRAGMENT && key->force_sample_interp) { 767 nir_foreach_shader_in_variable(var, nir) { 768 if (!var->data.centroid) 769 var->data.sample = true; 770 } 771 } 772 773 NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_push_const, 774 nir_address_format_32bit_offset); 775 776 NIR_PASS_V(nir, nir_lower_explicit_io, 777 nir_var_mem_ubo | nir_var_mem_ssbo, 778 nir_address_format_vec2_index_32bit_offset); 779 780 NIR_PASS_V(nir, nir_lower_explicit_io, 781 nir_var_mem_global, 782 nir_address_format_64bit_global); 783 784 if (nir->info.stage == MESA_SHADER_COMPUTE) { 785 NIR_PASS_V(nir, nir_lower_vars_to_explicit_types, 786 nir_var_mem_shared, shared_type_info); 787 NIR_PASS_V(nir, nir_lower_explicit_io, 788 nir_var_mem_shared, 789 nir_address_format_32bit_offset); 790 791 if (nir->info.zero_initialize_shared_memory && nir->info.shared_size > 0) { 792 const unsigned chunk_size = 16; /* max single store size */ 793 /* Shared memory is allocated in 1024b chunks in HW, but the zero-init 794 * extension only requires us to initialize the memory that the shader 795 * is allocated at the API level, and it's up to the user to ensure 796 * that accesses are limited to those bounds. 797 */ 798 const unsigned shared_size = ALIGN(nir->info.shared_size, chunk_size); 799 NIR_PASS_V(nir, nir_zero_initialize_shared_memory, shared_size, chunk_size); 800 } 801 802 const struct nir_lower_compute_system_values_options compute_sysval_options = { 803 .has_base_workgroup_id = true, 804 }; 805 NIR_PASS_V(nir, nir_lower_compute_system_values, &compute_sysval_options); 806 } 807 808 nir_assign_io_var_locations(nir, nir_var_shader_in, &nir->num_inputs, nir->info.stage); 809 nir_assign_io_var_locations(nir, nir_var_shader_out, &nir->num_outputs, nir->info.stage); 810 811 /* Gather information for transform feedback. This should be called after: 812 * - nir_split_per_member_structs. 813 * - nir_remove_dead_variables with varyings, so that we could align 814 * stream outputs correctly. 815 * - nir_assign_io_var_locations - to have valid driver_location 816 */ 817 struct ir3_stream_output_info so_info = {}; 818 if (nir->info.stage == MESA_SHADER_VERTEX || 819 nir->info.stage == MESA_SHADER_TESS_EVAL || 820 nir->info.stage == MESA_SHADER_GEOMETRY) 821 tu_gather_xfb_info(nir, &so_info); 822 823 NIR_PASS_V(nir, tu_lower_io, dev, shader, layout); 824 825 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir)); 826 827 ir3_finalize_nir(dev->compiler, nir); 828 829 uint32_t reserved_consts_vec4 = align(shader->push_consts.dwords, 16) / 4; 830 bool shared_consts_enable = tu6_shared_constants_enable(layout, dev->compiler); 831 if (shared_consts_enable) 832 assert(!shader->push_consts.dwords); 833 834 shader->ir3_shader = 835 ir3_shader_from_nir(dev->compiler, nir, &(struct ir3_shader_options) { 836 .reserved_user_consts = reserved_consts_vec4, 837 .shared_consts_enable = shared_consts_enable, 838 .api_wavesize = key->api_wavesize, 839 .real_wavesize = key->real_wavesize, 840 }, &so_info); 841 842 return shader; 843} 844 845void 846tu_shader_destroy(struct tu_device *dev, 847 struct tu_shader *shader, 848 const VkAllocationCallbacks *alloc) 849{ 850 ir3_shader_destroy(shader->ir3_shader); 851 852 vk_free2(&dev->vk.alloc, alloc, shader); 853} 854