xref: /third_party/mesa3d/src/freedreno/isa/ir3-cat4.xml

<?xml version="1.0" encoding="UTF-8"?>
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
 -->

<isa>

<!--
	Cat4 Instructions:  SFU (aka EFU) instructions
 -->

<bitset name="#instruction-cat4" extends="#instruction">
	<display>
		{SY}{SS}{JP}{SAT}{REPEAT}{UL}{NAME} {DST_HALF}{DST}, {SRC}
	</display>
	<field name="SRC" low="0" high="15" type="#multisrc">
		<param name="SRC_R"/>
		<param name="FULL"/>
	</field>
	<pattern low="16" high="31">xxxxxxxxxxxxxxxx</pattern>
	<field name="DST" low="32" high="39" type="#reg-gpr"/>
	<field name="REPEAT" low="40" high="41" type="#rptN"/>
	<field name="SAT" pos="42" type="bool" display="(sat)"/>
	<field name="SRC_R" pos="43" type="bool" display="(r)"/>
	<field name="SS" pos="44" type="bool" display="(ss)"/>
	<field name="UL" pos="45" type="bool" display="(ul)"/>
	<field name="DST_CONV" pos="46" type="bool">
		<doc>
			Destination register is opposite precision as source, ie.
			if {FULL} is true then destination is half precision, and
			visa versa.
		</doc>
	</field>
	<derived name="DST_HALF" expr="#dest-half" type="bool" display="h"/>
	<pattern low="47" high="51">xxxxx</pattern>
	<field name="FULL" pos="52" type="bool">
		<doc>Full precision source registers</doc>
	</field>
	<!-- 6b opc -->
	<field name="JP" pos="59" type="bool" display="(jp)"/>
	<field name="SY" pos="60" type="bool" display="(sy)"/>
	<pattern low="61" high="63">100</pattern>  <!-- cat4 -->
	<encode>
		<map name="SRC">src->srcs[0]</map>
		<map name="DST_CONV">
			((src->dsts[0]->num >> 2) == 62) ? 0 :
			!!((src->srcs[0]->flags ^ src->dsts[0]->flags) &amp; IR3_REG_HALF)
		</map>
		<map name="FULL">!(src->srcs[0]->flags &amp; IR3_REG_HALF)</map>
		<map name="SRC_R">!!(src->srcs[0]->flags &amp; IR3_REG_R)</map>
	</encode>
</bitset>

<bitset name="rcp" extends="#instruction-cat4">
	<pattern low="53" high="58">000000</pattern> <!-- OPC -->
</bitset>

<bitset name="rsq" extends="#instruction-cat4">
	<pattern low="53" high="58">000001</pattern> <!-- OPC -->
</bitset>

<bitset name="log2" extends="#instruction-cat4">
	<pattern low="53" high="58">000010</pattern> <!-- OPC -->
</bitset>

<bitset name="exp2" extends="#instruction-cat4">
	<pattern low="53" high="58">000011</pattern> <!-- OPC -->
</bitset>

<bitset name="sin" extends="#instruction-cat4">
	<pattern low="53" high="58">000100</pattern> <!-- OPC -->
</bitset>

<bitset name="cos" extends="#instruction-cat4">
	<pattern low="53" high="58">000101</pattern> <!-- OPC -->
</bitset>

<bitset name="sqrt" extends="#instruction-cat4">
	<pattern low="53" high="58">000110</pattern> <!-- OPC -->
</bitset>

<!--
	NOTE that these are 8+opc from their highp equivs, so it's possible
	that the high order bit in the opc field has been repurposed for
	half-precision use?  But note that other ops (rcp/lsin/cos/sqrt)
	still use the same opc as highp
 -->

<bitset name="hrsq" extends="#instruction-cat4">
	<pattern low="53" high="58">001001</pattern> <!-- OPC -->
</bitset>

<bitset name="hlog2" extends="#instruction-cat4">
	<pattern low="53" high="58">001010</pattern> <!-- OPC -->
</bitset>

<bitset name="hexp2" extends="#instruction-cat4">
	<pattern low="53" high="58">001011</pattern> <!-- OPC -->
</bitset>

</isa>