1/* 2 * Copyright © 2016-2018 Broadcom 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24#include "v3d_compiler.h" 25 26/* We don't do any address packing. */ 27#define __gen_user_data void 28#define __gen_address_type uint32_t 29#define __gen_address_offset(reloc) (*reloc) 30#define __gen_emit_reloc(cl, reloc) 31#include "cle/v3d_packet_v33_pack.h" 32 33void 34v3d33_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr) 35{ 36 /* FIXME: We don't bother implementing pipelining for texture reads 37 * for any pre 4.x hardware. It should be straight forward to do but 38 * we are not really testing or even targetting this hardware at 39 * present. 40 */ 41 ntq_flush_tmu(c); 42 43 unsigned unit = instr->texture_index; 44 45 struct V3D33_TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1 p0_unpacked = { 46 V3D33_TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1_header, 47 48 .fetch_sample_mode = instr->op == nir_texop_txf, 49 }; 50 51 struct V3D33_TEXTURE_UNIFORM_PARAMETER_1_CFG_MODE1 p1_unpacked = { 52 }; 53 54 switch (instr->sampler_dim) { 55 case GLSL_SAMPLER_DIM_1D: 56 if (instr->is_array) 57 p0_unpacked.lookup_type = TEXTURE_1D_ARRAY; 58 else 59 p0_unpacked.lookup_type = TEXTURE_1D; 60 break; 61 case GLSL_SAMPLER_DIM_2D: 62 case GLSL_SAMPLER_DIM_RECT: 63 if (instr->is_array) 64 p0_unpacked.lookup_type = TEXTURE_2D_ARRAY; 65 else 66 p0_unpacked.lookup_type = TEXTURE_2D; 67 break; 68 case GLSL_SAMPLER_DIM_3D: 69 p0_unpacked.lookup_type = TEXTURE_3D; 70 break; 71 case GLSL_SAMPLER_DIM_CUBE: 72 p0_unpacked.lookup_type = TEXTURE_CUBE_MAP; 73 break; 74 default: 75 unreachable("Bad sampler type"); 76 } 77 78 struct qreg coords[5]; 79 int next_coord = 0; 80 for (unsigned i = 0; i < instr->num_srcs; i++) { 81 switch (instr->src[i].src_type) { 82 case nir_tex_src_coord: 83 for (int j = 0; j < instr->coord_components; j++) { 84 coords[next_coord++] = 85 ntq_get_src(c, instr->src[i].src, j); 86 } 87 if (instr->coord_components < 2) 88 coords[next_coord++] = vir_uniform_f(c, 0.5); 89 break; 90 case nir_tex_src_bias: 91 coords[next_coord++] = 92 ntq_get_src(c, instr->src[i].src, 0); 93 94 p0_unpacked.bias_supplied = true; 95 break; 96 case nir_tex_src_lod: 97 coords[next_coord++] = 98 vir_FADD(c, 99 ntq_get_src(c, instr->src[i].src, 0), 100 vir_uniform(c, QUNIFORM_TEXTURE_FIRST_LEVEL, 101 unit)); 102 103 if (instr->op != nir_texop_txf && 104 instr->op != nir_texop_tg4) { 105 p0_unpacked.disable_autolod_use_bias_only = true; 106 } 107 break; 108 case nir_tex_src_comparator: 109 coords[next_coord++] = 110 ntq_get_src(c, instr->src[i].src, 0); 111 112 p0_unpacked.shadow = true; 113 break; 114 115 case nir_tex_src_offset: { 116 p0_unpacked.texel_offset_for_s_coordinate = 117 nir_src_comp_as_int(instr->src[i].src, 0); 118 119 if (instr->coord_components >= 2) 120 p0_unpacked.texel_offset_for_t_coordinate = 121 nir_src_comp_as_int(instr->src[i].src, 1); 122 123 if (instr->coord_components >= 3) 124 p0_unpacked.texel_offset_for_r_coordinate = 125 nir_src_comp_as_int(instr->src[i].src, 2); 126 break; 127 } 128 129 default: 130 unreachable("unknown texture source"); 131 } 132 } 133 134 /* Limit the number of channels returned to both how many the NIR 135 * instruction writes and how many the instruction could produce. 136 */ 137 p1_unpacked.return_words_of_texture_data = 138 instr->dest.is_ssa ? 139 nir_ssa_def_components_read(&instr->dest.ssa) : 140 (1 << instr->dest.reg.reg->num_components) - 1; 141 142 uint32_t p0_packed; 143 V3D33_TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1_pack(NULL, 144 (uint8_t *)&p0_packed, 145 &p0_unpacked); 146 147 uint32_t p1_packed; 148 V3D33_TEXTURE_UNIFORM_PARAMETER_1_CFG_MODE1_pack(NULL, 149 (uint8_t *)&p1_packed, 150 &p1_unpacked); 151 /* Load unit number into the address field, which will be be used by 152 * the driver to decide which texture to put in the actual address 153 * field. 154 */ 155 p1_packed |= unit << 5; 156 157 /* There is no native support for GL texture rectangle coordinates, so 158 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0, 159 * 1]). 160 */ 161 if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) { 162 coords[0] = vir_FMUL(c, coords[0], 163 vir_uniform(c, QUNIFORM_TEXRECT_SCALE_X, 164 unit)); 165 coords[1] = vir_FMUL(c, coords[1], 166 vir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y, 167 unit)); 168 } 169 170 int texture_u[] = { 171 vir_get_uniform_index(c, QUNIFORM_TEXTURE_CONFIG_P0_0 + unit, p0_packed), 172 vir_get_uniform_index(c, QUNIFORM_TEXTURE_CONFIG_P1, p1_packed), 173 }; 174 175 for (int i = 0; i < next_coord; i++) { 176 struct qreg dst; 177 178 if (i == next_coord - 1) 179 dst = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUL); 180 else 181 dst = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMU); 182 183 struct qinst *tmu = vir_MOV_dest(c, dst, coords[i]); 184 185 if (i < 2) 186 tmu->uniform = texture_u[i]; 187 } 188 189 vir_emit_thrsw(c); 190 191 for (int i = 0; i < 4; i++) { 192 if (p1_unpacked.return_words_of_texture_data & (1 << i)) 193 ntq_store_dest(c, &instr->dest, i, vir_LDTMU(c)); 194 } 195} 196