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367    {"name": "IMG_NUM_FORMAT_SSCALED", "value": 3},
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371    {"name": "IMG_NUM_FORMAT_FLOAT", "value": 7},
372    {"name": "IMG_NUM_FORMAT_RESERVED_8", "value": 8},
373    {"name": "IMG_NUM_FORMAT_SRGB", "value": 9},
374    {"name": "IMG_NUM_FORMAT_RESERVED_10", "value": 10},
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377    {"name": "IMG_NUM_FORMAT_RESERVED_13", "value": 13},
378    {"name": "IMG_NUM_FORMAT_RESERVED_14", "value": 14},
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382  "MacroTileAspect": {
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385    {"name": "ADDR_SURF_MACRO_ASPECT_2", "value": 1},
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387    {"name": "ADDR_SURF_MACRO_ASPECT_8", "value": 3}
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389  },
390  "MicroTileMode": {
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393    {"name": "ADDR_SURF_THIN_MICRO_TILING", "value": 1},
394    {"name": "ADDR_SURF_DEPTH_MICRO_TILING", "value": 2},
395    {"name": "ADDR_SURF_ROTATED_MICRO_TILING", "value": 3},
396    {"name": "ADDR_SURF_THICK_MICRO_TILING", "value": 4}
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399  "NumBanks": {
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402    {"name": "ADDR_SURF_4_BANK", "value": 1},
403    {"name": "ADDR_SURF_8_BANK", "value": 2},
404    {"name": "ADDR_SURF_16_BANK", "value": 3}
405   ]
406  },
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410    {"name": "X_DRAW_LINES", "value": 1},
411    {"name": "X_DRAW_TRIANGLES", "value": 2}
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413  },
414  "PA_SU_SC_MODE_CNTL__POLY_MODE": {
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424    {"name": "X_ROUND_TO_EVEN", "value": 2},
425    {"name": "X_ROUND_TO_ODD", "value": 3}
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427  },
428  "PipeConfig": {
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431    {"name": "ADDR_SURF_P2_RESERVED0", "value": 1},
432    {"name": "ADDR_SURF_P2_RESERVED1", "value": 2},
433    {"name": "ADDR_SURF_P2_RESERVED2", "value": 3},
434    {"name": "ADDR_SURF_P4_8x16", "value": 4},
435    {"name": "ADDR_SURF_P4_16x16", "value": 5},
436    {"name": "ADDR_SURF_P4_16x32", "value": 6},
437    {"name": "ADDR_SURF_P4_32x32", "value": 7},
438    {"name": "ADDR_SURF_P8_16x16_8x16", "value": 8},
439    {"name": "ADDR_SURF_P8_16x32_8x16", "value": 9},
440    {"name": "ADDR_SURF_P8_32x32_8x16", "value": 10},
441    {"name": "ADDR_SURF_P8_16x32_16x16", "value": 11},
442    {"name": "ADDR_SURF_P8_32x32_16x16", "value": 12},
443    {"name": "ADDR_SURF_P8_32x32_16x32", "value": 13},
444    {"name": "ADDR_SURF_P8_32x64_32x32", "value": 14},
445    {"name": "ADDR_SURF_P8_RESERVED0", "value": 15},
446    {"name": "ADDR_SURF_P16_32x32_8x16", "value": 16},
447    {"name": "ADDR_SURF_P16_32x32_16x16", "value": 17}
448   ]
449  },
450  "PkrMap": {
451   "entries": [
452    {"name": "RASTER_CONFIG_PKR_MAP_0", "value": 0},
453    {"name": "RASTER_CONFIG_PKR_MAP_1", "value": 1},
454    {"name": "RASTER_CONFIG_PKR_MAP_2", "value": 2},
455    {"name": "RASTER_CONFIG_PKR_MAP_3", "value": 3}
456   ]
457  },
458  "PkrXsel": {
459   "entries": [
460    {"name": "RASTER_CONFIG_PKR_XSEL_0", "value": 0},
461    {"name": "RASTER_CONFIG_PKR_XSEL_1", "value": 1},
462    {"name": "RASTER_CONFIG_PKR_XSEL_2", "value": 2},
463    {"name": "RASTER_CONFIG_PKR_XSEL_3", "value": 3}
464   ]
465  },
466  "PkrXsel2": {
467   "entries": [
468    {"name": "RASTER_CONFIG_PKR_XSEL2_0", "value": 0},
469    {"name": "RASTER_CONFIG_PKR_XSEL2_1", "value": 1},
470    {"name": "RASTER_CONFIG_PKR_XSEL2_2", "value": 2},
471    {"name": "RASTER_CONFIG_PKR_XSEL2_3", "value": 3}
472   ]
473  },
474  "PkrYsel": {
475   "entries": [
476    {"name": "RASTER_CONFIG_PKR_YSEL_0", "value": 0},
477    {"name": "RASTER_CONFIG_PKR_YSEL_1", "value": 1},
478    {"name": "RASTER_CONFIG_PKR_YSEL_2", "value": 2},
479    {"name": "RASTER_CONFIG_PKR_YSEL_3", "value": 3}
480   ]
481  },
482  "QUANT_MODE": {
483   "entries": [
484    {"name": "X_16_8_FIXED_POINT_1_16TH", "value": 0},
485    {"name": "X_16_8_FIXED_POINT_1_8TH", "value": 1},
486    {"name": "X_16_8_FIXED_POINT_1_4TH", "value": 2},
487    {"name": "X_16_8_FIXED_POINT_1_2", "value": 3},
488    {"name": "X_16_8_FIXED_POINT_1", "value": 4},
489    {"name": "X_16_8_FIXED_POINT_1_256TH", "value": 5},
490    {"name": "X_14_10_FIXED_POINT_1_1024TH", "value": 6},
491    {"name": "X_12_12_FIXED_POINT_1_4096TH", "value": 7}
492   ]
493  },
494  "ROP3": {
495   "entries": [
496    {"name": "ROP3_CLEAR", "value": 0},
497    {"name": "X_0X05", "value": 5},
498    {"name": "X_0X0A", "value": 10},
499    {"name": "X_0X0F", "value": 15},
500    {"name": "ROP3_NOR", "value": 17},
501    {"name": "ROP3_AND_INVERTED", "value": 34},
502    {"name": "ROP3_COPY_INVERTED", "value": 51},
503    {"name": "ROP3_AND_REVERSE", "value": 68},
504    {"name": "X_0X50", "value": 80},
505    {"name": "ROP3_INVERT", "value": 85},
506    {"name": "X_0X5A", "value": 90},
507    {"name": "X_0X5F", "value": 95},
508    {"name": "ROP3_XOR", "value": 102},
509    {"name": "ROP3_NAND", "value": 119},
510    {"name": "ROP3_AND", "value": 136},
511    {"name": "ROP3_EQUIVALENT", "value": 153},
512    {"name": "X_0XA0", "value": 160},
513    {"name": "X_0XA5", "value": 165},
514    {"name": "ROP3_NO_OP", "value": 170},
515    {"name": "X_0XAF", "value": 175},
516    {"name": "ROP3_OR_INVERTED", "value": 187},
517    {"name": "ROP3_COPY", "value": 204},
518    {"name": "ROP3_OR_REVERSE", "value": 221},
519    {"name": "ROP3_OR", "value": 238},
520    {"name": "X_0XF0", "value": 240},
521    {"name": "X_0XF5", "value": 245},
522    {"name": "X_0XFA", "value": 250},
523    {"name": "ROP3_SET", "value": 255}
524   ]
525  },
526  "RbMap": {
527   "entries": [
528    {"name": "RASTER_CONFIG_RB_MAP_0", "value": 0},
529    {"name": "RASTER_CONFIG_RB_MAP_1", "value": 1},
530    {"name": "RASTER_CONFIG_RB_MAP_2", "value": 2},
531    {"name": "RASTER_CONFIG_RB_MAP_3", "value": 3}
532   ]
533  },
534  "RbXsel": {
535   "entries": [
536    {"name": "RASTER_CONFIG_RB_XSEL_0", "value": 0},
537    {"name": "RASTER_CONFIG_RB_XSEL_1", "value": 1}
538   ]
539  },
540  "RbXsel2": {
541   "entries": [
542    {"name": "RASTER_CONFIG_RB_XSEL2_0", "value": 0},
543    {"name": "RASTER_CONFIG_RB_XSEL2_1", "value": 1},
544    {"name": "RASTER_CONFIG_RB_XSEL2_2", "value": 2},
545    {"name": "RASTER_CONFIG_RB_XSEL2_3", "value": 3}
546   ]
547  },
548  "RbYsel": {
549   "entries": [
550    {"name": "RASTER_CONFIG_RB_YSEL_0", "value": 0},
551    {"name": "RASTER_CONFIG_RB_YSEL_1", "value": 1}
552   ]
553  },
554  "SPI_PNT_SPRITE_OVERRIDE": {
555   "entries": [
556    {"name": "SPI_PNT_SPRITE_SEL_0", "value": 0},
557    {"name": "SPI_PNT_SPRITE_SEL_1", "value": 1},
558    {"name": "SPI_PNT_SPRITE_SEL_S", "value": 2},
559    {"name": "SPI_PNT_SPRITE_SEL_T", "value": 3},
560    {"name": "SPI_PNT_SPRITE_SEL_NONE", "value": 4}
561   ]
562  },
563  "SPI_SHADER_EX_FORMAT": {
564   "entries": [
565    {"name": "SPI_SHADER_ZERO", "value": 0},
566    {"name": "SPI_SHADER_32_R", "value": 1},
567    {"name": "SPI_SHADER_32_GR", "value": 2},
568    {"name": "SPI_SHADER_32_AR", "value": 3},
569    {"name": "SPI_SHADER_FP16_ABGR", "value": 4},
570    {"name": "SPI_SHADER_UNORM16_ABGR", "value": 5},
571    {"name": "SPI_SHADER_SNORM16_ABGR", "value": 6},
572    {"name": "SPI_SHADER_UINT16_ABGR", "value": 7},
573    {"name": "SPI_SHADER_SINT16_ABGR", "value": 8},
574    {"name": "SPI_SHADER_32_ABGR", "value": 9}
575   ]
576  },
577  "SPI_SHADER_FORMAT": {
578   "entries": [
579    {"name": "SPI_SHADER_NONE", "value": 0},
580    {"name": "SPI_SHADER_1COMP", "value": 1},
581    {"name": "SPI_SHADER_2COMP", "value": 2},
582    {"name": "SPI_SHADER_4COMPRESS", "value": 3},
583    {"name": "SPI_SHADER_4COMP", "value": 4}
584   ]
585  },
586  "SPM_PERFMON_STATE": {
587   "entries": [
588    {"name": "STRM_PERFMON_STATE_DISABLE_AND_RESET", "value": 0},
589    {"name": "STRM_PERFMON_STATE_START_COUNTING", "value": 1},
590    {"name": "STRM_PERFMON_STATE_STOP_COUNTING", "value": 2},
591    {"name": "STRM_PERFMON_STATE_RESERVED_3", "value": 3},
592    {"name": "STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM", "value": 4},
593    {"name": "STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM", "value": 5}
594   ]
595  },
596  "SQ_IMG_FILTER_TYPE": {
597   "entries": [
598    {"name": "SQ_IMG_FILTER_MODE_BLEND", "value": 0},
599    {"name": "SQ_IMG_FILTER_MODE_MIN", "value": 1},
600    {"name": "SQ_IMG_FILTER_MODE_MAX", "value": 2}
601   ]
602  },
603  "SQ_RSRC_BUF_TYPE": {
604   "entries": [
605    {"name": "SQ_RSRC_BUF", "value": 0},
606    {"name": "SQ_RSRC_BUF_RSVD_1", "value": 1},
607    {"name": "SQ_RSRC_BUF_RSVD_2", "value": 2},
608    {"name": "SQ_RSRC_BUF_RSVD_3", "value": 3}
609   ]
610  },
611  "SQ_RSRC_IMG_TYPE": {
612   "entries": [
613    {"name": "SQ_RSRC_IMG_RSVD_0", "value": 0},
614    {"name": "SQ_RSRC_IMG_RSVD_1", "value": 1},
615    {"name": "SQ_RSRC_IMG_RSVD_2", "value": 2},
616    {"name": "SQ_RSRC_IMG_RSVD_3", "value": 3},
617    {"name": "SQ_RSRC_IMG_RSVD_4", "value": 4},
618    {"name": "SQ_RSRC_IMG_RSVD_5", "value": 5},
619    {"name": "SQ_RSRC_IMG_RSVD_6", "value": 6},
620    {"name": "SQ_RSRC_IMG_RSVD_7", "value": 7},
621    {"name": "SQ_RSRC_IMG_1D", "value": 8},
622    {"name": "SQ_RSRC_IMG_2D", "value": 9},
623    {"name": "SQ_RSRC_IMG_3D", "value": 10},
624    {"name": "SQ_RSRC_IMG_CUBE", "value": 11},
625    {"name": "SQ_RSRC_IMG_1D_ARRAY", "value": 12},
626    {"name": "SQ_RSRC_IMG_2D_ARRAY", "value": 13},
627    {"name": "SQ_RSRC_IMG_2D_MSAA", "value": 14},
628    {"name": "SQ_RSRC_IMG_2D_MSAA_ARRAY", "value": 15}
629   ]
630  },
631  "SQ_SEL_XYZW01": {
632   "entries": [
633    {"name": "SQ_SEL_0", "value": 0},
634    {"name": "SQ_SEL_1", "value": 1},
635    {"name": "SQ_SEL_RESERVED_0", "value": 2},
636    {"name": "SQ_SEL_RESERVED_1", "value": 3},
637    {"name": "SQ_SEL_X", "value": 4},
638    {"name": "SQ_SEL_Y", "value": 5},
639    {"name": "SQ_SEL_Z", "value": 6},
640    {"name": "SQ_SEL_W", "value": 7}
641   ]
642  },
643  "SQ_TEX_BORDER_COLOR": {
644   "entries": [
645    {"name": "SQ_TEX_BORDER_COLOR_TRANS_BLACK", "value": 0},
646    {"name": "SQ_TEX_BORDER_COLOR_OPAQUE_BLACK", "value": 1},
647    {"name": "SQ_TEX_BORDER_COLOR_OPAQUE_WHITE", "value": 2},
648    {"name": "SQ_TEX_BORDER_COLOR_REGISTER", "value": 3}
649   ]
650  },
651  "SQ_TEX_CLAMP": {
652   "entries": [
653    {"name": "SQ_TEX_WRAP", "value": 0},
654    {"name": "SQ_TEX_MIRROR", "value": 1},
655    {"name": "SQ_TEX_CLAMP_LAST_TEXEL", "value": 2},
656    {"name": "SQ_TEX_MIRROR_ONCE_LAST_TEXEL", "value": 3},
657    {"name": "SQ_TEX_CLAMP_HALF_BORDER", "value": 4},
658    {"name": "SQ_TEX_MIRROR_ONCE_HALF_BORDER", "value": 5},
659    {"name": "SQ_TEX_CLAMP_BORDER", "value": 6},
660    {"name": "SQ_TEX_MIRROR_ONCE_BORDER", "value": 7}
661   ]
662  },
663  "SQ_TEX_DEPTH_COMPARE": {
664   "entries": [
665    {"name": "SQ_TEX_DEPTH_COMPARE_NEVER", "value": 0},
666    {"name": "SQ_TEX_DEPTH_COMPARE_LESS", "value": 1},
667    {"name": "SQ_TEX_DEPTH_COMPARE_EQUAL", "value": 2},
668    {"name": "SQ_TEX_DEPTH_COMPARE_LESSEQUAL", "value": 3},
669    {"name": "SQ_TEX_DEPTH_COMPARE_GREATER", "value": 4},
670    {"name": "SQ_TEX_DEPTH_COMPARE_NOTEQUAL", "value": 5},
671    {"name": "SQ_TEX_DEPTH_COMPARE_GREATEREQUAL", "value": 6},
672    {"name": "SQ_TEX_DEPTH_COMPARE_ALWAYS", "value": 7}
673   ]
674  },
675  "SQ_TEX_MIP_FILTER": {
676   "entries": [
677    {"name": "SQ_TEX_MIP_FILTER_NONE", "value": 0},
678    {"name": "SQ_TEX_MIP_FILTER_POINT", "value": 1},
679    {"name": "SQ_TEX_MIP_FILTER_LINEAR", "value": 2},
680    {"name": "SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ", "value": 3}
681   ]
682  },
683  "SQ_TEX_XY_FILTER": {
684   "entries": [
685    {"name": "SQ_TEX_XY_FILTER_POINT", "value": 0},
686    {"name": "SQ_TEX_XY_FILTER_BILINEAR", "value": 1},
687    {"name": "SQ_TEX_XY_FILTER_ANISO_POINT", "value": 2},
688    {"name": "SQ_TEX_XY_FILTER_ANISO_BILINEAR", "value": 3}
689   ]
690  },
691  "SQ_TEX_Z_FILTER": {
692   "entries": [
693    {"name": "SQ_TEX_Z_FILTER_NONE", "value": 0},
694    {"name": "SQ_TEX_Z_FILTER_POINT", "value": 1},
695    {"name": "SQ_TEX_Z_FILTER_LINEAR", "value": 2}
696   ]
697  },
698  "SX_BLEND_OPT": {
699   "entries": [
700    {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_ALL", "value": 0},
701    {"name": "BLEND_OPT_PRESERVE_ALL_IGNORE_NONE", "value": 1},
702    {"name": "BLEND_OPT_PRESERVE_C1_IGNORE_C0", "value": 2},
703    {"name": "BLEND_OPT_PRESERVE_C0_IGNORE_C1", "value": 3},
704    {"name": "BLEND_OPT_PRESERVE_A1_IGNORE_A0", "value": 4},
705    {"name": "BLEND_OPT_PRESERVE_A0_IGNORE_A1", "value": 5},
706    {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_A0", "value": 6},
707    {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_NONE", "value": 7}
708   ]
709  },
710  "SX_BLEND_OPT_EPSILON__MRT0_EPSILON": {
711   "entries": [
712    {"name": "EXACT", "value": 0},
713    {"name": "11BIT_FORMAT", "value": 1},
714    {"name": "10BIT_FORMAT", "value": 3},
715    {"name": "8BIT_FORMAT", "value": 6},
716    {"name": "6BIT_FORMAT", "value": 11},
717    {"name": "5BIT_FORMAT", "value": 13},
718    {"name": "4BIT_FORMAT", "value": 15}
719   ]
720  },
721  "SX_DOWNCONVERT_FORMAT": {
722   "entries": [
723    {"name": "SX_RT_EXPORT_NO_CONVERSION", "value": 0},
724    {"name": "SX_RT_EXPORT_32_R", "value": 1},
725    {"name": "SX_RT_EXPORT_32_A", "value": 2},
726    {"name": "SX_RT_EXPORT_10_11_11", "value": 3},
727    {"name": "SX_RT_EXPORT_2_10_10_10", "value": 4},
728    {"name": "SX_RT_EXPORT_8_8_8_8", "value": 5},
729    {"name": "SX_RT_EXPORT_5_6_5", "value": 6},
730    {"name": "SX_RT_EXPORT_1_5_5_5", "value": 7},
731    {"name": "SX_RT_EXPORT_4_4_4_4", "value": 8},
732    {"name": "SX_RT_EXPORT_16_16_GR", "value": 9},
733    {"name": "SX_RT_EXPORT_16_16_AR", "value": 10}
734   ]
735  },
736  "SX_OPT_COMB_FCN": {
737   "entries": [
738    {"name": "OPT_COMB_NONE", "value": 0},
739    {"name": "OPT_COMB_ADD", "value": 1},
740    {"name": "OPT_COMB_SUBTRACT", "value": 2},
741    {"name": "OPT_COMB_MIN", "value": 3},
742    {"name": "OPT_COMB_MAX", "value": 4},
743    {"name": "OPT_COMB_REVSUBTRACT", "value": 5},
744    {"name": "OPT_COMB_BLEND_DISABLED", "value": 6},
745    {"name": "OPT_COMB_SAFE_ADD", "value": 7}
746   ]
747  },
748  "ScMap": {
749   "entries": [
750    {"name": "RASTER_CONFIG_SC_MAP_0", "value": 0},
751    {"name": "RASTER_CONFIG_SC_MAP_1", "value": 1},
752    {"name": "RASTER_CONFIG_SC_MAP_2", "value": 2},
753    {"name": "RASTER_CONFIG_SC_MAP_3", "value": 3}
754   ]
755  },
756  "ScXsel": {
757   "entries": [
758    {"name": "RASTER_CONFIG_SC_XSEL_8_WIDE_TILE", "value": 0},
759    {"name": "RASTER_CONFIG_SC_XSEL_16_WIDE_TILE", "value": 1},
760    {"name": "RASTER_CONFIG_SC_XSEL_32_WIDE_TILE", "value": 2},
761    {"name": "RASTER_CONFIG_SC_XSEL_64_WIDE_TILE", "value": 3}
762   ]
763  },
764  "ScYsel": {
765   "entries": [
766    {"name": "RASTER_CONFIG_SC_YSEL_8_WIDE_TILE", "value": 0},
767    {"name": "RASTER_CONFIG_SC_YSEL_16_WIDE_TILE", "value": 1},
768    {"name": "RASTER_CONFIG_SC_YSEL_32_WIDE_TILE", "value": 2},
769    {"name": "RASTER_CONFIG_SC_YSEL_64_WIDE_TILE", "value": 3}
770   ]
771  },
772  "SeMap": {
773   "entries": [
774    {"name": "RASTER_CONFIG_SE_MAP_0", "value": 0},
775    {"name": "RASTER_CONFIG_SE_MAP_1", "value": 1},
776    {"name": "RASTER_CONFIG_SE_MAP_2", "value": 2},
777    {"name": "RASTER_CONFIG_SE_MAP_3", "value": 3}
778   ]
779  },
780  "SePairMap": {
781   "entries": [
782    {"name": "RASTER_CONFIG_SE_PAIR_MAP_0", "value": 0},
783    {"name": "RASTER_CONFIG_SE_PAIR_MAP_1", "value": 1},
784    {"name": "RASTER_CONFIG_SE_PAIR_MAP_2", "value": 2},
785    {"name": "RASTER_CONFIG_SE_PAIR_MAP_3", "value": 3}
786   ]
787  },
788  "SePairXsel": {
789   "entries": [
790    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE", "value": 0},
791    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE", "value": 1},
792    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE", "value": 2},
793    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE", "value": 3}
794   ]
795  },
796  "SePairYsel": {
797   "entries": [
798    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE", "value": 0},
799    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE", "value": 1},
800    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE", "value": 2},
801    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE", "value": 3}
802   ]
803  },
804  "SeXsel": {
805   "entries": [
806    {"name": "RASTER_CONFIG_SE_XSEL_8_WIDE_TILE", "value": 0},
807    {"name": "RASTER_CONFIG_SE_XSEL_16_WIDE_TILE", "value": 1},
808    {"name": "RASTER_CONFIG_SE_XSEL_32_WIDE_TILE", "value": 2},
809    {"name": "RASTER_CONFIG_SE_XSEL_64_WIDE_TILE", "value": 3}
810   ]
811  },
812  "SeYsel": {
813   "entries": [
814    {"name": "RASTER_CONFIG_SE_YSEL_8_WIDE_TILE", "value": 0},
815    {"name": "RASTER_CONFIG_SE_YSEL_16_WIDE_TILE", "value": 1},
816    {"name": "RASTER_CONFIG_SE_YSEL_32_WIDE_TILE", "value": 2},
817    {"name": "RASTER_CONFIG_SE_YSEL_64_WIDE_TILE", "value": 3}
818   ]
819  },
820  "StencilFormat": {
821   "entries": [
822    {"name": "STENCIL_INVALID", "value": 0},
823    {"name": "STENCIL_8", "value": 1}
824   ]
825  },
826  "StencilOp": {
827   "entries": [
828    {"name": "STENCIL_KEEP", "value": 0},
829    {"name": "STENCIL_ZERO", "value": 1},
830    {"name": "STENCIL_ONES", "value": 2},
831    {"name": "STENCIL_REPLACE_TEST", "value": 3},
832    {"name": "STENCIL_REPLACE_OP", "value": 4},
833    {"name": "STENCIL_ADD_CLAMP", "value": 5},
834    {"name": "STENCIL_SUB_CLAMP", "value": 6},
835    {"name": "STENCIL_INVERT", "value": 7},
836    {"name": "STENCIL_ADD_WRAP", "value": 8},
837    {"name": "STENCIL_SUB_WRAP", "value": 9},
838    {"name": "STENCIL_AND", "value": 10},
839    {"name": "STENCIL_OR", "value": 11},
840    {"name": "STENCIL_XOR", "value": 12},
841    {"name": "STENCIL_NAND", "value": 13},
842    {"name": "STENCIL_NOR", "value": 14},
843    {"name": "STENCIL_XNOR", "value": 15}
844   ]
845  },
846  "SurfaceEndian": {
847   "entries": [
848    {"name": "ENDIAN_NONE", "value": 0},
849    {"name": "ENDIAN_8IN16", "value": 1},
850    {"name": "ENDIAN_8IN32", "value": 2},
851    {"name": "ENDIAN_8IN64", "value": 3}
852   ]
853  },
854  "SurfaceNumber": {
855   "entries": [
856    {"name": "NUMBER_UNORM", "value": 0},
857    {"name": "NUMBER_SNORM", "value": 1},
858    {"name": "NUMBER_USCALED", "value": 2},
859    {"name": "NUMBER_SSCALED", "value": 3},
860    {"name": "NUMBER_UINT", "value": 4},
861    {"name": "NUMBER_SINT", "value": 5},
862    {"name": "NUMBER_SRGB", "value": 6},
863    {"name": "NUMBER_FLOAT", "value": 7}
864   ]
865  },
866  "SurfaceSwap": {
867   "entries": [
868    {"name": "SWAP_STD", "value": 0},
869    {"name": "SWAP_ALT", "value": 1},
870    {"name": "SWAP_STD_REV", "value": 2},
871    {"name": "SWAP_ALT_REV", "value": 3}
872   ]
873  },
874  "TileSplit": {
875   "entries": [
876    {"name": "ADDR_SURF_TILE_SPLIT_64B", "value": 0},
877    {"name": "ADDR_SURF_TILE_SPLIT_128B", "value": 1},
878    {"name": "ADDR_SURF_TILE_SPLIT_256B", "value": 2},
879    {"name": "ADDR_SURF_TILE_SPLIT_512B", "value": 3},
880    {"name": "ADDR_SURF_TILE_SPLIT_1KB", "value": 4},
881    {"name": "ADDR_SURF_TILE_SPLIT_2KB", "value": 5},
882    {"name": "ADDR_SURF_TILE_SPLIT_4KB", "value": 6}
883   ]
884  },
885  "VGT_DIST_MODE": {
886   "entries": [
887    {"name": "NO_DIST", "value": 0},
888    {"name": "PATCHES", "value": 1},
889    {"name": "DONUTS", "value": 2}
890   ]
891  },
892  "VGT_DI_MAJOR_MODE_SELECT": {
893   "entries": [
894    {"name": "DI_MAJOR_MODE_0", "value": 0},
895    {"name": "DI_MAJOR_MODE_1", "value": 1}
896   ]
897  },
898  "VGT_DI_PRIM_TYPE": {
899   "entries": [
900    {"name": "DI_PT_NONE", "value": 0},
901    {"name": "DI_PT_POINTLIST", "value": 1},
902    {"name": "DI_PT_LINELIST", "value": 2},
903    {"name": "DI_PT_LINESTRIP", "value": 3},
904    {"name": "DI_PT_TRILIST", "value": 4},
905    {"name": "DI_PT_TRIFAN", "value": 5},
906    {"name": "DI_PT_TRISTRIP", "value": 6},
907    {"name": "DI_PT_UNUSED_0", "value": 7},
908    {"name": "DI_PT_UNUSED_1", "value": 8},
909    {"name": "DI_PT_PATCH", "value": 9},
910    {"name": "DI_PT_LINELIST_ADJ", "value": 10},
911    {"name": "DI_PT_LINESTRIP_ADJ", "value": 11},
912    {"name": "DI_PT_TRILIST_ADJ", "value": 12},
913    {"name": "DI_PT_TRISTRIP_ADJ", "value": 13},
914    {"name": "DI_PT_UNUSED_3", "value": 14},
915    {"name": "DI_PT_UNUSED_4", "value": 15},
916    {"name": "DI_PT_TRI_WITH_WFLAGS", "value": 16},
917    {"name": "DI_PT_RECTLIST", "value": 17},
918    {"name": "DI_PT_LINELOOP", "value": 18},
919    {"name": "DI_PT_QUADLIST", "value": 19},
920    {"name": "DI_PT_QUADSTRIP", "value": 20},
921    {"name": "DI_PT_POLYGON", "value": 21},
922    {"name": "DI_PT_2D_COPY_RECT_LIST_V0", "value": 22},
923    {"name": "DI_PT_2D_COPY_RECT_LIST_V1", "value": 23},
924    {"name": "DI_PT_2D_COPY_RECT_LIST_V2", "value": 24},
925    {"name": "DI_PT_2D_COPY_RECT_LIST_V3", "value": 25},
926    {"name": "DI_PT_2D_FILL_RECT_LIST", "value": 26},
927    {"name": "DI_PT_2D_LINE_STRIP", "value": 27},
928    {"name": "DI_PT_2D_TRI_STRIP", "value": 28}
929   ]
930  },
931  "VGT_DI_SOURCE_SELECT": {
932   "entries": [
933    {"name": "DI_SRC_SEL_DMA", "value": 0},
934    {"name": "DI_SRC_SEL_IMMEDIATE", "value": 1},
935    {"name": "DI_SRC_SEL_AUTO_INDEX", "value": 2},
936    {"name": "DI_SRC_SEL_RESERVED", "value": 3}
937   ]
938  },
939  "VGT_DMA_BUF_TYPE": {
940   "entries": [
941    {"name": "VGT_DMA_BUF_MEM", "value": 0},
942    {"name": "VGT_DMA_BUF_RING", "value": 1},
943    {"name": "VGT_DMA_BUF_SETUP", "value": 2},
944    {"name": "VGT_DMA_PTR_UPDATE", "value": 3}
945   ]
946  },
947  "VGT_DMA_SWAP_MODE": {
948   "entries": [
949    {"name": "VGT_DMA_SWAP_NONE", "value": 0},
950    {"name": "VGT_DMA_SWAP_16_BIT", "value": 1},
951    {"name": "VGT_DMA_SWAP_32_BIT", "value": 2},
952    {"name": "VGT_DMA_SWAP_WORD", "value": 3}
953   ]
954  },
955  "VGT_EVENT_TYPE": {
956   "entries": [
957    {"name": "Reserved_0x00", "value": 0},
958    {"name": "SAMPLE_STREAMOUTSTATS1", "value": 1},
959    {"name": "SAMPLE_STREAMOUTSTATS2", "value": 2},
960    {"name": "SAMPLE_STREAMOUTSTATS3", "value": 3},
961    {"name": "CACHE_FLUSH_TS", "value": 4},
962    {"name": "CONTEXT_DONE", "value": 5},
963    {"name": "CACHE_FLUSH", "value": 6},
964    {"name": "CS_PARTIAL_FLUSH", "value": 7},
965    {"name": "VGT_STREAMOUT_SYNC", "value": 8},
966    {"name": "Reserved_0x09", "value": 9},
967    {"name": "VGT_STREAMOUT_RESET", "value": 10},
968    {"name": "END_OF_PIPE_INCR_DE", "value": 11},
969    {"name": "END_OF_PIPE_IB_END", "value": 12},
970    {"name": "RST_PIX_CNT", "value": 13},
971    {"name": "Reserved_0x0E", "value": 14},
972    {"name": "VS_PARTIAL_FLUSH", "value": 15},
973    {"name": "PS_PARTIAL_FLUSH", "value": 16},
974    {"name": "FLUSH_HS_OUTPUT", "value": 17},
975    {"name": "FLUSH_LS_OUTPUT", "value": 18},
976    {"name": "Reserved_0x13", "value": 19},
977    {"name": "CACHE_FLUSH_AND_INV_TS_EVENT", "value": 20},
978    {"name": "ZPASS_DONE", "value": 21},
979    {"name": "CACHE_FLUSH_AND_INV_EVENT", "value": 22},
980    {"name": "PERFCOUNTER_START", "value": 23},
981    {"name": "PERFCOUNTER_STOP", "value": 24},
982    {"name": "PIPELINESTAT_START", "value": 25},
983    {"name": "PIPELINESTAT_STOP", "value": 26},
984    {"name": "PERFCOUNTER_SAMPLE", "value": 27},
985    {"name": "FLUSH_ES_OUTPUT", "value": 28},
986    {"name": "FLUSH_GS_OUTPUT", "value": 29},
987    {"name": "SAMPLE_PIPELINESTAT", "value": 30},
988    {"name": "SO_VGTSTREAMOUT_FLUSH", "value": 31},
989    {"name": "SAMPLE_STREAMOUTSTATS", "value": 32},
990    {"name": "RESET_VTX_CNT", "value": 33},
991    {"name": "BLOCK_CONTEXT_DONE", "value": 34},
992    {"name": "CS_CONTEXT_DONE", "value": 35},
993    {"name": "VGT_FLUSH", "value": 36},
994    {"name": "TGID_ROLLOVER", "value": 37},
995    {"name": "SQ_NON_EVENT", "value": 38},
996    {"name": "SC_SEND_DB_VPZ", "value": 39},
997    {"name": "BOTTOM_OF_PIPE_TS", "value": 40},
998    {"name": "FLUSH_SX_TS", "value": 41},
999    {"name": "DB_CACHE_FLUSH_AND_INV", "value": 42},
1000    {"name": "FLUSH_AND_INV_DB_DATA_TS", "value": 43},
1001    {"name": "FLUSH_AND_INV_DB_META", "value": 44},
1002    {"name": "FLUSH_AND_INV_CB_DATA_TS", "value": 45},
1003    {"name": "FLUSH_AND_INV_CB_META", "value": 46},
1004    {"name": "CS_DONE", "value": 47},
1005    {"name": "PS_DONE", "value": 48},
1006    {"name": "FLUSH_AND_INV_CB_PIXEL_DATA", "value": 49},
1007    {"name": "SX_CB_RAT_ACK_REQUEST", "value": 50},
1008    {"name": "THREAD_TRACE_START", "value": 51},
1009    {"name": "THREAD_TRACE_STOP", "value": 52},
1010    {"name": "THREAD_TRACE_MARKER", "value": 53},
1011    {"name": "THREAD_TRACE_FLUSH", "value": 54},
1012    {"name": "THREAD_TRACE_FINISH", "value": 55},
1013    {"name": "PIXEL_PIPE_STAT_CONTROL", "value": 56},
1014    {"name": "PIXEL_PIPE_STAT_DUMP", "value": 57},
1015    {"name": "PIXEL_PIPE_STAT_RESET", "value": 58},
1016    {"name": "CONTEXT_SUSPEND", "value": 59},
1017    {"name": "OFFCHIP_HS_DEALLOC", "value": 60}
1018   ]
1019  },
1020  "VGT_GS_CUT_MODE": {
1021   "entries": [
1022    {"name": "GS_CUT_1024", "value": 0},
1023    {"name": "GS_CUT_512", "value": 1},
1024    {"name": "GS_CUT_256", "value": 2},
1025    {"name": "GS_CUT_128", "value": 3}
1026   ]
1027  },
1028  "VGT_GS_MODE_TYPE": {
1029   "entries": [
1030    {"name": "GS_OFF", "value": 0},
1031    {"name": "GS_SCENARIO_A", "value": 1},
1032    {"name": "GS_SCENARIO_B", "value": 2},
1033    {"name": "GS_SCENARIO_G", "value": 3},
1034    {"name": "GS_SCENARIO_C", "value": 4},
1035    {"name": "SPRITE_EN", "value": 5}
1036   ]
1037  },
1038  "VGT_GS_OUTPRIM_TYPE": {
1039   "entries": [
1040    {"name": "POINTLIST", "value": 0},
1041    {"name": "LINESTRIP", "value": 1},
1042    {"name": "TRISTRIP", "value": 2}
1043   ]
1044  },
1045  "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY": {
1046   "entries": [
1047    {"name": "X_8K_DWORDS", "value": 0},
1048    {"name": "X_4K_DWORDS", "value": 1},
1049    {"name": "X_2K_DWORDS", "value": 2},
1050    {"name": "X_1K_DWORDS", "value": 3}
1051   ]
1052  },
1053  "VGT_INDEX_TYPE_MODE": {
1054   "entries": [
1055    {"name": "VGT_INDEX_16", "value": 0},
1056    {"name": "VGT_INDEX_32", "value": 1},
1057    {"name": "VGT_INDEX_8", "value": 2}
1058   ]
1059  },
1060  "VGT_RDREQ_POLICY": {
1061   "entries": [
1062    {"name": "VGT_POLICY_LRU", "value": 0},
1063    {"name": "VGT_POLICY_STREAM", "value": 1}
1064   ]
1065  },
1066  "VGT_STAGES_ES_EN": {
1067   "entries": [
1068    {"name": "ES_STAGE_OFF", "value": 0},
1069    {"name": "ES_STAGE_DS", "value": 1},
1070    {"name": "ES_STAGE_REAL", "value": 2},
1071    {"name": "RESERVED_ES", "value": 3}
1072   ]
1073  },
1074  "VGT_STAGES_GS_EN": {
1075   "entries": [
1076    {"name": "GS_STAGE_OFF", "value": 0},
1077    {"name": "GS_STAGE_ON", "value": 1}
1078   ]
1079  },
1080  "VGT_STAGES_HS_EN": {
1081   "entries": [
1082    {"name": "HS_STAGE_OFF", "value": 0},
1083    {"name": "HS_STAGE_ON", "value": 1}
1084   ]
1085  },
1086  "VGT_STAGES_LS_EN": {
1087   "entries": [
1088    {"name": "LS_STAGE_OFF", "value": 0},
1089    {"name": "LS_STAGE_ON", "value": 1},
1090    {"name": "CS_STAGE_ON", "value": 2},
1091    {"name": "RESERVED_LS", "value": 3}
1092   ]
1093  },
1094  "VGT_STAGES_VS_EN": {
1095   "entries": [
1096    {"name": "VS_STAGE_REAL", "value": 0},
1097    {"name": "VS_STAGE_DS", "value": 1},
1098    {"name": "VS_STAGE_COPY_SHADER", "value": 2},
1099    {"name": "RESERVED_VS", "value": 3}
1100   ]
1101  },
1102  "VGT_TESS_PARTITION": {
1103   "entries": [
1104    {"name": "PART_INTEGER", "value": 0},
1105    {"name": "PART_POW2", "value": 1},
1106    {"name": "PART_FRAC_ODD", "value": 2},
1107    {"name": "PART_FRAC_EVEN", "value": 3}
1108   ]
1109  },
1110  "VGT_TESS_TOPOLOGY": {
1111   "entries": [
1112    {"name": "OUTPUT_POINT", "value": 0},
1113    {"name": "OUTPUT_LINE", "value": 1},
1114    {"name": "OUTPUT_TRIANGLE_CW", "value": 2},
1115    {"name": "OUTPUT_TRIANGLE_CCW", "value": 3}
1116   ]
1117  },
1118  "VGT_TESS_TYPE": {
1119   "entries": [
1120    {"name": "TESS_ISOLINE", "value": 0},
1121    {"name": "TESS_TRIANGLE", "value": 1},
1122    {"name": "TESS_QUAD", "value": 2}
1123   ]
1124  },
1125  "ZFormat": {
1126   "entries": [
1127    {"name": "Z_INVALID", "value": 0},
1128    {"name": "Z_16", "value": 1},
1129    {"name": "Z_24", "value": 2},
1130    {"name": "Z_32_FLOAT", "value": 3}
1131   ]
1132  },
1133  "ZLimitSumm": {
1134   "entries": [
1135    {"name": "FORCE_SUMM_OFF", "value": 0},
1136    {"name": "FORCE_SUMM_MINZ", "value": 1},
1137    {"name": "FORCE_SUMM_MAXZ", "value": 2},
1138    {"name": "FORCE_SUMM_BOTH", "value": 3}
1139   ]
1140  },
1141  "ZOrder": {
1142   "entries": [
1143    {"name": "LATE_Z", "value": 0},
1144    {"name": "EARLY_Z_THEN_LATE_Z", "value": 1},
1145    {"name": "RE_Z", "value": 2},
1146    {"name": "EARLY_Z_THEN_RE_Z", "value": 3}
1147   ]
1148  }
1149 },
1150 "register_mappings": [
1151  {
1152   "chips": ["gfx81"],
1153   "map": {"at": 68, "to": "mm"},
1154   "name": "SQ_WAVE_MODE",
1155   "type_ref": "SQ_WAVE_MODE"
1156  },
1157  {
1158   "chips": ["gfx81"],
1159   "map": {"at": 72, "to": "mm"},
1160   "name": "SQ_WAVE_STATUS",
1161   "type_ref": "SQ_WAVE_STATUS"
1162  },
1163  {
1164   "chips": ["gfx81"],
1165   "map": {"at": 76, "to": "mm"},
1166   "name": "SQ_WAVE_TRAPSTS",
1167   "type_ref": "SQ_WAVE_TRAPSTS"
1168  },
1169  {
1170   "chips": ["gfx81"],
1171   "map": {"at": 80, "to": "mm"},
1172   "name": "SQ_WAVE_HW_ID",
1173   "type_ref": "SQ_WAVE_HW_ID"
1174  },
1175  {
1176   "chips": ["gfx81"],
1177   "map": {"at": 84, "to": "mm"},
1178   "name": "SQ_WAVE_GPR_ALLOC",
1179   "type_ref": "SQ_WAVE_GPR_ALLOC"
1180  },
1181  {
1182   "chips": ["gfx81"],
1183   "map": {"at": 88, "to": "mm"},
1184   "name": "SQ_WAVE_LDS_ALLOC",
1185   "type_ref": "SQ_WAVE_LDS_ALLOC"
1186  },
1187  {
1188   "chips": ["gfx81"],
1189   "map": {"at": 92, "to": "mm"},
1190   "name": "SQ_WAVE_IB_STS",
1191   "type_ref": "SQ_WAVE_IB_STS"
1192  },
1193  {
1194   "chips": ["gfx81"],
1195   "map": {"at": 96, "to": "mm"},
1196   "name": "SQ_WAVE_PC_LO"
1197  },
1198  {
1199   "chips": ["gfx81"],
1200   "map": {"at": 100, "to": "mm"},
1201   "name": "SQ_WAVE_PC_HI",
1202   "type_ref": "SQ_WAVE_PC_HI"
1203  },
1204  {
1205   "chips": ["gfx81"],
1206   "map": {"at": 104, "to": "mm"},
1207   "name": "SQ_WAVE_INST_DW0"
1208  },
1209  {
1210   "chips": ["gfx81"],
1211   "map": {"at": 108, "to": "mm"},
1212   "name": "SQ_WAVE_INST_DW1"
1213  },
1214  {
1215   "chips": ["gfx81"],
1216   "map": {"at": 112, "to": "mm"},
1217   "name": "SQ_WAVE_IB_DBG0",
1218   "type_ref": "SQ_WAVE_IB_DBG0"
1219  },
1220  {
1221   "chips": ["gfx81"],
1222   "map": {"at": 116, "to": "mm"},
1223   "name": "SQ_WAVE_IB_DBG1",
1224   "type_ref": "SQ_WAVE_IB_DBG1"
1225  },
1226  {
1227   "chips": ["gfx81"],
1228   "map": {"at": 2480, "to": "mm"},
1229   "name": "SQ_WAVE_TBA_LO"
1230  },
1231  {
1232   "chips": ["gfx81"],
1233   "map": {"at": 2484, "to": "mm"},
1234   "name": "SQ_WAVE_TBA_HI",
1235   "type_ref": "SQ_WAVE_TBA_HI"
1236  },
1237  {
1238   "chips": ["gfx81"],
1239   "map": {"at": 2488, "to": "mm"},
1240   "name": "SQ_WAVE_TMA_LO"
1241  },
1242  {
1243   "chips": ["gfx81"],
1244   "map": {"at": 2492, "to": "mm"},
1245   "name": "SQ_WAVE_TMA_HI",
1246   "type_ref": "SQ_WAVE_TBA_HI"
1247  },
1248  {
1249   "chips": ["gfx81"],
1250   "map": {"at": 2496, "to": "mm"},
1251   "name": "SQ_WAVE_TTMP0"
1252  },
1253  {
1254   "chips": ["gfx81"],
1255   "map": {"at": 2500, "to": "mm"},
1256   "name": "SQ_WAVE_TTMP1"
1257  },
1258  {
1259   "chips": ["gfx81"],
1260   "map": {"at": 2504, "to": "mm"},
1261   "name": "SQ_WAVE_TTMP2"
1262  },
1263  {
1264   "chips": ["gfx81"],
1265   "map": {"at": 2508, "to": "mm"},
1266   "name": "SQ_WAVE_TTMP3"
1267  },
1268  {
1269   "chips": ["gfx81"],
1270   "map": {"at": 2512, "to": "mm"},
1271   "name": "SQ_WAVE_TTMP4"
1272  },
1273  {
1274   "chips": ["gfx81"],
1275   "map": {"at": 2516, "to": "mm"},
1276   "name": "SQ_WAVE_TTMP5"
1277  },
1278  {
1279   "chips": ["gfx81"],
1280   "map": {"at": 2520, "to": "mm"},
1281   "name": "SQ_WAVE_TTMP6"
1282  },
1283  {
1284   "chips": ["gfx81"],
1285   "map": {"at": 2524, "to": "mm"},
1286   "name": "SQ_WAVE_TTMP7"
1287  },
1288  {
1289   "chips": ["gfx81"],
1290   "map": {"at": 2528, "to": "mm"},
1291   "name": "SQ_WAVE_TTMP8"
1292  },
1293  {
1294   "chips": ["gfx81"],
1295   "map": {"at": 2532, "to": "mm"},
1296   "name": "SQ_WAVE_TTMP9"
1297  },
1298  {
1299   "chips": ["gfx81"],
1300   "map": {"at": 2536, "to": "mm"},
1301   "name": "SQ_WAVE_TTMP10"
1302  },
1303  {
1304   "chips": ["gfx81"],
1305   "map": {"at": 2540, "to": "mm"},
1306   "name": "SQ_WAVE_TTMP11"
1307  },
1308  {
1309   "chips": ["gfx81"],
1310   "map": {"at": 2544, "to": "mm"},
1311   "name": "SQ_WAVE_M0"
1312  },
1313  {
1314   "chips": ["gfx81"],
1315   "map": {"at": 2552, "to": "mm"},
1316   "name": "SQ_WAVE_EXEC_LO"
1317  },
1318  {
1319   "chips": ["gfx81"],
1320   "map": {"at": 2556, "to": "mm"},
1321   "name": "SQ_WAVE_EXEC_HI"
1322  },
1323  {
1324   "chips": ["gfx81"],
1325   "map": {"at": 32776, "to": "mm"},
1326   "name": "GRBM_STATUS2",
1327   "type_ref": "GRBM_STATUS2"
1328  },
1329  {
1330   "chips": ["gfx81"],
1331   "map": {"at": 32784, "to": "mm"},
1332   "name": "GRBM_STATUS",
1333   "type_ref": "GRBM_STATUS"
1334  },
1335  {
1336   "chips": ["gfx81"],
1337   "map": {"at": 32788, "to": "mm"},
1338   "name": "GRBM_STATUS_SE0",
1339   "type_ref": "GRBM_STATUS_SE0"
1340  },
1341  {
1342   "chips": ["gfx81"],
1343   "map": {"at": 32792, "to": "mm"},
1344   "name": "GRBM_STATUS_SE1",
1345   "type_ref": "GRBM_STATUS_SE0"
1346  },
1347  {
1348   "chips": ["gfx81"],
1349   "map": {"at": 32824, "to": "mm"},
1350   "name": "GRBM_STATUS_SE2",
1351   "type_ref": "GRBM_STATUS_SE0"
1352  },
1353  {
1354   "chips": ["gfx81"],
1355   "map": {"at": 32828, "to": "mm"},
1356   "name": "GRBM_STATUS_SE3",
1357   "type_ref": "GRBM_STATUS_SE0"
1358  },
1359  {
1360   "chips": ["gfx81"],
1361   "map": {"at": 33296, "to": "mm"},
1362   "name": "CP_CPC_STATUS",
1363   "type_ref": "CP_CPC_STATUS"
1364  },
1365  {
1366   "chips": ["gfx81"],
1367   "map": {"at": 33300, "to": "mm"},
1368   "name": "CP_CPC_BUSY_STAT",
1369   "type_ref": "CP_CPC_BUSY_STAT"
1370  },
1371  {
1372   "chips": ["gfx81"],
1373   "map": {"at": 33304, "to": "mm"},
1374   "name": "CP_CPC_STALLED_STAT1",
1375   "type_ref": "CP_CPC_STALLED_STAT1"
1376  },
1377  {
1378   "chips": ["gfx81"],
1379   "map": {"at": 33308, "to": "mm"},
1380   "name": "CP_CPF_STATUS",
1381   "type_ref": "CP_CPF_STATUS"
1382  },
1383  {
1384   "chips": ["gfx81"],
1385   "map": {"at": 33312, "to": "mm"},
1386   "name": "CP_CPF_BUSY_STAT",
1387   "type_ref": "CP_CPF_BUSY_STAT"
1388  },
1389  {
1390   "chips": ["gfx81"],
1391   "map": {"at": 33316, "to": "mm"},
1392   "name": "CP_CPF_STALLED_STAT1",
1393   "type_ref": "CP_CPF_STALLED_STAT1"
1394  },
1395  {
1396   "chips": ["gfx81"],
1397   "map": {"at": 33324, "to": "mm"},
1398   "name": "CP_CPC_GRBM_FREE_COUNT",
1399   "type_ref": "CP_CPC_GRBM_FREE_COUNT"
1400  },
1401  {
1402   "chips": ["gfx81"],
1403   "map": {"at": 33344, "to": "mm"},
1404   "name": "CP_CPC_SCRATCH_INDEX",
1405   "type_ref": "CP_CPC_SCRATCH_INDEX"
1406  },
1407  {
1408   "chips": ["gfx81"],
1409   "map": {"at": 33348, "to": "mm"},
1410   "name": "CP_CPC_SCRATCH_DATA"
1411  },
1412  {
1413   "chips": ["gfx81"],
1414   "map": {"at": 33436, "to": "mm"},
1415   "name": "CP_CPC_HALT_HYST_COUNT",
1416   "type_ref": "CP_CPC_HALT_HYST_COUNT"
1417  },
1418  {
1419   "chips": ["gfx81"],
1420   "map": {"at": 36416, "to": "mm"},
1421   "name": "SQ_THREAD_TRACE_CNTR"
1422  },
1423  {
1424   "chips": ["gfx81"],
1425   "map": {"at": 36608, "to": "mm"},
1426   "name": "SQ_BUF_RSRC_WORD0"
1427  },
1428  {
1429   "chips": ["gfx81"],
1430   "map": {"at": 36612, "to": "mm"},
1431   "name": "SQ_BUF_RSRC_WORD1",
1432   "type_ref": "SQ_BUF_RSRC_WORD1"
1433  },
1434  {
1435   "chips": ["gfx81"],
1436   "map": {"at": 36616, "to": "mm"},
1437   "name": "SQ_BUF_RSRC_WORD2"
1438  },
1439  {
1440   "chips": ["gfx81"],
1441   "map": {"at": 36620, "to": "mm"},
1442   "name": "SQ_BUF_RSRC_WORD3",
1443   "type_ref": "SQ_BUF_RSRC_WORD3"
1444  },
1445  {
1446   "chips": ["gfx81"],
1447   "map": {"at": 36624, "to": "mm"},
1448   "name": "SQ_IMG_RSRC_WORD0"
1449  },
1450  {
1451   "chips": ["gfx81"],
1452   "map": {"at": 36628, "to": "mm"},
1453   "name": "SQ_IMG_RSRC_WORD1",
1454   "type_ref": "SQ_IMG_RSRC_WORD1"
1455  },
1456  {
1457   "chips": ["gfx81"],
1458   "map": {"at": 36632, "to": "mm"},
1459   "name": "SQ_IMG_RSRC_WORD2",
1460   "type_ref": "SQ_IMG_RSRC_WORD2"
1461  },
1462  {
1463   "chips": ["gfx81"],
1464   "map": {"at": 36636, "to": "mm"},
1465   "name": "SQ_IMG_RSRC_WORD3",
1466   "type_ref": "SQ_IMG_RSRC_WORD3"
1467  },
1468  {
1469   "chips": ["gfx81"],
1470   "map": {"at": 36640, "to": "mm"},
1471   "name": "SQ_IMG_RSRC_WORD4",
1472   "type_ref": "SQ_IMG_RSRC_WORD4"
1473  },
1474  {
1475   "chips": ["gfx81"],
1476   "map": {"at": 36644, "to": "mm"},
1477   "name": "SQ_IMG_RSRC_WORD5",
1478   "type_ref": "SQ_IMG_RSRC_WORD5"
1479  },
1480  {
1481   "chips": ["gfx81"],
1482   "map": {"at": 36648, "to": "mm"},
1483   "name": "SQ_IMG_RSRC_WORD6",
1484   "type_ref": "SQ_IMG_RSRC_WORD6"
1485  },
1486  {
1487   "chips": ["gfx81"],
1488   "map": {"at": 36652, "to": "mm"},
1489   "name": "SQ_IMG_RSRC_WORD7"
1490  },
1491  {
1492   "chips": ["gfx81"],
1493   "map": {"at": 36656, "to": "mm"},
1494   "name": "SQ_IMG_SAMP_WORD0",
1495   "type_ref": "SQ_IMG_SAMP_WORD0"
1496  },
1497  {
1498   "chips": ["gfx81"],
1499   "map": {"at": 36660, "to": "mm"},
1500   "name": "SQ_IMG_SAMP_WORD1",
1501   "type_ref": "SQ_IMG_SAMP_WORD1"
1502  },
1503  {
1504   "chips": ["gfx81"],
1505   "map": {"at": 36664, "to": "mm"},
1506   "name": "SQ_IMG_SAMP_WORD2",
1507   "type_ref": "SQ_IMG_SAMP_WORD2"
1508  },
1509  {
1510   "chips": ["gfx81"],
1511   "map": {"at": 36668, "to": "mm"},
1512   "name": "SQ_IMG_SAMP_WORD3",
1513   "type_ref": "SQ_IMG_SAMP_WORD3"
1514  },
1515  {
1516   "chips": ["gfx81"],
1517   "map": {"at": 37120, "to": "mm"},
1518   "name": "SPI_CONFIG_CNTL",
1519   "type_ref": "SPI_CONFIG_CNTL"
1520  },
1521  {
1522   "chips": ["gfx81"],
1523   "map": {"at": 39160, "to": "mm"},
1524   "name": "GB_ADDR_CONFIG",
1525   "type_ref": "GB_ADDR_CONFIG"
1526  },
1527  {
1528   "chips": ["gfx81"],
1529   "map": {"at": 39184, "to": "mm"},
1530   "name": "GB_TILE_MODE0",
1531   "type_ref": "GB_TILE_MODE0"
1532  },
1533  {
1534   "chips": ["gfx81"],
1535   "map": {"at": 39188, "to": "mm"},
1536   "name": "GB_TILE_MODE1",
1537   "type_ref": "GB_TILE_MODE0"
1538  },
1539  {
1540   "chips": ["gfx81"],
1541   "map": {"at": 39192, "to": "mm"},
1542   "name": "GB_TILE_MODE2",
1543   "type_ref": "GB_TILE_MODE0"
1544  },
1545  {
1546   "chips": ["gfx81"],
1547   "map": {"at": 39196, "to": "mm"},
1548   "name": "GB_TILE_MODE3",
1549   "type_ref": "GB_TILE_MODE0"
1550  },
1551  {
1552   "chips": ["gfx81"],
1553   "map": {"at": 39200, "to": "mm"},
1554   "name": "GB_TILE_MODE4",
1555   "type_ref": "GB_TILE_MODE0"
1556  },
1557  {
1558   "chips": ["gfx81"],
1559   "map": {"at": 39204, "to": "mm"},
1560   "name": "GB_TILE_MODE5",
1561   "type_ref": "GB_TILE_MODE0"
1562  },
1563  {
1564   "chips": ["gfx81"],
1565   "map": {"at": 39208, "to": "mm"},
1566   "name": "GB_TILE_MODE6",
1567   "type_ref": "GB_TILE_MODE0"
1568  },
1569  {
1570   "chips": ["gfx81"],
1571   "map": {"at": 39212, "to": "mm"},
1572   "name": "GB_TILE_MODE7",
1573   "type_ref": "GB_TILE_MODE0"
1574  },
1575  {
1576   "chips": ["gfx81"],
1577   "map": {"at": 39216, "to": "mm"},
1578   "name": "GB_TILE_MODE8",
1579   "type_ref": "GB_TILE_MODE0"
1580  },
1581  {
1582   "chips": ["gfx81"],
1583   "map": {"at": 39220, "to": "mm"},
1584   "name": "GB_TILE_MODE9",
1585   "type_ref": "GB_TILE_MODE0"
1586  },
1587  {
1588   "chips": ["gfx81"],
1589   "map": {"at": 39224, "to": "mm"},
1590   "name": "GB_TILE_MODE10",
1591   "type_ref": "GB_TILE_MODE0"
1592  },
1593  {
1594   "chips": ["gfx81"],
1595   "map": {"at": 39228, "to": "mm"},
1596   "name": "GB_TILE_MODE11",
1597   "type_ref": "GB_TILE_MODE0"
1598  },
1599  {
1600   "chips": ["gfx81"],
1601   "map": {"at": 39232, "to": "mm"},
1602   "name": "GB_TILE_MODE12",
1603   "type_ref": "GB_TILE_MODE0"
1604  },
1605  {
1606   "chips": ["gfx81"],
1607   "map": {"at": 39236, "to": "mm"},
1608   "name": "GB_TILE_MODE13",
1609   "type_ref": "GB_TILE_MODE0"
1610  },
1611  {
1612   "chips": ["gfx81"],
1613   "map": {"at": 39240, "to": "mm"},
1614   "name": "GB_TILE_MODE14",
1615   "type_ref": "GB_TILE_MODE0"
1616  },
1617  {
1618   "chips": ["gfx81"],
1619   "map": {"at": 39244, "to": "mm"},
1620   "name": "GB_TILE_MODE15",
1621   "type_ref": "GB_TILE_MODE0"
1622  },
1623  {
1624   "chips": ["gfx81"],
1625   "map": {"at": 39248, "to": "mm"},
1626   "name": "GB_TILE_MODE16",
1627   "type_ref": "GB_TILE_MODE0"
1628  },
1629  {
1630   "chips": ["gfx81"],
1631   "map": {"at": 39252, "to": "mm"},
1632   "name": "GB_TILE_MODE17",
1633   "type_ref": "GB_TILE_MODE0"
1634  },
1635  {
1636   "chips": ["gfx81"],
1637   "map": {"at": 39256, "to": "mm"},
1638   "name": "GB_TILE_MODE18",
1639   "type_ref": "GB_TILE_MODE0"
1640  },
1641  {
1642   "chips": ["gfx81"],
1643   "map": {"at": 39260, "to": "mm"},
1644   "name": "GB_TILE_MODE19",
1645   "type_ref": "GB_TILE_MODE0"
1646  },
1647  {
1648   "chips": ["gfx81"],
1649   "map": {"at": 39264, "to": "mm"},
1650   "name": "GB_TILE_MODE20",
1651   "type_ref": "GB_TILE_MODE0"
1652  },
1653  {
1654   "chips": ["gfx81"],
1655   "map": {"at": 39268, "to": "mm"},
1656   "name": "GB_TILE_MODE21",
1657   "type_ref": "GB_TILE_MODE0"
1658  },
1659  {
1660   "chips": ["gfx81"],
1661   "map": {"at": 39272, "to": "mm"},
1662   "name": "GB_TILE_MODE22",
1663   "type_ref": "GB_TILE_MODE0"
1664  },
1665  {
1666   "chips": ["gfx81"],
1667   "map": {"at": 39276, "to": "mm"},
1668   "name": "GB_TILE_MODE23",
1669   "type_ref": "GB_TILE_MODE0"
1670  },
1671  {
1672   "chips": ["gfx81"],
1673   "map": {"at": 39280, "to": "mm"},
1674   "name": "GB_TILE_MODE24",
1675   "type_ref": "GB_TILE_MODE0"
1676  },
1677  {
1678   "chips": ["gfx81"],
1679   "map": {"at": 39284, "to": "mm"},
1680   "name": "GB_TILE_MODE25",
1681   "type_ref": "GB_TILE_MODE0"
1682  },
1683  {
1684   "chips": ["gfx81"],
1685   "map": {"at": 39288, "to": "mm"},
1686   "name": "GB_TILE_MODE26",
1687   "type_ref": "GB_TILE_MODE0"
1688  },
1689  {
1690   "chips": ["gfx81"],
1691   "map": {"at": 39292, "to": "mm"},
1692   "name": "GB_TILE_MODE27",
1693   "type_ref": "GB_TILE_MODE0"
1694  },
1695  {
1696   "chips": ["gfx81"],
1697   "map": {"at": 39296, "to": "mm"},
1698   "name": "GB_TILE_MODE28",
1699   "type_ref": "GB_TILE_MODE0"
1700  },
1701  {
1702   "chips": ["gfx81"],
1703   "map": {"at": 39300, "to": "mm"},
1704   "name": "GB_TILE_MODE29",
1705   "type_ref": "GB_TILE_MODE0"
1706  },
1707  {
1708   "chips": ["gfx81"],
1709   "map": {"at": 39304, "to": "mm"},
1710   "name": "GB_TILE_MODE30",
1711   "type_ref": "GB_TILE_MODE0"
1712  },
1713  {
1714   "chips": ["gfx81"],
1715   "map": {"at": 39308, "to": "mm"},
1716   "name": "GB_TILE_MODE31",
1717   "type_ref": "GB_TILE_MODE0"
1718  },
1719  {
1720   "chips": ["gfx81"],
1721   "map": {"at": 39312, "to": "mm"},
1722   "name": "GB_MACROTILE_MODE0",
1723   "type_ref": "GB_MACROTILE_MODE0"
1724  },
1725  {
1726   "chips": ["gfx81"],
1727   "map": {"at": 39316, "to": "mm"},
1728   "name": "GB_MACROTILE_MODE1",
1729   "type_ref": "GB_MACROTILE_MODE0"
1730  },
1731  {
1732   "chips": ["gfx81"],
1733   "map": {"at": 39320, "to": "mm"},
1734   "name": "GB_MACROTILE_MODE2",
1735   "type_ref": "GB_MACROTILE_MODE0"
1736  },
1737  {
1738   "chips": ["gfx81"],
1739   "map": {"at": 39324, "to": "mm"},
1740   "name": "GB_MACROTILE_MODE3",
1741   "type_ref": "GB_MACROTILE_MODE0"
1742  },
1743  {
1744   "chips": ["gfx81"],
1745   "map": {"at": 39328, "to": "mm"},
1746   "name": "GB_MACROTILE_MODE4",
1747   "type_ref": "GB_MACROTILE_MODE0"
1748  },
1749  {
1750   "chips": ["gfx81"],
1751   "map": {"at": 39332, "to": "mm"},
1752   "name": "GB_MACROTILE_MODE5",
1753   "type_ref": "GB_MACROTILE_MODE0"
1754  },
1755  {
1756   "chips": ["gfx81"],
1757   "map": {"at": 39336, "to": "mm"},
1758   "name": "GB_MACROTILE_MODE6",
1759   "type_ref": "GB_MACROTILE_MODE0"
1760  },
1761  {
1762   "chips": ["gfx81"],
1763   "map": {"at": 39340, "to": "mm"},
1764   "name": "GB_MACROTILE_MODE7",
1765   "type_ref": "GB_MACROTILE_MODE0"
1766  },
1767  {
1768   "chips": ["gfx81"],
1769   "map": {"at": 39344, "to": "mm"},
1770   "name": "GB_MACROTILE_MODE8",
1771   "type_ref": "GB_MACROTILE_MODE0"
1772  },
1773  {
1774   "chips": ["gfx81"],
1775   "map": {"at": 39348, "to": "mm"},
1776   "name": "GB_MACROTILE_MODE9",
1777   "type_ref": "GB_MACROTILE_MODE0"
1778  },
1779  {
1780   "chips": ["gfx81"],
1781   "map": {"at": 39352, "to": "mm"},
1782   "name": "GB_MACROTILE_MODE10",
1783   "type_ref": "GB_MACROTILE_MODE0"
1784  },
1785  {
1786   "chips": ["gfx81"],
1787   "map": {"at": 39356, "to": "mm"},
1788   "name": "GB_MACROTILE_MODE11",
1789   "type_ref": "GB_MACROTILE_MODE0"
1790  },
1791  {
1792   "chips": ["gfx81"],
1793   "map": {"at": 39360, "to": "mm"},
1794   "name": "GB_MACROTILE_MODE12",
1795   "type_ref": "GB_MACROTILE_MODE0"
1796  },
1797  {
1798   "chips": ["gfx81"],
1799   "map": {"at": 39364, "to": "mm"},
1800   "name": "GB_MACROTILE_MODE13",
1801   "type_ref": "GB_MACROTILE_MODE0"
1802  },
1803  {
1804   "chips": ["gfx81"],
1805   "map": {"at": 39368, "to": "mm"},
1806   "name": "GB_MACROTILE_MODE14",
1807   "type_ref": "GB_MACROTILE_MODE0"
1808  },
1809  {
1810   "chips": ["gfx81"],
1811   "map": {"at": 39372, "to": "mm"},
1812   "name": "GB_MACROTILE_MODE15",
1813   "type_ref": "GB_MACROTILE_MODE0"
1814  },
1815  {
1816   "chips": ["gfx81"],
1817   "map": {"at": 45056, "to": "mm"},
1818   "name": "SPI_SHADER_TBA_LO_PS"
1819  },
1820  {
1821   "chips": ["gfx81"],
1822   "map": {"at": 45060, "to": "mm"},
1823   "name": "SPI_SHADER_TBA_HI_PS",
1824   "type_ref": "SPI_SHADER_TBA_HI_PS"
1825  },
1826  {
1827   "chips": ["gfx81"],
1828   "map": {"at": 45064, "to": "mm"},
1829   "name": "SPI_SHADER_TMA_LO_PS"
1830  },
1831  {
1832   "chips": ["gfx81"],
1833   "map": {"at": 45068, "to": "mm"},
1834   "name": "SPI_SHADER_TMA_HI_PS",
1835   "type_ref": "SPI_SHADER_TBA_HI_PS"
1836  },
1837  {
1838   "chips": ["gfx81"],
1839   "map": {"at": 45084, "to": "mm"},
1840   "name": "SPI_SHADER_PGM_RSRC3_PS",
1841   "type_ref": "SPI_SHADER_PGM_RSRC3_PS"
1842  },
1843  {
1844   "chips": ["gfx81"],
1845   "map": {"at": 45088, "to": "mm"},
1846   "name": "SPI_SHADER_PGM_LO_PS"
1847  },
1848  {
1849   "chips": ["gfx81"],
1850   "map": {"at": 45092, "to": "mm"},
1851   "name": "SPI_SHADER_PGM_HI_PS",
1852   "type_ref": "SPI_SHADER_TBA_HI_PS"
1853  },
1854  {
1855   "chips": ["gfx81"],
1856   "map": {"at": 45096, "to": "mm"},
1857   "name": "SPI_SHADER_PGM_RSRC1_PS",
1858   "type_ref": "SPI_SHADER_PGM_RSRC1_PS"
1859  },
1860  {
1861   "chips": ["gfx81"],
1862   "map": {"at": 45100, "to": "mm"},
1863   "name": "SPI_SHADER_PGM_RSRC2_PS",
1864   "type_ref": "SPI_SHADER_PGM_RSRC2_PS"
1865  },
1866  {
1867   "chips": ["gfx81"],
1868   "map": {"at": 45104, "to": "mm"},
1869   "name": "SPI_SHADER_USER_DATA_PS_0"
1870  },
1871  {
1872   "chips": ["gfx81"],
1873   "map": {"at": 45108, "to": "mm"},
1874   "name": "SPI_SHADER_USER_DATA_PS_1"
1875  },
1876  {
1877   "chips": ["gfx81"],
1878   "map": {"at": 45112, "to": "mm"},
1879   "name": "SPI_SHADER_USER_DATA_PS_2"
1880  },
1881  {
1882   "chips": ["gfx81"],
1883   "map": {"at": 45116, "to": "mm"},
1884   "name": "SPI_SHADER_USER_DATA_PS_3"
1885  },
1886  {
1887   "chips": ["gfx81"],
1888   "map": {"at": 45120, "to": "mm"},
1889   "name": "SPI_SHADER_USER_DATA_PS_4"
1890  },
1891  {
1892   "chips": ["gfx81"],
1893   "map": {"at": 45124, "to": "mm"},
1894   "name": "SPI_SHADER_USER_DATA_PS_5"
1895  },
1896  {
1897   "chips": ["gfx81"],
1898   "map": {"at": 45128, "to": "mm"},
1899   "name": "SPI_SHADER_USER_DATA_PS_6"
1900  },
1901  {
1902   "chips": ["gfx81"],
1903   "map": {"at": 45132, "to": "mm"},
1904   "name": "SPI_SHADER_USER_DATA_PS_7"
1905  },
1906  {
1907   "chips": ["gfx81"],
1908   "map": {"at": 45136, "to": "mm"},
1909   "name": "SPI_SHADER_USER_DATA_PS_8"
1910  },
1911  {
1912   "chips": ["gfx81"],
1913   "map": {"at": 45140, "to": "mm"},
1914   "name": "SPI_SHADER_USER_DATA_PS_9"
1915  },
1916  {
1917   "chips": ["gfx81"],
1918   "map": {"at": 45144, "to": "mm"},
1919   "name": "SPI_SHADER_USER_DATA_PS_10"
1920  },
1921  {
1922   "chips": ["gfx81"],
1923   "map": {"at": 45148, "to": "mm"},
1924   "name": "SPI_SHADER_USER_DATA_PS_11"
1925  },
1926  {
1927   "chips": ["gfx81"],
1928   "map": {"at": 45152, "to": "mm"},
1929   "name": "SPI_SHADER_USER_DATA_PS_12"
1930  },
1931  {
1932   "chips": ["gfx81"],
1933   "map": {"at": 45156, "to": "mm"},
1934   "name": "SPI_SHADER_USER_DATA_PS_13"
1935  },
1936  {
1937   "chips": ["gfx81"],
1938   "map": {"at": 45160, "to": "mm"},
1939   "name": "SPI_SHADER_USER_DATA_PS_14"
1940  },
1941  {
1942   "chips": ["gfx81"],
1943   "map": {"at": 45164, "to": "mm"},
1944   "name": "SPI_SHADER_USER_DATA_PS_15"
1945  },
1946  {
1947   "chips": ["gfx81"],
1948   "map": {"at": 45312, "to": "mm"},
1949   "name": "SPI_SHADER_TBA_LO_VS"
1950  },
1951  {
1952   "chips": ["gfx81"],
1953   "map": {"at": 45316, "to": "mm"},
1954   "name": "SPI_SHADER_TBA_HI_VS",
1955   "type_ref": "SPI_SHADER_TBA_HI_PS"
1956  },
1957  {
1958   "chips": ["gfx81"],
1959   "map": {"at": 45320, "to": "mm"},
1960   "name": "SPI_SHADER_TMA_LO_VS"
1961  },
1962  {
1963   "chips": ["gfx81"],
1964   "map": {"at": 45324, "to": "mm"},
1965   "name": "SPI_SHADER_TMA_HI_VS",
1966   "type_ref": "SPI_SHADER_TBA_HI_PS"
1967  },
1968  {
1969   "chips": ["gfx81"],
1970   "map": {"at": 45336, "to": "mm"},
1971   "name": "SPI_SHADER_PGM_RSRC3_VS",
1972   "type_ref": "SPI_SHADER_PGM_RSRC3_PS"
1973  },
1974  {
1975   "chips": ["gfx81"],
1976   "map": {"at": 45340, "to": "mm"},
1977   "name": "SPI_SHADER_LATE_ALLOC_VS",
1978   "type_ref": "SPI_SHADER_LATE_ALLOC_VS"
1979  },
1980  {
1981   "chips": ["gfx81"],
1982   "map": {"at": 45344, "to": "mm"},
1983   "name": "SPI_SHADER_PGM_LO_VS"
1984  },
1985  {
1986   "chips": ["gfx81"],
1987   "map": {"at": 45348, "to": "mm"},
1988   "name": "SPI_SHADER_PGM_HI_VS",
1989   "type_ref": "SPI_SHADER_TBA_HI_PS"
1990  },
1991  {
1992   "chips": ["gfx81"],
1993   "map": {"at": 45352, "to": "mm"},
1994   "name": "SPI_SHADER_PGM_RSRC1_VS",
1995   "type_ref": "SPI_SHADER_PGM_RSRC1_VS"
1996  },
1997  {
1998   "chips": ["gfx81"],
1999   "map": {"at": 45356, "to": "mm"},
2000   "name": "SPI_SHADER_PGM_RSRC2_VS",
2001   "type_ref": "SPI_SHADER_PGM_RSRC2_VS"
2002  },
2003  {
2004   "chips": ["gfx81"],
2005   "map": {"at": 45360, "to": "mm"},
2006   "name": "SPI_SHADER_USER_DATA_VS_0"
2007  },
2008  {
2009   "chips": ["gfx81"],
2010   "map": {"at": 45364, "to": "mm"},
2011   "name": "SPI_SHADER_USER_DATA_VS_1"
2012  },
2013  {
2014   "chips": ["gfx81"],
2015   "map": {"at": 45368, "to": "mm"},
2016   "name": "SPI_SHADER_USER_DATA_VS_2"
2017  },
2018  {
2019   "chips": ["gfx81"],
2020   "map": {"at": 45372, "to": "mm"},
2021   "name": "SPI_SHADER_USER_DATA_VS_3"
2022  },
2023  {
2024   "chips": ["gfx81"],
2025   "map": {"at": 45376, "to": "mm"},
2026   "name": "SPI_SHADER_USER_DATA_VS_4"
2027  },
2028  {
2029   "chips": ["gfx81"],
2030   "map": {"at": 45380, "to": "mm"},
2031   "name": "SPI_SHADER_USER_DATA_VS_5"
2032  },
2033  {
2034   "chips": ["gfx81"],
2035   "map": {"at": 45384, "to": "mm"},
2036   "name": "SPI_SHADER_USER_DATA_VS_6"
2037  },
2038  {
2039   "chips": ["gfx81"],
2040   "map": {"at": 45388, "to": "mm"},
2041   "name": "SPI_SHADER_USER_DATA_VS_7"
2042  },
2043  {
2044   "chips": ["gfx81"],
2045   "map": {"at": 45392, "to": "mm"},
2046   "name": "SPI_SHADER_USER_DATA_VS_8"
2047  },
2048  {
2049   "chips": ["gfx81"],
2050   "map": {"at": 45396, "to": "mm"},
2051   "name": "SPI_SHADER_USER_DATA_VS_9"
2052  },
2053  {
2054   "chips": ["gfx81"],
2055   "map": {"at": 45400, "to": "mm"},
2056   "name": "SPI_SHADER_USER_DATA_VS_10"
2057  },
2058  {
2059   "chips": ["gfx81"],
2060   "map": {"at": 45404, "to": "mm"},
2061   "name": "SPI_SHADER_USER_DATA_VS_11"
2062  },
2063  {
2064   "chips": ["gfx81"],
2065   "map": {"at": 45408, "to": "mm"},
2066   "name": "SPI_SHADER_USER_DATA_VS_12"
2067  },
2068  {
2069   "chips": ["gfx81"],
2070   "map": {"at": 45412, "to": "mm"},
2071   "name": "SPI_SHADER_USER_DATA_VS_13"
2072  },
2073  {
2074   "chips": ["gfx81"],
2075   "map": {"at": 45416, "to": "mm"},
2076   "name": "SPI_SHADER_USER_DATA_VS_14"
2077  },
2078  {
2079   "chips": ["gfx81"],
2080   "map": {"at": 45420, "to": "mm"},
2081   "name": "SPI_SHADER_USER_DATA_VS_15"
2082  },
2083  {
2084   "chips": ["gfx81"],
2085   "map": {"at": 45552, "to": "mm"},
2086   "name": "SPI_SHADER_PGM_RSRC2_ES_VS",
2087   "type_ref": "SPI_SHADER_PGM_RSRC2_ES_VS"
2088  },
2089  {
2090   "chips": ["gfx81"],
2091   "map": {"at": 45556, "to": "mm"},
2092   "name": "SPI_SHADER_PGM_RSRC2_LS_VS",
2093   "type_ref": "SPI_SHADER_PGM_RSRC2_LS_VS"
2094  },
2095  {
2096   "chips": ["gfx81"],
2097   "map": {"at": 45568, "to": "mm"},
2098   "name": "SPI_SHADER_TBA_LO_GS"
2099  },
2100  {
2101   "chips": ["gfx81"],
2102   "map": {"at": 45572, "to": "mm"},
2103   "name": "SPI_SHADER_TBA_HI_GS",
2104   "type_ref": "SPI_SHADER_TBA_HI_PS"
2105  },
2106  {
2107   "chips": ["gfx81"],
2108   "map": {"at": 45576, "to": "mm"},
2109   "name": "SPI_SHADER_TMA_LO_GS"
2110  },
2111  {
2112   "chips": ["gfx81"],
2113   "map": {"at": 45580, "to": "mm"},
2114   "name": "SPI_SHADER_TMA_HI_GS",
2115   "type_ref": "SPI_SHADER_TBA_HI_PS"
2116  },
2117  {
2118   "chips": ["gfx81"],
2119   "map": {"at": 45596, "to": "mm"},
2120   "name": "SPI_SHADER_PGM_RSRC3_GS",
2121   "type_ref": "SPI_SHADER_PGM_RSRC3_GS"
2122  },
2123  {
2124   "chips": ["gfx81"],
2125   "map": {"at": 45600, "to": "mm"},
2126   "name": "SPI_SHADER_PGM_LO_GS"
2127  },
2128  {
2129   "chips": ["gfx81"],
2130   "map": {"at": 45604, "to": "mm"},
2131   "name": "SPI_SHADER_PGM_HI_GS",
2132   "type_ref": "SPI_SHADER_TBA_HI_PS"
2133  },
2134  {
2135   "chips": ["gfx81"],
2136   "map": {"at": 45608, "to": "mm"},
2137   "name": "SPI_SHADER_PGM_RSRC1_GS",
2138   "type_ref": "SPI_SHADER_PGM_RSRC1_GS"
2139  },
2140  {
2141   "chips": ["gfx81"],
2142   "map": {"at": 45612, "to": "mm"},
2143   "name": "SPI_SHADER_PGM_RSRC2_GS",
2144   "type_ref": "SPI_SHADER_PGM_RSRC2_GS"
2145  },
2146  {
2147   "chips": ["gfx81"],
2148   "map": {"at": 45616, "to": "mm"},
2149   "name": "SPI_SHADER_USER_DATA_GS_0"
2150  },
2151  {
2152   "chips": ["gfx81"],
2153   "map": {"at": 45620, "to": "mm"},
2154   "name": "SPI_SHADER_USER_DATA_GS_1"
2155  },
2156  {
2157   "chips": ["gfx81"],
2158   "map": {"at": 45624, "to": "mm"},
2159   "name": "SPI_SHADER_USER_DATA_GS_2"
2160  },
2161  {
2162   "chips": ["gfx81"],
2163   "map": {"at": 45628, "to": "mm"},
2164   "name": "SPI_SHADER_USER_DATA_GS_3"
2165  },
2166  {
2167   "chips": ["gfx81"],
2168   "map": {"at": 45632, "to": "mm"},
2169   "name": "SPI_SHADER_USER_DATA_GS_4"
2170  },
2171  {
2172   "chips": ["gfx81"],
2173   "map": {"at": 45636, "to": "mm"},
2174   "name": "SPI_SHADER_USER_DATA_GS_5"
2175  },
2176  {
2177   "chips": ["gfx81"],
2178   "map": {"at": 45640, "to": "mm"},
2179   "name": "SPI_SHADER_USER_DATA_GS_6"
2180  },
2181  {
2182   "chips": ["gfx81"],
2183   "map": {"at": 45644, "to": "mm"},
2184   "name": "SPI_SHADER_USER_DATA_GS_7"
2185  },
2186  {
2187   "chips": ["gfx81"],
2188   "map": {"at": 45648, "to": "mm"},
2189   "name": "SPI_SHADER_USER_DATA_GS_8"
2190  },
2191  {
2192   "chips": ["gfx81"],
2193   "map": {"at": 45652, "to": "mm"},
2194   "name": "SPI_SHADER_USER_DATA_GS_9"
2195  },
2196  {
2197   "chips": ["gfx81"],
2198   "map": {"at": 45656, "to": "mm"},
2199   "name": "SPI_SHADER_USER_DATA_GS_10"
2200  },
2201  {
2202   "chips": ["gfx81"],
2203   "map": {"at": 45660, "to": "mm"},
2204   "name": "SPI_SHADER_USER_DATA_GS_11"
2205  },
2206  {
2207   "chips": ["gfx81"],
2208   "map": {"at": 45664, "to": "mm"},
2209   "name": "SPI_SHADER_USER_DATA_GS_12"
2210  },
2211  {
2212   "chips": ["gfx81"],
2213   "map": {"at": 45668, "to": "mm"},
2214   "name": "SPI_SHADER_USER_DATA_GS_13"
2215  },
2216  {
2217   "chips": ["gfx81"],
2218   "map": {"at": 45672, "to": "mm"},
2219   "name": "SPI_SHADER_USER_DATA_GS_14"
2220  },
2221  {
2222   "chips": ["gfx81"],
2223   "map": {"at": 45676, "to": "mm"},
2224   "name": "SPI_SHADER_USER_DATA_GS_15"
2225  },
2226  {
2227   "chips": ["gfx81"],
2228   "map": {"at": 45808, "to": "mm"},
2229   "name": "SPI_SHADER_PGM_RSRC2_ES_GS",
2230   "type_ref": "SPI_SHADER_PGM_RSRC2_ES_VS"
2231  },
2232  {
2233   "chips": ["gfx81"],
2234   "map": {"at": 45824, "to": "mm"},
2235   "name": "SPI_SHADER_TBA_LO_ES"
2236  },
2237  {
2238   "chips": ["gfx81"],
2239   "map": {"at": 45828, "to": "mm"},
2240   "name": "SPI_SHADER_TBA_HI_ES",
2241   "type_ref": "SPI_SHADER_TBA_HI_PS"
2242  },
2243  {
2244   "chips": ["gfx81"],
2245   "map": {"at": 45832, "to": "mm"},
2246   "name": "SPI_SHADER_TMA_LO_ES"
2247  },
2248  {
2249   "chips": ["gfx81"],
2250   "map": {"at": 45836, "to": "mm"},
2251   "name": "SPI_SHADER_TMA_HI_ES",
2252   "type_ref": "SPI_SHADER_TBA_HI_PS"
2253  },
2254  {
2255   "chips": ["gfx81"],
2256   "map": {"at": 45852, "to": "mm"},
2257   "name": "SPI_SHADER_PGM_RSRC3_ES",
2258   "type_ref": "SPI_SHADER_PGM_RSRC3_GS"
2259  },
2260  {
2261   "chips": ["gfx81"],
2262   "map": {"at": 45856, "to": "mm"},
2263   "name": "SPI_SHADER_PGM_LO_ES"
2264  },
2265  {
2266   "chips": ["gfx81"],
2267   "map": {"at": 45860, "to": "mm"},
2268   "name": "SPI_SHADER_PGM_HI_ES",
2269   "type_ref": "SPI_SHADER_TBA_HI_PS"
2270  },
2271  {
2272   "chips": ["gfx81"],
2273   "map": {"at": 45864, "to": "mm"},
2274   "name": "SPI_SHADER_PGM_RSRC1_ES",
2275   "type_ref": "SPI_SHADER_PGM_RSRC1_VS"
2276  },
2277  {
2278   "chips": ["gfx81"],
2279   "map": {"at": 45868, "to": "mm"},
2280   "name": "SPI_SHADER_PGM_RSRC2_ES",
2281   "type_ref": "SPI_SHADER_PGM_RSRC2_ES_VS"
2282  },
2283  {
2284   "chips": ["gfx81"],
2285   "map": {"at": 45872, "to": "mm"},
2286   "name": "SPI_SHADER_USER_DATA_ES_0"
2287  },
2288  {
2289   "chips": ["gfx81"],
2290   "map": {"at": 45876, "to": "mm"},
2291   "name": "SPI_SHADER_USER_DATA_ES_1"
2292  },
2293  {
2294   "chips": ["gfx81"],
2295   "map": {"at": 45880, "to": "mm"},
2296   "name": "SPI_SHADER_USER_DATA_ES_2"
2297  },
2298  {
2299   "chips": ["gfx81"],
2300   "map": {"at": 45884, "to": "mm"},
2301   "name": "SPI_SHADER_USER_DATA_ES_3"
2302  },
2303  {
2304   "chips": ["gfx81"],
2305   "map": {"at": 45888, "to": "mm"},
2306   "name": "SPI_SHADER_USER_DATA_ES_4"
2307  },
2308  {
2309   "chips": ["gfx81"],
2310   "map": {"at": 45892, "to": "mm"},
2311   "name": "SPI_SHADER_USER_DATA_ES_5"
2312  },
2313  {
2314   "chips": ["gfx81"],
2315   "map": {"at": 45896, "to": "mm"},
2316   "name": "SPI_SHADER_USER_DATA_ES_6"
2317  },
2318  {
2319   "chips": ["gfx81"],
2320   "map": {"at": 45900, "to": "mm"},
2321   "name": "SPI_SHADER_USER_DATA_ES_7"
2322  },
2323  {
2324   "chips": ["gfx81"],
2325   "map": {"at": 45904, "to": "mm"},
2326   "name": "SPI_SHADER_USER_DATA_ES_8"
2327  },
2328  {
2329   "chips": ["gfx81"],
2330   "map": {"at": 45908, "to": "mm"},
2331   "name": "SPI_SHADER_USER_DATA_ES_9"
2332  },
2333  {
2334   "chips": ["gfx81"],
2335   "map": {"at": 45912, "to": "mm"},
2336   "name": "SPI_SHADER_USER_DATA_ES_10"
2337  },
2338  {
2339   "chips": ["gfx81"],
2340   "map": {"at": 45916, "to": "mm"},
2341   "name": "SPI_SHADER_USER_DATA_ES_11"
2342  },
2343  {
2344   "chips": ["gfx81"],
2345   "map": {"at": 45920, "to": "mm"},
2346   "name": "SPI_SHADER_USER_DATA_ES_12"
2347  },
2348  {
2349   "chips": ["gfx81"],
2350   "map": {"at": 45924, "to": "mm"},
2351   "name": "SPI_SHADER_USER_DATA_ES_13"
2352  },
2353  {
2354   "chips": ["gfx81"],
2355   "map": {"at": 45928, "to": "mm"},
2356   "name": "SPI_SHADER_USER_DATA_ES_14"
2357  },
2358  {
2359   "chips": ["gfx81"],
2360   "map": {"at": 45932, "to": "mm"},
2361   "name": "SPI_SHADER_USER_DATA_ES_15"
2362  },
2363  {
2364   "chips": ["gfx81"],
2365   "map": {"at": 46068, "to": "mm"},
2366   "name": "SPI_SHADER_PGM_RSRC2_LS_ES",
2367   "type_ref": "SPI_SHADER_PGM_RSRC2_LS_VS"
2368  },
2369  {
2370   "chips": ["gfx81"],
2371   "map": {"at": 46080, "to": "mm"},
2372   "name": "SPI_SHADER_TBA_LO_HS"
2373  },
2374  {
2375   "chips": ["gfx81"],
2376   "map": {"at": 46084, "to": "mm"},
2377   "name": "SPI_SHADER_TBA_HI_HS",
2378   "type_ref": "SPI_SHADER_TBA_HI_PS"
2379  },
2380  {
2381   "chips": ["gfx81"],
2382   "map": {"at": 46088, "to": "mm"},
2383   "name": "SPI_SHADER_TMA_LO_HS"
2384  },
2385  {
2386   "chips": ["gfx81"],
2387   "map": {"at": 46092, "to": "mm"},
2388   "name": "SPI_SHADER_TMA_HI_HS",
2389   "type_ref": "SPI_SHADER_TBA_HI_PS"
2390  },
2391  {
2392   "chips": ["gfx81"],
2393   "map": {"at": 46108, "to": "mm"},
2394   "name": "SPI_SHADER_PGM_RSRC3_HS",
2395   "type_ref": "SPI_SHADER_PGM_RSRC3_HS"
2396  },
2397  {
2398   "chips": ["gfx81"],
2399   "map": {"at": 46112, "to": "mm"},
2400   "name": "SPI_SHADER_PGM_LO_HS"
2401  },
2402  {
2403   "chips": ["gfx81"],
2404   "map": {"at": 46116, "to": "mm"},
2405   "name": "SPI_SHADER_PGM_HI_HS",
2406   "type_ref": "SPI_SHADER_TBA_HI_PS"
2407  },
2408  {
2409   "chips": ["gfx81"],
2410   "map": {"at": 46120, "to": "mm"},
2411   "name": "SPI_SHADER_PGM_RSRC1_HS",
2412   "type_ref": "SPI_SHADER_PGM_RSRC1_HS"
2413  },
2414  {
2415   "chips": ["gfx81"],
2416   "map": {"at": 46124, "to": "mm"},
2417   "name": "SPI_SHADER_PGM_RSRC2_HS",
2418   "type_ref": "SPI_SHADER_PGM_RSRC2_HS"
2419  },
2420  {
2421   "chips": ["gfx81"],
2422   "map": {"at": 46128, "to": "mm"},
2423   "name": "SPI_SHADER_USER_DATA_HS_0"
2424  },
2425  {
2426   "chips": ["gfx81"],
2427   "map": {"at": 46132, "to": "mm"},
2428   "name": "SPI_SHADER_USER_DATA_HS_1"
2429  },
2430  {
2431   "chips": ["gfx81"],
2432   "map": {"at": 46136, "to": "mm"},
2433   "name": "SPI_SHADER_USER_DATA_HS_2"
2434  },
2435  {
2436   "chips": ["gfx81"],
2437   "map": {"at": 46140, "to": "mm"},
2438   "name": "SPI_SHADER_USER_DATA_HS_3"
2439  },
2440  {
2441   "chips": ["gfx81"],
2442   "map": {"at": 46144, "to": "mm"},
2443   "name": "SPI_SHADER_USER_DATA_HS_4"
2444  },
2445  {
2446   "chips": ["gfx81"],
2447   "map": {"at": 46148, "to": "mm"},
2448   "name": "SPI_SHADER_USER_DATA_HS_5"
2449  },
2450  {
2451   "chips": ["gfx81"],
2452   "map": {"at": 46152, "to": "mm"},
2453   "name": "SPI_SHADER_USER_DATA_HS_6"
2454  },
2455  {
2456   "chips": ["gfx81"],
2457   "map": {"at": 46156, "to": "mm"},
2458   "name": "SPI_SHADER_USER_DATA_HS_7"
2459  },
2460  {
2461   "chips": ["gfx81"],
2462   "map": {"at": 46160, "to": "mm"},
2463   "name": "SPI_SHADER_USER_DATA_HS_8"
2464  },
2465  {
2466   "chips": ["gfx81"],
2467   "map": {"at": 46164, "to": "mm"},
2468   "name": "SPI_SHADER_USER_DATA_HS_9"
2469  },
2470  {
2471   "chips": ["gfx81"],
2472   "map": {"at": 46168, "to": "mm"},
2473   "name": "SPI_SHADER_USER_DATA_HS_10"
2474  },
2475  {
2476   "chips": ["gfx81"],
2477   "map": {"at": 46172, "to": "mm"},
2478   "name": "SPI_SHADER_USER_DATA_HS_11"
2479  },
2480  {
2481   "chips": ["gfx81"],
2482   "map": {"at": 46176, "to": "mm"},
2483   "name": "SPI_SHADER_USER_DATA_HS_12"
2484  },
2485  {
2486   "chips": ["gfx81"],
2487   "map": {"at": 46180, "to": "mm"},
2488   "name": "SPI_SHADER_USER_DATA_HS_13"
2489  },
2490  {
2491   "chips": ["gfx81"],
2492   "map": {"at": 46184, "to": "mm"},
2493   "name": "SPI_SHADER_USER_DATA_HS_14"
2494  },
2495  {
2496   "chips": ["gfx81"],
2497   "map": {"at": 46188, "to": "mm"},
2498   "name": "SPI_SHADER_USER_DATA_HS_15"
2499  },
2500  {
2501   "chips": ["gfx81"],
2502   "map": {"at": 46324, "to": "mm"},
2503   "name": "SPI_SHADER_PGM_RSRC2_LS_HS",
2504   "type_ref": "SPI_SHADER_PGM_RSRC2_LS_VS"
2505  },
2506  {
2507   "chips": ["gfx81"],
2508   "map": {"at": 46336, "to": "mm"},
2509   "name": "SPI_SHADER_TBA_LO_LS"
2510  },
2511  {
2512   "chips": ["gfx81"],
2513   "map": {"at": 46340, "to": "mm"},
2514   "name": "SPI_SHADER_TBA_HI_LS",
2515   "type_ref": "SPI_SHADER_TBA_HI_PS"
2516  },
2517  {
2518   "chips": ["gfx81"],
2519   "map": {"at": 46344, "to": "mm"},
2520   "name": "SPI_SHADER_TMA_LO_LS"
2521  },
2522  {
2523   "chips": ["gfx81"],
2524   "map": {"at": 46348, "to": "mm"},
2525   "name": "SPI_SHADER_TMA_HI_LS",
2526   "type_ref": "SPI_SHADER_TBA_HI_PS"
2527  },
2528  {
2529   "chips": ["gfx81"],
2530   "map": {"at": 46364, "to": "mm"},
2531   "name": "SPI_SHADER_PGM_RSRC3_LS",
2532   "type_ref": "SPI_SHADER_PGM_RSRC3_GS"
2533  },
2534  {
2535   "chips": ["gfx81"],
2536   "map": {"at": 46368, "to": "mm"},
2537   "name": "SPI_SHADER_PGM_LO_LS"
2538  },
2539  {
2540   "chips": ["gfx81"],
2541   "map": {"at": 46372, "to": "mm"},
2542   "name": "SPI_SHADER_PGM_HI_LS",
2543   "type_ref": "SPI_SHADER_TBA_HI_PS"
2544  },
2545  {
2546   "chips": ["gfx81"],
2547   "map": {"at": 46376, "to": "mm"},
2548   "name": "SPI_SHADER_PGM_RSRC1_LS",
2549   "type_ref": "SPI_SHADER_PGM_RSRC1_LS"
2550  },
2551  {
2552   "chips": ["gfx81"],
2553   "map": {"at": 46380, "to": "mm"},
2554   "name": "SPI_SHADER_PGM_RSRC2_LS",
2555   "type_ref": "SPI_SHADER_PGM_RSRC2_LS_VS"
2556  },
2557  {
2558   "chips": ["gfx81"],
2559   "map": {"at": 46384, "to": "mm"},
2560   "name": "SPI_SHADER_USER_DATA_LS_0"
2561  },
2562  {
2563   "chips": ["gfx81"],
2564   "map": {"at": 46388, "to": "mm"},
2565   "name": "SPI_SHADER_USER_DATA_LS_1"
2566  },
2567  {
2568   "chips": ["gfx81"],
2569   "map": {"at": 46392, "to": "mm"},
2570   "name": "SPI_SHADER_USER_DATA_LS_2"
2571  },
2572  {
2573   "chips": ["gfx81"],
2574   "map": {"at": 46396, "to": "mm"},
2575   "name": "SPI_SHADER_USER_DATA_LS_3"
2576  },
2577  {
2578   "chips": ["gfx81"],
2579   "map": {"at": 46400, "to": "mm"},
2580   "name": "SPI_SHADER_USER_DATA_LS_4"
2581  },
2582  {
2583   "chips": ["gfx81"],
2584   "map": {"at": 46404, "to": "mm"},
2585   "name": "SPI_SHADER_USER_DATA_LS_5"
2586  },
2587  {
2588   "chips": ["gfx81"],
2589   "map": {"at": 46408, "to": "mm"},
2590   "name": "SPI_SHADER_USER_DATA_LS_6"
2591  },
2592  {
2593   "chips": ["gfx81"],
2594   "map": {"at": 46412, "to": "mm"},
2595   "name": "SPI_SHADER_USER_DATA_LS_7"
2596  },
2597  {
2598   "chips": ["gfx81"],
2599   "map": {"at": 46416, "to": "mm"},
2600   "name": "SPI_SHADER_USER_DATA_LS_8"
2601  },
2602  {
2603   "chips": ["gfx81"],
2604   "map": {"at": 46420, "to": "mm"},
2605   "name": "SPI_SHADER_USER_DATA_LS_9"
2606  },
2607  {
2608   "chips": ["gfx81"],
2609   "map": {"at": 46424, "to": "mm"},
2610   "name": "SPI_SHADER_USER_DATA_LS_10"
2611  },
2612  {
2613   "chips": ["gfx81"],
2614   "map": {"at": 46428, "to": "mm"},
2615   "name": "SPI_SHADER_USER_DATA_LS_11"
2616  },
2617  {
2618   "chips": ["gfx81"],
2619   "map": {"at": 46432, "to": "mm"},
2620   "name": "SPI_SHADER_USER_DATA_LS_12"
2621  },
2622  {
2623   "chips": ["gfx81"],
2624   "map": {"at": 46436, "to": "mm"},
2625   "name": "SPI_SHADER_USER_DATA_LS_13"
2626  },
2627  {
2628   "chips": ["gfx81"],
2629   "map": {"at": 46440, "to": "mm"},
2630   "name": "SPI_SHADER_USER_DATA_LS_14"
2631  },
2632  {
2633   "chips": ["gfx81"],
2634   "map": {"at": 46444, "to": "mm"},
2635   "name": "SPI_SHADER_USER_DATA_LS_15"
2636  },
2637  {
2638   "chips": ["gfx81"],
2639   "map": {"at": 47104, "to": "mm"},
2640   "name": "COMPUTE_DISPATCH_INITIATOR",
2641   "type_ref": "COMPUTE_DISPATCH_INITIATOR"
2642  },
2643  {
2644   "chips": ["gfx81"],
2645   "map": {"at": 47108, "to": "mm"},
2646   "name": "COMPUTE_DIM_X"
2647  },
2648  {
2649   "chips": ["gfx81"],
2650   "map": {"at": 47112, "to": "mm"},
2651   "name": "COMPUTE_DIM_Y"
2652  },
2653  {
2654   "chips": ["gfx81"],
2655   "map": {"at": 47116, "to": "mm"},
2656   "name": "COMPUTE_DIM_Z"
2657  },
2658  {
2659   "chips": ["gfx81"],
2660   "map": {"at": 47120, "to": "mm"},
2661   "name": "COMPUTE_START_X"
2662  },
2663  {
2664   "chips": ["gfx81"],
2665   "map": {"at": 47124, "to": "mm"},
2666   "name": "COMPUTE_START_Y"
2667  },
2668  {
2669   "chips": ["gfx81"],
2670   "map": {"at": 47128, "to": "mm"},
2671   "name": "COMPUTE_START_Z"
2672  },
2673  {
2674   "chips": ["gfx81"],
2675   "map": {"at": 47132, "to": "mm"},
2676   "name": "COMPUTE_NUM_THREAD_X",
2677   "type_ref": "COMPUTE_NUM_THREAD_X"
2678  },
2679  {
2680   "chips": ["gfx81"],
2681   "map": {"at": 47136, "to": "mm"},
2682   "name": "COMPUTE_NUM_THREAD_Y",
2683   "type_ref": "COMPUTE_NUM_THREAD_X"
2684  },
2685  {
2686   "chips": ["gfx81"],
2687   "map": {"at": 47140, "to": "mm"},
2688   "name": "COMPUTE_NUM_THREAD_Z",
2689   "type_ref": "COMPUTE_NUM_THREAD_X"
2690  },
2691  {
2692   "chips": ["gfx81"],
2693   "map": {"at": 47144, "to": "mm"},
2694   "name": "COMPUTE_PIPELINESTAT_ENABLE",
2695   "type_ref": "COMPUTE_PIPELINESTAT_ENABLE"
2696  },
2697  {
2698   "chips": ["gfx81"],
2699   "map": {"at": 47148, "to": "mm"},
2700   "name": "COMPUTE_PERFCOUNT_ENABLE",
2701   "type_ref": "COMPUTE_PERFCOUNT_ENABLE"
2702  },
2703  {
2704   "chips": ["gfx81"],
2705   "map": {"at": 47152, "to": "mm"},
2706   "name": "COMPUTE_PGM_LO"
2707  },
2708  {
2709   "chips": ["gfx81"],
2710   "map": {"at": 47156, "to": "mm"},
2711   "name": "COMPUTE_PGM_HI",
2712   "type_ref": "COMPUTE_PGM_HI"
2713  },
2714  {
2715   "chips": ["gfx81"],
2716   "map": {"at": 47160, "to": "mm"},
2717   "name": "COMPUTE_TBA_LO"
2718  },
2719  {
2720   "chips": ["gfx81"],
2721   "map": {"at": 47164, "to": "mm"},
2722   "name": "COMPUTE_TBA_HI",
2723   "type_ref": "COMPUTE_TBA_HI"
2724  },
2725  {
2726   "chips": ["gfx81"],
2727   "map": {"at": 47168, "to": "mm"},
2728   "name": "COMPUTE_TMA_LO"
2729  },
2730  {
2731   "chips": ["gfx81"],
2732   "map": {"at": 47172, "to": "mm"},
2733   "name": "COMPUTE_TMA_HI",
2734   "type_ref": "COMPUTE_TBA_HI"
2735  },
2736  {
2737   "chips": ["gfx81"],
2738   "map": {"at": 47176, "to": "mm"},
2739   "name": "COMPUTE_PGM_RSRC1",
2740   "type_ref": "COMPUTE_PGM_RSRC1"
2741  },
2742  {
2743   "chips": ["gfx81"],
2744   "map": {"at": 47180, "to": "mm"},
2745   "name": "COMPUTE_PGM_RSRC2",
2746   "type_ref": "COMPUTE_PGM_RSRC2"
2747  },
2748  {
2749   "chips": ["gfx81"],
2750   "map": {"at": 47184, "to": "mm"},
2751   "name": "COMPUTE_VMID",
2752   "type_ref": "COMPUTE_VMID"
2753  },
2754  {
2755   "chips": ["gfx81"],
2756   "map": {"at": 47188, "to": "mm"},
2757   "name": "COMPUTE_RESOURCE_LIMITS",
2758   "type_ref": "COMPUTE_RESOURCE_LIMITS"
2759  },
2760  {
2761   "chips": ["gfx81"],
2762   "map": {"at": 47192, "to": "mm"},
2763   "name": "COMPUTE_STATIC_THREAD_MGMT_SE0",
2764   "type_ref": "COMPUTE_STATIC_THREAD_MGMT_SE0"
2765  },
2766  {
2767   "chips": ["gfx81"],
2768   "map": {"at": 47196, "to": "mm"},
2769   "name": "COMPUTE_STATIC_THREAD_MGMT_SE1",
2770   "type_ref": "COMPUTE_STATIC_THREAD_MGMT_SE0"
2771  },
2772  {
2773   "chips": ["gfx81"],
2774   "map": {"at": 47200, "to": "mm"},
2775   "name": "COMPUTE_TMPRING_SIZE",
2776   "type_ref": "COMPUTE_TMPRING_SIZE"
2777  },
2778  {
2779   "chips": ["gfx81"],
2780   "map": {"at": 47204, "to": "mm"},
2781   "name": "COMPUTE_STATIC_THREAD_MGMT_SE2",
2782   "type_ref": "COMPUTE_STATIC_THREAD_MGMT_SE0"
2783  },
2784  {
2785   "chips": ["gfx81"],
2786   "map": {"at": 47208, "to": "mm"},
2787   "name": "COMPUTE_STATIC_THREAD_MGMT_SE3",
2788   "type_ref": "COMPUTE_STATIC_THREAD_MGMT_SE0"
2789  },
2790  {
2791   "chips": ["gfx81"],
2792   "map": {"at": 47212, "to": "mm"},
2793   "name": "COMPUTE_RESTART_X"
2794  },
2795  {
2796   "chips": ["gfx81"],
2797   "map": {"at": 47216, "to": "mm"},
2798   "name": "COMPUTE_RESTART_Y"
2799  },
2800  {
2801   "chips": ["gfx81"],
2802   "map": {"at": 47220, "to": "mm"},
2803   "name": "COMPUTE_RESTART_Z"
2804  },
2805  {
2806   "chips": ["gfx81"],
2807   "map": {"at": 47224, "to": "mm"},
2808   "name": "COMPUTE_THREAD_TRACE_ENABLE",
2809   "type_ref": "COMPUTE_THREAD_TRACE_ENABLE"
2810  },
2811  {
2812   "chips": ["gfx81"],
2813   "map": {"at": 47228, "to": "mm"},
2814   "name": "COMPUTE_MISC_RESERVED",
2815   "type_ref": "COMPUTE_MISC_RESERVED"
2816  },
2817  {
2818   "chips": ["gfx81"],
2819   "map": {"at": 47232, "to": "mm"},
2820   "name": "COMPUTE_DISPATCH_ID"
2821  },
2822  {
2823   "chips": ["gfx81"],
2824   "map": {"at": 47236, "to": "mm"},
2825   "name": "COMPUTE_THREADGROUP_ID"
2826  },
2827  {
2828   "chips": ["gfx81"],
2829   "map": {"at": 47240, "to": "mm"},
2830   "name": "COMPUTE_RELAUNCH",
2831   "type_ref": "COMPUTE_RELAUNCH"
2832  },
2833  {
2834   "chips": ["gfx81"],
2835   "map": {"at": 47244, "to": "mm"},
2836   "name": "COMPUTE_WAVE_RESTORE_ADDR_LO"
2837  },
2838  {
2839   "chips": ["gfx81"],
2840   "map": {"at": 47248, "to": "mm"},
2841   "name": "COMPUTE_WAVE_RESTORE_ADDR_HI",
2842   "type_ref": "COMPUTE_WAVE_RESTORE_ADDR_HI"
2843  },
2844  {
2845   "chips": ["gfx81"],
2846   "map": {"at": 47252, "to": "mm"},
2847   "name": "COMPUTE_WAVE_RESTORE_CONTROL",
2848   "type_ref": "COMPUTE_WAVE_RESTORE_CONTROL"
2849  },
2850  {
2851   "chips": ["gfx81"],
2852   "map": {"at": 47360, "to": "mm"},
2853   "name": "COMPUTE_USER_DATA_0"
2854  },
2855  {
2856   "chips": ["gfx81"],
2857   "map": {"at": 47364, "to": "mm"},
2858   "name": "COMPUTE_USER_DATA_1"
2859  },
2860  {
2861   "chips": ["gfx81"],
2862   "map": {"at": 47368, "to": "mm"},
2863   "name": "COMPUTE_USER_DATA_2"
2864  },
2865  {
2866   "chips": ["gfx81"],
2867   "map": {"at": 47372, "to": "mm"},
2868   "name": "COMPUTE_USER_DATA_3"
2869  },
2870  {
2871   "chips": ["gfx81"],
2872   "map": {"at": 47376, "to": "mm"},
2873   "name": "COMPUTE_USER_DATA_4"
2874  },
2875  {
2876   "chips": ["gfx81"],
2877   "map": {"at": 47380, "to": "mm"},
2878   "name": "COMPUTE_USER_DATA_5"
2879  },
2880  {
2881   "chips": ["gfx81"],
2882   "map": {"at": 47384, "to": "mm"},
2883   "name": "COMPUTE_USER_DATA_6"
2884  },
2885  {
2886   "chips": ["gfx81"],
2887   "map": {"at": 47388, "to": "mm"},
2888   "name": "COMPUTE_USER_DATA_7"
2889  },
2890  {
2891   "chips": ["gfx81"],
2892   "map": {"at": 47392, "to": "mm"},
2893   "name": "COMPUTE_USER_DATA_8"
2894  },
2895  {
2896   "chips": ["gfx81"],
2897   "map": {"at": 47396, "to": "mm"},
2898   "name": "COMPUTE_USER_DATA_9"
2899  },
2900  {
2901   "chips": ["gfx81"],
2902   "map": {"at": 47400, "to": "mm"},
2903   "name": "COMPUTE_USER_DATA_10"
2904  },
2905  {
2906   "chips": ["gfx81"],
2907   "map": {"at": 47404, "to": "mm"},
2908   "name": "COMPUTE_USER_DATA_11"
2909  },
2910  {
2911   "chips": ["gfx81"],
2912   "map": {"at": 47408, "to": "mm"},
2913   "name": "COMPUTE_USER_DATA_12"
2914  },
2915  {
2916   "chips": ["gfx81"],
2917   "map": {"at": 47412, "to": "mm"},
2918   "name": "COMPUTE_USER_DATA_13"
2919  },
2920  {
2921   "chips": ["gfx81"],
2922   "map": {"at": 47416, "to": "mm"},
2923   "name": "COMPUTE_USER_DATA_14"
2924  },
2925  {
2926   "chips": ["gfx81"],
2927   "map": {"at": 47420, "to": "mm"},
2928   "name": "COMPUTE_USER_DATA_15"
2929  },
2930  {
2931   "chips": ["gfx81"],
2932   "map": {"at": 47612, "to": "mm"},
2933   "name": "COMPUTE_NOWHERE"
2934  },
2935  {
2936   "chips": ["gfx81"],
2937   "map": {"at": 163840, "to": "mm"},
2938   "name": "DB_RENDER_CONTROL",
2939   "type_ref": "DB_RENDER_CONTROL"
2940  },
2941  {
2942   "chips": ["gfx81"],
2943   "map": {"at": 163844, "to": "mm"},
2944   "name": "DB_COUNT_CONTROL",
2945   "type_ref": "DB_COUNT_CONTROL"
2946  },
2947  {
2948   "chips": ["gfx81"],
2949   "map": {"at": 163848, "to": "mm"},
2950   "name": "DB_DEPTH_VIEW",
2951   "type_ref": "DB_DEPTH_VIEW"
2952  },
2953  {
2954   "chips": ["gfx81"],
2955   "map": {"at": 163852, "to": "mm"},
2956   "name": "DB_RENDER_OVERRIDE",
2957   "type_ref": "DB_RENDER_OVERRIDE"
2958  },
2959  {
2960   "chips": ["gfx81"],
2961   "map": {"at": 163856, "to": "mm"},
2962   "name": "DB_RENDER_OVERRIDE2",
2963   "type_ref": "DB_RENDER_OVERRIDE2"
2964  },
2965  {
2966   "chips": ["gfx81"],
2967   "map": {"at": 163860, "to": "mm"},
2968   "name": "DB_HTILE_DATA_BASE"
2969  },
2970  {
2971   "chips": ["gfx81"],
2972   "map": {"at": 163872, "to": "mm"},
2973   "name": "DB_DEPTH_BOUNDS_MIN"
2974  },
2975  {
2976   "chips": ["gfx81"],
2977   "map": {"at": 163876, "to": "mm"},
2978   "name": "DB_DEPTH_BOUNDS_MAX"
2979  },
2980  {
2981   "chips": ["gfx81"],
2982   "map": {"at": 163880, "to": "mm"},
2983   "name": "DB_STENCIL_CLEAR",
2984   "type_ref": "DB_STENCIL_CLEAR"
2985  },
2986  {
2987   "chips": ["gfx81"],
2988   "map": {"at": 163884, "to": "mm"},
2989   "name": "DB_DEPTH_CLEAR"
2990  },
2991  {
2992   "chips": ["gfx81"],
2993   "map": {"at": 163888, "to": "mm"},
2994   "name": "PA_SC_SCREEN_SCISSOR_TL",
2995   "type_ref": "PA_SC_SCREEN_SCISSOR_TL"
2996  },
2997  {
2998   "chips": ["gfx81"],
2999   "map": {"at": 163892, "to": "mm"},
3000   "name": "PA_SC_SCREEN_SCISSOR_BR",
3001   "type_ref": "PA_SC_SCREEN_SCISSOR_BR"
3002  },
3003  {
3004   "chips": ["gfx81"],
3005   "map": {"at": 163900, "to": "mm"},
3006   "name": "DB_DEPTH_INFO",
3007   "type_ref": "DB_DEPTH_INFO"
3008  },
3009  {
3010   "chips": ["gfx81"],
3011   "map": {"at": 163904, "to": "mm"},
3012   "name": "DB_Z_INFO",
3013   "type_ref": "DB_Z_INFO"
3014  },
3015  {
3016   "chips": ["gfx81"],
3017   "map": {"at": 163908, "to": "mm"},
3018   "name": "DB_STENCIL_INFO",
3019   "type_ref": "DB_STENCIL_INFO"
3020  },
3021  {
3022   "chips": ["gfx81"],
3023   "map": {"at": 163912, "to": "mm"},
3024   "name": "DB_Z_READ_BASE"
3025  },
3026  {
3027   "chips": ["gfx81"],
3028   "map": {"at": 163916, "to": "mm"},
3029   "name": "DB_STENCIL_READ_BASE"
3030  },
3031  {
3032   "chips": ["gfx81"],
3033   "map": {"at": 163920, "to": "mm"},
3034   "name": "DB_Z_WRITE_BASE"
3035  },
3036  {
3037   "chips": ["gfx81"],
3038   "map": {"at": 163924, "to": "mm"},
3039   "name": "DB_STENCIL_WRITE_BASE"
3040  },
3041  {
3042   "chips": ["gfx81"],
3043   "map": {"at": 163928, "to": "mm"},
3044   "name": "DB_DEPTH_SIZE",
3045   "type_ref": "DB_DEPTH_SIZE"
3046  },
3047  {
3048   "chips": ["gfx81"],
3049   "map": {"at": 163932, "to": "mm"},
3050   "name": "DB_DEPTH_SLICE",
3051   "type_ref": "DB_DEPTH_SLICE"
3052  },
3053  {
3054   "chips": ["gfx81"],
3055   "map": {"at": 163968, "to": "mm"},
3056   "name": "TA_BC_BASE_ADDR"
3057  },
3058  {
3059   "chips": ["gfx81"],
3060   "map": {"at": 163972, "to": "mm"},
3061   "name": "TA_BC_BASE_ADDR_HI",
3062   "type_ref": "TA_BC_BASE_ADDR_HI"
3063  },
3064  {
3065   "chips": ["gfx81"],
3066   "map": {"at": 164328, "to": "mm"},
3067   "name": "COHER_DEST_BASE_HI_0"
3068  },
3069  {
3070   "chips": ["gfx81"],
3071   "map": {"at": 164332, "to": "mm"},
3072   "name": "COHER_DEST_BASE_HI_1"
3073  },
3074  {
3075   "chips": ["gfx81"],
3076   "map": {"at": 164336, "to": "mm"},
3077   "name": "COHER_DEST_BASE_HI_2"
3078  },
3079  {
3080   "chips": ["gfx81"],
3081   "map": {"at": 164340, "to": "mm"},
3082   "name": "COHER_DEST_BASE_HI_3"
3083  },
3084  {
3085   "chips": ["gfx81"],
3086   "map": {"at": 164344, "to": "mm"},
3087   "name": "COHER_DEST_BASE_2"
3088  },
3089  {
3090   "chips": ["gfx81"],
3091   "map": {"at": 164348, "to": "mm"},
3092   "name": "COHER_DEST_BASE_3"
3093  },
3094  {
3095   "chips": ["gfx81"],
3096   "map": {"at": 164352, "to": "mm"},
3097   "name": "PA_SC_WINDOW_OFFSET",
3098   "type_ref": "PA_SC_WINDOW_OFFSET"
3099  },
3100  {
3101   "chips": ["gfx81"],
3102   "map": {"at": 164356, "to": "mm"},
3103   "name": "PA_SC_WINDOW_SCISSOR_TL",
3104   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3105  },
3106  {
3107   "chips": ["gfx81"],
3108   "map": {"at": 164360, "to": "mm"},
3109   "name": "PA_SC_WINDOW_SCISSOR_BR",
3110   "type_ref": "PA_SC_CLIPRECT_0_BR"
3111  },
3112  {
3113   "chips": ["gfx81"],
3114   "map": {"at": 164364, "to": "mm"},
3115   "name": "PA_SC_CLIPRECT_RULE",
3116   "type_ref": "PA_SC_CLIPRECT_RULE"
3117  },
3118  {
3119   "chips": ["gfx81"],
3120   "map": {"at": 164368, "to": "mm"},
3121   "name": "PA_SC_CLIPRECT_0_TL",
3122   "type_ref": "PA_SC_CLIPRECT_0_TL"
3123  },
3124  {
3125   "chips": ["gfx81"],
3126   "map": {"at": 164372, "to": "mm"},
3127   "name": "PA_SC_CLIPRECT_0_BR",
3128   "type_ref": "PA_SC_CLIPRECT_0_BR"
3129  },
3130  {
3131   "chips": ["gfx81"],
3132   "map": {"at": 164376, "to": "mm"},
3133   "name": "PA_SC_CLIPRECT_1_TL",
3134   "type_ref": "PA_SC_CLIPRECT_0_TL"
3135  },
3136  {
3137   "chips": ["gfx81"],
3138   "map": {"at": 164380, "to": "mm"},
3139   "name": "PA_SC_CLIPRECT_1_BR",
3140   "type_ref": "PA_SC_CLIPRECT_0_BR"
3141  },
3142  {
3143   "chips": ["gfx81"],
3144   "map": {"at": 164384, "to": "mm"},
3145   "name": "PA_SC_CLIPRECT_2_TL",
3146   "type_ref": "PA_SC_CLIPRECT_0_TL"
3147  },
3148  {
3149   "chips": ["gfx81"],
3150   "map": {"at": 164388, "to": "mm"},
3151   "name": "PA_SC_CLIPRECT_2_BR",
3152   "type_ref": "PA_SC_CLIPRECT_0_BR"
3153  },
3154  {
3155   "chips": ["gfx81"],
3156   "map": {"at": 164392, "to": "mm"},
3157   "name": "PA_SC_CLIPRECT_3_TL",
3158   "type_ref": "PA_SC_CLIPRECT_0_TL"
3159  },
3160  {
3161   "chips": ["gfx81"],
3162   "map": {"at": 164396, "to": "mm"},
3163   "name": "PA_SC_CLIPRECT_3_BR",
3164   "type_ref": "PA_SC_CLIPRECT_0_BR"
3165  },
3166  {
3167   "chips": ["gfx81"],
3168   "map": {"at": 164400, "to": "mm"},
3169   "name": "PA_SC_EDGERULE",
3170   "type_ref": "PA_SC_EDGERULE"
3171  },
3172  {
3173   "chips": ["gfx81"],
3174   "map": {"at": 164404, "to": "mm"},
3175   "name": "PA_SU_HARDWARE_SCREEN_OFFSET",
3176   "type_ref": "PA_SU_HARDWARE_SCREEN_OFFSET"
3177  },
3178  {
3179   "chips": ["gfx81"],
3180   "map": {"at": 164408, "to": "mm"},
3181   "name": "CB_TARGET_MASK",
3182   "type_ref": "CB_TARGET_MASK"
3183  },
3184  {
3185   "chips": ["gfx81"],
3186   "map": {"at": 164412, "to": "mm"},
3187   "name": "CB_SHADER_MASK",
3188   "type_ref": "CB_SHADER_MASK"
3189  },
3190  {
3191   "chips": ["gfx81"],
3192   "map": {"at": 164416, "to": "mm"},
3193   "name": "PA_SC_GENERIC_SCISSOR_TL",
3194   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3195  },
3196  {
3197   "chips": ["gfx81"],
3198   "map": {"at": 164420, "to": "mm"},
3199   "name": "PA_SC_GENERIC_SCISSOR_BR",
3200   "type_ref": "PA_SC_CLIPRECT_0_BR"
3201  },
3202  {
3203   "chips": ["gfx81"],
3204   "map": {"at": 164424, "to": "mm"},
3205   "name": "COHER_DEST_BASE_0"
3206  },
3207  {
3208   "chips": ["gfx81"],
3209   "map": {"at": 164428, "to": "mm"},
3210   "name": "COHER_DEST_BASE_1"
3211  },
3212  {
3213   "chips": ["gfx81"],
3214   "map": {"at": 164432, "to": "mm"},
3215   "name": "PA_SC_VPORT_SCISSOR_0_TL",
3216   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3217  },
3218  {
3219   "chips": ["gfx81"],
3220   "map": {"at": 164436, "to": "mm"},
3221   "name": "PA_SC_VPORT_SCISSOR_0_BR",
3222   "type_ref": "PA_SC_CLIPRECT_0_BR"
3223  },
3224  {
3225   "chips": ["gfx81"],
3226   "map": {"at": 164440, "to": "mm"},
3227   "name": "PA_SC_VPORT_SCISSOR_1_TL",
3228   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3229  },
3230  {
3231   "chips": ["gfx81"],
3232   "map": {"at": 164444, "to": "mm"},
3233   "name": "PA_SC_VPORT_SCISSOR_1_BR",
3234   "type_ref": "PA_SC_CLIPRECT_0_BR"
3235  },
3236  {
3237   "chips": ["gfx81"],
3238   "map": {"at": 164448, "to": "mm"},
3239   "name": "PA_SC_VPORT_SCISSOR_2_TL",
3240   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3241  },
3242  {
3243   "chips": ["gfx81"],
3244   "map": {"at": 164452, "to": "mm"},
3245   "name": "PA_SC_VPORT_SCISSOR_2_BR",
3246   "type_ref": "PA_SC_CLIPRECT_0_BR"
3247  },
3248  {
3249   "chips": ["gfx81"],
3250   "map": {"at": 164456, "to": "mm"},
3251   "name": "PA_SC_VPORT_SCISSOR_3_TL",
3252   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3253  },
3254  {
3255   "chips": ["gfx81"],
3256   "map": {"at": 164460, "to": "mm"},
3257   "name": "PA_SC_VPORT_SCISSOR_3_BR",
3258   "type_ref": "PA_SC_CLIPRECT_0_BR"
3259  },
3260  {
3261   "chips": ["gfx81"],
3262   "map": {"at": 164464, "to": "mm"},
3263   "name": "PA_SC_VPORT_SCISSOR_4_TL",
3264   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3265  },
3266  {
3267   "chips": ["gfx81"],
3268   "map": {"at": 164468, "to": "mm"},
3269   "name": "PA_SC_VPORT_SCISSOR_4_BR",
3270   "type_ref": "PA_SC_CLIPRECT_0_BR"
3271  },
3272  {
3273   "chips": ["gfx81"],
3274   "map": {"at": 164472, "to": "mm"},
3275   "name": "PA_SC_VPORT_SCISSOR_5_TL",
3276   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3277  },
3278  {
3279   "chips": ["gfx81"],
3280   "map": {"at": 164476, "to": "mm"},
3281   "name": "PA_SC_VPORT_SCISSOR_5_BR",
3282   "type_ref": "PA_SC_CLIPRECT_0_BR"
3283  },
3284  {
3285   "chips": ["gfx81"],
3286   "map": {"at": 164480, "to": "mm"},
3287   "name": "PA_SC_VPORT_SCISSOR_6_TL",
3288   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3289  },
3290  {
3291   "chips": ["gfx81"],
3292   "map": {"at": 164484, "to": "mm"},
3293   "name": "PA_SC_VPORT_SCISSOR_6_BR",
3294   "type_ref": "PA_SC_CLIPRECT_0_BR"
3295  },
3296  {
3297   "chips": ["gfx81"],
3298   "map": {"at": 164488, "to": "mm"},
3299   "name": "PA_SC_VPORT_SCISSOR_7_TL",
3300   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3301  },
3302  {
3303   "chips": ["gfx81"],
3304   "map": {"at": 164492, "to": "mm"},
3305   "name": "PA_SC_VPORT_SCISSOR_7_BR",
3306   "type_ref": "PA_SC_CLIPRECT_0_BR"
3307  },
3308  {
3309   "chips": ["gfx81"],
3310   "map": {"at": 164496, "to": "mm"},
3311   "name": "PA_SC_VPORT_SCISSOR_8_TL",
3312   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3313  },
3314  {
3315   "chips": ["gfx81"],
3316   "map": {"at": 164500, "to": "mm"},
3317   "name": "PA_SC_VPORT_SCISSOR_8_BR",
3318   "type_ref": "PA_SC_CLIPRECT_0_BR"
3319  },
3320  {
3321   "chips": ["gfx81"],
3322   "map": {"at": 164504, "to": "mm"},
3323   "name": "PA_SC_VPORT_SCISSOR_9_TL",
3324   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3325  },
3326  {
3327   "chips": ["gfx81"],
3328   "map": {"at": 164508, "to": "mm"},
3329   "name": "PA_SC_VPORT_SCISSOR_9_BR",
3330   "type_ref": "PA_SC_CLIPRECT_0_BR"
3331  },
3332  {
3333   "chips": ["gfx81"],
3334   "map": {"at": 164512, "to": "mm"},
3335   "name": "PA_SC_VPORT_SCISSOR_10_TL",
3336   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3337  },
3338  {
3339   "chips": ["gfx81"],
3340   "map": {"at": 164516, "to": "mm"},
3341   "name": "PA_SC_VPORT_SCISSOR_10_BR",
3342   "type_ref": "PA_SC_CLIPRECT_0_BR"
3343  },
3344  {
3345   "chips": ["gfx81"],
3346   "map": {"at": 164520, "to": "mm"},
3347   "name": "PA_SC_VPORT_SCISSOR_11_TL",
3348   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3349  },
3350  {
3351   "chips": ["gfx81"],
3352   "map": {"at": 164524, "to": "mm"},
3353   "name": "PA_SC_VPORT_SCISSOR_11_BR",
3354   "type_ref": "PA_SC_CLIPRECT_0_BR"
3355  },
3356  {
3357   "chips": ["gfx81"],
3358   "map": {"at": 164528, "to": "mm"},
3359   "name": "PA_SC_VPORT_SCISSOR_12_TL",
3360   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3361  },
3362  {
3363   "chips": ["gfx81"],
3364   "map": {"at": 164532, "to": "mm"},
3365   "name": "PA_SC_VPORT_SCISSOR_12_BR",
3366   "type_ref": "PA_SC_CLIPRECT_0_BR"
3367  },
3368  {
3369   "chips": ["gfx81"],
3370   "map": {"at": 164536, "to": "mm"},
3371   "name": "PA_SC_VPORT_SCISSOR_13_TL",
3372   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3373  },
3374  {
3375   "chips": ["gfx81"],
3376   "map": {"at": 164540, "to": "mm"},
3377   "name": "PA_SC_VPORT_SCISSOR_13_BR",
3378   "type_ref": "PA_SC_CLIPRECT_0_BR"
3379  },
3380  {
3381   "chips": ["gfx81"],
3382   "map": {"at": 164544, "to": "mm"},
3383   "name": "PA_SC_VPORT_SCISSOR_14_TL",
3384   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3385  },
3386  {
3387   "chips": ["gfx81"],
3388   "map": {"at": 164548, "to": "mm"},
3389   "name": "PA_SC_VPORT_SCISSOR_14_BR",
3390   "type_ref": "PA_SC_CLIPRECT_0_BR"
3391  },
3392  {
3393   "chips": ["gfx81"],
3394   "map": {"at": 164552, "to": "mm"},
3395   "name": "PA_SC_VPORT_SCISSOR_15_TL",
3396   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3397  },
3398  {
3399   "chips": ["gfx81"],
3400   "map": {"at": 164556, "to": "mm"},
3401   "name": "PA_SC_VPORT_SCISSOR_15_BR",
3402   "type_ref": "PA_SC_CLIPRECT_0_BR"
3403  },
3404  {
3405   "chips": ["gfx81"],
3406   "map": {"at": 164560, "to": "mm"},
3407   "name": "PA_SC_VPORT_ZMIN_0"
3408  },
3409  {
3410   "chips": ["gfx81"],
3411   "map": {"at": 164564, "to": "mm"},
3412   "name": "PA_SC_VPORT_ZMAX_0"
3413  },
3414  {
3415   "chips": ["gfx81"],
3416   "map": {"at": 164568, "to": "mm"},
3417   "name": "PA_SC_VPORT_ZMIN_1"
3418  },
3419  {
3420   "chips": ["gfx81"],
3421   "map": {"at": 164572, "to": "mm"},
3422   "name": "PA_SC_VPORT_ZMAX_1"
3423  },
3424  {
3425   "chips": ["gfx81"],
3426   "map": {"at": 164576, "to": "mm"},
3427   "name": "PA_SC_VPORT_ZMIN_2"
3428  },
3429  {
3430   "chips": ["gfx81"],
3431   "map": {"at": 164580, "to": "mm"},
3432   "name": "PA_SC_VPORT_ZMAX_2"
3433  },
3434  {
3435   "chips": ["gfx81"],
3436   "map": {"at": 164584, "to": "mm"},
3437   "name": "PA_SC_VPORT_ZMIN_3"
3438  },
3439  {
3440   "chips": ["gfx81"],
3441   "map": {"at": 164588, "to": "mm"},
3442   "name": "PA_SC_VPORT_ZMAX_3"
3443  },
3444  {
3445   "chips": ["gfx81"],
3446   "map": {"at": 164592, "to": "mm"},
3447   "name": "PA_SC_VPORT_ZMIN_4"
3448  },
3449  {
3450   "chips": ["gfx81"],
3451   "map": {"at": 164596, "to": "mm"},
3452   "name": "PA_SC_VPORT_ZMAX_4"
3453  },
3454  {
3455   "chips": ["gfx81"],
3456   "map": {"at": 164600, "to": "mm"},
3457   "name": "PA_SC_VPORT_ZMIN_5"
3458  },
3459  {
3460   "chips": ["gfx81"],
3461   "map": {"at": 164604, "to": "mm"},
3462   "name": "PA_SC_VPORT_ZMAX_5"
3463  },
3464  {
3465   "chips": ["gfx81"],
3466   "map": {"at": 164608, "to": "mm"},
3467   "name": "PA_SC_VPORT_ZMIN_6"
3468  },
3469  {
3470   "chips": ["gfx81"],
3471   "map": {"at": 164612, "to": "mm"},
3472   "name": "PA_SC_VPORT_ZMAX_6"
3473  },
3474  {
3475   "chips": ["gfx81"],
3476   "map": {"at": 164616, "to": "mm"},
3477   "name": "PA_SC_VPORT_ZMIN_7"
3478  },
3479  {
3480   "chips": ["gfx81"],
3481   "map": {"at": 164620, "to": "mm"},
3482   "name": "PA_SC_VPORT_ZMAX_7"
3483  },
3484  {
3485   "chips": ["gfx81"],
3486   "map": {"at": 164624, "to": "mm"},
3487   "name": "PA_SC_VPORT_ZMIN_8"
3488  },
3489  {
3490   "chips": ["gfx81"],
3491   "map": {"at": 164628, "to": "mm"},
3492   "name": "PA_SC_VPORT_ZMAX_8"
3493  },
3494  {
3495   "chips": ["gfx81"],
3496   "map": {"at": 164632, "to": "mm"},
3497   "name": "PA_SC_VPORT_ZMIN_9"
3498  },
3499  {
3500   "chips": ["gfx81"],
3501   "map": {"at": 164636, "to": "mm"},
3502   "name": "PA_SC_VPORT_ZMAX_9"
3503  },
3504  {
3505   "chips": ["gfx81"],
3506   "map": {"at": 164640, "to": "mm"},
3507   "name": "PA_SC_VPORT_ZMIN_10"
3508  },
3509  {
3510   "chips": ["gfx81"],
3511   "map": {"at": 164644, "to": "mm"},
3512   "name": "PA_SC_VPORT_ZMAX_10"
3513  },
3514  {
3515   "chips": ["gfx81"],
3516   "map": {"at": 164648, "to": "mm"},
3517   "name": "PA_SC_VPORT_ZMIN_11"
3518  },
3519  {
3520   "chips": ["gfx81"],
3521   "map": {"at": 164652, "to": "mm"},
3522   "name": "PA_SC_VPORT_ZMAX_11"
3523  },
3524  {
3525   "chips": ["gfx81"],
3526   "map": {"at": 164656, "to": "mm"},
3527   "name": "PA_SC_VPORT_ZMIN_12"
3528  },
3529  {
3530   "chips": ["gfx81"],
3531   "map": {"at": 164660, "to": "mm"},
3532   "name": "PA_SC_VPORT_ZMAX_12"
3533  },
3534  {
3535   "chips": ["gfx81"],
3536   "map": {"at": 164664, "to": "mm"},
3537   "name": "PA_SC_VPORT_ZMIN_13"
3538  },
3539  {
3540   "chips": ["gfx81"],
3541   "map": {"at": 164668, "to": "mm"},
3542   "name": "PA_SC_VPORT_ZMAX_13"
3543  },
3544  {
3545   "chips": ["gfx81"],
3546   "map": {"at": 164672, "to": "mm"},
3547   "name": "PA_SC_VPORT_ZMIN_14"
3548  },
3549  {
3550   "chips": ["gfx81"],
3551   "map": {"at": 164676, "to": "mm"},
3552   "name": "PA_SC_VPORT_ZMAX_14"
3553  },
3554  {
3555   "chips": ["gfx81"],
3556   "map": {"at": 164680, "to": "mm"},
3557   "name": "PA_SC_VPORT_ZMIN_15"
3558  },
3559  {
3560   "chips": ["gfx81"],
3561   "map": {"at": 164684, "to": "mm"},
3562   "name": "PA_SC_VPORT_ZMAX_15"
3563  },
3564  {
3565   "chips": ["gfx81"],
3566   "map": {"at": 164688, "to": "mm"},
3567   "name": "PA_SC_RASTER_CONFIG",
3568   "type_ref": "PA_SC_RASTER_CONFIG"
3569  },
3570  {
3571   "chips": ["gfx81"],
3572   "map": {"at": 164692, "to": "mm"},
3573   "name": "PA_SC_RASTER_CONFIG_1",
3574   "type_ref": "PA_SC_RASTER_CONFIG_1"
3575  },
3576  {
3577   "chips": ["gfx81"],
3578   "map": {"at": 164696, "to": "mm"},
3579   "name": "PA_SC_SCREEN_EXTENT_CONTROL",
3580   "type_ref": "PA_SC_SCREEN_EXTENT_CONTROL"
3581  },
3582  {
3583   "chips": ["gfx81"],
3584   "map": {"at": 164704, "to": "mm"},
3585   "name": "CP_PERFMON_CNTX_CNTL",
3586   "type_ref": "CP_PERFMON_CNTX_CNTL"
3587  },
3588  {
3589   "chips": ["gfx81"],
3590   "map": {"at": 164708, "to": "mm"},
3591   "name": "CP_RINGID",
3592   "type_ref": "CP_RINGID"
3593  },
3594  {
3595   "chips": ["gfx81"],
3596   "map": {"at": 164712, "to": "mm"},
3597   "name": "CP_VMID",
3598   "type_ref": "CP_VMID"
3599  },
3600  {
3601   "chips": ["gfx81"],
3602   "map": {"at": 164864, "to": "mm"},
3603   "name": "VGT_MAX_VTX_INDX"
3604  },
3605  {
3606   "chips": ["gfx81"],
3607   "map": {"at": 164868, "to": "mm"},
3608   "name": "VGT_MIN_VTX_INDX"
3609  },
3610  {
3611   "chips": ["gfx81"],
3612   "map": {"at": 164872, "to": "mm"},
3613   "name": "VGT_INDX_OFFSET"
3614  },
3615  {
3616   "chips": ["gfx81"],
3617   "map": {"at": 164876, "to": "mm"},
3618   "name": "VGT_MULTI_PRIM_IB_RESET_INDX"
3619  },
3620  {
3621   "chips": ["gfx81"],
3622   "map": {"at": 164884, "to": "mm"},
3623   "name": "CB_BLEND_RED"
3624  },
3625  {
3626   "chips": ["gfx81"],
3627   "map": {"at": 164888, "to": "mm"},
3628   "name": "CB_BLEND_GREEN"
3629  },
3630  {
3631   "chips": ["gfx81"],
3632   "map": {"at": 164892, "to": "mm"},
3633   "name": "CB_BLEND_BLUE"
3634  },
3635  {
3636   "chips": ["gfx81"],
3637   "map": {"at": 164896, "to": "mm"},
3638   "name": "CB_BLEND_ALPHA"
3639  },
3640  {
3641   "chips": ["gfx81"],
3642   "map": {"at": 164900, "to": "mm"},
3643   "name": "CB_DCC_CONTROL",
3644   "type_ref": "CB_DCC_CONTROL"
3645  },
3646  {
3647   "chips": ["gfx81"],
3648   "map": {"at": 164908, "to": "mm"},
3649   "name": "DB_STENCIL_CONTROL",
3650   "type_ref": "DB_STENCIL_CONTROL"
3651  },
3652  {
3653   "chips": ["gfx81"],
3654   "map": {"at": 164912, "to": "mm"},
3655   "name": "DB_STENCILREFMASK",
3656   "type_ref": "DB_STENCILREFMASK"
3657  },
3658  {
3659   "chips": ["gfx81"],
3660   "map": {"at": 164916, "to": "mm"},
3661   "name": "DB_STENCILREFMASK_BF",
3662   "type_ref": "DB_STENCILREFMASK_BF"
3663  },
3664  {
3665   "chips": ["gfx81"],
3666   "map": {"at": 164924, "to": "mm"},
3667   "name": "PA_CL_VPORT_XSCALE"
3668  },
3669  {
3670   "chips": ["gfx81"],
3671   "map": {"at": 164928, "to": "mm"},
3672   "name": "PA_CL_VPORT_XOFFSET"
3673  },
3674  {
3675   "chips": ["gfx81"],
3676   "map": {"at": 164932, "to": "mm"},
3677   "name": "PA_CL_VPORT_YSCALE"
3678  },
3679  {
3680   "chips": ["gfx81"],
3681   "map": {"at": 164936, "to": "mm"},
3682   "name": "PA_CL_VPORT_YOFFSET"
3683  },
3684  {
3685   "chips": ["gfx81"],
3686   "map": {"at": 164940, "to": "mm"},
3687   "name": "PA_CL_VPORT_ZSCALE"
3688  },
3689  {
3690   "chips": ["gfx81"],
3691   "map": {"at": 164944, "to": "mm"},
3692   "name": "PA_CL_VPORT_ZOFFSET"
3693  },
3694  {
3695   "chips": ["gfx81"],
3696   "map": {"at": 164948, "to": "mm"},
3697   "name": "PA_CL_VPORT_XSCALE_1"
3698  },
3699  {
3700   "chips": ["gfx81"],
3701   "map": {"at": 164952, "to": "mm"},
3702   "name": "PA_CL_VPORT_XOFFSET_1"
3703  },
3704  {
3705   "chips": ["gfx81"],
3706   "map": {"at": 164956, "to": "mm"},
3707   "name": "PA_CL_VPORT_YSCALE_1"
3708  },
3709  {
3710   "chips": ["gfx81"],
3711   "map": {"at": 164960, "to": "mm"},
3712   "name": "PA_CL_VPORT_YOFFSET_1"
3713  },
3714  {
3715   "chips": ["gfx81"],
3716   "map": {"at": 164964, "to": "mm"},
3717   "name": "PA_CL_VPORT_ZSCALE_1"
3718  },
3719  {
3720   "chips": ["gfx81"],
3721   "map": {"at": 164968, "to": "mm"},
3722   "name": "PA_CL_VPORT_ZOFFSET_1"
3723  },
3724  {
3725   "chips": ["gfx81"],
3726   "map": {"at": 164972, "to": "mm"},
3727   "name": "PA_CL_VPORT_XSCALE_2"
3728  },
3729  {
3730   "chips": ["gfx81"],
3731   "map": {"at": 164976, "to": "mm"},
3732   "name": "PA_CL_VPORT_XOFFSET_2"
3733  },
3734  {
3735   "chips": ["gfx81"],
3736   "map": {"at": 164980, "to": "mm"},
3737   "name": "PA_CL_VPORT_YSCALE_2"
3738  },
3739  {
3740   "chips": ["gfx81"],
3741   "map": {"at": 164984, "to": "mm"},
3742   "name": "PA_CL_VPORT_YOFFSET_2"
3743  },
3744  {
3745   "chips": ["gfx81"],
3746   "map": {"at": 164988, "to": "mm"},
3747   "name": "PA_CL_VPORT_ZSCALE_2"
3748  },
3749  {
3750   "chips": ["gfx81"],
3751   "map": {"at": 164992, "to": "mm"},
3752   "name": "PA_CL_VPORT_ZOFFSET_2"
3753  },
3754  {
3755   "chips": ["gfx81"],
3756   "map": {"at": 164996, "to": "mm"},
3757   "name": "PA_CL_VPORT_XSCALE_3"
3758  },
3759  {
3760   "chips": ["gfx81"],
3761   "map": {"at": 165000, "to": "mm"},
3762   "name": "PA_CL_VPORT_XOFFSET_3"
3763  },
3764  {
3765   "chips": ["gfx81"],
3766   "map": {"at": 165004, "to": "mm"},
3767   "name": "PA_CL_VPORT_YSCALE_3"
3768  },
3769  {
3770   "chips": ["gfx81"],
3771   "map": {"at": 165008, "to": "mm"},
3772   "name": "PA_CL_VPORT_YOFFSET_3"
3773  },
3774  {
3775   "chips": ["gfx81"],
3776   "map": {"at": 165012, "to": "mm"},
3777   "name": "PA_CL_VPORT_ZSCALE_3"
3778  },
3779  {
3780   "chips": ["gfx81"],
3781   "map": {"at": 165016, "to": "mm"},
3782   "name": "PA_CL_VPORT_ZOFFSET_3"
3783  },
3784  {
3785   "chips": ["gfx81"],
3786   "map": {"at": 165020, "to": "mm"},
3787   "name": "PA_CL_VPORT_XSCALE_4"
3788  },
3789  {
3790   "chips": ["gfx81"],
3791   "map": {"at": 165024, "to": "mm"},
3792   "name": "PA_CL_VPORT_XOFFSET_4"
3793  },
3794  {
3795   "chips": ["gfx81"],
3796   "map": {"at": 165028, "to": "mm"},
3797   "name": "PA_CL_VPORT_YSCALE_4"
3798  },
3799  {
3800   "chips": ["gfx81"],
3801   "map": {"at": 165032, "to": "mm"},
3802   "name": "PA_CL_VPORT_YOFFSET_4"
3803  },
3804  {
3805   "chips": ["gfx81"],
3806   "map": {"at": 165036, "to": "mm"},
3807   "name": "PA_CL_VPORT_ZSCALE_4"
3808  },
3809  {
3810   "chips": ["gfx81"],
3811   "map": {"at": 165040, "to": "mm"},
3812   "name": "PA_CL_VPORT_ZOFFSET_4"
3813  },
3814  {
3815   "chips": ["gfx81"],
3816   "map": {"at": 165044, "to": "mm"},
3817   "name": "PA_CL_VPORT_XSCALE_5"
3818  },
3819  {
3820   "chips": ["gfx81"],
3821   "map": {"at": 165048, "to": "mm"},
3822   "name": "PA_CL_VPORT_XOFFSET_5"
3823  },
3824  {
3825   "chips": ["gfx81"],
3826   "map": {"at": 165052, "to": "mm"},
3827   "name": "PA_CL_VPORT_YSCALE_5"
3828  },
3829  {
3830   "chips": ["gfx81"],
3831   "map": {"at": 165056, "to": "mm"},
3832   "name": "PA_CL_VPORT_YOFFSET_5"
3833  },
3834  {
3835   "chips": ["gfx81"],
3836   "map": {"at": 165060, "to": "mm"},
3837   "name": "PA_CL_VPORT_ZSCALE_5"
3838  },
3839  {
3840   "chips": ["gfx81"],
3841   "map": {"at": 165064, "to": "mm"},
3842   "name": "PA_CL_VPORT_ZOFFSET_5"
3843  },
3844  {
3845   "chips": ["gfx81"],
3846   "map": {"at": 165068, "to": "mm"},
3847   "name": "PA_CL_VPORT_XSCALE_6"
3848  },
3849  {
3850   "chips": ["gfx81"],
3851   "map": {"at": 165072, "to": "mm"},
3852   "name": "PA_CL_VPORT_XOFFSET_6"
3853  },
3854  {
3855   "chips": ["gfx81"],
3856   "map": {"at": 165076, "to": "mm"},
3857   "name": "PA_CL_VPORT_YSCALE_6"
3858  },
3859  {
3860   "chips": ["gfx81"],
3861   "map": {"at": 165080, "to": "mm"},
3862   "name": "PA_CL_VPORT_YOFFSET_6"
3863  },
3864  {
3865   "chips": ["gfx81"],
3866   "map": {"at": 165084, "to": "mm"},
3867   "name": "PA_CL_VPORT_ZSCALE_6"
3868  },
3869  {
3870   "chips": ["gfx81"],
3871   "map": {"at": 165088, "to": "mm"},
3872   "name": "PA_CL_VPORT_ZOFFSET_6"
3873  },
3874  {
3875   "chips": ["gfx81"],
3876   "map": {"at": 165092, "to": "mm"},
3877   "name": "PA_CL_VPORT_XSCALE_7"
3878  },
3879  {
3880   "chips": ["gfx81"],
3881   "map": {"at": 165096, "to": "mm"},
3882   "name": "PA_CL_VPORT_XOFFSET_7"
3883  },
3884  {
3885   "chips": ["gfx81"],
3886   "map": {"at": 165100, "to": "mm"},
3887   "name": "PA_CL_VPORT_YSCALE_7"
3888  },
3889  {
3890   "chips": ["gfx81"],
3891   "map": {"at": 165104, "to": "mm"},
3892   "name": "PA_CL_VPORT_YOFFSET_7"
3893  },
3894  {
3895   "chips": ["gfx81"],
3896   "map": {"at": 165108, "to": "mm"},
3897   "name": "PA_CL_VPORT_ZSCALE_7"
3898  },
3899  {
3900   "chips": ["gfx81"],
3901   "map": {"at": 165112, "to": "mm"},
3902   "name": "PA_CL_VPORT_ZOFFSET_7"
3903  },
3904  {
3905   "chips": ["gfx81"],
3906   "map": {"at": 165116, "to": "mm"},
3907   "name": "PA_CL_VPORT_XSCALE_8"
3908  },
3909  {
3910   "chips": ["gfx81"],
3911   "map": {"at": 165120, "to": "mm"},
3912   "name": "PA_CL_VPORT_XOFFSET_8"
3913  },
3914  {
3915   "chips": ["gfx81"],
3916   "map": {"at": 165124, "to": "mm"},
3917   "name": "PA_CL_VPORT_YSCALE_8"
3918  },
3919  {
3920   "chips": ["gfx81"],
3921   "map": {"at": 165128, "to": "mm"},
3922   "name": "PA_CL_VPORT_YOFFSET_8"
3923  },
3924  {
3925   "chips": ["gfx81"],
3926   "map": {"at": 165132, "to": "mm"},
3927   "name": "PA_CL_VPORT_ZSCALE_8"
3928  },
3929  {
3930   "chips": ["gfx81"],
3931   "map": {"at": 165136, "to": "mm"},
3932   "name": "PA_CL_VPORT_ZOFFSET_8"
3933  },
3934  {
3935   "chips": ["gfx81"],
3936   "map": {"at": 165140, "to": "mm"},
3937   "name": "PA_CL_VPORT_XSCALE_9"
3938  },
3939  {
3940   "chips": ["gfx81"],
3941   "map": {"at": 165144, "to": "mm"},
3942   "name": "PA_CL_VPORT_XOFFSET_9"
3943  },
3944  {
3945   "chips": ["gfx81"],
3946   "map": {"at": 165148, "to": "mm"},
3947   "name": "PA_CL_VPORT_YSCALE_9"
3948  },
3949  {
3950   "chips": ["gfx81"],
3951   "map": {"at": 165152, "to": "mm"},
3952   "name": "PA_CL_VPORT_YOFFSET_9"
3953  },
3954  {
3955   "chips": ["gfx81"],
3956   "map": {"at": 165156, "to": "mm"},
3957   "name": "PA_CL_VPORT_ZSCALE_9"
3958  },
3959  {
3960   "chips": ["gfx81"],
3961   "map": {"at": 165160, "to": "mm"},
3962   "name": "PA_CL_VPORT_ZOFFSET_9"
3963  },
3964  {
3965   "chips": ["gfx81"],
3966   "map": {"at": 165164, "to": "mm"},
3967   "name": "PA_CL_VPORT_XSCALE_10"
3968  },
3969  {
3970   "chips": ["gfx81"],
3971   "map": {"at": 165168, "to": "mm"},
3972   "name": "PA_CL_VPORT_XOFFSET_10"
3973  },
3974  {
3975   "chips": ["gfx81"],
3976   "map": {"at": 165172, "to": "mm"},
3977   "name": "PA_CL_VPORT_YSCALE_10"
3978  },
3979  {
3980   "chips": ["gfx81"],
3981   "map": {"at": 165176, "to": "mm"},
3982   "name": "PA_CL_VPORT_YOFFSET_10"
3983  },
3984  {
3985   "chips": ["gfx81"],
3986   "map": {"at": 165180, "to": "mm"},
3987   "name": "PA_CL_VPORT_ZSCALE_10"
3988  },
3989  {
3990   "chips": ["gfx81"],
3991   "map": {"at": 165184, "to": "mm"},
3992   "name": "PA_CL_VPORT_ZOFFSET_10"
3993  },
3994  {
3995   "chips": ["gfx81"],
3996   "map": {"at": 165188, "to": "mm"},
3997   "name": "PA_CL_VPORT_XSCALE_11"
3998  },
3999  {
4000   "chips": ["gfx81"],
4001   "map": {"at": 165192, "to": "mm"},
4002   "name": "PA_CL_VPORT_XOFFSET_11"
4003  },
4004  {
4005   "chips": ["gfx81"],
4006   "map": {"at": 165196, "to": "mm"},
4007   "name": "PA_CL_VPORT_YSCALE_11"
4008  },
4009  {
4010   "chips": ["gfx81"],
4011   "map": {"at": 165200, "to": "mm"},
4012   "name": "PA_CL_VPORT_YOFFSET_11"
4013  },
4014  {
4015   "chips": ["gfx81"],
4016   "map": {"at": 165204, "to": "mm"},
4017   "name": "PA_CL_VPORT_ZSCALE_11"
4018  },
4019  {
4020   "chips": ["gfx81"],
4021   "map": {"at": 165208, "to": "mm"},
4022   "name": "PA_CL_VPORT_ZOFFSET_11"
4023  },
4024  {
4025   "chips": ["gfx81"],
4026   "map": {"at": 165212, "to": "mm"},
4027   "name": "PA_CL_VPORT_XSCALE_12"
4028  },
4029  {
4030   "chips": ["gfx81"],
4031   "map": {"at": 165216, "to": "mm"},
4032   "name": "PA_CL_VPORT_XOFFSET_12"
4033  },
4034  {
4035   "chips": ["gfx81"],
4036   "map": {"at": 165220, "to": "mm"},
4037   "name": "PA_CL_VPORT_YSCALE_12"
4038  },
4039  {
4040   "chips": ["gfx81"],
4041   "map": {"at": 165224, "to": "mm"},
4042   "name": "PA_CL_VPORT_YOFFSET_12"
4043  },
4044  {
4045   "chips": ["gfx81"],
4046   "map": {"at": 165228, "to": "mm"},
4047   "name": "PA_CL_VPORT_ZSCALE_12"
4048  },
4049  {
4050   "chips": ["gfx81"],
4051   "map": {"at": 165232, "to": "mm"},
4052   "name": "PA_CL_VPORT_ZOFFSET_12"
4053  },
4054  {
4055   "chips": ["gfx81"],
4056   "map": {"at": 165236, "to": "mm"},
4057   "name": "PA_CL_VPORT_XSCALE_13"
4058  },
4059  {
4060   "chips": ["gfx81"],
4061   "map": {"at": 165240, "to": "mm"},
4062   "name": "PA_CL_VPORT_XOFFSET_13"
4063  },
4064  {
4065   "chips": ["gfx81"],
4066   "map": {"at": 165244, "to": "mm"},
4067   "name": "PA_CL_VPORT_YSCALE_13"
4068  },
4069  {
4070   "chips": ["gfx81"],
4071   "map": {"at": 165248, "to": "mm"},
4072   "name": "PA_CL_VPORT_YOFFSET_13"
4073  },
4074  {
4075   "chips": ["gfx81"],
4076   "map": {"at": 165252, "to": "mm"},
4077   "name": "PA_CL_VPORT_ZSCALE_13"
4078  },
4079  {
4080   "chips": ["gfx81"],
4081   "map": {"at": 165256, "to": "mm"},
4082   "name": "PA_CL_VPORT_ZOFFSET_13"
4083  },
4084  {
4085   "chips": ["gfx81"],
4086   "map": {"at": 165260, "to": "mm"},
4087   "name": "PA_CL_VPORT_XSCALE_14"
4088  },
4089  {
4090   "chips": ["gfx81"],
4091   "map": {"at": 165264, "to": "mm"},
4092   "name": "PA_CL_VPORT_XOFFSET_14"
4093  },
4094  {
4095   "chips": ["gfx81"],
4096   "map": {"at": 165268, "to": "mm"},
4097   "name": "PA_CL_VPORT_YSCALE_14"
4098  },
4099  {
4100   "chips": ["gfx81"],
4101   "map": {"at": 165272, "to": "mm"},
4102   "name": "PA_CL_VPORT_YOFFSET_14"
4103  },
4104  {
4105   "chips": ["gfx81"],
4106   "map": {"at": 165276, "to": "mm"},
4107   "name": "PA_CL_VPORT_ZSCALE_14"
4108  },
4109  {
4110   "chips": ["gfx81"],
4111   "map": {"at": 165280, "to": "mm"},
4112   "name": "PA_CL_VPORT_ZOFFSET_14"
4113  },
4114  {
4115   "chips": ["gfx81"],
4116   "map": {"at": 165284, "to": "mm"},
4117   "name": "PA_CL_VPORT_XSCALE_15"
4118  },
4119  {
4120   "chips": ["gfx81"],
4121   "map": {"at": 165288, "to": "mm"},
4122   "name": "PA_CL_VPORT_XOFFSET_15"
4123  },
4124  {
4125   "chips": ["gfx81"],
4126   "map": {"at": 165292, "to": "mm"},
4127   "name": "PA_CL_VPORT_YSCALE_15"
4128  },
4129  {
4130   "chips": ["gfx81"],
4131   "map": {"at": 165296, "to": "mm"},
4132   "name": "PA_CL_VPORT_YOFFSET_15"
4133  },
4134  {
4135   "chips": ["gfx81"],
4136   "map": {"at": 165300, "to": "mm"},
4137   "name": "PA_CL_VPORT_ZSCALE_15"
4138  },
4139  {
4140   "chips": ["gfx81"],
4141   "map": {"at": 165304, "to": "mm"},
4142   "name": "PA_CL_VPORT_ZOFFSET_15"
4143  },
4144  {
4145   "chips": ["gfx81"],
4146   "map": {"at": 165308, "to": "mm"},
4147   "name": "PA_CL_UCP_0_X"
4148  },
4149  {
4150   "chips": ["gfx81"],
4151   "map": {"at": 165312, "to": "mm"},
4152   "name": "PA_CL_UCP_0_Y"
4153  },
4154  {
4155   "chips": ["gfx81"],
4156   "map": {"at": 165316, "to": "mm"},
4157   "name": "PA_CL_UCP_0_Z"
4158  },
4159  {
4160   "chips": ["gfx81"],
4161   "map": {"at": 165320, "to": "mm"},
4162   "name": "PA_CL_UCP_0_W"
4163  },
4164  {
4165   "chips": ["gfx81"],
4166   "map": {"at": 165324, "to": "mm"},
4167   "name": "PA_CL_UCP_1_X"
4168  },
4169  {
4170   "chips": ["gfx81"],
4171   "map": {"at": 165328, "to": "mm"},
4172   "name": "PA_CL_UCP_1_Y"
4173  },
4174  {
4175   "chips": ["gfx81"],
4176   "map": {"at": 165332, "to": "mm"},
4177   "name": "PA_CL_UCP_1_Z"
4178  },
4179  {
4180   "chips": ["gfx81"],
4181   "map": {"at": 165336, "to": "mm"},
4182   "name": "PA_CL_UCP_1_W"
4183  },
4184  {
4185   "chips": ["gfx81"],
4186   "map": {"at": 165340, "to": "mm"},
4187   "name": "PA_CL_UCP_2_X"
4188  },
4189  {
4190   "chips": ["gfx81"],
4191   "map": {"at": 165344, "to": "mm"},
4192   "name": "PA_CL_UCP_2_Y"
4193  },
4194  {
4195   "chips": ["gfx81"],
4196   "map": {"at": 165348, "to": "mm"},
4197   "name": "PA_CL_UCP_2_Z"
4198  },
4199  {
4200   "chips": ["gfx81"],
4201   "map": {"at": 165352, "to": "mm"},
4202   "name": "PA_CL_UCP_2_W"
4203  },
4204  {
4205   "chips": ["gfx81"],
4206   "map": {"at": 165356, "to": "mm"},
4207   "name": "PA_CL_UCP_3_X"
4208  },
4209  {
4210   "chips": ["gfx81"],
4211   "map": {"at": 165360, "to": "mm"},
4212   "name": "PA_CL_UCP_3_Y"
4213  },
4214  {
4215   "chips": ["gfx81"],
4216   "map": {"at": 165364, "to": "mm"},
4217   "name": "PA_CL_UCP_3_Z"
4218  },
4219  {
4220   "chips": ["gfx81"],
4221   "map": {"at": 165368, "to": "mm"},
4222   "name": "PA_CL_UCP_3_W"
4223  },
4224  {
4225   "chips": ["gfx81"],
4226   "map": {"at": 165372, "to": "mm"},
4227   "name": "PA_CL_UCP_4_X"
4228  },
4229  {
4230   "chips": ["gfx81"],
4231   "map": {"at": 165376, "to": "mm"},
4232   "name": "PA_CL_UCP_4_Y"
4233  },
4234  {
4235   "chips": ["gfx81"],
4236   "map": {"at": 165380, "to": "mm"},
4237   "name": "PA_CL_UCP_4_Z"
4238  },
4239  {
4240   "chips": ["gfx81"],
4241   "map": {"at": 165384, "to": "mm"},
4242   "name": "PA_CL_UCP_4_W"
4243  },
4244  {
4245   "chips": ["gfx81"],
4246   "map": {"at": 165388, "to": "mm"},
4247   "name": "PA_CL_UCP_5_X"
4248  },
4249  {
4250   "chips": ["gfx81"],
4251   "map": {"at": 165392, "to": "mm"},
4252   "name": "PA_CL_UCP_5_Y"
4253  },
4254  {
4255   "chips": ["gfx81"],
4256   "map": {"at": 165396, "to": "mm"},
4257   "name": "PA_CL_UCP_5_Z"
4258  },
4259  {
4260   "chips": ["gfx81"],
4261   "map": {"at": 165400, "to": "mm"},
4262   "name": "PA_CL_UCP_5_W"
4263  },
4264  {
4265   "chips": ["gfx81"],
4266   "map": {"at": 165444, "to": "mm"},
4267   "name": "SPI_PS_INPUT_CNTL_0",
4268   "type_ref": "SPI_PS_INPUT_CNTL_0"
4269  },
4270  {
4271   "chips": ["gfx81"],
4272   "map": {"at": 165448, "to": "mm"},
4273   "name": "SPI_PS_INPUT_CNTL_1",
4274   "type_ref": "SPI_PS_INPUT_CNTL_0"
4275  },
4276  {
4277   "chips": ["gfx81"],
4278   "map": {"at": 165452, "to": "mm"},
4279   "name": "SPI_PS_INPUT_CNTL_2",
4280   "type_ref": "SPI_PS_INPUT_CNTL_0"
4281  },
4282  {
4283   "chips": ["gfx81"],
4284   "map": {"at": 165456, "to": "mm"},
4285   "name": "SPI_PS_INPUT_CNTL_3",
4286   "type_ref": "SPI_PS_INPUT_CNTL_0"
4287  },
4288  {
4289   "chips": ["gfx81"],
4290   "map": {"at": 165460, "to": "mm"},
4291   "name": "SPI_PS_INPUT_CNTL_4",
4292   "type_ref": "SPI_PS_INPUT_CNTL_0"
4293  },
4294  {
4295   "chips": ["gfx81"],
4296   "map": {"at": 165464, "to": "mm"},
4297   "name": "SPI_PS_INPUT_CNTL_5",
4298   "type_ref": "SPI_PS_INPUT_CNTL_0"
4299  },
4300  {
4301   "chips": ["gfx81"],
4302   "map": {"at": 165468, "to": "mm"},
4303   "name": "SPI_PS_INPUT_CNTL_6",
4304   "type_ref": "SPI_PS_INPUT_CNTL_0"
4305  },
4306  {
4307   "chips": ["gfx81"],
4308   "map": {"at": 165472, "to": "mm"},
4309   "name": "SPI_PS_INPUT_CNTL_7",
4310   "type_ref": "SPI_PS_INPUT_CNTL_0"
4311  },
4312  {
4313   "chips": ["gfx81"],
4314   "map": {"at": 165476, "to": "mm"},
4315   "name": "SPI_PS_INPUT_CNTL_8",
4316   "type_ref": "SPI_PS_INPUT_CNTL_0"
4317  },
4318  {
4319   "chips": ["gfx81"],
4320   "map": {"at": 165480, "to": "mm"},
4321   "name": "SPI_PS_INPUT_CNTL_9",
4322   "type_ref": "SPI_PS_INPUT_CNTL_0"
4323  },
4324  {
4325   "chips": ["gfx81"],
4326   "map": {"at": 165484, "to": "mm"},
4327   "name": "SPI_PS_INPUT_CNTL_10",
4328   "type_ref": "SPI_PS_INPUT_CNTL_0"
4329  },
4330  {
4331   "chips": ["gfx81"],
4332   "map": {"at": 165488, "to": "mm"},
4333   "name": "SPI_PS_INPUT_CNTL_11",
4334   "type_ref": "SPI_PS_INPUT_CNTL_0"
4335  },
4336  {
4337   "chips": ["gfx81"],
4338   "map": {"at": 165492, "to": "mm"},
4339   "name": "SPI_PS_INPUT_CNTL_12",
4340   "type_ref": "SPI_PS_INPUT_CNTL_0"
4341  },
4342  {
4343   "chips": ["gfx81"],
4344   "map": {"at": 165496, "to": "mm"},
4345   "name": "SPI_PS_INPUT_CNTL_13",
4346   "type_ref": "SPI_PS_INPUT_CNTL_0"
4347  },
4348  {
4349   "chips": ["gfx81"],
4350   "map": {"at": 165500, "to": "mm"},
4351   "name": "SPI_PS_INPUT_CNTL_14",
4352   "type_ref": "SPI_PS_INPUT_CNTL_0"
4353  },
4354  {
4355   "chips": ["gfx81"],
4356   "map": {"at": 165504, "to": "mm"},
4357   "name": "SPI_PS_INPUT_CNTL_15",
4358   "type_ref": "SPI_PS_INPUT_CNTL_0"
4359  },
4360  {
4361   "chips": ["gfx81"],
4362   "map": {"at": 165508, "to": "mm"},
4363   "name": "SPI_PS_INPUT_CNTL_16",
4364   "type_ref": "SPI_PS_INPUT_CNTL_0"
4365  },
4366  {
4367   "chips": ["gfx81"],
4368   "map": {"at": 165512, "to": "mm"},
4369   "name": "SPI_PS_INPUT_CNTL_17",
4370   "type_ref": "SPI_PS_INPUT_CNTL_0"
4371  },
4372  {
4373   "chips": ["gfx81"],
4374   "map": {"at": 165516, "to": "mm"},
4375   "name": "SPI_PS_INPUT_CNTL_18",
4376   "type_ref": "SPI_PS_INPUT_CNTL_0"
4377  },
4378  {
4379   "chips": ["gfx81"],
4380   "map": {"at": 165520, "to": "mm"},
4381   "name": "SPI_PS_INPUT_CNTL_19",
4382   "type_ref": "SPI_PS_INPUT_CNTL_0"
4383  },
4384  {
4385   "chips": ["gfx81"],
4386   "map": {"at": 165524, "to": "mm"},
4387   "name": "SPI_PS_INPUT_CNTL_20",
4388   "type_ref": "SPI_PS_INPUT_CNTL_20"
4389  },
4390  {
4391   "chips": ["gfx81"],
4392   "map": {"at": 165528, "to": "mm"},
4393   "name": "SPI_PS_INPUT_CNTL_21",
4394   "type_ref": "SPI_PS_INPUT_CNTL_20"
4395  },
4396  {
4397   "chips": ["gfx81"],
4398   "map": {"at": 165532, "to": "mm"},
4399   "name": "SPI_PS_INPUT_CNTL_22",
4400   "type_ref": "SPI_PS_INPUT_CNTL_20"
4401  },
4402  {
4403   "chips": ["gfx81"],
4404   "map": {"at": 165536, "to": "mm"},
4405   "name": "SPI_PS_INPUT_CNTL_23",
4406   "type_ref": "SPI_PS_INPUT_CNTL_20"
4407  },
4408  {
4409   "chips": ["gfx81"],
4410   "map": {"at": 165540, "to": "mm"},
4411   "name": "SPI_PS_INPUT_CNTL_24",
4412   "type_ref": "SPI_PS_INPUT_CNTL_20"
4413  },
4414  {
4415   "chips": ["gfx81"],
4416   "map": {"at": 165544, "to": "mm"},
4417   "name": "SPI_PS_INPUT_CNTL_25",
4418   "type_ref": "SPI_PS_INPUT_CNTL_20"
4419  },
4420  {
4421   "chips": ["gfx81"],
4422   "map": {"at": 165548, "to": "mm"},
4423   "name": "SPI_PS_INPUT_CNTL_26",
4424   "type_ref": "SPI_PS_INPUT_CNTL_20"
4425  },
4426  {
4427   "chips": ["gfx81"],
4428   "map": {"at": 165552, "to": "mm"},
4429   "name": "SPI_PS_INPUT_CNTL_27",
4430   "type_ref": "SPI_PS_INPUT_CNTL_20"
4431  },
4432  {
4433   "chips": ["gfx81"],
4434   "map": {"at": 165556, "to": "mm"},
4435   "name": "SPI_PS_INPUT_CNTL_28",
4436   "type_ref": "SPI_PS_INPUT_CNTL_20"
4437  },
4438  {
4439   "chips": ["gfx81"],
4440   "map": {"at": 165560, "to": "mm"},
4441   "name": "SPI_PS_INPUT_CNTL_29",
4442   "type_ref": "SPI_PS_INPUT_CNTL_20"
4443  },
4444  {
4445   "chips": ["gfx81"],
4446   "map": {"at": 165564, "to": "mm"},
4447   "name": "SPI_PS_INPUT_CNTL_30",
4448   "type_ref": "SPI_PS_INPUT_CNTL_20"
4449  },
4450  {
4451   "chips": ["gfx81"],
4452   "map": {"at": 165568, "to": "mm"},
4453   "name": "SPI_PS_INPUT_CNTL_31",
4454   "type_ref": "SPI_PS_INPUT_CNTL_20"
4455  },
4456  {
4457   "chips": ["gfx81"],
4458   "map": {"at": 165572, "to": "mm"},
4459   "name": "SPI_VS_OUT_CONFIG",
4460   "type_ref": "SPI_VS_OUT_CONFIG"
4461  },
4462  {
4463   "chips": ["gfx81"],
4464   "map": {"at": 165580, "to": "mm"},
4465   "name": "SPI_PS_INPUT_ENA",
4466   "type_ref": "SPI_PS_INPUT_ENA"
4467  },
4468  {
4469   "chips": ["gfx81"],
4470   "map": {"at": 165584, "to": "mm"},
4471   "name": "SPI_PS_INPUT_ADDR",
4472   "type_ref": "SPI_PS_INPUT_ENA"
4473  },
4474  {
4475   "chips": ["gfx81"],
4476   "map": {"at": 165588, "to": "mm"},
4477   "name": "SPI_INTERP_CONTROL_0",
4478   "type_ref": "SPI_INTERP_CONTROL_0"
4479  },
4480  {
4481   "chips": ["gfx81"],
4482   "map": {"at": 165592, "to": "mm"},
4483   "name": "SPI_PS_IN_CONTROL",
4484   "type_ref": "SPI_PS_IN_CONTROL"
4485  },
4486  {
4487   "chips": ["gfx81"],
4488   "map": {"at": 165600, "to": "mm"},
4489   "name": "SPI_BARYC_CNTL",
4490   "type_ref": "SPI_BARYC_CNTL"
4491  },
4492  {
4493   "chips": ["gfx81"],
4494   "map": {"at": 165608, "to": "mm"},
4495   "name": "SPI_TMPRING_SIZE",
4496   "type_ref": "COMPUTE_TMPRING_SIZE"
4497  },
4498  {
4499   "chips": ["gfx81"],
4500   "map": {"at": 165644, "to": "mm"},
4501   "name": "SPI_SHADER_POS_FORMAT",
4502   "type_ref": "SPI_SHADER_POS_FORMAT"
4503  },
4504  {
4505   "chips": ["gfx81"],
4506   "map": {"at": 165648, "to": "mm"},
4507   "name": "SPI_SHADER_Z_FORMAT",
4508   "type_ref": "SPI_SHADER_Z_FORMAT"
4509  },
4510  {
4511   "chips": ["gfx81"],
4512   "map": {"at": 165652, "to": "mm"},
4513   "name": "SPI_SHADER_COL_FORMAT",
4514   "type_ref": "SPI_SHADER_COL_FORMAT"
4515  },
4516  {
4517   "chips": ["gfx81"],
4518   "map": {"at": 165716, "to": "mm"},
4519   "name": "SX_PS_DOWNCONVERT",
4520   "type_ref": "SX_PS_DOWNCONVERT"
4521  },
4522  {
4523   "chips": ["gfx81"],
4524   "map": {"at": 165720, "to": "mm"},
4525   "name": "SX_BLEND_OPT_EPSILON",
4526   "type_ref": "SX_BLEND_OPT_EPSILON"
4527  },
4528  {
4529   "chips": ["gfx81"],
4530   "map": {"at": 165724, "to": "mm"},
4531   "name": "SX_BLEND_OPT_CONTROL",
4532   "type_ref": "SX_BLEND_OPT_CONTROL"
4533  },
4534  {
4535   "chips": ["gfx81"],
4536   "map": {"at": 165728, "to": "mm"},
4537   "name": "SX_MRT0_BLEND_OPT",
4538   "type_ref": "SX_MRT0_BLEND_OPT"
4539  },
4540  {
4541   "chips": ["gfx81"],
4542   "map": {"at": 165732, "to": "mm"},
4543   "name": "SX_MRT1_BLEND_OPT",
4544   "type_ref": "SX_MRT0_BLEND_OPT"
4545  },
4546  {
4547   "chips": ["gfx81"],
4548   "map": {"at": 165736, "to": "mm"},
4549   "name": "SX_MRT2_BLEND_OPT",
4550   "type_ref": "SX_MRT0_BLEND_OPT"
4551  },
4552  {
4553   "chips": ["gfx81"],
4554   "map": {"at": 165740, "to": "mm"},
4555   "name": "SX_MRT3_BLEND_OPT",
4556   "type_ref": "SX_MRT0_BLEND_OPT"
4557  },
4558  {
4559   "chips": ["gfx81"],
4560   "map": {"at": 165744, "to": "mm"},
4561   "name": "SX_MRT4_BLEND_OPT",
4562   "type_ref": "SX_MRT0_BLEND_OPT"
4563  },
4564  {
4565   "chips": ["gfx81"],
4566   "map": {"at": 165748, "to": "mm"},
4567   "name": "SX_MRT5_BLEND_OPT",
4568   "type_ref": "SX_MRT0_BLEND_OPT"
4569  },
4570  {
4571   "chips": ["gfx81"],
4572   "map": {"at": 165752, "to": "mm"},
4573   "name": "SX_MRT6_BLEND_OPT",
4574   "type_ref": "SX_MRT0_BLEND_OPT"
4575  },
4576  {
4577   "chips": ["gfx81"],
4578   "map": {"at": 165756, "to": "mm"},
4579   "name": "SX_MRT7_BLEND_OPT",
4580   "type_ref": "SX_MRT0_BLEND_OPT"
4581  },
4582  {
4583   "chips": ["gfx81"],
4584   "map": {"at": 165760, "to": "mm"},
4585   "name": "CB_BLEND0_CONTROL",
4586   "type_ref": "CB_BLEND0_CONTROL"
4587  },
4588  {
4589   "chips": ["gfx81"],
4590   "map": {"at": 165764, "to": "mm"},
4591   "name": "CB_BLEND1_CONTROL",
4592   "type_ref": "CB_BLEND0_CONTROL"
4593  },
4594  {
4595   "chips": ["gfx81"],
4596   "map": {"at": 165768, "to": "mm"},
4597   "name": "CB_BLEND2_CONTROL",
4598   "type_ref": "CB_BLEND0_CONTROL"
4599  },
4600  {
4601   "chips": ["gfx81"],
4602   "map": {"at": 165772, "to": "mm"},
4603   "name": "CB_BLEND3_CONTROL",
4604   "type_ref": "CB_BLEND0_CONTROL"
4605  },
4606  {
4607   "chips": ["gfx81"],
4608   "map": {"at": 165776, "to": "mm"},
4609   "name": "CB_BLEND4_CONTROL",
4610   "type_ref": "CB_BLEND0_CONTROL"
4611  },
4612  {
4613   "chips": ["gfx81"],
4614   "map": {"at": 165780, "to": "mm"},
4615   "name": "CB_BLEND5_CONTROL",
4616   "type_ref": "CB_BLEND0_CONTROL"
4617  },
4618  {
4619   "chips": ["gfx81"],
4620   "map": {"at": 165784, "to": "mm"},
4621   "name": "CB_BLEND6_CONTROL",
4622   "type_ref": "CB_BLEND0_CONTROL"
4623  },
4624  {
4625   "chips": ["gfx81"],
4626   "map": {"at": 165788, "to": "mm"},
4627   "name": "CB_BLEND7_CONTROL",
4628   "type_ref": "CB_BLEND0_CONTROL"
4629  },
4630  {
4631   "chips": ["gfx81"],
4632   "map": {"at": 165836, "to": "mm"},
4633   "name": "CS_COPY_STATE",
4634   "type_ref": "CS_COPY_STATE"
4635  },
4636  {
4637   "chips": ["gfx81"],
4638   "map": {"at": 165840, "to": "mm"},
4639   "name": "GFX_COPY_STATE",
4640   "type_ref": "CS_COPY_STATE"
4641  },
4642  {
4643   "chips": ["gfx81"],
4644   "map": {"at": 165844, "to": "mm"},
4645   "name": "PA_CL_POINT_X_RAD"
4646  },
4647  {
4648   "chips": ["gfx81"],
4649   "map": {"at": 165848, "to": "mm"},
4650   "name": "PA_CL_POINT_Y_RAD"
4651  },
4652  {
4653   "chips": ["gfx81"],
4654   "map": {"at": 165852, "to": "mm"},
4655   "name": "PA_CL_POINT_SIZE"
4656  },
4657  {
4658   "chips": ["gfx81"],
4659   "map": {"at": 165856, "to": "mm"},
4660   "name": "PA_CL_POINT_CULL_RAD"
4661  },
4662  {
4663   "chips": ["gfx81"],
4664   "map": {"at": 165860, "to": "mm"},
4665   "name": "VGT_DMA_BASE_HI",
4666   "type_ref": "VGT_DMA_BASE_HI"
4667  },
4668  {
4669   "chips": ["gfx81"],
4670   "map": {"at": 165864, "to": "mm"},
4671   "name": "VGT_DMA_BASE"
4672  },
4673  {
4674   "chips": ["gfx81"],
4675   "map": {"at": 165872, "to": "mm"},
4676   "name": "VGT_DRAW_INITIATOR",
4677   "type_ref": "VGT_DRAW_INITIATOR"
4678  },
4679  {
4680   "chips": ["gfx81"],
4681   "map": {"at": 165876, "to": "mm"},
4682   "name": "VGT_IMMED_DATA"
4683  },
4684  {
4685   "chips": ["gfx81"],
4686   "map": {"at": 165880, "to": "mm"},
4687   "name": "VGT_EVENT_ADDRESS_REG",
4688   "type_ref": "VGT_EVENT_ADDRESS_REG"
4689  },
4690  {
4691   "chips": ["gfx81"],
4692   "map": {"at": 165888, "to": "mm"},
4693   "name": "DB_DEPTH_CONTROL",
4694   "type_ref": "DB_DEPTH_CONTROL"
4695  },
4696  {
4697   "chips": ["gfx81"],
4698   "map": {"at": 165892, "to": "mm"},
4699   "name": "DB_EQAA",
4700   "type_ref": "DB_EQAA"
4701  },
4702  {
4703   "chips": ["gfx81"],
4704   "map": {"at": 165896, "to": "mm"},
4705   "name": "CB_COLOR_CONTROL",
4706   "type_ref": "CB_COLOR_CONTROL"
4707  },
4708  {
4709   "chips": ["gfx81"],
4710   "map": {"at": 165900, "to": "mm"},
4711   "name": "DB_SHADER_CONTROL",
4712   "type_ref": "DB_SHADER_CONTROL"
4713  },
4714  {
4715   "chips": ["gfx81"],
4716   "map": {"at": 165904, "to": "mm"},
4717   "name": "PA_CL_CLIP_CNTL",
4718   "type_ref": "PA_CL_CLIP_CNTL"
4719  },
4720  {
4721   "chips": ["gfx81"],
4722   "map": {"at": 165908, "to": "mm"},
4723   "name": "PA_SU_SC_MODE_CNTL",
4724   "type_ref": "PA_SU_SC_MODE_CNTL"
4725  },
4726  {
4727   "chips": ["gfx81"],
4728   "map": {"at": 165912, "to": "mm"},
4729   "name": "PA_CL_VTE_CNTL",
4730   "type_ref": "PA_CL_VTE_CNTL"
4731  },
4732  {
4733   "chips": ["gfx81"],
4734   "map": {"at": 165916, "to": "mm"},
4735   "name": "PA_CL_VS_OUT_CNTL",
4736   "type_ref": "PA_CL_VS_OUT_CNTL"
4737  },
4738  {
4739   "chips": ["gfx81"],
4740   "map": {"at": 165920, "to": "mm"},
4741   "name": "PA_CL_NANINF_CNTL",
4742   "type_ref": "PA_CL_NANINF_CNTL"
4743  },
4744  {
4745   "chips": ["gfx81"],
4746   "map": {"at": 165924, "to": "mm"},
4747   "name": "PA_SU_LINE_STIPPLE_CNTL",
4748   "type_ref": "PA_SU_LINE_STIPPLE_CNTL"
4749  },
4750  {
4751   "chips": ["gfx81"],
4752   "map": {"at": 165928, "to": "mm"},
4753   "name": "PA_SU_LINE_STIPPLE_SCALE"
4754  },
4755  {
4756   "chips": ["gfx81"],
4757   "map": {"at": 165932, "to": "mm"},
4758   "name": "PA_SU_PRIM_FILTER_CNTL",
4759   "type_ref": "PA_SU_PRIM_FILTER_CNTL"
4760  },
4761  {
4762   "chips": ["gfx81"],
4763   "map": {"at": 166400, "to": "mm"},
4764   "name": "PA_SU_POINT_SIZE",
4765   "type_ref": "PA_SU_POINT_SIZE"
4766  },
4767  {
4768   "chips": ["gfx81"],
4769   "map": {"at": 166404, "to": "mm"},
4770   "name": "PA_SU_POINT_MINMAX",
4771   "type_ref": "PA_SU_POINT_MINMAX"
4772  },
4773  {
4774   "chips": ["gfx81"],
4775   "map": {"at": 166408, "to": "mm"},
4776   "name": "PA_SU_LINE_CNTL",
4777   "type_ref": "PA_SU_LINE_CNTL"
4778  },
4779  {
4780   "chips": ["gfx81"],
4781   "map": {"at": 166412, "to": "mm"},
4782   "name": "PA_SC_LINE_STIPPLE",
4783   "type_ref": "PA_SC_LINE_STIPPLE"
4784  },
4785  {
4786   "chips": ["gfx81"],
4787   "map": {"at": 166416, "to": "mm"},
4788   "name": "VGT_OUTPUT_PATH_CNTL",
4789   "type_ref": "VGT_OUTPUT_PATH_CNTL"
4790  },
4791  {
4792   "chips": ["gfx81"],
4793   "map": {"at": 166420, "to": "mm"},
4794   "name": "VGT_HOS_CNTL",
4795   "type_ref": "VGT_HOS_CNTL"
4796  },
4797  {
4798   "chips": ["gfx81"],
4799   "map": {"at": 166424, "to": "mm"},
4800   "name": "VGT_HOS_MAX_TESS_LEVEL"
4801  },
4802  {
4803   "chips": ["gfx81"],
4804   "map": {"at": 166428, "to": "mm"},
4805   "name": "VGT_HOS_MIN_TESS_LEVEL"
4806  },
4807  {
4808   "chips": ["gfx81"],
4809   "map": {"at": 166432, "to": "mm"},
4810   "name": "VGT_HOS_REUSE_DEPTH",
4811   "type_ref": "VGT_HOS_REUSE_DEPTH"
4812  },
4813  {
4814   "chips": ["gfx81"],
4815   "map": {"at": 166436, "to": "mm"},
4816   "name": "VGT_GROUP_PRIM_TYPE",
4817   "type_ref": "VGT_GROUP_PRIM_TYPE"
4818  },
4819  {
4820   "chips": ["gfx81"],
4821   "map": {"at": 166440, "to": "mm"},
4822   "name": "VGT_GROUP_FIRST_DECR",
4823   "type_ref": "VGT_GROUP_FIRST_DECR"
4824  },
4825  {
4826   "chips": ["gfx81"],
4827   "map": {"at": 166444, "to": "mm"},
4828   "name": "VGT_GROUP_DECR",
4829   "type_ref": "VGT_GROUP_DECR"
4830  },
4831  {
4832   "chips": ["gfx81"],
4833   "map": {"at": 166448, "to": "mm"},
4834   "name": "VGT_GROUP_VECT_0_CNTL",
4835   "type_ref": "VGT_GROUP_VECT_0_CNTL"
4836  },
4837  {
4838   "chips": ["gfx81"],
4839   "map": {"at": 166452, "to": "mm"},
4840   "name": "VGT_GROUP_VECT_1_CNTL",
4841   "type_ref": "VGT_GROUP_VECT_0_CNTL"
4842  },
4843  {
4844   "chips": ["gfx81"],
4845   "map": {"at": 166456, "to": "mm"},
4846   "name": "VGT_GROUP_VECT_0_FMT_CNTL",
4847   "type_ref": "VGT_GROUP_VECT_0_FMT_CNTL"
4848  },
4849  {
4850   "chips": ["gfx81"],
4851   "map": {"at": 166460, "to": "mm"},
4852   "name": "VGT_GROUP_VECT_1_FMT_CNTL",
4853   "type_ref": "VGT_GROUP_VECT_0_FMT_CNTL"
4854  },
4855  {
4856   "chips": ["gfx81"],
4857   "map": {"at": 166464, "to": "mm"},
4858   "name": "VGT_GS_MODE",
4859   "type_ref": "VGT_GS_MODE"
4860  },
4861  {
4862   "chips": ["gfx81"],
4863   "map": {"at": 166468, "to": "mm"},
4864   "name": "VGT_GS_ONCHIP_CNTL",
4865   "type_ref": "VGT_GS_ONCHIP_CNTL"
4866  },
4867  {
4868   "chips": ["gfx81"],
4869   "map": {"at": 166472, "to": "mm"},
4870   "name": "PA_SC_MODE_CNTL_0",
4871   "type_ref": "PA_SC_MODE_CNTL_0"
4872  },
4873  {
4874   "chips": ["gfx81"],
4875   "map": {"at": 166476, "to": "mm"},
4876   "name": "PA_SC_MODE_CNTL_1",
4877   "type_ref": "PA_SC_MODE_CNTL_1"
4878  },
4879  {
4880   "chips": ["gfx81"],
4881   "map": {"at": 166480, "to": "mm"},
4882   "name": "VGT_ENHANCE"
4883  },
4884  {
4885   "chips": ["gfx81"],
4886   "map": {"at": 166484, "to": "mm"},
4887   "name": "VGT_GS_PER_ES",
4888   "type_ref": "VGT_GS_PER_ES"
4889  },
4890  {
4891   "chips": ["gfx81"],
4892   "map": {"at": 166488, "to": "mm"},
4893   "name": "VGT_ES_PER_GS",
4894   "type_ref": "VGT_ES_PER_GS"
4895  },
4896  {
4897   "chips": ["gfx81"],
4898   "map": {"at": 166492, "to": "mm"},
4899   "name": "VGT_GS_PER_VS",
4900   "type_ref": "VGT_GS_PER_VS"
4901  },
4902  {
4903   "chips": ["gfx81"],
4904   "map": {"at": 166496, "to": "mm"},
4905   "name": "VGT_GSVS_RING_OFFSET_1",
4906   "type_ref": "VGT_GSVS_RING_OFFSET_1"
4907  },
4908  {
4909   "chips": ["gfx81"],
4910   "map": {"at": 166500, "to": "mm"},
4911   "name": "VGT_GSVS_RING_OFFSET_2",
4912   "type_ref": "VGT_GSVS_RING_OFFSET_1"
4913  },
4914  {
4915   "chips": ["gfx81"],
4916   "map": {"at": 166504, "to": "mm"},
4917   "name": "VGT_GSVS_RING_OFFSET_3",
4918   "type_ref": "VGT_GSVS_RING_OFFSET_1"
4919  },
4920  {
4921   "chips": ["gfx81"],
4922   "map": {"at": 166508, "to": "mm"},
4923   "name": "VGT_GS_OUT_PRIM_TYPE",
4924   "type_ref": "VGT_GS_OUT_PRIM_TYPE"
4925  },
4926  {
4927   "chips": ["gfx81"],
4928   "map": {"at": 166512, "to": "mm"},
4929   "name": "IA_ENHANCE"
4930  },
4931  {
4932   "chips": ["gfx81"],
4933   "map": {"at": 166516, "to": "mm"},
4934   "name": "VGT_DMA_SIZE"
4935  },
4936  {
4937   "chips": ["gfx81"],
4938   "map": {"at": 166520, "to": "mm"},
4939   "name": "VGT_DMA_MAX_SIZE"
4940  },
4941  {
4942   "chips": ["gfx81"],
4943   "map": {"at": 166524, "to": "mm"},
4944   "name": "VGT_DMA_INDEX_TYPE",
4945   "type_ref": "VGT_DMA_INDEX_TYPE"
4946  },
4947  {
4948   "chips": ["gfx81"],
4949   "map": {"at": 166528, "to": "mm"},
4950   "name": "WD_ENHANCE"
4951  },
4952  {
4953   "chips": ["gfx81"],
4954   "map": {"at": 166532, "to": "mm"},
4955   "name": "VGT_PRIMITIVEID_EN",
4956   "type_ref": "VGT_PRIMITIVEID_EN"
4957  },
4958  {
4959   "chips": ["gfx81"],
4960   "map": {"at": 166536, "to": "mm"},
4961   "name": "VGT_DMA_NUM_INSTANCES"
4962  },
4963  {
4964   "chips": ["gfx81"],
4965   "map": {"at": 166540, "to": "mm"},
4966   "name": "VGT_PRIMITIVEID_RESET"
4967  },
4968  {
4969   "chips": ["gfx81"],
4970   "map": {"at": 166544, "to": "mm"},
4971   "name": "VGT_EVENT_INITIATOR",
4972   "type_ref": "VGT_EVENT_INITIATOR"
4973  },
4974  {
4975   "chips": ["gfx81"],
4976   "map": {"at": 166548, "to": "mm"},
4977   "name": "VGT_MULTI_PRIM_IB_RESET_EN",
4978   "type_ref": "VGT_MULTI_PRIM_IB_RESET_EN"
4979  },
4980  {
4981   "chips": ["gfx81"],
4982   "map": {"at": 166560, "to": "mm"},
4983   "name": "VGT_INSTANCE_STEP_RATE_0"
4984  },
4985  {
4986   "chips": ["gfx81"],
4987   "map": {"at": 166564, "to": "mm"},
4988   "name": "VGT_INSTANCE_STEP_RATE_1"
4989  },
4990  {
4991   "chips": ["gfx81"],
4992   "map": {"at": 166568, "to": "mm"},
4993   "name": "IA_MULTI_VGT_PARAM",
4994   "type_ref": "IA_MULTI_VGT_PARAM"
4995  },
4996  {
4997   "chips": ["gfx81"],
4998   "map": {"at": 166572, "to": "mm"},
4999   "name": "VGT_ESGS_RING_ITEMSIZE",
5000   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5001  },
5002  {
5003   "chips": ["gfx81"],
5004   "map": {"at": 166576, "to": "mm"},
5005   "name": "VGT_GSVS_RING_ITEMSIZE",
5006   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5007  },
5008  {
5009   "chips": ["gfx81"],
5010   "map": {"at": 166580, "to": "mm"},
5011   "name": "VGT_REUSE_OFF",
5012   "type_ref": "VGT_REUSE_OFF"
5013  },
5014  {
5015   "chips": ["gfx81"],
5016   "map": {"at": 166584, "to": "mm"},
5017   "name": "VGT_VTX_CNT_EN",
5018   "type_ref": "VGT_VTX_CNT_EN"
5019  },
5020  {
5021   "chips": ["gfx81"],
5022   "map": {"at": 166588, "to": "mm"},
5023   "name": "DB_HTILE_SURFACE",
5024   "type_ref": "DB_HTILE_SURFACE"
5025  },
5026  {
5027   "chips": ["gfx81"],
5028   "map": {"at": 166592, "to": "mm"},
5029   "name": "DB_SRESULTS_COMPARE_STATE0",
5030   "type_ref": "DB_SRESULTS_COMPARE_STATE0"
5031  },
5032  {
5033   "chips": ["gfx81"],
5034   "map": {"at": 166596, "to": "mm"},
5035   "name": "DB_SRESULTS_COMPARE_STATE1",
5036   "type_ref": "DB_SRESULTS_COMPARE_STATE1"
5037  },
5038  {
5039   "chips": ["gfx81"],
5040   "map": {"at": 166600, "to": "mm"},
5041   "name": "DB_PRELOAD_CONTROL",
5042   "type_ref": "DB_PRELOAD_CONTROL"
5043  },
5044  {
5045   "chips": ["gfx81"],
5046   "map": {"at": 166608, "to": "mm"},
5047   "name": "VGT_STRMOUT_BUFFER_SIZE_0"
5048  },
5049  {
5050   "chips": ["gfx81"],
5051   "map": {"at": 166612, "to": "mm"},
5052   "name": "VGT_STRMOUT_VTX_STRIDE_0",
5053   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
5054  },
5055  {
5056   "chips": ["gfx81"],
5057   "map": {"at": 166620, "to": "mm"},
5058   "name": "VGT_STRMOUT_BUFFER_OFFSET_0"
5059  },
5060  {
5061   "chips": ["gfx81"],
5062   "map": {"at": 166624, "to": "mm"},
5063   "name": "VGT_STRMOUT_BUFFER_SIZE_1"
5064  },
5065  {
5066   "chips": ["gfx81"],
5067   "map": {"at": 166628, "to": "mm"},
5068   "name": "VGT_STRMOUT_VTX_STRIDE_1",
5069   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
5070  },
5071  {
5072   "chips": ["gfx81"],
5073   "map": {"at": 166636, "to": "mm"},
5074   "name": "VGT_STRMOUT_BUFFER_OFFSET_1"
5075  },
5076  {
5077   "chips": ["gfx81"],
5078   "map": {"at": 166640, "to": "mm"},
5079   "name": "VGT_STRMOUT_BUFFER_SIZE_2"
5080  },
5081  {
5082   "chips": ["gfx81"],
5083   "map": {"at": 166644, "to": "mm"},
5084   "name": "VGT_STRMOUT_VTX_STRIDE_2",
5085   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
5086  },
5087  {
5088   "chips": ["gfx81"],
5089   "map": {"at": 166652, "to": "mm"},
5090   "name": "VGT_STRMOUT_BUFFER_OFFSET_2"
5091  },
5092  {
5093   "chips": ["gfx81"],
5094   "map": {"at": 166656, "to": "mm"},
5095   "name": "VGT_STRMOUT_BUFFER_SIZE_3"
5096  },
5097  {
5098   "chips": ["gfx81"],
5099   "map": {"at": 166660, "to": "mm"},
5100   "name": "VGT_STRMOUT_VTX_STRIDE_3",
5101   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
5102  },
5103  {
5104   "chips": ["gfx81"],
5105   "map": {"at": 166668, "to": "mm"},
5106   "name": "VGT_STRMOUT_BUFFER_OFFSET_3"
5107  },
5108  {
5109   "chips": ["gfx81"],
5110   "map": {"at": 166696, "to": "mm"},
5111   "name": "VGT_STRMOUT_DRAW_OPAQUE_OFFSET"
5112  },
5113  {
5114   "chips": ["gfx81"],
5115   "map": {"at": 166700, "to": "mm"},
5116   "name": "VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE"
5117  },
5118  {
5119   "chips": ["gfx81"],
5120   "map": {"at": 166704, "to": "mm"},
5121   "name": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE",
5122   "type_ref": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE"
5123  },
5124  {
5125   "chips": ["gfx81"],
5126   "map": {"at": 166712, "to": "mm"},
5127   "name": "VGT_GS_MAX_VERT_OUT",
5128   "type_ref": "VGT_GS_MAX_VERT_OUT"
5129  },
5130  {
5131   "chips": ["gfx81"],
5132   "map": {"at": 166736, "to": "mm"},
5133   "name": "VGT_TESS_DISTRIBUTION",
5134   "type_ref": "VGT_TESS_DISTRIBUTION"
5135  },
5136  {
5137   "chips": ["gfx81"],
5138   "map": {"at": 166740, "to": "mm"},
5139   "name": "VGT_SHADER_STAGES_EN",
5140   "type_ref": "VGT_SHADER_STAGES_EN"
5141  },
5142  {
5143   "chips": ["gfx81"],
5144   "map": {"at": 166744, "to": "mm"},
5145   "name": "VGT_LS_HS_CONFIG",
5146   "type_ref": "VGT_LS_HS_CONFIG"
5147  },
5148  {
5149   "chips": ["gfx81"],
5150   "map": {"at": 166748, "to": "mm"},
5151   "name": "VGT_GS_VERT_ITEMSIZE",
5152   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5153  },
5154  {
5155   "chips": ["gfx81"],
5156   "map": {"at": 166752, "to": "mm"},
5157   "name": "VGT_GS_VERT_ITEMSIZE_1",
5158   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5159  },
5160  {
5161   "chips": ["gfx81"],
5162   "map": {"at": 166756, "to": "mm"},
5163   "name": "VGT_GS_VERT_ITEMSIZE_2",
5164   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5165  },
5166  {
5167   "chips": ["gfx81"],
5168   "map": {"at": 166760, "to": "mm"},
5169   "name": "VGT_GS_VERT_ITEMSIZE_3",
5170   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5171  },
5172  {
5173   "chips": ["gfx81"],
5174   "map": {"at": 166764, "to": "mm"},
5175   "name": "VGT_TF_PARAM",
5176   "type_ref": "VGT_TF_PARAM"
5177  },
5178  {
5179   "chips": ["gfx81"],
5180   "map": {"at": 166768, "to": "mm"},
5181   "name": "DB_ALPHA_TO_MASK",
5182   "type_ref": "DB_ALPHA_TO_MASK"
5183  },
5184  {
5185   "chips": ["gfx81"],
5186   "map": {"at": 166772, "to": "mm"},
5187   "name": "VGT_DISPATCH_DRAW_INDEX"
5188  },
5189  {
5190   "chips": ["gfx81"],
5191   "map": {"at": 166776, "to": "mm"},
5192   "name": "PA_SU_POLY_OFFSET_DB_FMT_CNTL",
5193   "type_ref": "PA_SU_POLY_OFFSET_DB_FMT_CNTL"
5194  },
5195  {
5196   "chips": ["gfx81"],
5197   "map": {"at": 166780, "to": "mm"},
5198   "name": "PA_SU_POLY_OFFSET_CLAMP"
5199  },
5200  {
5201   "chips": ["gfx81"],
5202   "map": {"at": 166784, "to": "mm"},
5203   "name": "PA_SU_POLY_OFFSET_FRONT_SCALE"
5204  },
5205  {
5206   "chips": ["gfx81"],
5207   "map": {"at": 166788, "to": "mm"},
5208   "name": "PA_SU_POLY_OFFSET_FRONT_OFFSET"
5209  },
5210  {
5211   "chips": ["gfx81"],
5212   "map": {"at": 166792, "to": "mm"},
5213   "name": "PA_SU_POLY_OFFSET_BACK_SCALE"
5214  },
5215  {
5216   "chips": ["gfx81"],
5217   "map": {"at": 166796, "to": "mm"},
5218   "name": "PA_SU_POLY_OFFSET_BACK_OFFSET"
5219  },
5220  {
5221   "chips": ["gfx81"],
5222   "map": {"at": 166800, "to": "mm"},
5223   "name": "VGT_GS_INSTANCE_CNT",
5224   "type_ref": "VGT_GS_INSTANCE_CNT"
5225  },
5226  {
5227   "chips": ["gfx81"],
5228   "map": {"at": 166804, "to": "mm"},
5229   "name": "VGT_STRMOUT_CONFIG",
5230   "type_ref": "VGT_STRMOUT_CONFIG"
5231  },
5232  {
5233   "chips": ["gfx81"],
5234   "map": {"at": 166808, "to": "mm"},
5235   "name": "VGT_STRMOUT_BUFFER_CONFIG",
5236   "type_ref": "VGT_STRMOUT_BUFFER_CONFIG"
5237  },
5238  {
5239   "chips": ["gfx81"],
5240   "map": {"at": 166868, "to": "mm"},
5241   "name": "PA_SC_CENTROID_PRIORITY_0",
5242   "type_ref": "PA_SC_CENTROID_PRIORITY_0"
5243  },
5244  {
5245   "chips": ["gfx81"],
5246   "map": {"at": 166872, "to": "mm"},
5247   "name": "PA_SC_CENTROID_PRIORITY_1",
5248   "type_ref": "PA_SC_CENTROID_PRIORITY_1"
5249  },
5250  {
5251   "chips": ["gfx81"],
5252   "map": {"at": 166876, "to": "mm"},
5253   "name": "PA_SC_LINE_CNTL",
5254   "type_ref": "PA_SC_LINE_CNTL"
5255  },
5256  {
5257   "chips": ["gfx81"],
5258   "map": {"at": 166880, "to": "mm"},
5259   "name": "PA_SC_AA_CONFIG",
5260   "type_ref": "PA_SC_AA_CONFIG"
5261  },
5262  {
5263   "chips": ["gfx81"],
5264   "map": {"at": 166884, "to": "mm"},
5265   "name": "PA_SU_VTX_CNTL",
5266   "type_ref": "PA_SU_VTX_CNTL"
5267  },
5268  {
5269   "chips": ["gfx81"],
5270   "map": {"at": 166888, "to": "mm"},
5271   "name": "PA_CL_GB_VERT_CLIP_ADJ"
5272  },
5273  {
5274   "chips": ["gfx81"],
5275   "map": {"at": 166892, "to": "mm"},
5276   "name": "PA_CL_GB_VERT_DISC_ADJ"
5277  },
5278  {
5279   "chips": ["gfx81"],
5280   "map": {"at": 166896, "to": "mm"},
5281   "name": "PA_CL_GB_HORZ_CLIP_ADJ"
5282  },
5283  {
5284   "chips": ["gfx81"],
5285   "map": {"at": 166900, "to": "mm"},
5286   "name": "PA_CL_GB_HORZ_DISC_ADJ"
5287  },
5288  {
5289   "chips": ["gfx81"],
5290   "map": {"at": 166904, "to": "mm"},
5291   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0",
5292   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
5293  },
5294  {
5295   "chips": ["gfx81"],
5296   "map": {"at": 166908, "to": "mm"},
5297   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1",
5298   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
5299  },
5300  {
5301   "chips": ["gfx81"],
5302   "map": {"at": 166912, "to": "mm"},
5303   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2",
5304   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
5305  },
5306  {
5307   "chips": ["gfx81"],
5308   "map": {"at": 166916, "to": "mm"},
5309   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3",
5310   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
5311  },
5312  {
5313   "chips": ["gfx81"],
5314   "map": {"at": 166920, "to": "mm"},
5315   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0",
5316   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
5317  },
5318  {
5319   "chips": ["gfx81"],
5320   "map": {"at": 166924, "to": "mm"},
5321   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1",
5322   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
5323  },
5324  {
5325   "chips": ["gfx81"],
5326   "map": {"at": 166928, "to": "mm"},
5327   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2",
5328   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
5329  },
5330  {
5331   "chips": ["gfx81"],
5332   "map": {"at": 166932, "to": "mm"},
5333   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3",
5334   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
5335  },
5336  {
5337   "chips": ["gfx81"],
5338   "map": {"at": 166936, "to": "mm"},
5339   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0",
5340   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
5341  },
5342  {
5343   "chips": ["gfx81"],
5344   "map": {"at": 166940, "to": "mm"},
5345   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1",
5346   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
5347  },
5348  {
5349   "chips": ["gfx81"],
5350   "map": {"at": 166944, "to": "mm"},
5351   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2",
5352   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
5353  },
5354  {
5355   "chips": ["gfx81"],
5356   "map": {"at": 166948, "to": "mm"},
5357   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3",
5358   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
5359  },
5360  {
5361   "chips": ["gfx81"],
5362   "map": {"at": 166952, "to": "mm"},
5363   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0",
5364   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
5365  },
5366  {
5367   "chips": ["gfx81"],
5368   "map": {"at": 166956, "to": "mm"},
5369   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1",
5370   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
5371  },
5372  {
5373   "chips": ["gfx81"],
5374   "map": {"at": 166960, "to": "mm"},
5375   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2",
5376   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
5377  },
5378  {
5379   "chips": ["gfx81"],
5380   "map": {"at": 166964, "to": "mm"},
5381   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3",
5382   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
5383  },
5384  {
5385   "chips": ["gfx81"],
5386   "map": {"at": 166968, "to": "mm"},
5387   "name": "PA_SC_AA_MASK_X0Y0_X1Y0",
5388   "type_ref": "PA_SC_AA_MASK_X0Y0_X1Y0"
5389  },
5390  {
5391   "chips": ["gfx81"],
5392   "map": {"at": 166972, "to": "mm"},
5393   "name": "PA_SC_AA_MASK_X0Y1_X1Y1",
5394   "type_ref": "PA_SC_AA_MASK_X0Y1_X1Y1"
5395  },
5396  {
5397   "chips": ["gfx81"],
5398   "map": {"at": 166976, "to": "mm"},
5399   "name": "PA_SC_SHADER_CONTROL",
5400   "type_ref": "PA_SC_SHADER_CONTROL"
5401  },
5402  {
5403   "chips": ["gfx81"],
5404   "map": {"at": 167000, "to": "mm"},
5405   "name": "VGT_VERTEX_REUSE_BLOCK_CNTL",
5406   "type_ref": "VGT_VERTEX_REUSE_BLOCK_CNTL"
5407  },
5408  {
5409   "chips": ["gfx81"],
5410   "map": {"at": 167004, "to": "mm"},
5411   "name": "VGT_OUT_DEALLOC_CNTL",
5412   "type_ref": "VGT_OUT_DEALLOC_CNTL"
5413  },
5414  {
5415   "chips": ["gfx81"],
5416   "map": {"at": 167008, "to": "mm"},
5417   "name": "CB_COLOR0_BASE"
5418  },
5419  {
5420   "chips": ["gfx81"],
5421   "map": {"at": 167012, "to": "mm"},
5422   "name": "CB_COLOR0_PITCH",
5423   "type_ref": "CB_COLOR0_PITCH"
5424  },
5425  {
5426   "chips": ["gfx81"],
5427   "map": {"at": 167016, "to": "mm"},
5428   "name": "CB_COLOR0_SLICE",
5429   "type_ref": "CB_COLOR0_SLICE"
5430  },
5431  {
5432   "chips": ["gfx81"],
5433   "map": {"at": 167020, "to": "mm"},
5434   "name": "CB_COLOR0_VIEW",
5435   "type_ref": "CB_COLOR0_VIEW"
5436  },
5437  {
5438   "chips": ["gfx81"],
5439   "map": {"at": 167024, "to": "mm"},
5440   "name": "CB_COLOR0_INFO",
5441   "type_ref": "CB_COLOR0_INFO"
5442  },
5443  {
5444   "chips": ["gfx81"],
5445   "map": {"at": 167028, "to": "mm"},
5446   "name": "CB_COLOR0_ATTRIB",
5447   "type_ref": "CB_COLOR0_ATTRIB"
5448  },
5449  {
5450   "chips": ["gfx81"],
5451   "map": {"at": 167032, "to": "mm"},
5452   "name": "CB_COLOR0_DCC_CONTROL",
5453   "type_ref": "CB_COLOR0_DCC_CONTROL"
5454  },
5455  {
5456   "chips": ["gfx81"],
5457   "map": {"at": 167036, "to": "mm"},
5458   "name": "CB_COLOR0_CMASK"
5459  },
5460  {
5461   "chips": ["gfx81"],
5462   "map": {"at": 167040, "to": "mm"},
5463   "name": "CB_COLOR0_CMASK_SLICE",
5464   "type_ref": "CB_COLOR0_CMASK_SLICE"
5465  },
5466  {
5467   "chips": ["gfx81"],
5468   "map": {"at": 167044, "to": "mm"},
5469   "name": "CB_COLOR0_FMASK"
5470  },
5471  {
5472   "chips": ["gfx81"],
5473   "map": {"at": 167048, "to": "mm"},
5474   "name": "CB_COLOR0_FMASK_SLICE",
5475   "type_ref": "CB_COLOR0_SLICE"
5476  },
5477  {
5478   "chips": ["gfx81"],
5479   "map": {"at": 167052, "to": "mm"},
5480   "name": "CB_COLOR0_CLEAR_WORD0"
5481  },
5482  {
5483   "chips": ["gfx81"],
5484   "map": {"at": 167056, "to": "mm"},
5485   "name": "CB_COLOR0_CLEAR_WORD1"
5486  },
5487  {
5488   "chips": ["gfx81"],
5489   "map": {"at": 167060, "to": "mm"},
5490   "name": "CB_COLOR0_DCC_BASE"
5491  },
5492  {
5493   "chips": ["gfx81"],
5494   "map": {"at": 167068, "to": "mm"},
5495   "name": "CB_COLOR1_BASE"
5496  },
5497  {
5498   "chips": ["gfx81"],
5499   "map": {"at": 167072, "to": "mm"},
5500   "name": "CB_COLOR1_PITCH",
5501   "type_ref": "CB_COLOR0_PITCH"
5502  },
5503  {
5504   "chips": ["gfx81"],
5505   "map": {"at": 167076, "to": "mm"},
5506   "name": "CB_COLOR1_SLICE",
5507   "type_ref": "CB_COLOR0_SLICE"
5508  },
5509  {
5510   "chips": ["gfx81"],
5511   "map": {"at": 167080, "to": "mm"},
5512   "name": "CB_COLOR1_VIEW",
5513   "type_ref": "CB_COLOR0_VIEW"
5514  },
5515  {
5516   "chips": ["gfx81"],
5517   "map": {"at": 167084, "to": "mm"},
5518   "name": "CB_COLOR1_INFO",
5519   "type_ref": "CB_COLOR0_INFO"
5520  },
5521  {
5522   "chips": ["gfx81"],
5523   "map": {"at": 167088, "to": "mm"},
5524   "name": "CB_COLOR1_ATTRIB",
5525   "type_ref": "CB_COLOR0_ATTRIB"
5526  },
5527  {
5528   "chips": ["gfx81"],
5529   "map": {"at": 167092, "to": "mm"},
5530   "name": "CB_COLOR1_DCC_CONTROL",
5531   "type_ref": "CB_COLOR0_DCC_CONTROL"
5532  },
5533  {
5534   "chips": ["gfx81"],
5535   "map": {"at": 167096, "to": "mm"},
5536   "name": "CB_COLOR1_CMASK"
5537  },
5538  {
5539   "chips": ["gfx81"],
5540   "map": {"at": 167100, "to": "mm"},
5541   "name": "CB_COLOR1_CMASK_SLICE",
5542   "type_ref": "CB_COLOR0_CMASK_SLICE"
5543  },
5544  {
5545   "chips": ["gfx81"],
5546   "map": {"at": 167104, "to": "mm"},
5547   "name": "CB_COLOR1_FMASK"
5548  },
5549  {
5550   "chips": ["gfx81"],
5551   "map": {"at": 167108, "to": "mm"},
5552   "name": "CB_COLOR1_FMASK_SLICE",
5553   "type_ref": "CB_COLOR0_SLICE"
5554  },
5555  {
5556   "chips": ["gfx81"],
5557   "map": {"at": 167112, "to": "mm"},
5558   "name": "CB_COLOR1_CLEAR_WORD0"
5559  },
5560  {
5561   "chips": ["gfx81"],
5562   "map": {"at": 167116, "to": "mm"},
5563   "name": "CB_COLOR1_CLEAR_WORD1"
5564  },
5565  {
5566   "chips": ["gfx81"],
5567   "map": {"at": 167120, "to": "mm"},
5568   "name": "CB_COLOR1_DCC_BASE"
5569  },
5570  {
5571   "chips": ["gfx81"],
5572   "map": {"at": 167128, "to": "mm"},
5573   "name": "CB_COLOR2_BASE"
5574  },
5575  {
5576   "chips": ["gfx81"],
5577   "map": {"at": 167132, "to": "mm"},
5578   "name": "CB_COLOR2_PITCH",
5579   "type_ref": "CB_COLOR0_PITCH"
5580  },
5581  {
5582   "chips": ["gfx81"],
5583   "map": {"at": 167136, "to": "mm"},
5584   "name": "CB_COLOR2_SLICE",
5585   "type_ref": "CB_COLOR0_SLICE"
5586  },
5587  {
5588   "chips": ["gfx81"],
5589   "map": {"at": 167140, "to": "mm"},
5590   "name": "CB_COLOR2_VIEW",
5591   "type_ref": "CB_COLOR0_VIEW"
5592  },
5593  {
5594   "chips": ["gfx81"],
5595   "map": {"at": 167144, "to": "mm"},
5596   "name": "CB_COLOR2_INFO",
5597   "type_ref": "CB_COLOR0_INFO"
5598  },
5599  {
5600   "chips": ["gfx81"],
5601   "map": {"at": 167148, "to": "mm"},
5602   "name": "CB_COLOR2_ATTRIB",
5603   "type_ref": "CB_COLOR0_ATTRIB"
5604  },
5605  {
5606   "chips": ["gfx81"],
5607   "map": {"at": 167152, "to": "mm"},
5608   "name": "CB_COLOR2_DCC_CONTROL",
5609   "type_ref": "CB_COLOR0_DCC_CONTROL"
5610  },
5611  {
5612   "chips": ["gfx81"],
5613   "map": {"at": 167156, "to": "mm"},
5614   "name": "CB_COLOR2_CMASK"
5615  },
5616  {
5617   "chips": ["gfx81"],
5618   "map": {"at": 167160, "to": "mm"},
5619   "name": "CB_COLOR2_CMASK_SLICE",
5620   "type_ref": "CB_COLOR0_CMASK_SLICE"
5621  },
5622  {
5623   "chips": ["gfx81"],
5624   "map": {"at": 167164, "to": "mm"},
5625   "name": "CB_COLOR2_FMASK"
5626  },
5627  {
5628   "chips": ["gfx81"],
5629   "map": {"at": 167168, "to": "mm"},
5630   "name": "CB_COLOR2_FMASK_SLICE",
5631   "type_ref": "CB_COLOR0_SLICE"
5632  },
5633  {
5634   "chips": ["gfx81"],
5635   "map": {"at": 167172, "to": "mm"},
5636   "name": "CB_COLOR2_CLEAR_WORD0"
5637  },
5638  {
5639   "chips": ["gfx81"],
5640   "map": {"at": 167176, "to": "mm"},
5641   "name": "CB_COLOR2_CLEAR_WORD1"
5642  },
5643  {
5644   "chips": ["gfx81"],
5645   "map": {"at": 167180, "to": "mm"},
5646   "name": "CB_COLOR2_DCC_BASE"
5647  },
5648  {
5649   "chips": ["gfx81"],
5650   "map": {"at": 167188, "to": "mm"},
5651   "name": "CB_COLOR3_BASE"
5652  },
5653  {
5654   "chips": ["gfx81"],
5655   "map": {"at": 167192, "to": "mm"},
5656   "name": "CB_COLOR3_PITCH",
5657   "type_ref": "CB_COLOR0_PITCH"
5658  },
5659  {
5660   "chips": ["gfx81"],
5661   "map": {"at": 167196, "to": "mm"},
5662   "name": "CB_COLOR3_SLICE",
5663   "type_ref": "CB_COLOR0_SLICE"
5664  },
5665  {
5666   "chips": ["gfx81"],
5667   "map": {"at": 167200, "to": "mm"},
5668   "name": "CB_COLOR3_VIEW",
5669   "type_ref": "CB_COLOR0_VIEW"
5670  },
5671  {
5672   "chips": ["gfx81"],
5673   "map": {"at": 167204, "to": "mm"},
5674   "name": "CB_COLOR3_INFO",
5675   "type_ref": "CB_COLOR0_INFO"
5676  },
5677  {
5678   "chips": ["gfx81"],
5679   "map": {"at": 167208, "to": "mm"},
5680   "name": "CB_COLOR3_ATTRIB",
5681   "type_ref": "CB_COLOR0_ATTRIB"
5682  },
5683  {
5684   "chips": ["gfx81"],
5685   "map": {"at": 167212, "to": "mm"},
5686   "name": "CB_COLOR3_DCC_CONTROL",
5687   "type_ref": "CB_COLOR0_DCC_CONTROL"
5688  },
5689  {
5690   "chips": ["gfx81"],
5691   "map": {"at": 167216, "to": "mm"},
5692   "name": "CB_COLOR3_CMASK"
5693  },
5694  {
5695   "chips": ["gfx81"],
5696   "map": {"at": 167220, "to": "mm"},
5697   "name": "CB_COLOR3_CMASK_SLICE",
5698   "type_ref": "CB_COLOR0_CMASK_SLICE"
5699  },
5700  {
5701   "chips": ["gfx81"],
5702   "map": {"at": 167224, "to": "mm"},
5703   "name": "CB_COLOR3_FMASK"
5704  },
5705  {
5706   "chips": ["gfx81"],
5707   "map": {"at": 167228, "to": "mm"},
5708   "name": "CB_COLOR3_FMASK_SLICE",
5709   "type_ref": "CB_COLOR0_SLICE"
5710  },
5711  {
5712   "chips": ["gfx81"],
5713   "map": {"at": 167232, "to": "mm"},
5714   "name": "CB_COLOR3_CLEAR_WORD0"
5715  },
5716  {
5717   "chips": ["gfx81"],
5718   "map": {"at": 167236, "to": "mm"},
5719   "name": "CB_COLOR3_CLEAR_WORD1"
5720  },
5721  {
5722   "chips": ["gfx81"],
5723   "map": {"at": 167240, "to": "mm"},
5724   "name": "CB_COLOR3_DCC_BASE"
5725  },
5726  {
5727   "chips": ["gfx81"],
5728   "map": {"at": 167248, "to": "mm"},
5729   "name": "CB_COLOR4_BASE"
5730  },
5731  {
5732   "chips": ["gfx81"],
5733   "map": {"at": 167252, "to": "mm"},
5734   "name": "CB_COLOR4_PITCH",
5735   "type_ref": "CB_COLOR0_PITCH"
5736  },
5737  {
5738   "chips": ["gfx81"],
5739   "map": {"at": 167256, "to": "mm"},
5740   "name": "CB_COLOR4_SLICE",
5741   "type_ref": "CB_COLOR0_SLICE"
5742  },
5743  {
5744   "chips": ["gfx81"],
5745   "map": {"at": 167260, "to": "mm"},
5746   "name": "CB_COLOR4_VIEW",
5747   "type_ref": "CB_COLOR0_VIEW"
5748  },
5749  {
5750   "chips": ["gfx81"],
5751   "map": {"at": 167264, "to": "mm"},
5752   "name": "CB_COLOR4_INFO",
5753   "type_ref": "CB_COLOR0_INFO"
5754  },
5755  {
5756   "chips": ["gfx81"],
5757   "map": {"at": 167268, "to": "mm"},
5758   "name": "CB_COLOR4_ATTRIB",
5759   "type_ref": "CB_COLOR0_ATTRIB"
5760  },
5761  {
5762   "chips": ["gfx81"],
5763   "map": {"at": 167272, "to": "mm"},
5764   "name": "CB_COLOR4_DCC_CONTROL",
5765   "type_ref": "CB_COLOR0_DCC_CONTROL"
5766  },
5767  {
5768   "chips": ["gfx81"],
5769   "map": {"at": 167276, "to": "mm"},
5770   "name": "CB_COLOR4_CMASK"
5771  },
5772  {
5773   "chips": ["gfx81"],
5774   "map": {"at": 167280, "to": "mm"},
5775   "name": "CB_COLOR4_CMASK_SLICE",
5776   "type_ref": "CB_COLOR0_CMASK_SLICE"
5777  },
5778  {
5779   "chips": ["gfx81"],
5780   "map": {"at": 167284, "to": "mm"},
5781   "name": "CB_COLOR4_FMASK"
5782  },
5783  {
5784   "chips": ["gfx81"],
5785   "map": {"at": 167288, "to": "mm"},
5786   "name": "CB_COLOR4_FMASK_SLICE",
5787   "type_ref": "CB_COLOR0_SLICE"
5788  },
5789  {
5790   "chips": ["gfx81"],
5791   "map": {"at": 167292, "to": "mm"},
5792   "name": "CB_COLOR4_CLEAR_WORD0"
5793  },
5794  {
5795   "chips": ["gfx81"],
5796   "map": {"at": 167296, "to": "mm"},
5797   "name": "CB_COLOR4_CLEAR_WORD1"
5798  },
5799  {
5800   "chips": ["gfx81"],
5801   "map": {"at": 167300, "to": "mm"},
5802   "name": "CB_COLOR4_DCC_BASE"
5803  },
5804  {
5805   "chips": ["gfx81"],
5806   "map": {"at": 167308, "to": "mm"},
5807   "name": "CB_COLOR5_BASE"
5808  },
5809  {
5810   "chips": ["gfx81"],
5811   "map": {"at": 167312, "to": "mm"},
5812   "name": "CB_COLOR5_PITCH",
5813   "type_ref": "CB_COLOR0_PITCH"
5814  },
5815  {
5816   "chips": ["gfx81"],
5817   "map": {"at": 167316, "to": "mm"},
5818   "name": "CB_COLOR5_SLICE",
5819   "type_ref": "CB_COLOR0_SLICE"
5820  },
5821  {
5822   "chips": ["gfx81"],
5823   "map": {"at": 167320, "to": "mm"},
5824   "name": "CB_COLOR5_VIEW",
5825   "type_ref": "CB_COLOR0_VIEW"
5826  },
5827  {
5828   "chips": ["gfx81"],
5829   "map": {"at": 167324, "to": "mm"},
5830   "name": "CB_COLOR5_INFO",
5831   "type_ref": "CB_COLOR0_INFO"
5832  },
5833  {
5834   "chips": ["gfx81"],
5835   "map": {"at": 167328, "to": "mm"},
5836   "name": "CB_COLOR5_ATTRIB",
5837   "type_ref": "CB_COLOR0_ATTRIB"
5838  },
5839  {
5840   "chips": ["gfx81"],
5841   "map": {"at": 167332, "to": "mm"},
5842   "name": "CB_COLOR5_DCC_CONTROL",
5843   "type_ref": "CB_COLOR0_DCC_CONTROL"
5844  },
5845  {
5846   "chips": ["gfx81"],
5847   "map": {"at": 167336, "to": "mm"},
5848   "name": "CB_COLOR5_CMASK"
5849  },
5850  {
5851   "chips": ["gfx81"],
5852   "map": {"at": 167340, "to": "mm"},
5853   "name": "CB_COLOR5_CMASK_SLICE",
5854   "type_ref": "CB_COLOR0_CMASK_SLICE"
5855  },
5856  {
5857   "chips": ["gfx81"],
5858   "map": {"at": 167344, "to": "mm"},
5859   "name": "CB_COLOR5_FMASK"
5860  },
5861  {
5862   "chips": ["gfx81"],
5863   "map": {"at": 167348, "to": "mm"},
5864   "name": "CB_COLOR5_FMASK_SLICE",
5865   "type_ref": "CB_COLOR0_SLICE"
5866  },
5867  {
5868   "chips": ["gfx81"],
5869   "map": {"at": 167352, "to": "mm"},
5870   "name": "CB_COLOR5_CLEAR_WORD0"
5871  },
5872  {
5873   "chips": ["gfx81"],
5874   "map": {"at": 167356, "to": "mm"},
5875   "name": "CB_COLOR5_CLEAR_WORD1"
5876  },
5877  {
5878   "chips": ["gfx81"],
5879   "map": {"at": 167360, "to": "mm"},
5880   "name": "CB_COLOR5_DCC_BASE"
5881  },
5882  {
5883   "chips": ["gfx81"],
5884   "map": {"at": 167368, "to": "mm"},
5885   "name": "CB_COLOR6_BASE"
5886  },
5887  {
5888   "chips": ["gfx81"],
5889   "map": {"at": 167372, "to": "mm"},
5890   "name": "CB_COLOR6_PITCH",
5891   "type_ref": "CB_COLOR0_PITCH"
5892  },
5893  {
5894   "chips": ["gfx81"],
5895   "map": {"at": 167376, "to": "mm"},
5896   "name": "CB_COLOR6_SLICE",
5897   "type_ref": "CB_COLOR0_SLICE"
5898  },
5899  {
5900   "chips": ["gfx81"],
5901   "map": {"at": 167380, "to": "mm"},
5902   "name": "CB_COLOR6_VIEW",
5903   "type_ref": "CB_COLOR0_VIEW"
5904  },
5905  {
5906   "chips": ["gfx81"],
5907   "map": {"at": 167384, "to": "mm"},
5908   "name": "CB_COLOR6_INFO",
5909   "type_ref": "CB_COLOR0_INFO"
5910  },
5911  {
5912   "chips": ["gfx81"],
5913   "map": {"at": 167388, "to": "mm"},
5914   "name": "CB_COLOR6_ATTRIB",
5915   "type_ref": "CB_COLOR0_ATTRIB"
5916  },
5917  {
5918   "chips": ["gfx81"],
5919   "map": {"at": 167392, "to": "mm"},
5920   "name": "CB_COLOR6_DCC_CONTROL",
5921   "type_ref": "CB_COLOR0_DCC_CONTROL"
5922  },
5923  {
5924   "chips": ["gfx81"],
5925   "map": {"at": 167396, "to": "mm"},
5926   "name": "CB_COLOR6_CMASK"
5927  },
5928  {
5929   "chips": ["gfx81"],
5930   "map": {"at": 167400, "to": "mm"},
5931   "name": "CB_COLOR6_CMASK_SLICE",
5932   "type_ref": "CB_COLOR0_CMASK_SLICE"
5933  },
5934  {
5935   "chips": ["gfx81"],
5936   "map": {"at": 167404, "to": "mm"},
5937   "name": "CB_COLOR6_FMASK"
5938  },
5939  {
5940   "chips": ["gfx81"],
5941   "map": {"at": 167408, "to": "mm"},
5942   "name": "CB_COLOR6_FMASK_SLICE",
5943   "type_ref": "CB_COLOR0_SLICE"
5944  },
5945  {
5946   "chips": ["gfx81"],
5947   "map": {"at": 167412, "to": "mm"},
5948   "name": "CB_COLOR6_CLEAR_WORD0"
5949  },
5950  {
5951   "chips": ["gfx81"],
5952   "map": {"at": 167416, "to": "mm"},
5953   "name": "CB_COLOR6_CLEAR_WORD1"
5954  },
5955  {
5956   "chips": ["gfx81"],
5957   "map": {"at": 167420, "to": "mm"},
5958   "name": "CB_COLOR6_DCC_BASE"
5959  },
5960  {
5961   "chips": ["gfx81"],
5962   "map": {"at": 167428, "to": "mm"},
5963   "name": "CB_COLOR7_BASE"
5964  },
5965  {
5966   "chips": ["gfx81"],
5967   "map": {"at": 167432, "to": "mm"},
5968   "name": "CB_COLOR7_PITCH",
5969   "type_ref": "CB_COLOR0_PITCH"
5970  },
5971  {
5972   "chips": ["gfx81"],
5973   "map": {"at": 167436, "to": "mm"},
5974   "name": "CB_COLOR7_SLICE",
5975   "type_ref": "CB_COLOR0_SLICE"
5976  },
5977  {
5978   "chips": ["gfx81"],
5979   "map": {"at": 167440, "to": "mm"},
5980   "name": "CB_COLOR7_VIEW",
5981   "type_ref": "CB_COLOR0_VIEW"
5982  },
5983  {
5984   "chips": ["gfx81"],
5985   "map": {"at": 167444, "to": "mm"},
5986   "name": "CB_COLOR7_INFO",
5987   "type_ref": "CB_COLOR0_INFO"
5988  },
5989  {
5990   "chips": ["gfx81"],
5991   "map": {"at": 167448, "to": "mm"},
5992   "name": "CB_COLOR7_ATTRIB",
5993   "type_ref": "CB_COLOR0_ATTRIB"
5994  },
5995  {
5996   "chips": ["gfx81"],
5997   "map": {"at": 167452, "to": "mm"},
5998   "name": "CB_COLOR7_DCC_CONTROL",
5999   "type_ref": "CB_COLOR0_DCC_CONTROL"
6000  },
6001  {
6002   "chips": ["gfx81"],
6003   "map": {"at": 167456, "to": "mm"},
6004   "name": "CB_COLOR7_CMASK"
6005  },
6006  {
6007   "chips": ["gfx81"],
6008   "map": {"at": 167460, "to": "mm"},
6009   "name": "CB_COLOR7_CMASK_SLICE",
6010   "type_ref": "CB_COLOR0_CMASK_SLICE"
6011  },
6012  {
6013   "chips": ["gfx81"],
6014   "map": {"at": 167464, "to": "mm"},
6015   "name": "CB_COLOR7_FMASK"
6016  },
6017  {
6018   "chips": ["gfx81"],
6019   "map": {"at": 167468, "to": "mm"},
6020   "name": "CB_COLOR7_FMASK_SLICE",
6021   "type_ref": "CB_COLOR0_SLICE"
6022  },
6023  {
6024   "chips": ["gfx81"],
6025   "map": {"at": 167472, "to": "mm"},
6026   "name": "CB_COLOR7_CLEAR_WORD0"
6027  },
6028  {
6029   "chips": ["gfx81"],
6030   "map": {"at": 167476, "to": "mm"},
6031   "name": "CB_COLOR7_CLEAR_WORD1"
6032  },
6033  {
6034   "chips": ["gfx81"],
6035   "map": {"at": 167480, "to": "mm"},
6036   "name": "CB_COLOR7_DCC_BASE"
6037  },
6038  {
6039   "chips": ["gfx81"],
6040   "map": {"at": 196608, "to": "mm"},
6041   "name": "CP_EOP_DONE_ADDR_LO",
6042   "type_ref": "CP_EOP_DONE_ADDR_LO"
6043  },
6044  {
6045   "chips": ["gfx81"],
6046   "map": {"at": 196612, "to": "mm"},
6047   "name": "CP_EOP_DONE_ADDR_HI",
6048   "type_ref": "CP_EOP_DONE_ADDR_HI"
6049  },
6050  {
6051   "chips": ["gfx81"],
6052   "map": {"at": 196616, "to": "mm"},
6053   "name": "CP_EOP_DONE_DATA_LO"
6054  },
6055  {
6056   "chips": ["gfx81"],
6057   "map": {"at": 196620, "to": "mm"},
6058   "name": "CP_EOP_DONE_DATA_HI"
6059  },
6060  {
6061   "chips": ["gfx81"],
6062   "map": {"at": 196624, "to": "mm"},
6063   "name": "CP_EOP_LAST_FENCE_LO"
6064  },
6065  {
6066   "chips": ["gfx81"],
6067   "map": {"at": 196628, "to": "mm"},
6068   "name": "CP_EOP_LAST_FENCE_HI"
6069  },
6070  {
6071   "chips": ["gfx81"],
6072   "map": {"at": 196632, "to": "mm"},
6073   "name": "CP_STREAM_OUT_ADDR_LO",
6074   "type_ref": "CP_STREAM_OUT_ADDR_LO"
6075  },
6076  {
6077   "chips": ["gfx81"],
6078   "map": {"at": 196636, "to": "mm"},
6079   "name": "CP_STREAM_OUT_ADDR_HI",
6080   "type_ref": "CP_STREAM_OUT_ADDR_HI"
6081  },
6082  {
6083   "chips": ["gfx81"],
6084   "map": {"at": 196640, "to": "mm"},
6085   "name": "CP_NUM_PRIM_WRITTEN_COUNT0_LO"
6086  },
6087  {
6088   "chips": ["gfx81"],
6089   "map": {"at": 196644, "to": "mm"},
6090   "name": "CP_NUM_PRIM_WRITTEN_COUNT0_HI"
6091  },
6092  {
6093   "chips": ["gfx81"],
6094   "map": {"at": 196648, "to": "mm"},
6095   "name": "CP_NUM_PRIM_NEEDED_COUNT0_LO"
6096  },
6097  {
6098   "chips": ["gfx81"],
6099   "map": {"at": 196652, "to": "mm"},
6100   "name": "CP_NUM_PRIM_NEEDED_COUNT0_HI"
6101  },
6102  {
6103   "chips": ["gfx81"],
6104   "map": {"at": 196656, "to": "mm"},
6105   "name": "CP_NUM_PRIM_WRITTEN_COUNT1_LO"
6106  },
6107  {
6108   "chips": ["gfx81"],
6109   "map": {"at": 196660, "to": "mm"},
6110   "name": "CP_NUM_PRIM_WRITTEN_COUNT1_HI"
6111  },
6112  {
6113   "chips": ["gfx81"],
6114   "map": {"at": 196664, "to": "mm"},
6115   "name": "CP_NUM_PRIM_NEEDED_COUNT1_LO"
6116  },
6117  {
6118   "chips": ["gfx81"],
6119   "map": {"at": 196668, "to": "mm"},
6120   "name": "CP_NUM_PRIM_NEEDED_COUNT1_HI"
6121  },
6122  {
6123   "chips": ["gfx81"],
6124   "map": {"at": 196672, "to": "mm"},
6125   "name": "CP_NUM_PRIM_WRITTEN_COUNT2_LO"
6126  },
6127  {
6128   "chips": ["gfx81"],
6129   "map": {"at": 196676, "to": "mm"},
6130   "name": "CP_NUM_PRIM_WRITTEN_COUNT2_HI"
6131  },
6132  {
6133   "chips": ["gfx81"],
6134   "map": {"at": 196680, "to": "mm"},
6135   "name": "CP_NUM_PRIM_NEEDED_COUNT2_LO"
6136  },
6137  {
6138   "chips": ["gfx81"],
6139   "map": {"at": 196684, "to": "mm"},
6140   "name": "CP_NUM_PRIM_NEEDED_COUNT2_HI"
6141  },
6142  {
6143   "chips": ["gfx81"],
6144   "map": {"at": 196688, "to": "mm"},
6145   "name": "CP_NUM_PRIM_WRITTEN_COUNT3_LO"
6146  },
6147  {
6148   "chips": ["gfx81"],
6149   "map": {"at": 196692, "to": "mm"},
6150   "name": "CP_NUM_PRIM_WRITTEN_COUNT3_HI"
6151  },
6152  {
6153   "chips": ["gfx81"],
6154   "map": {"at": 196696, "to": "mm"},
6155   "name": "CP_NUM_PRIM_NEEDED_COUNT3_LO"
6156  },
6157  {
6158   "chips": ["gfx81"],
6159   "map": {"at": 196700, "to": "mm"},
6160   "name": "CP_NUM_PRIM_NEEDED_COUNT3_HI"
6161  },
6162  {
6163   "chips": ["gfx81"],
6164   "map": {"at": 196704, "to": "mm"},
6165   "name": "CP_PIPE_STATS_ADDR_LO",
6166   "type_ref": "CP_PIPE_STATS_ADDR_LO"
6167  },
6168  {
6169   "chips": ["gfx81"],
6170   "map": {"at": 196708, "to": "mm"},
6171   "name": "CP_PIPE_STATS_ADDR_HI",
6172   "type_ref": "CP_PIPE_STATS_ADDR_HI"
6173  },
6174  {
6175   "chips": ["gfx81"],
6176   "map": {"at": 196712, "to": "mm"},
6177   "name": "CP_VGT_IAVERT_COUNT_LO"
6178  },
6179  {
6180   "chips": ["gfx81"],
6181   "map": {"at": 196716, "to": "mm"},
6182   "name": "CP_VGT_IAVERT_COUNT_HI"
6183  },
6184  {
6185   "chips": ["gfx81"],
6186   "map": {"at": 196720, "to": "mm"},
6187   "name": "CP_VGT_IAPRIM_COUNT_LO"
6188  },
6189  {
6190   "chips": ["gfx81"],
6191   "map": {"at": 196724, "to": "mm"},
6192   "name": "CP_VGT_IAPRIM_COUNT_HI"
6193  },
6194  {
6195   "chips": ["gfx81"],
6196   "map": {"at": 196728, "to": "mm"},
6197   "name": "CP_VGT_GSPRIM_COUNT_LO"
6198  },
6199  {
6200   "chips": ["gfx81"],
6201   "map": {"at": 196732, "to": "mm"},
6202   "name": "CP_VGT_GSPRIM_COUNT_HI"
6203  },
6204  {
6205   "chips": ["gfx81"],
6206   "map": {"at": 196736, "to": "mm"},
6207   "name": "CP_VGT_VSINVOC_COUNT_LO"
6208  },
6209  {
6210   "chips": ["gfx81"],
6211   "map": {"at": 196740, "to": "mm"},
6212   "name": "CP_VGT_VSINVOC_COUNT_HI"
6213  },
6214  {
6215   "chips": ["gfx81"],
6216   "map": {"at": 196744, "to": "mm"},
6217   "name": "CP_VGT_GSINVOC_COUNT_LO"
6218  },
6219  {
6220   "chips": ["gfx81"],
6221   "map": {"at": 196748, "to": "mm"},
6222   "name": "CP_VGT_GSINVOC_COUNT_HI"
6223  },
6224  {
6225   "chips": ["gfx81"],
6226   "map": {"at": 196752, "to": "mm"},
6227   "name": "CP_VGT_HSINVOC_COUNT_LO"
6228  },
6229  {
6230   "chips": ["gfx81"],
6231   "map": {"at": 196756, "to": "mm"},
6232   "name": "CP_VGT_HSINVOC_COUNT_HI"
6233  },
6234  {
6235   "chips": ["gfx81"],
6236   "map": {"at": 196760, "to": "mm"},
6237   "name": "CP_VGT_DSINVOC_COUNT_LO"
6238  },
6239  {
6240   "chips": ["gfx81"],
6241   "map": {"at": 196764, "to": "mm"},
6242   "name": "CP_VGT_DSINVOC_COUNT_HI"
6243  },
6244  {
6245   "chips": ["gfx81"],
6246   "map": {"at": 196768, "to": "mm"},
6247   "name": "CP_PA_CINVOC_COUNT_LO"
6248  },
6249  {
6250   "chips": ["gfx81"],
6251   "map": {"at": 196772, "to": "mm"},
6252   "name": "CP_PA_CINVOC_COUNT_HI"
6253  },
6254  {
6255   "chips": ["gfx81"],
6256   "map": {"at": 196776, "to": "mm"},
6257   "name": "CP_PA_CPRIM_COUNT_LO"
6258  },
6259  {
6260   "chips": ["gfx81"],
6261   "map": {"at": 196780, "to": "mm"},
6262   "name": "CP_PA_CPRIM_COUNT_HI"
6263  },
6264  {
6265   "chips": ["gfx81"],
6266   "map": {"at": 196784, "to": "mm"},
6267   "name": "CP_SC_PSINVOC_COUNT0_LO"
6268  },
6269  {
6270   "chips": ["gfx81"],
6271   "map": {"at": 196788, "to": "mm"},
6272   "name": "CP_SC_PSINVOC_COUNT0_HI"
6273  },
6274  {
6275   "chips": ["gfx81"],
6276   "map": {"at": 196792, "to": "mm"},
6277   "name": "CP_SC_PSINVOC_COUNT1_LO"
6278  },
6279  {
6280   "chips": ["gfx81"],
6281   "map": {"at": 196796, "to": "mm"},
6282   "name": "CP_SC_PSINVOC_COUNT1_HI"
6283  },
6284  {
6285   "chips": ["gfx81"],
6286   "map": {"at": 196800, "to": "mm"},
6287   "name": "CP_VGT_CSINVOC_COUNT_LO"
6288  },
6289  {
6290   "chips": ["gfx81"],
6291   "map": {"at": 196804, "to": "mm"},
6292   "name": "CP_VGT_CSINVOC_COUNT_HI"
6293  },
6294  {
6295   "chips": ["gfx81"],
6296   "map": {"at": 196852, "to": "mm"},
6297   "name": "CP_PIPE_STATS_CONTROL",
6298   "type_ref": "CP_PIPE_STATS_CONTROL"
6299  },
6300  {
6301   "chips": ["gfx81"],
6302   "map": {"at": 196856, "to": "mm"},
6303   "name": "CP_STREAM_OUT_CONTROL",
6304   "type_ref": "CP_PIPE_STATS_CONTROL"
6305  },
6306  {
6307   "chips": ["gfx81"],
6308   "map": {"at": 196860, "to": "mm"},
6309   "name": "CP_STRMOUT_CNTL",
6310   "type_ref": "CP_STRMOUT_CNTL"
6311  },
6312  {
6313   "chips": ["gfx81"],
6314   "map": {"at": 196864, "to": "mm"},
6315   "name": "SCRATCH_REG0"
6316  },
6317  {
6318   "chips": ["gfx81"],
6319   "map": {"at": 196868, "to": "mm"},
6320   "name": "SCRATCH_REG1"
6321  },
6322  {
6323   "chips": ["gfx81"],
6324   "map": {"at": 196872, "to": "mm"},
6325   "name": "SCRATCH_REG2"
6326  },
6327  {
6328   "chips": ["gfx81"],
6329   "map": {"at": 196876, "to": "mm"},
6330   "name": "SCRATCH_REG3"
6331  },
6332  {
6333   "chips": ["gfx81"],
6334   "map": {"at": 196880, "to": "mm"},
6335   "name": "SCRATCH_REG4"
6336  },
6337  {
6338   "chips": ["gfx81"],
6339   "map": {"at": 196884, "to": "mm"},
6340   "name": "SCRATCH_REG5"
6341  },
6342  {
6343   "chips": ["gfx81"],
6344   "map": {"at": 196888, "to": "mm"},
6345   "name": "SCRATCH_REG6"
6346  },
6347  {
6348   "chips": ["gfx81"],
6349   "map": {"at": 196892, "to": "mm"},
6350   "name": "SCRATCH_REG7"
6351  },
6352  {
6353   "chips": ["gfx81"],
6354   "map": {"at": 196928, "to": "mm"},
6355   "name": "SCRATCH_UMSK",
6356   "type_ref": "SCRATCH_UMSK"
6357  },
6358  {
6359   "chips": ["gfx81"],
6360   "map": {"at": 196932, "to": "mm"},
6361   "name": "SCRATCH_ADDR"
6362  },
6363  {
6364   "chips": ["gfx81"],
6365   "map": {"at": 196936, "to": "mm"},
6366   "name": "CP_PFP_ATOMIC_PREOP_LO"
6367  },
6368  {
6369   "chips": ["gfx81"],
6370   "map": {"at": 196940, "to": "mm"},
6371   "name": "CP_PFP_ATOMIC_PREOP_HI"
6372  },
6373  {
6374   "chips": ["gfx81"],
6375   "map": {"at": 196944, "to": "mm"},
6376   "name": "CP_PFP_GDS_ATOMIC0_PREOP_LO"
6377  },
6378  {
6379   "chips": ["gfx81"],
6380   "map": {"at": 196948, "to": "mm"},
6381   "name": "CP_PFP_GDS_ATOMIC0_PREOP_HI"
6382  },
6383  {
6384   "chips": ["gfx81"],
6385   "map": {"at": 196952, "to": "mm"},
6386   "name": "CP_PFP_GDS_ATOMIC1_PREOP_LO"
6387  },
6388  {
6389   "chips": ["gfx81"],
6390   "map": {"at": 196956, "to": "mm"},
6391   "name": "CP_PFP_GDS_ATOMIC1_PREOP_HI"
6392  },
6393  {
6394   "chips": ["gfx81"],
6395   "map": {"at": 196960, "to": "mm"},
6396   "name": "CP_APPEND_ADDR_LO",
6397   "type_ref": "CP_APPEND_ADDR_LO"
6398  },
6399  {
6400   "chips": ["gfx81"],
6401   "map": {"at": 196964, "to": "mm"},
6402   "name": "CP_APPEND_ADDR_HI",
6403   "type_ref": "CP_APPEND_ADDR_HI"
6404  },
6405  {
6406   "chips": ["gfx81"],
6407   "map": {"at": 196968, "to": "mm"},
6408   "name": "CP_APPEND_DATA"
6409  },
6410  {
6411   "chips": ["gfx81"],
6412   "map": {"at": 196972, "to": "mm"},
6413   "name": "CP_APPEND_LAST_CS_FENCE"
6414  },
6415  {
6416   "chips": ["gfx81"],
6417   "map": {"at": 196976, "to": "mm"},
6418   "name": "CP_APPEND_LAST_PS_FENCE"
6419  },
6420  {
6421   "chips": ["gfx81"],
6422   "map": {"at": 196980, "to": "mm"},
6423   "name": "CP_ATOMIC_PREOP_LO"
6424  },
6425  {
6426   "chips": ["gfx81"],
6427   "map": {"at": 196984, "to": "mm"},
6428   "name": "CP_ATOMIC_PREOP_HI"
6429  },
6430  {
6431   "chips": ["gfx81"],
6432   "map": {"at": 196988, "to": "mm"},
6433   "name": "CP_GDS_ATOMIC0_PREOP_LO"
6434  },
6435  {
6436   "chips": ["gfx81"],
6437   "map": {"at": 196992, "to": "mm"},
6438   "name": "CP_GDS_ATOMIC0_PREOP_HI"
6439  },
6440  {
6441   "chips": ["gfx81"],
6442   "map": {"at": 196996, "to": "mm"},
6443   "name": "CP_GDS_ATOMIC1_PREOP_LO"
6444  },
6445  {
6446   "chips": ["gfx81"],
6447   "map": {"at": 197000, "to": "mm"},
6448   "name": "CP_GDS_ATOMIC1_PREOP_HI"
6449  },
6450  {
6451   "chips": ["gfx81"],
6452   "map": {"at": 197028, "to": "mm"},
6453   "name": "CP_ME_MC_WADDR_LO",
6454   "type_ref": "CP_ME_MC_WADDR_LO"
6455  },
6456  {
6457   "chips": ["gfx81"],
6458   "map": {"at": 197032, "to": "mm"},
6459   "name": "CP_ME_MC_WADDR_HI",
6460   "type_ref": "CP_ME_MC_WADDR_HI"
6461  },
6462  {
6463   "chips": ["gfx81"],
6464   "map": {"at": 197036, "to": "mm"},
6465   "name": "CP_ME_MC_WDATA_LO"
6466  },
6467  {
6468   "chips": ["gfx81"],
6469   "map": {"at": 197040, "to": "mm"},
6470   "name": "CP_ME_MC_WDATA_HI"
6471  },
6472  {
6473   "chips": ["gfx81"],
6474   "map": {"at": 197044, "to": "mm"},
6475   "name": "CP_ME_MC_RADDR_LO",
6476   "type_ref": "CP_ME_MC_RADDR_LO"
6477  },
6478  {
6479   "chips": ["gfx81"],
6480   "map": {"at": 197048, "to": "mm"},
6481   "name": "CP_ME_MC_RADDR_HI",
6482   "type_ref": "CP_ME_MC_RADDR_HI"
6483  },
6484  {
6485   "chips": ["gfx81"],
6486   "map": {"at": 197052, "to": "mm"},
6487   "name": "CP_SEM_WAIT_TIMER"
6488  },
6489  {
6490   "chips": ["gfx81"],
6491   "map": {"at": 197056, "to": "mm"},
6492   "name": "CP_SIG_SEM_ADDR_LO",
6493   "type_ref": "CP_SIG_SEM_ADDR_LO"
6494  },
6495  {
6496   "chips": ["gfx81"],
6497   "map": {"at": 197060, "to": "mm"},
6498   "name": "CP_SIG_SEM_ADDR_HI",
6499   "type_ref": "CP_SIG_SEM_ADDR_HI"
6500  },
6501  {
6502   "chips": ["gfx81"],
6503   "map": {"at": 197072, "to": "mm"},
6504   "name": "CP_WAIT_REG_MEM_TIMEOUT"
6505  },
6506  {
6507   "chips": ["gfx81"],
6508   "map": {"at": 197076, "to": "mm"},
6509   "name": "CP_WAIT_SEM_ADDR_LO",
6510   "type_ref": "CP_SIG_SEM_ADDR_LO"
6511  },
6512  {
6513   "chips": ["gfx81"],
6514   "map": {"at": 197080, "to": "mm"},
6515   "name": "CP_WAIT_SEM_ADDR_HI",
6516   "type_ref": "CP_SIG_SEM_ADDR_HI"
6517  },
6518  {
6519   "chips": ["gfx81"],
6520   "map": {"at": 197084, "to": "mm"},
6521   "name": "CP_DMA_PFP_CONTROL",
6522   "type_ref": "CP_DMA_ME_CONTROL"
6523  },
6524  {
6525   "chips": ["gfx81"],
6526   "map": {"at": 197088, "to": "mm"},
6527   "name": "CP_DMA_ME_CONTROL",
6528   "type_ref": "CP_DMA_ME_CONTROL"
6529  },
6530  {
6531   "chips": ["gfx81"],
6532   "map": {"at": 197092, "to": "mm"},
6533   "name": "CP_COHER_BASE_HI",
6534   "type_ref": "CP_COHER_BASE_HI"
6535  },
6536  {
6537   "chips": ["gfx81"],
6538   "map": {"at": 197100, "to": "mm"},
6539   "name": "CP_COHER_START_DELAY",
6540   "type_ref": "CP_COHER_START_DELAY"
6541  },
6542  {
6543   "chips": ["gfx81"],
6544   "map": {"at": 197104, "to": "mm"},
6545   "name": "CP_COHER_CNTL",
6546   "type_ref": "CP_COHER_CNTL"
6547  },
6548  {
6549   "chips": ["gfx81"],
6550   "map": {"at": 197108, "to": "mm"},
6551   "name": "CP_COHER_SIZE"
6552  },
6553  {
6554   "chips": ["gfx81"],
6555   "map": {"at": 197112, "to": "mm"},
6556   "name": "CP_COHER_BASE"
6557  },
6558  {
6559   "chips": ["gfx81"],
6560   "map": {"at": 197116, "to": "mm"},
6561   "name": "CP_COHER_STATUS",
6562   "type_ref": "CP_COHER_STATUS"
6563  },
6564  {
6565   "chips": ["gfx81"],
6566   "map": {"at": 197120, "to": "mm"},
6567   "name": "CP_DMA_ME_SRC_ADDR"
6568  },
6569  {
6570   "chips": ["gfx81"],
6571   "map": {"at": 197124, "to": "mm"},
6572   "name": "CP_DMA_ME_SRC_ADDR_HI",
6573   "type_ref": "CP_DMA_ME_SRC_ADDR_HI"
6574  },
6575  {
6576   "chips": ["gfx81"],
6577   "map": {"at": 197128, "to": "mm"},
6578   "name": "CP_DMA_ME_DST_ADDR"
6579  },
6580  {
6581   "chips": ["gfx81"],
6582   "map": {"at": 197132, "to": "mm"},
6583   "name": "CP_DMA_ME_DST_ADDR_HI",
6584   "type_ref": "CP_DMA_ME_DST_ADDR_HI"
6585  },
6586  {
6587   "chips": ["gfx81"],
6588   "map": {"at": 197136, "to": "mm"},
6589   "name": "CP_DMA_ME_COMMAND",
6590   "type_ref": "CP_DMA_ME_COMMAND"
6591  },
6592  {
6593   "chips": ["gfx81"],
6594   "map": {"at": 197140, "to": "mm"},
6595   "name": "CP_DMA_PFP_SRC_ADDR"
6596  },
6597  {
6598   "chips": ["gfx81"],
6599   "map": {"at": 197144, "to": "mm"},
6600   "name": "CP_DMA_PFP_SRC_ADDR_HI",
6601   "type_ref": "CP_DMA_ME_SRC_ADDR_HI"
6602  },
6603  {
6604   "chips": ["gfx81"],
6605   "map": {"at": 197148, "to": "mm"},
6606   "name": "CP_DMA_PFP_DST_ADDR"
6607  },
6608  {
6609   "chips": ["gfx81"],
6610   "map": {"at": 197152, "to": "mm"},
6611   "name": "CP_DMA_PFP_DST_ADDR_HI",
6612   "type_ref": "CP_DMA_ME_DST_ADDR_HI"
6613  },
6614  {
6615   "chips": ["gfx81"],
6616   "map": {"at": 197156, "to": "mm"},
6617   "name": "CP_DMA_PFP_COMMAND",
6618   "type_ref": "CP_DMA_ME_COMMAND"
6619  },
6620  {
6621   "chips": ["gfx81"],
6622   "map": {"at": 197160, "to": "mm"},
6623   "name": "CP_DMA_CNTL",
6624   "type_ref": "CP_DMA_CNTL"
6625  },
6626  {
6627   "chips": ["gfx81"],
6628   "map": {"at": 197164, "to": "mm"},
6629   "name": "CP_DMA_READ_TAGS",
6630   "type_ref": "CP_DMA_READ_TAGS"
6631  },
6632  {
6633   "chips": ["gfx81"],
6634   "map": {"at": 197168, "to": "mm"},
6635   "name": "CP_COHER_SIZE_HI",
6636   "type_ref": "CP_COHER_SIZE_HI"
6637  },
6638  {
6639   "chips": ["gfx81"],
6640   "map": {"at": 197172, "to": "mm"},
6641   "name": "CP_PFP_IB_CONTROL",
6642   "type_ref": "CP_PFP_IB_CONTROL"
6643  },
6644  {
6645   "chips": ["gfx81"],
6646   "map": {"at": 197176, "to": "mm"},
6647   "name": "CP_PFP_LOAD_CONTROL",
6648   "type_ref": "CP_PFP_LOAD_CONTROL"
6649  },
6650  {
6651   "chips": ["gfx81"],
6652   "map": {"at": 197180, "to": "mm"},
6653   "name": "CP_SCRATCH_INDEX",
6654   "type_ref": "CP_SCRATCH_INDEX"
6655  },
6656  {
6657   "chips": ["gfx81"],
6658   "map": {"at": 197184, "to": "mm"},
6659   "name": "CP_SCRATCH_DATA"
6660  },
6661  {
6662   "chips": ["gfx81"],
6663   "map": {"at": 197188, "to": "mm"},
6664   "name": "CP_RB_OFFSET",
6665   "type_ref": "CP_RB_OFFSET"
6666  },
6667  {
6668   "chips": ["gfx81"],
6669   "map": {"at": 197192, "to": "mm"},
6670   "name": "CP_IB1_OFFSET",
6671   "type_ref": "CP_IB1_OFFSET"
6672  },
6673  {
6674   "chips": ["gfx81"],
6675   "map": {"at": 197196, "to": "mm"},
6676   "name": "CP_IB2_OFFSET",
6677   "type_ref": "CP_IB2_OFFSET"
6678  },
6679  {
6680   "chips": ["gfx81"],
6681   "map": {"at": 197200, "to": "mm"},
6682   "name": "CP_IB1_PREAMBLE_BEGIN",
6683   "type_ref": "CP_IB1_PREAMBLE_BEGIN"
6684  },
6685  {
6686   "chips": ["gfx81"],
6687   "map": {"at": 197204, "to": "mm"},
6688   "name": "CP_IB1_PREAMBLE_END",
6689   "type_ref": "CP_IB1_PREAMBLE_END"
6690  },
6691  {
6692   "chips": ["gfx81"],
6693   "map": {"at": 197208, "to": "mm"},
6694   "name": "CP_IB2_PREAMBLE_BEGIN",
6695   "type_ref": "CP_IB2_PREAMBLE_BEGIN"
6696  },
6697  {
6698   "chips": ["gfx81"],
6699   "map": {"at": 197212, "to": "mm"},
6700   "name": "CP_IB2_PREAMBLE_END",
6701   "type_ref": "CP_IB2_PREAMBLE_END"
6702  },
6703  {
6704   "chips": ["gfx81"],
6705   "map": {"at": 197216, "to": "mm"},
6706   "name": "CP_CE_IB1_OFFSET",
6707   "type_ref": "CP_IB1_OFFSET"
6708  },
6709  {
6710   "chips": ["gfx81"],
6711   "map": {"at": 197220, "to": "mm"},
6712   "name": "CP_CE_IB2_OFFSET",
6713   "type_ref": "CP_IB2_OFFSET"
6714  },
6715  {
6716   "chips": ["gfx81"],
6717   "map": {"at": 197224, "to": "mm"},
6718   "name": "CP_CE_COUNTER"
6719  },
6720  {
6721   "chips": ["gfx81"],
6722   "map": {"at": 197228, "to": "mm"},
6723   "name": "CP_CE_RB_OFFSET",
6724   "type_ref": "CP_RB_OFFSET"
6725  },
6726  {
6727   "chips": ["gfx81"],
6728   "map": {"at": 197388, "to": "mm"},
6729   "name": "CP_CE_INIT_BASE_LO",
6730   "type_ref": "CP_CE_INIT_BASE_LO"
6731  },
6732  {
6733   "chips": ["gfx81"],
6734   "map": {"at": 197392, "to": "mm"},
6735   "name": "CP_CE_INIT_BASE_HI",
6736   "type_ref": "CP_CE_INIT_BASE_HI"
6737  },
6738  {
6739   "chips": ["gfx81"],
6740   "map": {"at": 197396, "to": "mm"},
6741   "name": "CP_CE_INIT_BUFSZ",
6742   "type_ref": "CP_CE_INIT_BUFSZ"
6743  },
6744  {
6745   "chips": ["gfx81"],
6746   "map": {"at": 197400, "to": "mm"},
6747   "name": "CP_CE_IB1_BASE_LO",
6748   "type_ref": "CP_CE_IB1_BASE_LO"
6749  },
6750  {
6751   "chips": ["gfx81"],
6752   "map": {"at": 197404, "to": "mm"},
6753   "name": "CP_CE_IB1_BASE_HI",
6754   "type_ref": "CP_CE_IB1_BASE_HI"
6755  },
6756  {
6757   "chips": ["gfx81"],
6758   "map": {"at": 197408, "to": "mm"},
6759   "name": "CP_CE_IB1_BUFSZ",
6760   "type_ref": "CP_CE_IB1_BUFSZ"
6761  },
6762  {
6763   "chips": ["gfx81"],
6764   "map": {"at": 197412, "to": "mm"},
6765   "name": "CP_CE_IB2_BASE_LO",
6766   "type_ref": "CP_CE_IB2_BASE_LO"
6767  },
6768  {
6769   "chips": ["gfx81"],
6770   "map": {"at": 197416, "to": "mm"},
6771   "name": "CP_CE_IB2_BASE_HI",
6772   "type_ref": "CP_CE_IB2_BASE_HI"
6773  },
6774  {
6775   "chips": ["gfx81"],
6776   "map": {"at": 197420, "to": "mm"},
6777   "name": "CP_CE_IB2_BUFSZ",
6778   "type_ref": "CP_CE_IB2_BUFSZ"
6779  },
6780  {
6781   "chips": ["gfx81"],
6782   "map": {"at": 197424, "to": "mm"},
6783   "name": "CP_IB1_BASE_LO",
6784   "type_ref": "CP_CE_IB1_BASE_LO"
6785  },
6786  {
6787   "chips": ["gfx81"],
6788   "map": {"at": 197428, "to": "mm"},
6789   "name": "CP_IB1_BASE_HI",
6790   "type_ref": "CP_CE_IB1_BASE_HI"
6791  },
6792  {
6793   "chips": ["gfx81"],
6794   "map": {"at": 197432, "to": "mm"},
6795   "name": "CP_IB1_BUFSZ",
6796   "type_ref": "CP_CE_IB1_BUFSZ"
6797  },
6798  {
6799   "chips": ["gfx81"],
6800   "map": {"at": 197436, "to": "mm"},
6801   "name": "CP_IB2_BASE_LO",
6802   "type_ref": "CP_CE_IB2_BASE_LO"
6803  },
6804  {
6805   "chips": ["gfx81"],
6806   "map": {"at": 197440, "to": "mm"},
6807   "name": "CP_IB2_BASE_HI",
6808   "type_ref": "CP_CE_IB2_BASE_HI"
6809  },
6810  {
6811   "chips": ["gfx81"],
6812   "map": {"at": 197444, "to": "mm"},
6813   "name": "CP_IB2_BUFSZ",
6814   "type_ref": "CP_CE_IB2_BUFSZ"
6815  },
6816  {
6817   "chips": ["gfx81"],
6818   "map": {"at": 197448, "to": "mm"},
6819   "name": "CP_ST_BASE_LO",
6820   "type_ref": "CP_ST_BASE_LO"
6821  },
6822  {
6823   "chips": ["gfx81"],
6824   "map": {"at": 197452, "to": "mm"},
6825   "name": "CP_ST_BASE_HI",
6826   "type_ref": "CP_ST_BASE_HI"
6827  },
6828  {
6829   "chips": ["gfx81"],
6830   "map": {"at": 197456, "to": "mm"},
6831   "name": "CP_ST_BUFSZ",
6832   "type_ref": "CP_ST_BUFSZ"
6833  },
6834  {
6835   "chips": ["gfx81"],
6836   "map": {"at": 197460, "to": "mm"},
6837   "name": "CP_EOP_DONE_EVENT_CNTL",
6838   "type_ref": "CP_EOP_DONE_EVENT_CNTL"
6839  },
6840  {
6841   "chips": ["gfx81"],
6842   "map": {"at": 197464, "to": "mm"},
6843   "name": "CP_EOP_DONE_DATA_CNTL",
6844   "type_ref": "CP_EOP_DONE_DATA_CNTL"
6845  },
6846  {
6847   "chips": ["gfx81"],
6848   "map": {"at": 197468, "to": "mm"},
6849   "name": "CP_EOP_DONE_CNTX_ID",
6850   "type_ref": "CP_EOP_DONE_CNTX_ID"
6851  },
6852  {
6853   "chips": ["gfx81"],
6854   "map": {"at": 197552, "to": "mm"},
6855   "name": "CP_PFP_COMPLETION_STATUS",
6856   "type_ref": "CP_PFP_COMPLETION_STATUS"
6857  },
6858  {
6859   "chips": ["gfx81"],
6860   "map": {"at": 197556, "to": "mm"},
6861   "name": "CP_CE_COMPLETION_STATUS",
6862   "type_ref": "CP_PFP_COMPLETION_STATUS"
6863  },
6864  {
6865   "chips": ["gfx81"],
6866   "map": {"at": 197560, "to": "mm"},
6867   "name": "CP_PRED_NOT_VISIBLE",
6868   "type_ref": "CP_PRED_NOT_VISIBLE"
6869  },
6870  {
6871   "chips": ["gfx81"],
6872   "map": {"at": 197568, "to": "mm"},
6873   "name": "CP_PFP_METADATA_BASE_ADDR"
6874  },
6875  {
6876   "chips": ["gfx81"],
6877   "map": {"at": 197572, "to": "mm"},
6878   "name": "CP_PFP_METADATA_BASE_ADDR_HI",
6879   "type_ref": "CP_EOP_DONE_ADDR_HI"
6880  },
6881  {
6882   "chips": ["gfx81"],
6883   "map": {"at": 197576, "to": "mm"},
6884   "name": "CP_CE_METADATA_BASE_ADDR"
6885  },
6886  {
6887   "chips": ["gfx81"],
6888   "map": {"at": 197580, "to": "mm"},
6889   "name": "CP_CE_METADATA_BASE_ADDR_HI",
6890   "type_ref": "CP_EOP_DONE_ADDR_HI"
6891  },
6892  {
6893   "chips": ["gfx81"],
6894   "map": {"at": 197584, "to": "mm"},
6895   "name": "CP_DRAW_INDX_INDR_ADDR"
6896  },
6897  {
6898   "chips": ["gfx81"],
6899   "map": {"at": 197588, "to": "mm"},
6900   "name": "CP_DRAW_INDX_INDR_ADDR_HI",
6901   "type_ref": "CP_EOP_DONE_ADDR_HI"
6902  },
6903  {
6904   "chips": ["gfx81"],
6905   "map": {"at": 197592, "to": "mm"},
6906   "name": "CP_DISPATCH_INDR_ADDR"
6907  },
6908  {
6909   "chips": ["gfx81"],
6910   "map": {"at": 197596, "to": "mm"},
6911   "name": "CP_DISPATCH_INDR_ADDR_HI",
6912   "type_ref": "CP_EOP_DONE_ADDR_HI"
6913  },
6914  {
6915   "chips": ["gfx81"],
6916   "map": {"at": 197600, "to": "mm"},
6917   "name": "CP_INDEX_BASE_ADDR"
6918  },
6919  {
6920   "chips": ["gfx81"],
6921   "map": {"at": 197604, "to": "mm"},
6922   "name": "CP_INDEX_BASE_ADDR_HI",
6923   "type_ref": "CP_EOP_DONE_ADDR_HI"
6924  },
6925  {
6926   "chips": ["gfx81"],
6927   "map": {"at": 197608, "to": "mm"},
6928   "name": "CP_INDEX_TYPE",
6929   "type_ref": "CP_INDEX_TYPE"
6930  },
6931  {
6932   "chips": ["gfx81"],
6933   "map": {"at": 197612, "to": "mm"},
6934   "name": "CP_GDS_BKUP_ADDR"
6935  },
6936  {
6937   "chips": ["gfx81"],
6938   "map": {"at": 197616, "to": "mm"},
6939   "name": "CP_GDS_BKUP_ADDR_HI",
6940   "type_ref": "CP_EOP_DONE_ADDR_HI"
6941  },
6942  {
6943   "chips": ["gfx81"],
6944   "map": {"at": 197620, "to": "mm"},
6945   "name": "CP_SAMPLE_STATUS",
6946   "type_ref": "CP_SAMPLE_STATUS"
6947  },
6948  {
6949   "chips": ["gfx81"],
6950   "map": {"at": 198656, "to": "mm"},
6951   "name": "GRBM_GFX_INDEX",
6952   "type_ref": "GRBM_GFX_INDEX"
6953  },
6954  {
6955   "chips": ["gfx81"],
6956   "map": {"at": 198912, "to": "mm"},
6957   "name": "VGT_ESGS_RING_SIZE"
6958  },
6959  {
6960   "chips": ["gfx81"],
6961   "map": {"at": 198916, "to": "mm"},
6962   "name": "VGT_GSVS_RING_SIZE"
6963  },
6964  {
6965   "chips": ["gfx81"],
6966   "map": {"at": 198920, "to": "mm"},
6967   "name": "VGT_PRIMITIVE_TYPE",
6968   "type_ref": "VGT_PRIMITIVE_TYPE"
6969  },
6970  {
6971   "chips": ["gfx81"],
6972   "map": {"at": 198924, "to": "mm"},
6973   "name": "VGT_INDEX_TYPE",
6974   "type_ref": "CP_INDEX_TYPE"
6975  },
6976  {
6977   "chips": ["gfx81"],
6978   "map": {"at": 198928, "to": "mm"},
6979   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_0"
6980  },
6981  {
6982   "chips": ["gfx81"],
6983   "map": {"at": 198932, "to": "mm"},
6984   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_1"
6985  },
6986  {
6987   "chips": ["gfx81"],
6988   "map": {"at": 198936, "to": "mm"},
6989   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_2"
6990  },
6991  {
6992   "chips": ["gfx81"],
6993   "map": {"at": 198940, "to": "mm"},
6994   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_3"
6995  },
6996  {
6997   "chips": ["gfx81"],
6998   "map": {"at": 198960, "to": "mm"},
6999   "name": "VGT_NUM_INDICES"
7000  },
7001  {
7002   "chips": ["gfx81"],
7003   "map": {"at": 198964, "to": "mm"},
7004   "name": "VGT_NUM_INSTANCES"
7005  },
7006  {
7007   "chips": ["gfx81"],
7008   "map": {"at": 198968, "to": "mm"},
7009   "name": "VGT_TF_RING_SIZE",
7010   "type_ref": "VGT_TF_RING_SIZE"
7011  },
7012  {
7013   "chips": ["gfx81"],
7014   "map": {"at": 198972, "to": "mm"},
7015   "name": "VGT_HS_OFFCHIP_PARAM",
7016   "type_ref": "VGT_HS_OFFCHIP_PARAM"
7017  },
7018  {
7019   "chips": ["gfx81"],
7020   "map": {"at": 198976, "to": "mm"},
7021   "name": "VGT_TF_MEMORY_BASE"
7022  },
7023  {
7024   "chips": ["gfx81"],
7025   "map": {"at": 199168, "to": "mm"},
7026   "name": "PA_SU_LINE_STIPPLE_VALUE",
7027   "type_ref": "PA_SU_LINE_STIPPLE_VALUE"
7028  },
7029  {
7030   "chips": ["gfx81"],
7031   "map": {"at": 199172, "to": "mm"},
7032   "name": "PA_SC_LINE_STIPPLE_STATE",
7033   "type_ref": "PA_SC_LINE_STIPPLE_STATE"
7034  },
7035  {
7036   "chips": ["gfx81"],
7037   "map": {"at": 199184, "to": "mm"},
7038   "name": "PA_SC_SCREEN_EXTENT_MIN_0",
7039   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
7040  },
7041  {
7042   "chips": ["gfx81"],
7043   "map": {"at": 199188, "to": "mm"},
7044   "name": "PA_SC_SCREEN_EXTENT_MAX_0",
7045   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
7046  },
7047  {
7048   "chips": ["gfx81"],
7049   "map": {"at": 199192, "to": "mm"},
7050   "name": "PA_SC_SCREEN_EXTENT_MIN_1",
7051   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
7052  },
7053  {
7054   "chips": ["gfx81"],
7055   "map": {"at": 199212, "to": "mm"},
7056   "name": "PA_SC_SCREEN_EXTENT_MAX_1",
7057   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
7058  },
7059  {
7060   "chips": ["gfx81"],
7061   "map": {"at": 199296, "to": "mm"},
7062   "name": "PA_SC_P3D_TRAP_SCREEN_HV_EN",
7063   "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN"
7064  },
7065  {
7066   "chips": ["gfx81"],
7067   "map": {"at": 199300, "to": "mm"},
7068   "name": "PA_SC_P3D_TRAP_SCREEN_H",
7069   "type_ref": "PA_SC_P3D_TRAP_SCREEN_H"
7070  },
7071  {
7072   "chips": ["gfx81"],
7073   "map": {"at": 199304, "to": "mm"},
7074   "name": "PA_SC_P3D_TRAP_SCREEN_V",
7075   "type_ref": "PA_SC_P3D_TRAP_SCREEN_V"
7076  },
7077  {
7078   "chips": ["gfx81"],
7079   "map": {"at": 199308, "to": "mm"},
7080   "name": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE",
7081   "type_ref": "CP_DRAW_OBJECT_COUNTER"
7082  },
7083  {
7084   "chips": ["gfx81"],
7085   "map": {"at": 199312, "to": "mm"},
7086   "name": "PA_SC_P3D_TRAP_SCREEN_COUNT",
7087   "type_ref": "CP_DRAW_OBJECT_COUNTER"
7088  },
7089  {
7090   "chips": ["gfx81"],
7091   "map": {"at": 199328, "to": "mm"},
7092   "name": "PA_SC_HP3D_TRAP_SCREEN_HV_EN",
7093   "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN"
7094  },
7095  {
7096   "chips": ["gfx81"],
7097   "map": {"at": 199332, "to": "mm"},
7098   "name": "PA_SC_HP3D_TRAP_SCREEN_H",
7099   "type_ref": "PA_SC_P3D_TRAP_SCREEN_H"
7100  },
7101  {
7102   "chips": ["gfx81"],
7103   "map": {"at": 199336, "to": "mm"},
7104   "name": "PA_SC_HP3D_TRAP_SCREEN_V",
7105   "type_ref": "PA_SC_P3D_TRAP_SCREEN_V"
7106  },
7107  {
7108   "chips": ["gfx81"],
7109   "map": {"at": 199340, "to": "mm"},
7110   "name": "PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE",
7111   "type_ref": "CP_DRAW_OBJECT_COUNTER"
7112  },
7113  {
7114   "chips": ["gfx81"],
7115   "map": {"at": 199344, "to": "mm"},
7116   "name": "PA_SC_HP3D_TRAP_SCREEN_COUNT",
7117   "type_ref": "CP_DRAW_OBJECT_COUNTER"
7118  },
7119  {
7120   "chips": ["gfx81"],
7121   "map": {"at": 199360, "to": "mm"},
7122   "name": "PA_SC_TRAP_SCREEN_HV_EN",
7123   "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN"
7124  },
7125  {
7126   "chips": ["gfx81"],
7127   "map": {"at": 199364, "to": "mm"},
7128   "name": "PA_SC_TRAP_SCREEN_H",
7129   "type_ref": "PA_SC_P3D_TRAP_SCREEN_H"
7130  },
7131  {
7132   "chips": ["gfx81"],
7133   "map": {"at": 199368, "to": "mm"},
7134   "name": "PA_SC_TRAP_SCREEN_V",
7135   "type_ref": "PA_SC_P3D_TRAP_SCREEN_V"
7136  },
7137  {
7138   "chips": ["gfx81"],
7139   "map": {"at": 199372, "to": "mm"},
7140   "name": "PA_SC_TRAP_SCREEN_OCCURRENCE",
7141   "type_ref": "CP_DRAW_OBJECT_COUNTER"
7142  },
7143  {
7144   "chips": ["gfx81"],
7145   "map": {"at": 199376, "to": "mm"},
7146   "name": "PA_SC_TRAP_SCREEN_COUNT",
7147   "type_ref": "CP_DRAW_OBJECT_COUNTER"
7148  },
7149  {
7150   "chips": ["gfx81"],
7151   "map": {"at": 199872, "to": "mm"},
7152   "name": "SQ_THREAD_TRACE_BASE"
7153  },
7154  {
7155   "chips": ["gfx81"],
7156   "map": {"at": 199876, "to": "mm"},
7157   "name": "SQ_THREAD_TRACE_SIZE",
7158   "type_ref": "SQ_THREAD_TRACE_SIZE"
7159  },
7160  {
7161   "chips": ["gfx81"],
7162   "map": {"at": 199880, "to": "mm"},
7163   "name": "SQ_THREAD_TRACE_MASK",
7164   "type_ref": "SQ_THREAD_TRACE_MASK"
7165  },
7166  {
7167   "chips": ["gfx81"],
7168   "map": {"at": 199884, "to": "mm"},
7169   "name": "SQ_THREAD_TRACE_TOKEN_MASK",
7170   "type_ref": "SQ_THREAD_TRACE_TOKEN_MASK"
7171  },
7172  {
7173   "chips": ["gfx81"],
7174   "map": {"at": 199888, "to": "mm"},
7175   "name": "SQ_THREAD_TRACE_PERF_MASK",
7176   "type_ref": "SQ_PERFCOUNTER_MASK"
7177  },
7178  {
7179   "chips": ["gfx81"],
7180   "map": {"at": 199892, "to": "mm"},
7181   "name": "SQ_THREAD_TRACE_CTRL",
7182   "type_ref": "SQ_THREAD_TRACE_CTRL"
7183  },
7184  {
7185   "chips": ["gfx81"],
7186   "map": {"at": 199896, "to": "mm"},
7187   "name": "SQ_THREAD_TRACE_MODE",
7188   "type_ref": "SQ_THREAD_TRACE_MODE"
7189  },
7190  {
7191   "chips": ["gfx81"],
7192   "map": {"at": 199900, "to": "mm"},
7193   "name": "SQ_THREAD_TRACE_BASE2",
7194   "type_ref": "SQ_THREAD_TRACE_BASE2"
7195  },
7196  {
7197   "chips": ["gfx81"],
7198   "map": {"at": 199904, "to": "mm"},
7199   "name": "SQ_THREAD_TRACE_TOKEN_MASK2"
7200  },
7201  {
7202   "chips": ["gfx81"],
7203   "map": {"at": 199908, "to": "mm"},
7204   "name": "SQ_THREAD_TRACE_WPTR",
7205   "type_ref": "SQ_THREAD_TRACE_WPTR"
7206  },
7207  {
7208   "chips": ["gfx81"],
7209   "map": {"at": 199912, "to": "mm"},
7210   "name": "SQ_THREAD_TRACE_STATUS",
7211   "type_ref": "SQ_THREAD_TRACE_STATUS"
7212  },
7213  {
7214   "chips": ["gfx81"],
7215   "map": {"at": 199916, "to": "mm"},
7216   "name": "SQ_THREAD_TRACE_HIWATER",
7217   "type_ref": "SQ_THREAD_TRACE_HIWATER"
7218  },
7219  {
7220   "chips": ["gfx81"],
7221   "map": {"at": 199936, "to": "mm"},
7222   "name": "SQ_THREAD_TRACE_USERDATA_0"
7223  },
7224  {
7225   "chips": ["gfx81"],
7226   "map": {"at": 199940, "to": "mm"},
7227   "name": "SQ_THREAD_TRACE_USERDATA_1"
7228  },
7229  {
7230   "chips": ["gfx81"],
7231   "map": {"at": 199944, "to": "mm"},
7232   "name": "SQ_THREAD_TRACE_USERDATA_2"
7233  },
7234  {
7235   "chips": ["gfx81"],
7236   "map": {"at": 199948, "to": "mm"},
7237   "name": "SQ_THREAD_TRACE_USERDATA_3"
7238  },
7239  {
7240   "chips": ["gfx81"],
7241   "map": {"at": 199968, "to": "mm"},
7242   "name": "SQC_CACHES",
7243   "type_ref": "SQC_CACHES"
7244  },
7245  {
7246   "chips": ["gfx81"],
7247   "map": {"at": 199972, "to": "mm"},
7248   "name": "SQC_WRITEBACK",
7249   "type_ref": "SQC_WRITEBACK"
7250  },
7251  {
7252   "chips": ["gfx81"],
7253   "map": {"at": 200192, "to": "mm"},
7254   "name": "TA_CS_BC_BASE_ADDR"
7255  },
7256  {
7257   "chips": ["gfx81"],
7258   "map": {"at": 200196, "to": "mm"},
7259   "name": "TA_CS_BC_BASE_ADDR_HI",
7260   "type_ref": "TA_BC_BASE_ADDR_HI"
7261  },
7262  {
7263   "chips": ["gfx81"],
7264   "map": {"at": 200448, "to": "mm"},
7265   "name": "DB_OCCLUSION_COUNT0_LOW"
7266  },
7267  {
7268   "chips": ["gfx81"],
7269   "map": {"at": 200452, "to": "mm"},
7270   "name": "DB_OCCLUSION_COUNT0_HI",
7271   "type_ref": "DB_ZPASS_COUNT_HI"
7272  },
7273  {
7274   "chips": ["gfx81"],
7275   "map": {"at": 200456, "to": "mm"},
7276   "name": "DB_OCCLUSION_COUNT1_LOW"
7277  },
7278  {
7279   "chips": ["gfx81"],
7280   "map": {"at": 200460, "to": "mm"},
7281   "name": "DB_OCCLUSION_COUNT1_HI",
7282   "type_ref": "DB_ZPASS_COUNT_HI"
7283  },
7284  {
7285   "chips": ["gfx81"],
7286   "map": {"at": 200464, "to": "mm"},
7287   "name": "DB_OCCLUSION_COUNT2_LOW"
7288  },
7289  {
7290   "chips": ["gfx81"],
7291   "map": {"at": 200468, "to": "mm"},
7292   "name": "DB_OCCLUSION_COUNT2_HI",
7293   "type_ref": "DB_ZPASS_COUNT_HI"
7294  },
7295  {
7296   "chips": ["gfx81"],
7297   "map": {"at": 200472, "to": "mm"},
7298   "name": "DB_OCCLUSION_COUNT3_LOW"
7299  },
7300  {
7301   "chips": ["gfx81"],
7302   "map": {"at": 200476, "to": "mm"},
7303   "name": "DB_OCCLUSION_COUNT3_HI",
7304   "type_ref": "DB_ZPASS_COUNT_HI"
7305  },
7306  {
7307   "chips": ["gfx81"],
7308   "map": {"at": 200696, "to": "mm"},
7309   "name": "DB_ZPASS_COUNT_LOW"
7310  },
7311  {
7312   "chips": ["gfx81"],
7313   "map": {"at": 200700, "to": "mm"},
7314   "name": "DB_ZPASS_COUNT_HI",
7315   "type_ref": "DB_ZPASS_COUNT_HI"
7316  },
7317  {
7318   "chips": ["gfx81"],
7319   "map": {"at": 200704, "to": "mm"},
7320   "name": "GDS_RD_ADDR"
7321  },
7322  {
7323   "chips": ["gfx81"],
7324   "map": {"at": 200708, "to": "mm"},
7325   "name": "GDS_RD_DATA"
7326  },
7327  {
7328   "chips": ["gfx81"],
7329   "map": {"at": 200712, "to": "mm"},
7330   "name": "GDS_RD_BURST_ADDR"
7331  },
7332  {
7333   "chips": ["gfx81"],
7334   "map": {"at": 200716, "to": "mm"},
7335   "name": "GDS_RD_BURST_COUNT"
7336  },
7337  {
7338   "chips": ["gfx81"],
7339   "map": {"at": 200720, "to": "mm"},
7340   "name": "GDS_RD_BURST_DATA"
7341  },
7342  {
7343   "chips": ["gfx81"],
7344   "map": {"at": 200724, "to": "mm"},
7345   "name": "GDS_WR_ADDR"
7346  },
7347  {
7348   "chips": ["gfx81"],
7349   "map": {"at": 200728, "to": "mm"},
7350   "name": "GDS_WR_DATA"
7351  },
7352  {
7353   "chips": ["gfx81"],
7354   "map": {"at": 200732, "to": "mm"},
7355   "name": "GDS_WR_BURST_ADDR"
7356  },
7357  {
7358   "chips": ["gfx81"],
7359   "map": {"at": 200736, "to": "mm"},
7360   "name": "GDS_WR_BURST_DATA"
7361  },
7362  {
7363   "chips": ["gfx81"],
7364   "map": {"at": 200740, "to": "mm"},
7365   "name": "GDS_WRITE_COMPLETE"
7366  },
7367  {
7368   "chips": ["gfx81"],
7369   "map": {"at": 200744, "to": "mm"},
7370   "name": "GDS_ATOM_CNTL",
7371   "type_ref": "GDS_ATOM_CNTL"
7372  },
7373  {
7374   "chips": ["gfx81"],
7375   "map": {"at": 200748, "to": "mm"},
7376   "name": "GDS_ATOM_COMPLETE",
7377   "type_ref": "GDS_ATOM_COMPLETE"
7378  },
7379  {
7380   "chips": ["gfx81"],
7381   "map": {"at": 200752, "to": "mm"},
7382   "name": "GDS_ATOM_BASE",
7383   "type_ref": "GDS_ATOM_BASE"
7384  },
7385  {
7386   "chips": ["gfx81"],
7387   "map": {"at": 200756, "to": "mm"},
7388   "name": "GDS_ATOM_SIZE",
7389   "type_ref": "GDS_ATOM_SIZE"
7390  },
7391  {
7392   "chips": ["gfx81"],
7393   "map": {"at": 200760, "to": "mm"},
7394   "name": "GDS_ATOM_OFFSET0",
7395   "type_ref": "GDS_ATOM_OFFSET0"
7396  },
7397  {
7398   "chips": ["gfx81"],
7399   "map": {"at": 200764, "to": "mm"},
7400   "name": "GDS_ATOM_OFFSET1",
7401   "type_ref": "GDS_ATOM_OFFSET1"
7402  },
7403  {
7404   "chips": ["gfx81"],
7405   "map": {"at": 200768, "to": "mm"},
7406   "name": "GDS_ATOM_DST"
7407  },
7408  {
7409   "chips": ["gfx81"],
7410   "map": {"at": 200772, "to": "mm"},
7411   "name": "GDS_ATOM_OP",
7412   "type_ref": "GDS_ATOM_OP"
7413  },
7414  {
7415   "chips": ["gfx81"],
7416   "map": {"at": 200776, "to": "mm"},
7417   "name": "GDS_ATOM_SRC0"
7418  },
7419  {
7420   "chips": ["gfx81"],
7421   "map": {"at": 200780, "to": "mm"},
7422   "name": "GDS_ATOM_SRC0_U"
7423  },
7424  {
7425   "chips": ["gfx81"],
7426   "map": {"at": 200784, "to": "mm"},
7427   "name": "GDS_ATOM_SRC1"
7428  },
7429  {
7430   "chips": ["gfx81"],
7431   "map": {"at": 200788, "to": "mm"},
7432   "name": "GDS_ATOM_SRC1_U"
7433  },
7434  {
7435   "chips": ["gfx81"],
7436   "map": {"at": 200792, "to": "mm"},
7437   "name": "GDS_ATOM_READ0"
7438  },
7439  {
7440   "chips": ["gfx81"],
7441   "map": {"at": 200796, "to": "mm"},
7442   "name": "GDS_ATOM_READ0_U"
7443  },
7444  {
7445   "chips": ["gfx81"],
7446   "map": {"at": 200800, "to": "mm"},
7447   "name": "GDS_ATOM_READ1"
7448  },
7449  {
7450   "chips": ["gfx81"],
7451   "map": {"at": 200804, "to": "mm"},
7452   "name": "GDS_ATOM_READ1_U"
7453  },
7454  {
7455   "chips": ["gfx81"],
7456   "map": {"at": 200808, "to": "mm"},
7457   "name": "GDS_GWS_RESOURCE_CNTL",
7458   "type_ref": "GDS_GWS_RESOURCE_CNTL"
7459  },
7460  {
7461   "chips": ["gfx81"],
7462   "map": {"at": 200812, "to": "mm"},
7463   "name": "GDS_GWS_RESOURCE",
7464   "type_ref": "GDS_GWS_RESOURCE"
7465  },
7466  {
7467   "chips": ["gfx81"],
7468   "map": {"at": 200816, "to": "mm"},
7469   "name": "GDS_GWS_RESOURCE_CNT",
7470   "type_ref": "GDS_GWS_RESOURCE_CNT"
7471  },
7472  {
7473   "chips": ["gfx81"],
7474   "map": {"at": 200820, "to": "mm"},
7475   "name": "GDS_OA_CNTL",
7476   "type_ref": "GDS_OA_CNTL"
7477  },
7478  {
7479   "chips": ["gfx81"],
7480   "map": {"at": 200824, "to": "mm"},
7481   "name": "GDS_OA_COUNTER"
7482  },
7483  {
7484   "chips": ["gfx81"],
7485   "map": {"at": 200828, "to": "mm"},
7486   "name": "GDS_OA_ADDRESS",
7487   "type_ref": "GDS_OA_ADDRESS"
7488  },
7489  {
7490   "chips": ["gfx81"],
7491   "map": {"at": 200832, "to": "mm"},
7492   "name": "GDS_OA_INCDEC",
7493   "type_ref": "GDS_OA_INCDEC"
7494  },
7495  {
7496   "chips": ["gfx81"],
7497   "map": {"at": 200836, "to": "mm"},
7498   "name": "GDS_OA_RING_SIZE"
7499  },
7500  {
7501   "chips": ["gfx81"],
7502   "map": {"at": 212992, "to": "mm"},
7503   "name": "CPG_PERFCOUNTER1_LO"
7504  },
7505  {
7506   "chips": ["gfx81"],
7507   "map": {"at": 212996, "to": "mm"},
7508   "name": "CPG_PERFCOUNTER1_HI"
7509  },
7510  {
7511   "chips": ["gfx81"],
7512   "map": {"at": 213000, "to": "mm"},
7513   "name": "CPG_PERFCOUNTER0_LO"
7514  },
7515  {
7516   "chips": ["gfx81"],
7517   "map": {"at": 213004, "to": "mm"},
7518   "name": "CPG_PERFCOUNTER0_HI"
7519  },
7520  {
7521   "chips": ["gfx81"],
7522   "map": {"at": 213008, "to": "mm"},
7523   "name": "CPC_PERFCOUNTER1_LO"
7524  },
7525  {
7526   "chips": ["gfx81"],
7527   "map": {"at": 213012, "to": "mm"},
7528   "name": "CPC_PERFCOUNTER1_HI"
7529  },
7530  {
7531   "chips": ["gfx81"],
7532   "map": {"at": 213016, "to": "mm"},
7533   "name": "CPC_PERFCOUNTER0_LO"
7534  },
7535  {
7536   "chips": ["gfx81"],
7537   "map": {"at": 213020, "to": "mm"},
7538   "name": "CPC_PERFCOUNTER0_HI"
7539  },
7540  {
7541   "chips": ["gfx81"],
7542   "map": {"at": 213024, "to": "mm"},
7543   "name": "CPF_PERFCOUNTER1_LO"
7544  },
7545  {
7546   "chips": ["gfx81"],
7547   "map": {"at": 213028, "to": "mm"},
7548   "name": "CPF_PERFCOUNTER1_HI"
7549  },
7550  {
7551   "chips": ["gfx81"],
7552   "map": {"at": 213032, "to": "mm"},
7553   "name": "CPF_PERFCOUNTER0_LO"
7554  },
7555  {
7556   "chips": ["gfx81"],
7557   "map": {"at": 213036, "to": "mm"},
7558   "name": "CPF_PERFCOUNTER0_HI"
7559  },
7560  {
7561   "chips": ["gfx81"],
7562   "map": {"at": 213248, "to": "mm"},
7563   "name": "GRBM_PERFCOUNTER0_LO"
7564  },
7565  {
7566   "chips": ["gfx81"],
7567   "map": {"at": 213252, "to": "mm"},
7568   "name": "GRBM_PERFCOUNTER0_HI"
7569  },
7570  {
7571   "chips": ["gfx81"],
7572   "map": {"at": 213260, "to": "mm"},
7573   "name": "GRBM_PERFCOUNTER1_LO"
7574  },
7575  {
7576   "chips": ["gfx81"],
7577   "map": {"at": 213264, "to": "mm"},
7578   "name": "GRBM_PERFCOUNTER1_HI"
7579  },
7580  {
7581   "chips": ["gfx81"],
7582   "map": {"at": 213268, "to": "mm"},
7583   "name": "GRBM_SE0_PERFCOUNTER_LO"
7584  },
7585  {
7586   "chips": ["gfx81"],
7587   "map": {"at": 213272, "to": "mm"},
7588   "name": "GRBM_SE0_PERFCOUNTER_HI"
7589  },
7590  {
7591   "chips": ["gfx81"],
7592   "map": {"at": 213276, "to": "mm"},
7593   "name": "GRBM_SE1_PERFCOUNTER_LO"
7594  },
7595  {
7596   "chips": ["gfx81"],
7597   "map": {"at": 213280, "to": "mm"},
7598   "name": "GRBM_SE1_PERFCOUNTER_HI"
7599  },
7600  {
7601   "chips": ["gfx81"],
7602   "map": {"at": 213284, "to": "mm"},
7603   "name": "GRBM_SE2_PERFCOUNTER_LO"
7604  },
7605  {
7606   "chips": ["gfx81"],
7607   "map": {"at": 213288, "to": "mm"},
7608   "name": "GRBM_SE2_PERFCOUNTER_HI"
7609  },
7610  {
7611   "chips": ["gfx81"],
7612   "map": {"at": 213292, "to": "mm"},
7613   "name": "GRBM_SE3_PERFCOUNTER_LO"
7614  },
7615  {
7616   "chips": ["gfx81"],
7617   "map": {"at": 213296, "to": "mm"},
7618   "name": "GRBM_SE3_PERFCOUNTER_HI"
7619  },
7620  {
7621   "chips": ["gfx81"],
7622   "map": {"at": 213504, "to": "mm"},
7623   "name": "WD_PERFCOUNTER0_LO"
7624  },
7625  {
7626   "chips": ["gfx81"],
7627   "map": {"at": 213508, "to": "mm"},
7628   "name": "WD_PERFCOUNTER0_HI"
7629  },
7630  {
7631   "chips": ["gfx81"],
7632   "map": {"at": 213512, "to": "mm"},
7633   "name": "WD_PERFCOUNTER1_LO"
7634  },
7635  {
7636   "chips": ["gfx81"],
7637   "map": {"at": 213516, "to": "mm"},
7638   "name": "WD_PERFCOUNTER1_HI"
7639  },
7640  {
7641   "chips": ["gfx81"],
7642   "map": {"at": 213520, "to": "mm"},
7643   "name": "WD_PERFCOUNTER2_LO"
7644  },
7645  {
7646   "chips": ["gfx81"],
7647   "map": {"at": 213524, "to": "mm"},
7648   "name": "WD_PERFCOUNTER2_HI"
7649  },
7650  {
7651   "chips": ["gfx81"],
7652   "map": {"at": 213528, "to": "mm"},
7653   "name": "WD_PERFCOUNTER3_LO"
7654  },
7655  {
7656   "chips": ["gfx81"],
7657   "map": {"at": 213532, "to": "mm"},
7658   "name": "WD_PERFCOUNTER3_HI"
7659  },
7660  {
7661   "chips": ["gfx81"],
7662   "map": {"at": 213536, "to": "mm"},
7663   "name": "IA_PERFCOUNTER0_LO"
7664  },
7665  {
7666   "chips": ["gfx81"],
7667   "map": {"at": 213540, "to": "mm"},
7668   "name": "IA_PERFCOUNTER0_HI"
7669  },
7670  {
7671   "chips": ["gfx81"],
7672   "map": {"at": 213544, "to": "mm"},
7673   "name": "IA_PERFCOUNTER1_LO"
7674  },
7675  {
7676   "chips": ["gfx81"],
7677   "map": {"at": 213548, "to": "mm"},
7678   "name": "IA_PERFCOUNTER1_HI"
7679  },
7680  {
7681   "chips": ["gfx81"],
7682   "map": {"at": 213552, "to": "mm"},
7683   "name": "IA_PERFCOUNTER2_LO"
7684  },
7685  {
7686   "chips": ["gfx81"],
7687   "map": {"at": 213556, "to": "mm"},
7688   "name": "IA_PERFCOUNTER2_HI"
7689  },
7690  {
7691   "chips": ["gfx81"],
7692   "map": {"at": 213560, "to": "mm"},
7693   "name": "IA_PERFCOUNTER3_LO"
7694  },
7695  {
7696   "chips": ["gfx81"],
7697   "map": {"at": 213564, "to": "mm"},
7698   "name": "IA_PERFCOUNTER3_HI"
7699  },
7700  {
7701   "chips": ["gfx81"],
7702   "map": {"at": 213568, "to": "mm"},
7703   "name": "VGT_PERFCOUNTER0_LO"
7704  },
7705  {
7706   "chips": ["gfx81"],
7707   "map": {"at": 213572, "to": "mm"},
7708   "name": "VGT_PERFCOUNTER0_HI"
7709  },
7710  {
7711   "chips": ["gfx81"],
7712   "map": {"at": 213576, "to": "mm"},
7713   "name": "VGT_PERFCOUNTER1_LO"
7714  },
7715  {
7716   "chips": ["gfx81"],
7717   "map": {"at": 213580, "to": "mm"},
7718   "name": "VGT_PERFCOUNTER1_HI"
7719  },
7720  {
7721   "chips": ["gfx81"],
7722   "map": {"at": 213584, "to": "mm"},
7723   "name": "VGT_PERFCOUNTER2_LO"
7724  },
7725  {
7726   "chips": ["gfx81"],
7727   "map": {"at": 213588, "to": "mm"},
7728   "name": "VGT_PERFCOUNTER2_HI"
7729  },
7730  {
7731   "chips": ["gfx81"],
7732   "map": {"at": 213592, "to": "mm"},
7733   "name": "VGT_PERFCOUNTER3_LO"
7734  },
7735  {
7736   "chips": ["gfx81"],
7737   "map": {"at": 213596, "to": "mm"},
7738   "name": "VGT_PERFCOUNTER3_HI"
7739  },
7740  {
7741   "chips": ["gfx81"],
7742   "map": {"at": 214016, "to": "mm"},
7743   "name": "PA_SU_PERFCOUNTER0_LO"
7744  },
7745  {
7746   "chips": ["gfx81"],
7747   "map": {"at": 214020, "to": "mm"},
7748   "name": "PA_SU_PERFCOUNTER0_HI",
7749   "type_ref": "PA_SU_PERFCOUNTER0_HI"
7750  },
7751  {
7752   "chips": ["gfx81"],
7753   "map": {"at": 214024, "to": "mm"},
7754   "name": "PA_SU_PERFCOUNTER1_LO"
7755  },
7756  {
7757   "chips": ["gfx81"],
7758   "map": {"at": 214028, "to": "mm"},
7759   "name": "PA_SU_PERFCOUNTER1_HI",
7760   "type_ref": "PA_SU_PERFCOUNTER0_HI"
7761  },
7762  {
7763   "chips": ["gfx81"],
7764   "map": {"at": 214032, "to": "mm"},
7765   "name": "PA_SU_PERFCOUNTER2_LO"
7766  },
7767  {
7768   "chips": ["gfx81"],
7769   "map": {"at": 214036, "to": "mm"},
7770   "name": "PA_SU_PERFCOUNTER2_HI",
7771   "type_ref": "PA_SU_PERFCOUNTER0_HI"
7772  },
7773  {
7774   "chips": ["gfx81"],
7775   "map": {"at": 214040, "to": "mm"},
7776   "name": "PA_SU_PERFCOUNTER3_LO"
7777  },
7778  {
7779   "chips": ["gfx81"],
7780   "map": {"at": 214044, "to": "mm"},
7781   "name": "PA_SU_PERFCOUNTER3_HI",
7782   "type_ref": "PA_SU_PERFCOUNTER0_HI"
7783  },
7784  {
7785   "chips": ["gfx81"],
7786   "map": {"at": 214272, "to": "mm"},
7787   "name": "PA_SC_PERFCOUNTER0_LO"
7788  },
7789  {
7790   "chips": ["gfx81"],
7791   "map": {"at": 214276, "to": "mm"},
7792   "name": "PA_SC_PERFCOUNTER0_HI"
7793  },
7794  {
7795   "chips": ["gfx81"],
7796   "map": {"at": 214280, "to": "mm"},
7797   "name": "PA_SC_PERFCOUNTER1_LO"
7798  },
7799  {
7800   "chips": ["gfx81"],
7801   "map": {"at": 214284, "to": "mm"},
7802   "name": "PA_SC_PERFCOUNTER1_HI"
7803  },
7804  {
7805   "chips": ["gfx81"],
7806   "map": {"at": 214288, "to": "mm"},
7807   "name": "PA_SC_PERFCOUNTER2_LO"
7808  },
7809  {
7810   "chips": ["gfx81"],
7811   "map": {"at": 214292, "to": "mm"},
7812   "name": "PA_SC_PERFCOUNTER2_HI"
7813  },
7814  {
7815   "chips": ["gfx81"],
7816   "map": {"at": 214296, "to": "mm"},
7817   "name": "PA_SC_PERFCOUNTER3_LO"
7818  },
7819  {
7820   "chips": ["gfx81"],
7821   "map": {"at": 214300, "to": "mm"},
7822   "name": "PA_SC_PERFCOUNTER3_HI"
7823  },
7824  {
7825   "chips": ["gfx81"],
7826   "map": {"at": 214304, "to": "mm"},
7827   "name": "PA_SC_PERFCOUNTER4_LO"
7828  },
7829  {
7830   "chips": ["gfx81"],
7831   "map": {"at": 214308, "to": "mm"},
7832   "name": "PA_SC_PERFCOUNTER4_HI"
7833  },
7834  {
7835   "chips": ["gfx81"],
7836   "map": {"at": 214312, "to": "mm"},
7837   "name": "PA_SC_PERFCOUNTER5_LO"
7838  },
7839  {
7840   "chips": ["gfx81"],
7841   "map": {"at": 214316, "to": "mm"},
7842   "name": "PA_SC_PERFCOUNTER5_HI"
7843  },
7844  {
7845   "chips": ["gfx81"],
7846   "map": {"at": 214320, "to": "mm"},
7847   "name": "PA_SC_PERFCOUNTER6_LO"
7848  },
7849  {
7850   "chips": ["gfx81"],
7851   "map": {"at": 214324, "to": "mm"},
7852   "name": "PA_SC_PERFCOUNTER6_HI"
7853  },
7854  {
7855   "chips": ["gfx81"],
7856   "map": {"at": 214328, "to": "mm"},
7857   "name": "PA_SC_PERFCOUNTER7_LO"
7858  },
7859  {
7860   "chips": ["gfx81"],
7861   "map": {"at": 214332, "to": "mm"},
7862   "name": "PA_SC_PERFCOUNTER7_HI"
7863  },
7864  {
7865   "chips": ["gfx81"],
7866   "map": {"at": 214528, "to": "mm"},
7867   "name": "SPI_PERFCOUNTER0_HI"
7868  },
7869  {
7870   "chips": ["gfx81"],
7871   "map": {"at": 214532, "to": "mm"},
7872   "name": "SPI_PERFCOUNTER0_LO"
7873  },
7874  {
7875   "chips": ["gfx81"],
7876   "map": {"at": 214536, "to": "mm"},
7877   "name": "SPI_PERFCOUNTER1_HI"
7878  },
7879  {
7880   "chips": ["gfx81"],
7881   "map": {"at": 214540, "to": "mm"},
7882   "name": "SPI_PERFCOUNTER1_LO"
7883  },
7884  {
7885   "chips": ["gfx81"],
7886   "map": {"at": 214544, "to": "mm"},
7887   "name": "SPI_PERFCOUNTER2_HI"
7888  },
7889  {
7890   "chips": ["gfx81"],
7891   "map": {"at": 214548, "to": "mm"},
7892   "name": "SPI_PERFCOUNTER2_LO"
7893  },
7894  {
7895   "chips": ["gfx81"],
7896   "map": {"at": 214552, "to": "mm"},
7897   "name": "SPI_PERFCOUNTER3_HI"
7898  },
7899  {
7900   "chips": ["gfx81"],
7901   "map": {"at": 214556, "to": "mm"},
7902   "name": "SPI_PERFCOUNTER3_LO"
7903  },
7904  {
7905   "chips": ["gfx81"],
7906   "map": {"at": 214560, "to": "mm"},
7907   "name": "SPI_PERFCOUNTER4_HI"
7908  },
7909  {
7910   "chips": ["gfx81"],
7911   "map": {"at": 214564, "to": "mm"},
7912   "name": "SPI_PERFCOUNTER4_LO"
7913  },
7914  {
7915   "chips": ["gfx81"],
7916   "map": {"at": 214568, "to": "mm"},
7917   "name": "SPI_PERFCOUNTER5_HI"
7918  },
7919  {
7920   "chips": ["gfx81"],
7921   "map": {"at": 214572, "to": "mm"},
7922   "name": "SPI_PERFCOUNTER5_LO"
7923  },
7924  {
7925   "chips": ["gfx81"],
7926   "map": {"at": 214784, "to": "mm"},
7927   "name": "SQ_PERFCOUNTER0_LO"
7928  },
7929  {
7930   "chips": ["gfx81"],
7931   "map": {"at": 214788, "to": "mm"},
7932   "name": "SQ_PERFCOUNTER0_HI"
7933  },
7934  {
7935   "chips": ["gfx81"],
7936   "map": {"at": 214792, "to": "mm"},
7937   "name": "SQ_PERFCOUNTER1_LO"
7938  },
7939  {
7940   "chips": ["gfx81"],
7941   "map": {"at": 214796, "to": "mm"},
7942   "name": "SQ_PERFCOUNTER1_HI"
7943  },
7944  {
7945   "chips": ["gfx81"],
7946   "map": {"at": 214800, "to": "mm"},
7947   "name": "SQ_PERFCOUNTER2_LO"
7948  },
7949  {
7950   "chips": ["gfx81"],
7951   "map": {"at": 214804, "to": "mm"},
7952   "name": "SQ_PERFCOUNTER2_HI"
7953  },
7954  {
7955   "chips": ["gfx81"],
7956   "map": {"at": 214808, "to": "mm"},
7957   "name": "SQ_PERFCOUNTER3_LO"
7958  },
7959  {
7960   "chips": ["gfx81"],
7961   "map": {"at": 214812, "to": "mm"},
7962   "name": "SQ_PERFCOUNTER3_HI"
7963  },
7964  {
7965   "chips": ["gfx81"],
7966   "map": {"at": 214816, "to": "mm"},
7967   "name": "SQ_PERFCOUNTER4_LO"
7968  },
7969  {
7970   "chips": ["gfx81"],
7971   "map": {"at": 214820, "to": "mm"},
7972   "name": "SQ_PERFCOUNTER4_HI"
7973  },
7974  {
7975   "chips": ["gfx81"],
7976   "map": {"at": 214824, "to": "mm"},
7977   "name": "SQ_PERFCOUNTER5_LO"
7978  },
7979  {
7980   "chips": ["gfx81"],
7981   "map": {"at": 214828, "to": "mm"},
7982   "name": "SQ_PERFCOUNTER5_HI"
7983  },
7984  {
7985   "chips": ["gfx81"],
7986   "map": {"at": 214832, "to": "mm"},
7987   "name": "SQ_PERFCOUNTER6_LO"
7988  },
7989  {
7990   "chips": ["gfx81"],
7991   "map": {"at": 214836, "to": "mm"},
7992   "name": "SQ_PERFCOUNTER6_HI"
7993  },
7994  {
7995   "chips": ["gfx81"],
7996   "map": {"at": 214840, "to": "mm"},
7997   "name": "SQ_PERFCOUNTER7_LO"
7998  },
7999  {
8000   "chips": ["gfx81"],
8001   "map": {"at": 214844, "to": "mm"},
8002   "name": "SQ_PERFCOUNTER7_HI"
8003  },
8004  {
8005   "chips": ["gfx81"],
8006   "map": {"at": 214848, "to": "mm"},
8007   "name": "SQ_PERFCOUNTER8_LO"
8008  },
8009  {
8010   "chips": ["gfx81"],
8011   "map": {"at": 214852, "to": "mm"},
8012   "name": "SQ_PERFCOUNTER8_HI"
8013  },
8014  {
8015   "chips": ["gfx81"],
8016   "map": {"at": 214856, "to": "mm"},
8017   "name": "SQ_PERFCOUNTER9_LO"
8018  },
8019  {
8020   "chips": ["gfx81"],
8021   "map": {"at": 214860, "to": "mm"},
8022   "name": "SQ_PERFCOUNTER9_HI"
8023  },
8024  {
8025   "chips": ["gfx81"],
8026   "map": {"at": 214864, "to": "mm"},
8027   "name": "SQ_PERFCOUNTER10_LO"
8028  },
8029  {
8030   "chips": ["gfx81"],
8031   "map": {"at": 214868, "to": "mm"},
8032   "name": "SQ_PERFCOUNTER10_HI"
8033  },
8034  {
8035   "chips": ["gfx81"],
8036   "map": {"at": 214872, "to": "mm"},
8037   "name": "SQ_PERFCOUNTER11_LO"
8038  },
8039  {
8040   "chips": ["gfx81"],
8041   "map": {"at": 214876, "to": "mm"},
8042   "name": "SQ_PERFCOUNTER11_HI"
8043  },
8044  {
8045   "chips": ["gfx81"],
8046   "map": {"at": 214880, "to": "mm"},
8047   "name": "SQ_PERFCOUNTER12_LO"
8048  },
8049  {
8050   "chips": ["gfx81"],
8051   "map": {"at": 214884, "to": "mm"},
8052   "name": "SQ_PERFCOUNTER12_HI"
8053  },
8054  {
8055   "chips": ["gfx81"],
8056   "map": {"at": 214888, "to": "mm"},
8057   "name": "SQ_PERFCOUNTER13_LO"
8058  },
8059  {
8060   "chips": ["gfx81"],
8061   "map": {"at": 214892, "to": "mm"},
8062   "name": "SQ_PERFCOUNTER13_HI"
8063  },
8064  {
8065   "chips": ["gfx81"],
8066   "map": {"at": 214896, "to": "mm"},
8067   "name": "SQ_PERFCOUNTER14_LO"
8068  },
8069  {
8070   "chips": ["gfx81"],
8071   "map": {"at": 214900, "to": "mm"},
8072   "name": "SQ_PERFCOUNTER14_HI"
8073  },
8074  {
8075   "chips": ["gfx81"],
8076   "map": {"at": 214904, "to": "mm"},
8077   "name": "SQ_PERFCOUNTER15_LO"
8078  },
8079  {
8080   "chips": ["gfx81"],
8081   "map": {"at": 214908, "to": "mm"},
8082   "name": "SQ_PERFCOUNTER15_HI"
8083  },
8084  {
8085   "chips": ["gfx81"],
8086   "map": {"at": 215296, "to": "mm"},
8087   "name": "SX_PERFCOUNTER0_LO"
8088  },
8089  {
8090   "chips": ["gfx81"],
8091   "map": {"at": 215300, "to": "mm"},
8092   "name": "SX_PERFCOUNTER0_HI"
8093  },
8094  {
8095   "chips": ["gfx81"],
8096   "map": {"at": 215304, "to": "mm"},
8097   "name": "SX_PERFCOUNTER1_LO"
8098  },
8099  {
8100   "chips": ["gfx81"],
8101   "map": {"at": 215308, "to": "mm"},
8102   "name": "SX_PERFCOUNTER1_HI"
8103  },
8104  {
8105   "chips": ["gfx81"],
8106   "map": {"at": 215312, "to": "mm"},
8107   "name": "SX_PERFCOUNTER2_LO"
8108  },
8109  {
8110   "chips": ["gfx81"],
8111   "map": {"at": 215316, "to": "mm"},
8112   "name": "SX_PERFCOUNTER2_HI"
8113  },
8114  {
8115   "chips": ["gfx81"],
8116   "map": {"at": 215320, "to": "mm"},
8117   "name": "SX_PERFCOUNTER3_LO"
8118  },
8119  {
8120   "chips": ["gfx81"],
8121   "map": {"at": 215324, "to": "mm"},
8122   "name": "SX_PERFCOUNTER3_HI"
8123  },
8124  {
8125   "chips": ["gfx81"],
8126   "map": {"at": 215552, "to": "mm"},
8127   "name": "GDS_PERFCOUNTER0_LO"
8128  },
8129  {
8130   "chips": ["gfx81"],
8131   "map": {"at": 215556, "to": "mm"},
8132   "name": "GDS_PERFCOUNTER0_HI"
8133  },
8134  {
8135   "chips": ["gfx81"],
8136   "map": {"at": 215560, "to": "mm"},
8137   "name": "GDS_PERFCOUNTER1_LO"
8138  },
8139  {
8140   "chips": ["gfx81"],
8141   "map": {"at": 215564, "to": "mm"},
8142   "name": "GDS_PERFCOUNTER1_HI"
8143  },
8144  {
8145   "chips": ["gfx81"],
8146   "map": {"at": 215568, "to": "mm"},
8147   "name": "GDS_PERFCOUNTER2_LO"
8148  },
8149  {
8150   "chips": ["gfx81"],
8151   "map": {"at": 215572, "to": "mm"},
8152   "name": "GDS_PERFCOUNTER2_HI"
8153  },
8154  {
8155   "chips": ["gfx81"],
8156   "map": {"at": 215576, "to": "mm"},
8157   "name": "GDS_PERFCOUNTER3_LO"
8158  },
8159  {
8160   "chips": ["gfx81"],
8161   "map": {"at": 215580, "to": "mm"},
8162   "name": "GDS_PERFCOUNTER3_HI"
8163  },
8164  {
8165   "chips": ["gfx81"],
8166   "map": {"at": 215808, "to": "mm"},
8167   "name": "TA_PERFCOUNTER0_LO"
8168  },
8169  {
8170   "chips": ["gfx81"],
8171   "map": {"at": 215812, "to": "mm"},
8172   "name": "TA_PERFCOUNTER0_HI"
8173  },
8174  {
8175   "chips": ["gfx81"],
8176   "map": {"at": 215816, "to": "mm"},
8177   "name": "TA_PERFCOUNTER1_LO"
8178  },
8179  {
8180   "chips": ["gfx81"],
8181   "map": {"at": 215820, "to": "mm"},
8182   "name": "TA_PERFCOUNTER1_HI"
8183  },
8184  {
8185   "chips": ["gfx81"],
8186   "map": {"at": 216064, "to": "mm"},
8187   "name": "TD_PERFCOUNTER0_LO"
8188  },
8189  {
8190   "chips": ["gfx81"],
8191   "map": {"at": 216068, "to": "mm"},
8192   "name": "TD_PERFCOUNTER0_HI"
8193  },
8194  {
8195   "chips": ["gfx81"],
8196   "map": {"at": 216072, "to": "mm"},
8197   "name": "TD_PERFCOUNTER1_LO"
8198  },
8199  {
8200   "chips": ["gfx81"],
8201   "map": {"at": 216076, "to": "mm"},
8202   "name": "TD_PERFCOUNTER1_HI"
8203  },
8204  {
8205   "chips": ["gfx81"],
8206   "map": {"at": 216320, "to": "mm"},
8207   "name": "TCP_PERFCOUNTER0_LO"
8208  },
8209  {
8210   "chips": ["gfx81"],
8211   "map": {"at": 216324, "to": "mm"},
8212   "name": "TCP_PERFCOUNTER0_HI"
8213  },
8214  {
8215   "chips": ["gfx81"],
8216   "map": {"at": 216328, "to": "mm"},
8217   "name": "TCP_PERFCOUNTER1_LO"
8218  },
8219  {
8220   "chips": ["gfx81"],
8221   "map": {"at": 216332, "to": "mm"},
8222   "name": "TCP_PERFCOUNTER1_HI"
8223  },
8224  {
8225   "chips": ["gfx81"],
8226   "map": {"at": 216336, "to": "mm"},
8227   "name": "TCP_PERFCOUNTER2_LO"
8228  },
8229  {
8230   "chips": ["gfx81"],
8231   "map": {"at": 216340, "to": "mm"},
8232   "name": "TCP_PERFCOUNTER2_HI"
8233  },
8234  {
8235   "chips": ["gfx81"],
8236   "map": {"at": 216344, "to": "mm"},
8237   "name": "TCP_PERFCOUNTER3_LO"
8238  },
8239  {
8240   "chips": ["gfx81"],
8241   "map": {"at": 216348, "to": "mm"},
8242   "name": "TCP_PERFCOUNTER3_HI"
8243  },
8244  {
8245   "chips": ["gfx81"],
8246   "map": {"at": 216576, "to": "mm"},
8247   "name": "TCC_PERFCOUNTER0_LO"
8248  },
8249  {
8250   "chips": ["gfx81"],
8251   "map": {"at": 216580, "to": "mm"},
8252   "name": "TCC_PERFCOUNTER0_HI"
8253  },
8254  {
8255   "chips": ["gfx81"],
8256   "map": {"at": 216584, "to": "mm"},
8257   "name": "TCC_PERFCOUNTER1_LO"
8258  },
8259  {
8260   "chips": ["gfx81"],
8261   "map": {"at": 216588, "to": "mm"},
8262   "name": "TCC_PERFCOUNTER1_HI"
8263  },
8264  {
8265   "chips": ["gfx81"],
8266   "map": {"at": 216592, "to": "mm"},
8267   "name": "TCC_PERFCOUNTER2_LO"
8268  },
8269  {
8270   "chips": ["gfx81"],
8271   "map": {"at": 216596, "to": "mm"},
8272   "name": "TCC_PERFCOUNTER2_HI"
8273  },
8274  {
8275   "chips": ["gfx81"],
8276   "map": {"at": 216600, "to": "mm"},
8277   "name": "TCC_PERFCOUNTER3_LO"
8278  },
8279  {
8280   "chips": ["gfx81"],
8281   "map": {"at": 216604, "to": "mm"},
8282   "name": "TCC_PERFCOUNTER3_HI"
8283  },
8284  {
8285   "chips": ["gfx81"],
8286   "map": {"at": 216640, "to": "mm"},
8287   "name": "TCA_PERFCOUNTER0_LO"
8288  },
8289  {
8290   "chips": ["gfx81"],
8291   "map": {"at": 216644, "to": "mm"},
8292   "name": "TCA_PERFCOUNTER0_HI"
8293  },
8294  {
8295   "chips": ["gfx81"],
8296   "map": {"at": 216648, "to": "mm"},
8297   "name": "TCA_PERFCOUNTER1_LO"
8298  },
8299  {
8300   "chips": ["gfx81"],
8301   "map": {"at": 216652, "to": "mm"},
8302   "name": "TCA_PERFCOUNTER1_HI"
8303  },
8304  {
8305   "chips": ["gfx81"],
8306   "map": {"at": 216656, "to": "mm"},
8307   "name": "TCA_PERFCOUNTER2_LO"
8308  },
8309  {
8310   "chips": ["gfx81"],
8311   "map": {"at": 216660, "to": "mm"},
8312   "name": "TCA_PERFCOUNTER2_HI"
8313  },
8314  {
8315   "chips": ["gfx81"],
8316   "map": {"at": 216664, "to": "mm"},
8317   "name": "TCA_PERFCOUNTER3_LO"
8318  },
8319  {
8320   "chips": ["gfx81"],
8321   "map": {"at": 216668, "to": "mm"},
8322   "name": "TCA_PERFCOUNTER3_HI"
8323  },
8324  {
8325   "chips": ["gfx81"],
8326   "map": {"at": 217112, "to": "mm"},
8327   "name": "CB_PERFCOUNTER0_LO"
8328  },
8329  {
8330   "chips": ["gfx81"],
8331   "map": {"at": 217116, "to": "mm"},
8332   "name": "CB_PERFCOUNTER0_HI"
8333  },
8334  {
8335   "chips": ["gfx81"],
8336   "map": {"at": 217120, "to": "mm"},
8337   "name": "CB_PERFCOUNTER1_LO"
8338  },
8339  {
8340   "chips": ["gfx81"],
8341   "map": {"at": 217124, "to": "mm"},
8342   "name": "CB_PERFCOUNTER1_HI"
8343  },
8344  {
8345   "chips": ["gfx81"],
8346   "map": {"at": 217128, "to": "mm"},
8347   "name": "CB_PERFCOUNTER2_LO"
8348  },
8349  {
8350   "chips": ["gfx81"],
8351   "map": {"at": 217132, "to": "mm"},
8352   "name": "CB_PERFCOUNTER2_HI"
8353  },
8354  {
8355   "chips": ["gfx81"],
8356   "map": {"at": 217136, "to": "mm"},
8357   "name": "CB_PERFCOUNTER3_LO"
8358  },
8359  {
8360   "chips": ["gfx81"],
8361   "map": {"at": 217140, "to": "mm"},
8362   "name": "CB_PERFCOUNTER3_HI"
8363  },
8364  {
8365   "chips": ["gfx81"],
8366   "map": {"at": 217344, "to": "mm"},
8367   "name": "DB_PERFCOUNTER0_LO"
8368  },
8369  {
8370   "chips": ["gfx81"],
8371   "map": {"at": 217348, "to": "mm"},
8372   "name": "DB_PERFCOUNTER0_HI"
8373  },
8374  {
8375   "chips": ["gfx81"],
8376   "map": {"at": 217352, "to": "mm"},
8377   "name": "DB_PERFCOUNTER1_LO"
8378  },
8379  {
8380   "chips": ["gfx81"],
8381   "map": {"at": 217356, "to": "mm"},
8382   "name": "DB_PERFCOUNTER1_HI"
8383  },
8384  {
8385   "chips": ["gfx81"],
8386   "map": {"at": 217360, "to": "mm"},
8387   "name": "DB_PERFCOUNTER2_LO"
8388  },
8389  {
8390   "chips": ["gfx81"],
8391   "map": {"at": 217364, "to": "mm"},
8392   "name": "DB_PERFCOUNTER2_HI"
8393  },
8394  {
8395   "chips": ["gfx81"],
8396   "map": {"at": 217368, "to": "mm"},
8397   "name": "DB_PERFCOUNTER3_LO"
8398  },
8399  {
8400   "chips": ["gfx81"],
8401   "map": {"at": 217372, "to": "mm"},
8402   "name": "DB_PERFCOUNTER3_HI"
8403  },
8404  {
8405   "chips": ["gfx81"],
8406   "map": {"at": 217600, "to": "mm"},
8407   "name": "RLC_PERFCOUNTER0_LO"
8408  },
8409  {
8410   "chips": ["gfx81"],
8411   "map": {"at": 217604, "to": "mm"},
8412   "name": "RLC_PERFCOUNTER0_HI"
8413  },
8414  {
8415   "chips": ["gfx81"],
8416   "map": {"at": 217608, "to": "mm"},
8417   "name": "RLC_PERFCOUNTER1_LO"
8418  },
8419  {
8420   "chips": ["gfx81"],
8421   "map": {"at": 217612, "to": "mm"},
8422   "name": "RLC_PERFCOUNTER1_HI"
8423  },
8424  {
8425   "chips": ["gfx81"],
8426   "map": {"at": 221184, "to": "mm"},
8427   "name": "CPG_PERFCOUNTER1_SELECT",
8428   "type_ref": "CPG_PERFCOUNTER1_SELECT"
8429  },
8430  {
8431   "chips": ["gfx81"],
8432   "map": {"at": 221188, "to": "mm"},
8433   "name": "CPG_PERFCOUNTER0_SELECT1",
8434   "type_ref": "CPG_PERFCOUNTER0_SELECT1"
8435  },
8436  {
8437   "chips": ["gfx81"],
8438   "map": {"at": 221192, "to": "mm"},
8439   "name": "CPG_PERFCOUNTER0_SELECT",
8440   "type_ref": "CPG_PERFCOUNTER0_SELECT"
8441  },
8442  {
8443   "chips": ["gfx81"],
8444   "map": {"at": 221196, "to": "mm"},
8445   "name": "CPC_PERFCOUNTER1_SELECT",
8446   "type_ref": "CPG_PERFCOUNTER1_SELECT"
8447  },
8448  {
8449   "chips": ["gfx81"],
8450   "map": {"at": 221200, "to": "mm"},
8451   "name": "CPC_PERFCOUNTER0_SELECT1",
8452   "type_ref": "CPG_PERFCOUNTER0_SELECT1"
8453  },
8454  {
8455   "chips": ["gfx81"],
8456   "map": {"at": 221204, "to": "mm"},
8457   "name": "CPF_PERFCOUNTER1_SELECT",
8458   "type_ref": "CPG_PERFCOUNTER1_SELECT"
8459  },
8460  {
8461   "chips": ["gfx81"],
8462   "map": {"at": 221208, "to": "mm"},
8463   "name": "CPF_PERFCOUNTER0_SELECT1",
8464   "type_ref": "CPG_PERFCOUNTER0_SELECT1"
8465  },
8466  {
8467   "chips": ["gfx81"],
8468   "map": {"at": 221212, "to": "mm"},
8469   "name": "CPF_PERFCOUNTER0_SELECT",
8470   "type_ref": "CPG_PERFCOUNTER0_SELECT"
8471  },
8472  {
8473   "chips": ["gfx81"],
8474   "map": {"at": 221216, "to": "mm"},
8475   "name": "CP_PERFMON_CNTL",
8476   "type_ref": "CP_PERFMON_CNTL"
8477  },
8478  {
8479   "chips": ["gfx81"],
8480   "map": {"at": 221220, "to": "mm"},
8481   "name": "CPC_PERFCOUNTER0_SELECT",
8482   "type_ref": "CPG_PERFCOUNTER0_SELECT"
8483  },
8484  {
8485   "chips": ["gfx81"],
8486   "map": {"at": 221248, "to": "mm"},
8487   "name": "CP_DRAW_OBJECT"
8488  },
8489  {
8490   "chips": ["gfx81"],
8491   "map": {"at": 221252, "to": "mm"},
8492   "name": "CP_DRAW_OBJECT_COUNTER",
8493   "type_ref": "CP_DRAW_OBJECT_COUNTER"
8494  },
8495  {
8496   "chips": ["gfx81"],
8497   "map": {"at": 221256, "to": "mm"},
8498   "name": "CP_DRAW_WINDOW_MASK_HI"
8499  },
8500  {
8501   "chips": ["gfx81"],
8502   "map": {"at": 221260, "to": "mm"},
8503   "name": "CP_DRAW_WINDOW_HI"
8504  },
8505  {
8506   "chips": ["gfx81"],
8507   "map": {"at": 221264, "to": "mm"},
8508   "name": "CP_DRAW_WINDOW_LO",
8509   "type_ref": "CP_DRAW_WINDOW_LO"
8510  },
8511  {
8512   "chips": ["gfx81"],
8513   "map": {"at": 221268, "to": "mm"},
8514   "name": "CP_DRAW_WINDOW_CNTL",
8515   "type_ref": "CP_DRAW_WINDOW_CNTL"
8516  },
8517  {
8518   "chips": ["gfx81"],
8519   "map": {"at": 221440, "to": "mm"},
8520   "name": "GRBM_PERFCOUNTER0_SELECT",
8521   "type_ref": "GRBM_PERFCOUNTER0_SELECT"
8522  },
8523  {
8524   "chips": ["gfx81"],
8525   "map": {"at": 221444, "to": "mm"},
8526   "name": "GRBM_PERFCOUNTER1_SELECT",
8527   "type_ref": "GRBM_PERFCOUNTER0_SELECT"
8528  },
8529  {
8530   "chips": ["gfx81"],
8531   "map": {"at": 221448, "to": "mm"},
8532   "name": "GRBM_SE0_PERFCOUNTER_SELECT",
8533   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
8534  },
8535  {
8536   "chips": ["gfx81"],
8537   "map": {"at": 221452, "to": "mm"},
8538   "name": "GRBM_SE1_PERFCOUNTER_SELECT",
8539   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
8540  },
8541  {
8542   "chips": ["gfx81"],
8543   "map": {"at": 221456, "to": "mm"},
8544   "name": "GRBM_SE2_PERFCOUNTER_SELECT",
8545   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
8546  },
8547  {
8548   "chips": ["gfx81"],
8549   "map": {"at": 221460, "to": "mm"},
8550   "name": "GRBM_SE3_PERFCOUNTER_SELECT",
8551   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
8552  },
8553  {
8554   "chips": ["gfx81"],
8555   "map": {"at": 221696, "to": "mm"},
8556   "name": "WD_PERFCOUNTER0_SELECT",
8557   "type_ref": "VGT_PERFCOUNTER2_SELECT"
8558  },
8559  {
8560   "chips": ["gfx81"],
8561   "map": {"at": 221700, "to": "mm"},
8562   "name": "WD_PERFCOUNTER1_SELECT",
8563   "type_ref": "VGT_PERFCOUNTER2_SELECT"
8564  },
8565  {
8566   "chips": ["gfx81"],
8567   "map": {"at": 221704, "to": "mm"},
8568   "name": "WD_PERFCOUNTER2_SELECT",
8569   "type_ref": "VGT_PERFCOUNTER2_SELECT"
8570  },
8571  {
8572   "chips": ["gfx81"],
8573   "map": {"at": 221708, "to": "mm"},
8574   "name": "WD_PERFCOUNTER3_SELECT",
8575   "type_ref": "VGT_PERFCOUNTER2_SELECT"
8576  },
8577  {
8578   "chips": ["gfx81"],
8579   "map": {"at": 221712, "to": "mm"},
8580   "name": "IA_PERFCOUNTER0_SELECT",
8581   "type_ref": "DB_PERFCOUNTER0_SELECT"
8582  },
8583  {
8584   "chips": ["gfx81"],
8585   "map": {"at": 221716, "to": "mm"},
8586   "name": "IA_PERFCOUNTER1_SELECT",
8587   "type_ref": "VGT_PERFCOUNTER2_SELECT"
8588  },
8589  {
8590   "chips": ["gfx81"],
8591   "map": {"at": 221720, "to": "mm"},
8592   "name": "IA_PERFCOUNTER2_SELECT",
8593   "type_ref": "VGT_PERFCOUNTER2_SELECT"
8594  },
8595  {
8596   "chips": ["gfx81"],
8597   "map": {"at": 221724, "to": "mm"},
8598   "name": "IA_PERFCOUNTER3_SELECT",
8599   "type_ref": "VGT_PERFCOUNTER2_SELECT"
8600  },
8601  {
8602   "chips": ["gfx81"],
8603   "map": {"at": 221728, "to": "mm"},
8604   "name": "IA_PERFCOUNTER0_SELECT1",
8605   "type_ref": "DB_PERFCOUNTER0_SELECT1"
8606  },
8607  {
8608   "chips": ["gfx81"],
8609   "map": {"at": 221744, "to": "mm"},
8610   "name": "VGT_PERFCOUNTER0_SELECT",
8611   "type_ref": "DB_PERFCOUNTER0_SELECT"
8612  },
8613  {
8614   "chips": ["gfx81"],
8615   "map": {"at": 221748, "to": "mm"},
8616   "name": "VGT_PERFCOUNTER1_SELECT",
8617   "type_ref": "DB_PERFCOUNTER0_SELECT"
8618  },
8619  {
8620   "chips": ["gfx81"],
8621   "map": {"at": 221752, "to": "mm"},
8622   "name": "VGT_PERFCOUNTER2_SELECT",
8623   "type_ref": "VGT_PERFCOUNTER2_SELECT"
8624  },
8625  {
8626   "chips": ["gfx81"],
8627   "map": {"at": 221756, "to": "mm"},
8628   "name": "VGT_PERFCOUNTER3_SELECT",
8629   "type_ref": "VGT_PERFCOUNTER2_SELECT"
8630  },
8631  {
8632   "chips": ["gfx81"],
8633   "map": {"at": 221760, "to": "mm"},
8634   "name": "VGT_PERFCOUNTER0_SELECT1",
8635   "type_ref": "DB_PERFCOUNTER0_SELECT1"
8636  },
8637  {
8638   "chips": ["gfx81"],
8639   "map": {"at": 221764, "to": "mm"},
8640   "name": "VGT_PERFCOUNTER1_SELECT1",
8641   "type_ref": "DB_PERFCOUNTER0_SELECT1"
8642  },
8643  {
8644   "chips": ["gfx81"],
8645   "map": {"at": 221776, "to": "mm"},
8646   "name": "VGT_PERFCOUNTER_SEID_MASK",
8647   "type_ref": "VGT_PERFCOUNTER_SEID_MASK"
8648  },
8649  {
8650   "chips": ["gfx81"],
8651   "map": {"at": 222208, "to": "mm"},
8652   "name": "PA_SU_PERFCOUNTER0_SELECT",
8653   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
8654  },
8655  {
8656   "chips": ["gfx81"],
8657   "map": {"at": 222212, "to": "mm"},
8658   "name": "PA_SU_PERFCOUNTER0_SELECT1",
8659   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
8660  },
8661  {
8662   "chips": ["gfx81"],
8663   "map": {"at": 222216, "to": "mm"},
8664   "name": "PA_SU_PERFCOUNTER1_SELECT",
8665   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
8666  },
8667  {
8668   "chips": ["gfx81"],
8669   "map": {"at": 222220, "to": "mm"},
8670   "name": "PA_SU_PERFCOUNTER1_SELECT1",
8671   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
8672  },
8673  {
8674   "chips": ["gfx81"],
8675   "map": {"at": 222224, "to": "mm"},
8676   "name": "PA_SU_PERFCOUNTER2_SELECT",
8677   "type_ref": "PA_SU_PERFCOUNTER2_SELECT"
8678  },
8679  {
8680   "chips": ["gfx81"],
8681   "map": {"at": 222228, "to": "mm"},
8682   "name": "PA_SU_PERFCOUNTER3_SELECT",
8683   "type_ref": "PA_SU_PERFCOUNTER2_SELECT"
8684  },
8685  {
8686   "chips": ["gfx81"],
8687   "map": {"at": 222464, "to": "mm"},
8688   "name": "PA_SC_PERFCOUNTER0_SELECT",
8689   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
8690  },
8691  {
8692   "chips": ["gfx81"],
8693   "map": {"at": 222468, "to": "mm"},
8694   "name": "PA_SC_PERFCOUNTER0_SELECT1",
8695   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
8696  },
8697  {
8698   "chips": ["gfx81"],
8699   "map": {"at": 222472, "to": "mm"},
8700   "name": "PA_SC_PERFCOUNTER1_SELECT",
8701   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
8702  },
8703  {
8704   "chips": ["gfx81"],
8705   "map": {"at": 222476, "to": "mm"},
8706   "name": "PA_SC_PERFCOUNTER2_SELECT",
8707   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
8708  },
8709  {
8710   "chips": ["gfx81"],
8711   "map": {"at": 222480, "to": "mm"},
8712   "name": "PA_SC_PERFCOUNTER3_SELECT",
8713   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
8714  },
8715  {
8716   "chips": ["gfx81"],
8717   "map": {"at": 222484, "to": "mm"},
8718   "name": "PA_SC_PERFCOUNTER4_SELECT",
8719   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
8720  },
8721  {
8722   "chips": ["gfx81"],
8723   "map": {"at": 222488, "to": "mm"},
8724   "name": "PA_SC_PERFCOUNTER5_SELECT",
8725   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
8726  },
8727  {
8728   "chips": ["gfx81"],
8729   "map": {"at": 222492, "to": "mm"},
8730   "name": "PA_SC_PERFCOUNTER6_SELECT",
8731   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
8732  },
8733  {
8734   "chips": ["gfx81"],
8735   "map": {"at": 222496, "to": "mm"},
8736   "name": "PA_SC_PERFCOUNTER7_SELECT",
8737   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
8738  },
8739  {
8740   "chips": ["gfx81"],
8741   "map": {"at": 222720, "to": "mm"},
8742   "name": "SPI_PERFCOUNTER0_SELECT",
8743   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
8744  },
8745  {
8746   "chips": ["gfx81"],
8747   "map": {"at": 222724, "to": "mm"},
8748   "name": "SPI_PERFCOUNTER1_SELECT",
8749   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
8750  },
8751  {
8752   "chips": ["gfx81"],
8753   "map": {"at": 222728, "to": "mm"},
8754   "name": "SPI_PERFCOUNTER2_SELECT",
8755   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
8756  },
8757  {
8758   "chips": ["gfx81"],
8759   "map": {"at": 222732, "to": "mm"},
8760   "name": "SPI_PERFCOUNTER3_SELECT",
8761   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
8762  },
8763  {
8764   "chips": ["gfx81"],
8765   "map": {"at": 222736, "to": "mm"},
8766   "name": "SPI_PERFCOUNTER0_SELECT1",
8767   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
8768  },
8769  {
8770   "chips": ["gfx81"],
8771   "map": {"at": 222740, "to": "mm"},
8772   "name": "SPI_PERFCOUNTER1_SELECT1",
8773   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
8774  },
8775  {
8776   "chips": ["gfx81"],
8777   "map": {"at": 222744, "to": "mm"},
8778   "name": "SPI_PERFCOUNTER2_SELECT1",
8779   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
8780  },
8781  {
8782   "chips": ["gfx81"],
8783   "map": {"at": 222748, "to": "mm"},
8784   "name": "SPI_PERFCOUNTER3_SELECT1",
8785   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
8786  },
8787  {
8788   "chips": ["gfx81"],
8789   "map": {"at": 222752, "to": "mm"},
8790   "name": "SPI_PERFCOUNTER4_SELECT",
8791   "type_ref": "SPI_PERFCOUNTER4_SELECT"
8792  },
8793  {
8794   "chips": ["gfx81"],
8795   "map": {"at": 222756, "to": "mm"},
8796   "name": "SPI_PERFCOUNTER5_SELECT",
8797   "type_ref": "SPI_PERFCOUNTER4_SELECT"
8798  },
8799  {
8800   "chips": ["gfx81"],
8801   "map": {"at": 222760, "to": "mm"},
8802   "name": "SPI_PERFCOUNTER_BINS",
8803   "type_ref": "SPI_PERFCOUNTER_BINS"
8804  },
8805  {
8806   "chips": ["gfx81"],
8807   "map": {"at": 222976, "to": "mm"},
8808   "name": "SQ_PERFCOUNTER0_SELECT",
8809   "type_ref": "SQ_PERFCOUNTER0_SELECT"
8810  },
8811  {
8812   "chips": ["gfx81"],
8813   "map": {"at": 222980, "to": "mm"},
8814   "name": "SQ_PERFCOUNTER1_SELECT",
8815   "type_ref": "SQ_PERFCOUNTER0_SELECT"
8816  },
8817  {
8818   "chips": ["gfx81"],
8819   "map": {"at": 222984, "to": "mm"},
8820   "name": "SQ_PERFCOUNTER2_SELECT",
8821   "type_ref": "SQ_PERFCOUNTER0_SELECT"
8822  },
8823  {
8824   "chips": ["gfx81"],
8825   "map": {"at": 222988, "to": "mm"},
8826   "name": "SQ_PERFCOUNTER3_SELECT",
8827   "type_ref": "SQ_PERFCOUNTER0_SELECT"
8828  },
8829  {
8830   "chips": ["gfx81"],
8831   "map": {"at": 222992, "to": "mm"},
8832   "name": "SQ_PERFCOUNTER4_SELECT",
8833   "type_ref": "SQ_PERFCOUNTER0_SELECT"
8834  },
8835  {
8836   "chips": ["gfx81"],
8837   "map": {"at": 222996, "to": "mm"},
8838   "name": "SQ_PERFCOUNTER5_SELECT",
8839   "type_ref": "SQ_PERFCOUNTER0_SELECT"
8840  },
8841  {
8842   "chips": ["gfx81"],
8843   "map": {"at": 223000, "to": "mm"},
8844   "name": "SQ_PERFCOUNTER6_SELECT",
8845   "type_ref": "SQ_PERFCOUNTER0_SELECT"
8846  },
8847  {
8848   "chips": ["gfx81"],
8849   "map": {"at": 223004, "to": "mm"},
8850   "name": "SQ_PERFCOUNTER7_SELECT",
8851   "type_ref": "SQ_PERFCOUNTER0_SELECT"
8852  },
8853  {
8854   "chips": ["gfx81"],
8855   "map": {"at": 223008, "to": "mm"},
8856   "name": "SQ_PERFCOUNTER8_SELECT",
8857   "type_ref": "SQ_PERFCOUNTER0_SELECT"
8858  },
8859  {
8860   "chips": ["gfx81"],
8861   "map": {"at": 223012, "to": "mm"},
8862   "name": "SQ_PERFCOUNTER9_SELECT",
8863   "type_ref": "SQ_PERFCOUNTER0_SELECT"
8864  },
8865  {
8866   "chips": ["gfx81"],
8867   "map": {"at": 223016, "to": "mm"},
8868   "name": "SQ_PERFCOUNTER10_SELECT",
8869   "type_ref": "SQ_PERFCOUNTER0_SELECT"
8870  },
8871  {
8872   "chips": ["gfx81"],
8873   "map": {"at": 223020, "to": "mm"},
8874   "name": "SQ_PERFCOUNTER11_SELECT",
8875   "type_ref": "SQ_PERFCOUNTER0_SELECT"
8876  },
8877  {
8878   "chips": ["gfx81"],
8879   "map": {"at": 223024, "to": "mm"},
8880   "name": "SQ_PERFCOUNTER12_SELECT",
8881   "type_ref": "SQ_PERFCOUNTER0_SELECT"
8882  },
8883  {
8884   "chips": ["gfx81"],
8885   "map": {"at": 223028, "to": "mm"},
8886   "name": "SQ_PERFCOUNTER13_SELECT",
8887   "type_ref": "SQ_PERFCOUNTER0_SELECT"
8888  },
8889  {
8890   "chips": ["gfx81"],
8891   "map": {"at": 223032, "to": "mm"},
8892   "name": "SQ_PERFCOUNTER14_SELECT",
8893   "type_ref": "SQ_PERFCOUNTER0_SELECT"
8894  },
8895  {
8896   "chips": ["gfx81"],
8897   "map": {"at": 223036, "to": "mm"},
8898   "name": "SQ_PERFCOUNTER15_SELECT",
8899   "type_ref": "SQ_PERFCOUNTER0_SELECT"
8900  },
8901  {
8902   "chips": ["gfx81"],
8903   "map": {"at": 223104, "to": "mm"},
8904   "name": "SQ_PERFCOUNTER_CTRL",
8905   "type_ref": "SQ_PERFCOUNTER_CTRL"
8906  },
8907  {
8908   "chips": ["gfx81"],
8909   "map": {"at": 223108, "to": "mm"},
8910   "name": "SQ_PERFCOUNTER_MASK",
8911   "type_ref": "SQ_PERFCOUNTER_MASK"
8912  },
8913  {
8914   "chips": ["gfx81"],
8915   "map": {"at": 223112, "to": "mm"},
8916   "name": "SQ_PERFCOUNTER_CTRL2",
8917   "type_ref": "SQ_PERFCOUNTER_CTRL2"
8918  },
8919  {
8920   "chips": ["gfx81"],
8921   "map": {"at": 223488, "to": "mm"},
8922   "name": "SX_PERFCOUNTER0_SELECT",
8923   "type_ref": "SX_PERFCOUNTER0_SELECT"
8924  },
8925  {
8926   "chips": ["gfx81"],
8927   "map": {"at": 223492, "to": "mm"},
8928   "name": "SX_PERFCOUNTER1_SELECT",
8929   "type_ref": "SX_PERFCOUNTER0_SELECT"
8930  },
8931  {
8932   "chips": ["gfx81"],
8933   "map": {"at": 223496, "to": "mm"},
8934   "name": "SX_PERFCOUNTER2_SELECT",
8935   "type_ref": "SX_PERFCOUNTER0_SELECT"
8936  },
8937  {
8938   "chips": ["gfx81"],
8939   "map": {"at": 223500, "to": "mm"},
8940   "name": "SX_PERFCOUNTER3_SELECT",
8941   "type_ref": "SX_PERFCOUNTER0_SELECT"
8942  },
8943  {
8944   "chips": ["gfx81"],
8945   "map": {"at": 223504, "to": "mm"},
8946   "name": "SX_PERFCOUNTER0_SELECT1",
8947   "type_ref": "SX_PERFCOUNTER0_SELECT1"
8948  },
8949  {
8950   "chips": ["gfx81"],
8951   "map": {"at": 223508, "to": "mm"},
8952   "name": "SX_PERFCOUNTER1_SELECT1",
8953   "type_ref": "SX_PERFCOUNTER0_SELECT1"
8954  },
8955  {
8956   "chips": ["gfx81"],
8957   "map": {"at": 223744, "to": "mm"},
8958   "name": "GDS_PERFCOUNTER0_SELECT",
8959   "type_ref": "SX_PERFCOUNTER0_SELECT"
8960  },
8961  {
8962   "chips": ["gfx81"],
8963   "map": {"at": 223748, "to": "mm"},
8964   "name": "GDS_PERFCOUNTER1_SELECT",
8965   "type_ref": "SX_PERFCOUNTER0_SELECT"
8966  },
8967  {
8968   "chips": ["gfx81"],
8969   "map": {"at": 223752, "to": "mm"},
8970   "name": "GDS_PERFCOUNTER2_SELECT",
8971   "type_ref": "SX_PERFCOUNTER0_SELECT"
8972  },
8973  {
8974   "chips": ["gfx81"],
8975   "map": {"at": 223756, "to": "mm"},
8976   "name": "GDS_PERFCOUNTER3_SELECT",
8977   "type_ref": "SX_PERFCOUNTER0_SELECT"
8978  },
8979  {
8980   "chips": ["gfx81"],
8981   "map": {"at": 223760, "to": "mm"},
8982   "name": "GDS_PERFCOUNTER0_SELECT1",
8983   "type_ref": "SX_PERFCOUNTER0_SELECT1"
8984  },
8985  {
8986   "chips": ["gfx81"],
8987   "map": {"at": 224000, "to": "mm"},
8988   "name": "TA_PERFCOUNTER0_SELECT",
8989   "type_ref": "TD_PERFCOUNTER0_SELECT"
8990  },
8991  {
8992   "chips": ["gfx81"],
8993   "map": {"at": 224004, "to": "mm"},
8994   "name": "TA_PERFCOUNTER0_SELECT1",
8995   "type_ref": "TD_PERFCOUNTER0_SELECT1"
8996  },
8997  {
8998   "chips": ["gfx81"],
8999   "map": {"at": 224008, "to": "mm"},
9000   "name": "TA_PERFCOUNTER1_SELECT",
9001   "type_ref": "TD_PERFCOUNTER0_SELECT"
9002  },
9003  {
9004   "chips": ["gfx81"],
9005   "map": {"at": 224256, "to": "mm"},
9006   "name": "TD_PERFCOUNTER0_SELECT",
9007   "type_ref": "TD_PERFCOUNTER0_SELECT"
9008  },
9009  {
9010   "chips": ["gfx81"],
9011   "map": {"at": 224260, "to": "mm"},
9012   "name": "TD_PERFCOUNTER0_SELECT1",
9013   "type_ref": "TD_PERFCOUNTER0_SELECT1"
9014  },
9015  {
9016   "chips": ["gfx81"],
9017   "map": {"at": 224264, "to": "mm"},
9018   "name": "TD_PERFCOUNTER1_SELECT",
9019   "type_ref": "TD_PERFCOUNTER0_SELECT"
9020  },
9021  {
9022   "chips": ["gfx81"],
9023   "map": {"at": 224512, "to": "mm"},
9024   "name": "TCP_PERFCOUNTER0_SELECT",
9025   "type_ref": "DB_PERFCOUNTER0_SELECT"
9026  },
9027  {
9028   "chips": ["gfx81"],
9029   "map": {"at": 224516, "to": "mm"},
9030   "name": "TCP_PERFCOUNTER0_SELECT1",
9031   "type_ref": "DB_PERFCOUNTER0_SELECT1"
9032  },
9033  {
9034   "chips": ["gfx81"],
9035   "map": {"at": 224520, "to": "mm"},
9036   "name": "TCP_PERFCOUNTER1_SELECT",
9037   "type_ref": "DB_PERFCOUNTER0_SELECT"
9038  },
9039  {
9040   "chips": ["gfx81"],
9041   "map": {"at": 224524, "to": "mm"},
9042   "name": "TCP_PERFCOUNTER1_SELECT1",
9043   "type_ref": "DB_PERFCOUNTER0_SELECT1"
9044  },
9045  {
9046   "chips": ["gfx81"],
9047   "map": {"at": 224528, "to": "mm"},
9048   "name": "TCP_PERFCOUNTER2_SELECT",
9049   "type_ref": "TCC_PERFCOUNTER2_SELECT"
9050  },
9051  {
9052   "chips": ["gfx81"],
9053   "map": {"at": 224532, "to": "mm"},
9054   "name": "TCP_PERFCOUNTER3_SELECT",
9055   "type_ref": "TCC_PERFCOUNTER2_SELECT"
9056  },
9057  {
9058   "chips": ["gfx81"],
9059   "map": {"at": 224768, "to": "mm"},
9060   "name": "TCC_PERFCOUNTER0_SELECT",
9061   "type_ref": "DB_PERFCOUNTER0_SELECT"
9062  },
9063  {
9064   "chips": ["gfx81"],
9065   "map": {"at": 224772, "to": "mm"},
9066   "name": "TCC_PERFCOUNTER0_SELECT1",
9067   "type_ref": "TCC_PERFCOUNTER0_SELECT1"
9068  },
9069  {
9070   "chips": ["gfx81"],
9071   "map": {"at": 224776, "to": "mm"},
9072   "name": "TCC_PERFCOUNTER1_SELECT",
9073   "type_ref": "DB_PERFCOUNTER0_SELECT"
9074  },
9075  {
9076   "chips": ["gfx81"],
9077   "map": {"at": 224780, "to": "mm"},
9078   "name": "TCC_PERFCOUNTER1_SELECT1",
9079   "type_ref": "TCC_PERFCOUNTER0_SELECT1"
9080  },
9081  {
9082   "chips": ["gfx81"],
9083   "map": {"at": 224784, "to": "mm"},
9084   "name": "TCC_PERFCOUNTER2_SELECT",
9085   "type_ref": "TCC_PERFCOUNTER2_SELECT"
9086  },
9087  {
9088   "chips": ["gfx81"],
9089   "map": {"at": 224788, "to": "mm"},
9090   "name": "TCC_PERFCOUNTER3_SELECT",
9091   "type_ref": "TCC_PERFCOUNTER2_SELECT"
9092  },
9093  {
9094   "chips": ["gfx81"],
9095   "map": {"at": 224832, "to": "mm"},
9096   "name": "TCA_PERFCOUNTER0_SELECT",
9097   "type_ref": "DB_PERFCOUNTER0_SELECT"
9098  },
9099  {
9100   "chips": ["gfx81"],
9101   "map": {"at": 224836, "to": "mm"},
9102   "name": "TCA_PERFCOUNTER0_SELECT1",
9103   "type_ref": "TCC_PERFCOUNTER0_SELECT1"
9104  },
9105  {
9106   "chips": ["gfx81"],
9107   "map": {"at": 224840, "to": "mm"},
9108   "name": "TCA_PERFCOUNTER1_SELECT",
9109   "type_ref": "DB_PERFCOUNTER0_SELECT"
9110  },
9111  {
9112   "chips": ["gfx81"],
9113   "map": {"at": 224844, "to": "mm"},
9114   "name": "TCA_PERFCOUNTER1_SELECT1",
9115   "type_ref": "TCC_PERFCOUNTER0_SELECT1"
9116  },
9117  {
9118   "chips": ["gfx81"],
9119   "map": {"at": 224848, "to": "mm"},
9120   "name": "TCA_PERFCOUNTER2_SELECT",
9121   "type_ref": "TCC_PERFCOUNTER2_SELECT"
9122  },
9123  {
9124   "chips": ["gfx81"],
9125   "map": {"at": 224852, "to": "mm"},
9126   "name": "TCA_PERFCOUNTER3_SELECT",
9127   "type_ref": "TCC_PERFCOUNTER2_SELECT"
9128  },
9129  {
9130   "chips": ["gfx81"],
9131   "map": {"at": 225280, "to": "mm"},
9132   "name": "CB_PERFCOUNTER_FILTER",
9133   "type_ref": "CB_PERFCOUNTER_FILTER"
9134  },
9135  {
9136   "chips": ["gfx81"],
9137   "map": {"at": 225284, "to": "mm"},
9138   "name": "CB_PERFCOUNTER0_SELECT",
9139   "type_ref": "CB_PERFCOUNTER0_SELECT"
9140  },
9141  {
9142   "chips": ["gfx81"],
9143   "map": {"at": 225288, "to": "mm"},
9144   "name": "CB_PERFCOUNTER0_SELECT1",
9145   "type_ref": "CB_PERFCOUNTER0_SELECT1"
9146  },
9147  {
9148   "chips": ["gfx81"],
9149   "map": {"at": 225292, "to": "mm"},
9150   "name": "CB_PERFCOUNTER1_SELECT",
9151   "type_ref": "CB_PERFCOUNTER1_SELECT"
9152  },
9153  {
9154   "chips": ["gfx81"],
9155   "map": {"at": 225296, "to": "mm"},
9156   "name": "CB_PERFCOUNTER2_SELECT",
9157   "type_ref": "CB_PERFCOUNTER1_SELECT"
9158  },
9159  {
9160   "chips": ["gfx81"],
9161   "map": {"at": 225300, "to": "mm"},
9162   "name": "CB_PERFCOUNTER3_SELECT",
9163   "type_ref": "CB_PERFCOUNTER1_SELECT"
9164  },
9165  {
9166   "chips": ["gfx81"],
9167   "map": {"at": 225536, "to": "mm"},
9168   "name": "DB_PERFCOUNTER0_SELECT",
9169   "type_ref": "DB_PERFCOUNTER0_SELECT"
9170  },
9171  {
9172   "chips": ["gfx81"],
9173   "map": {"at": 225540, "to": "mm"},
9174   "name": "DB_PERFCOUNTER0_SELECT1",
9175   "type_ref": "DB_PERFCOUNTER0_SELECT1"
9176  },
9177  {
9178   "chips": ["gfx81"],
9179   "map": {"at": 225544, "to": "mm"},
9180   "name": "DB_PERFCOUNTER1_SELECT",
9181   "type_ref": "DB_PERFCOUNTER0_SELECT"
9182  },
9183  {
9184   "chips": ["gfx81"],
9185   "map": {"at": 225548, "to": "mm"},
9186   "name": "DB_PERFCOUNTER1_SELECT1",
9187   "type_ref": "DB_PERFCOUNTER0_SELECT1"
9188  },
9189  {
9190   "chips": ["gfx81"],
9191   "map": {"at": 225552, "to": "mm"},
9192   "name": "DB_PERFCOUNTER2_SELECT",
9193   "type_ref": "DB_PERFCOUNTER0_SELECT"
9194  },
9195  {
9196   "chips": ["gfx81"],
9197   "map": {"at": 225560, "to": "mm"},
9198   "name": "DB_PERFCOUNTER3_SELECT",
9199   "type_ref": "DB_PERFCOUNTER0_SELECT"
9200  },
9201  {
9202   "chips": ["gfx81"],
9203   "map": {"at": 225792, "to": "mm"},
9204   "name": "RLC_SPM_PERFMON_CNTL",
9205   "type_ref": "RLC_SPM_PERFMON_CNTL"
9206  },
9207  {
9208   "chips": ["gfx81"],
9209   "map": {"at": 225796, "to": "mm"},
9210   "name": "RLC_SPM_PERFMON_RING_BASE_LO"
9211  },
9212  {
9213   "chips": ["gfx81"],
9214   "map": {"at": 225800, "to": "mm"},
9215   "name": "RLC_SPM_PERFMON_RING_BASE_HI",
9216   "type_ref": "RLC_SPM_PERFMON_RING_BASE_HI"
9217  },
9218  {
9219   "chips": ["gfx81"],
9220   "map": {"at": 225804, "to": "mm"},
9221   "name": "RLC_SPM_PERFMON_RING_SIZE"
9222  },
9223  {
9224   "chips": ["gfx81"],
9225   "map": {"at": 225808, "to": "mm"},
9226   "name": "RLC_SPM_PERFMON_SEGMENT_SIZE",
9227   "type_ref": "RLC_SPM_PERFMON_SEGMENT_SIZE"
9228  },
9229  {
9230   "chips": ["gfx81"],
9231   "map": {"at": 225812, "to": "mm"},
9232   "name": "RLC_SPM_SE_MUXSEL_ADDR"
9233  },
9234  {
9235   "chips": ["gfx81"],
9236   "map": {"at": 225816, "to": "mm"},
9237   "name": "RLC_SPM_SE_MUXSEL_DATA"
9238  },
9239  {
9240   "chips": ["gfx81"],
9241   "map": {"at": 225820, "to": "mm"},
9242   "name": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY",
9243   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
9244  },
9245  {
9246   "chips": ["gfx81"],
9247   "map": {"at": 225824, "to": "mm"},
9248   "name": "RLC_SPM_CPC_PERFMON_SAMPLE_DELAY",
9249   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
9250  },
9251  {
9252   "chips": ["gfx81"],
9253   "map": {"at": 225828, "to": "mm"},
9254   "name": "RLC_SPM_CPF_PERFMON_SAMPLE_DELAY",
9255   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
9256  },
9257  {
9258   "chips": ["gfx81"],
9259   "map": {"at": 225832, "to": "mm"},
9260   "name": "RLC_SPM_CB_PERFMON_SAMPLE_DELAY",
9261   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
9262  },
9263  {
9264   "chips": ["gfx81"],
9265   "map": {"at": 225836, "to": "mm"},
9266   "name": "RLC_SPM_DB_PERFMON_SAMPLE_DELAY",
9267   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
9268  },
9269  {
9270   "chips": ["gfx81"],
9271   "map": {"at": 225840, "to": "mm"},
9272   "name": "RLC_SPM_PA_PERFMON_SAMPLE_DELAY",
9273   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
9274  },
9275  {
9276   "chips": ["gfx81"],
9277   "map": {"at": 225844, "to": "mm"},
9278   "name": "RLC_SPM_GDS_PERFMON_SAMPLE_DELAY",
9279   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
9280  },
9281  {
9282   "chips": ["gfx81"],
9283   "map": {"at": 225848, "to": "mm"},
9284   "name": "RLC_SPM_IA_PERFMON_SAMPLE_DELAY",
9285   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
9286  },
9287  {
9288   "chips": ["gfx81"],
9289   "map": {"at": 225856, "to": "mm"},
9290   "name": "RLC_SPM_SC_PERFMON_SAMPLE_DELAY",
9291   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
9292  },
9293  {
9294   "chips": ["gfx81"],
9295   "map": {"at": 225860, "to": "mm"},
9296   "name": "RLC_SPM_TCC_PERFMON_SAMPLE_DELAY",
9297   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
9298  },
9299  {
9300   "chips": ["gfx81"],
9301   "map": {"at": 225864, "to": "mm"},
9302   "name": "RLC_SPM_TCA_PERFMON_SAMPLE_DELAY",
9303   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
9304  },
9305  {
9306   "chips": ["gfx81"],
9307   "map": {"at": 225868, "to": "mm"},
9308   "name": "RLC_SPM_TCP_PERFMON_SAMPLE_DELAY",
9309   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
9310  },
9311  {
9312   "chips": ["gfx81"],
9313   "map": {"at": 225872, "to": "mm"},
9314   "name": "RLC_SPM_TA_PERFMON_SAMPLE_DELAY",
9315   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
9316  },
9317  {
9318   "chips": ["gfx81"],
9319   "map": {"at": 225876, "to": "mm"},
9320   "name": "RLC_SPM_TD_PERFMON_SAMPLE_DELAY",
9321   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
9322  },
9323  {
9324   "chips": ["gfx81"],
9325   "map": {"at": 225880, "to": "mm"},
9326   "name": "RLC_SPM_VGT_PERFMON_SAMPLE_DELAY",
9327   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
9328  },
9329  {
9330   "chips": ["gfx81"],
9331   "map": {"at": 225884, "to": "mm"},
9332   "name": "RLC_SPM_SPI_PERFMON_SAMPLE_DELAY",
9333   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
9334  },
9335  {
9336   "chips": ["gfx81"],
9337   "map": {"at": 225888, "to": "mm"},
9338   "name": "RLC_SPM_SQG_PERFMON_SAMPLE_DELAY",
9339   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
9340  },
9341  {
9342   "chips": ["gfx81"],
9343   "map": {"at": 225896, "to": "mm"},
9344   "name": "RLC_SPM_SX_PERFMON_SAMPLE_DELAY",
9345   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
9346  },
9347  {
9348   "chips": ["gfx81"],
9349   "map": {"at": 225900, "to": "mm"},
9350   "name": "RLC_SPM_GLOBAL_MUXSEL_ADDR"
9351  },
9352  {
9353   "chips": ["gfx81"],
9354   "map": {"at": 225904, "to": "mm"},
9355   "name": "RLC_SPM_GLOBAL_MUXSEL_DATA"
9356  },
9357  {
9358   "chips": ["gfx81"],
9359   "map": {"at": 225908, "to": "mm"},
9360   "name": "RLC_SPM_RING_RDPTR"
9361  },
9362  {
9363   "chips": ["gfx81"],
9364   "map": {"at": 225912, "to": "mm"},
9365   "name": "RLC_SPM_SEGMENT_THRESHOLD"
9366  },
9367  {
9368   "chips": ["gfx81"],
9369   "map": {"at": 226044, "to": "mm"},
9370   "name": "RLC_PERFMON_CLK_CNTL",
9371   "type_ref": "RLC_PERFMON_CLK_CNTL"
9372  },
9373  {
9374   "chips": ["gfx81"],
9375   "map": {"at": 226048, "to": "mm"},
9376   "name": "RLC_PERFMON_CNTL",
9377   "type_ref": "RLC_PERFMON_CNTL"
9378  },
9379  {
9380   "chips": ["gfx81"],
9381   "map": {"at": 226052, "to": "mm"},
9382   "name": "RLC_PERFCOUNTER0_SELECT",
9383   "type_ref": "RLC_PERFCOUNTER0_SELECT"
9384  },
9385  {
9386   "chips": ["gfx81"],
9387   "map": {"at": 226056, "to": "mm"},
9388   "name": "RLC_PERFCOUNTER1_SELECT",
9389   "type_ref": "RLC_PERFCOUNTER0_SELECT"
9390  }
9391 ],
9392 "register_types": {
9393  "CB_BLEND0_CONTROL": {
9394   "fields": [
9395    {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"},
9396    {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"},
9397    {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"},
9398    {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"},
9399    {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"},
9400    {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"},
9401    {"bits": [29, 29], "name": "SEPARATE_ALPHA_BLEND"},
9402    {"bits": [30, 30], "name": "ENABLE"},
9403    {"bits": [31, 31], "name": "DISABLE_ROP3"}
9404   ]
9405  },
9406  "CB_COLOR0_ATTRIB": {
9407   "fields": [
9408    {"bits": [0, 4], "name": "TILE_MODE_INDEX"},
9409    {"bits": [5, 9], "name": "FMASK_TILE_MODE_INDEX"},
9410    {"bits": [10, 11], "name": "FMASK_BANK_HEIGHT"},
9411    {"bits": [12, 14], "name": "NUM_SAMPLES"},
9412    {"bits": [15, 16], "name": "NUM_FRAGMENTS"},
9413    {"bits": [17, 17], "name": "FORCE_DST_ALPHA_1"}
9414   ]
9415  },
9416  "CB_COLOR0_CMASK_SLICE": {
9417   "fields": [
9418    {"bits": [0, 13], "name": "TILE_MAX"}
9419   ]
9420  },
9421  "CB_COLOR0_DCC_CONTROL": {
9422   "fields": [
9423    {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"},
9424    {"bits": [1, 1], "name": "KEY_CLEAR_ENABLE"},
9425    {"bits": [2, 3], "enum_ref": "CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE", "name": "MAX_UNCOMPRESSED_BLOCK_SIZE"},
9426    {"bits": [4, 4], "enum_ref": "CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE", "name": "MIN_COMPRESSED_BLOCK_SIZE"},
9427    {"bits": [5, 6], "name": "MAX_COMPRESSED_BLOCK_SIZE"},
9428    {"bits": [7, 8], "name": "COLOR_TRANSFORM"},
9429    {"bits": [9, 9], "name": "INDEPENDENT_64B_BLOCKS"},
9430    {"bits": [10, 13], "name": "LOSSY_RGB_PRECISION"},
9431    {"bits": [14, 17], "name": "LOSSY_ALPHA_PRECISION"}
9432   ]
9433  },
9434  "CB_COLOR0_INFO": {
9435   "fields": [
9436    {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"},
9437    {"bits": [2, 6], "enum_ref": "ColorFormat", "name": "FORMAT"},
9438    {"bits": [7, 7], "name": "LINEAR_GENERAL"},
9439    {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"},
9440    {"bits": [11, 12], "enum_ref": "SurfaceSwap", "name": "COMP_SWAP"},
9441    {"bits": [13, 13], "name": "FAST_CLEAR"},
9442    {"bits": [14, 14], "name": "COMPRESSION"},
9443    {"bits": [15, 15], "name": "BLEND_CLAMP"},
9444    {"bits": [16, 16], "name": "BLEND_BYPASS"},
9445    {"bits": [17, 17], "name": "SIMPLE_FLOAT"},
9446    {"bits": [18, 18], "name": "ROUND_MODE"},
9447    {"bits": [19, 19], "name": "CMASK_IS_LINEAR"},
9448    {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"},
9449    {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"},
9450    {"bits": [26, 26], "name": "FMASK_COMPRESSION_DISABLE"},
9451    {"bits": [27, 27], "name": "FMASK_COMPRESS_1FRAG_ONLY"},
9452    {"bits": [28, 28], "name": "DCC_ENABLE"},
9453    {"bits": [29, 30], "enum_ref": "CmaskAddr", "name": "CMASK_ADDR_TYPE"}
9454   ]
9455  },
9456  "CB_COLOR0_PITCH": {
9457   "fields": [
9458    {"bits": [0, 10], "name": "TILE_MAX"},
9459    {"bits": [20, 30], "name": "FMASK_TILE_MAX"}
9460   ]
9461  },
9462  "CB_COLOR0_SLICE": {
9463   "fields": [
9464    {"bits": [0, 21], "name": "TILE_MAX"}
9465   ]
9466  },
9467  "CB_COLOR0_VIEW": {
9468   "fields": [
9469    {"bits": [0, 10], "name": "SLICE_START"},
9470    {"bits": [13, 23], "name": "SLICE_MAX"}
9471   ]
9472  },
9473  "CB_COLOR_CONTROL": {
9474   "fields": [
9475    {"bits": [0, 0], "name": "DISABLE_DUAL_QUAD"},
9476    {"bits": [3, 3], "name": "DEGAMMA_ENABLE"},
9477    {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"},
9478    {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"}
9479   ]
9480  },
9481  "CB_DCC_CONTROL": {
9482   "fields": [
9483    {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"},
9484    {"bits": [1, 1], "name": "OVERWRITE_COMBINER_MRT_SHARING_DISABLE"},
9485    {"bits": [2, 6], "name": "OVERWRITE_COMBINER_WATERMARK"}
9486   ]
9487  },
9488  "CB_PERFCOUNTER0_SELECT": {
9489   "fields": [
9490    {"bits": [0, 8], "name": "PERF_SEL"},
9491    {"bits": [10, 18], "name": "PERF_SEL1"},
9492    {"bits": [20, 23], "name": "CNTR_MODE"},
9493    {"bits": [24, 27], "name": "PERF_MODE1"},
9494    {"bits": [28, 31], "name": "PERF_MODE"}
9495   ]
9496  },
9497  "CB_PERFCOUNTER0_SELECT1": {
9498   "fields": [
9499    {"bits": [0, 8], "name": "PERF_SEL2"},
9500    {"bits": [10, 18], "name": "PERF_SEL3"},
9501    {"bits": [24, 27], "name": "PERF_MODE3"},
9502    {"bits": [28, 31], "name": "PERF_MODE2"}
9503   ]
9504  },
9505  "CB_PERFCOUNTER1_SELECT": {
9506   "fields": [
9507    {"bits": [0, 8], "name": "PERF_SEL"},
9508    {"bits": [28, 31], "name": "PERF_MODE"}
9509   ]
9510  },
9511  "CB_PERFCOUNTER_FILTER": {
9512   "fields": [
9513    {"bits": [0, 0], "name": "OP_FILTER_ENABLE"},
9514    {"bits": [1, 3], "enum_ref": "CBPerfOpFilterSel", "name": "OP_FILTER_SEL"},
9515    {"bits": [4, 4], "name": "FORMAT_FILTER_ENABLE"},
9516    {"bits": [5, 9], "name": "FORMAT_FILTER_SEL"},
9517    {"bits": [10, 10], "name": "CLEAR_FILTER_ENABLE"},
9518    {"bits": [11, 11], "enum_ref": "CBPerfClearFilterSel", "name": "CLEAR_FILTER_SEL"},
9519    {"bits": [12, 12], "name": "MRT_FILTER_ENABLE"},
9520    {"bits": [13, 15], "name": "MRT_FILTER_SEL"},
9521    {"bits": [17, 17], "name": "NUM_SAMPLES_FILTER_ENABLE"},
9522    {"bits": [18, 20], "name": "NUM_SAMPLES_FILTER_SEL"},
9523    {"bits": [21, 21], "name": "NUM_FRAGMENTS_FILTER_ENABLE"},
9524    {"bits": [22, 23], "name": "NUM_FRAGMENTS_FILTER_SEL"}
9525   ]
9526  },
9527  "CB_SHADER_MASK": {
9528   "fields": [
9529    {"bits": [0, 3], "name": "OUTPUT0_ENABLE"},
9530    {"bits": [4, 7], "name": "OUTPUT1_ENABLE"},
9531    {"bits": [8, 11], "name": "OUTPUT2_ENABLE"},
9532    {"bits": [12, 15], "name": "OUTPUT3_ENABLE"},
9533    {"bits": [16, 19], "name": "OUTPUT4_ENABLE"},
9534    {"bits": [20, 23], "name": "OUTPUT5_ENABLE"},
9535    {"bits": [24, 27], "name": "OUTPUT6_ENABLE"},
9536    {"bits": [28, 31], "name": "OUTPUT7_ENABLE"}
9537   ]
9538  },
9539  "CB_TARGET_MASK": {
9540   "fields": [
9541    {"bits": [0, 3], "name": "TARGET0_ENABLE"},
9542    {"bits": [4, 7], "name": "TARGET1_ENABLE"},
9543    {"bits": [8, 11], "name": "TARGET2_ENABLE"},
9544    {"bits": [12, 15], "name": "TARGET3_ENABLE"},
9545    {"bits": [16, 19], "name": "TARGET4_ENABLE"},
9546    {"bits": [20, 23], "name": "TARGET5_ENABLE"},
9547    {"bits": [24, 27], "name": "TARGET6_ENABLE"},
9548    {"bits": [28, 31], "name": "TARGET7_ENABLE"}
9549   ]
9550  },
9551  "COMPUTE_DISPATCH_INITIATOR": {
9552   "fields": [
9553    {"bits": [0, 0], "name": "COMPUTE_SHADER_EN"},
9554    {"bits": [1, 1], "name": "PARTIAL_TG_EN"},
9555    {"bits": [2, 2], "name": "FORCE_START_AT_000"},
9556    {"bits": [3, 3], "name": "ORDERED_APPEND_ENBL"},
9557    {"bits": [4, 4], "name": "ORDERED_APPEND_MODE"},
9558    {"bits": [5, 5], "name": "USE_THREAD_DIMENSIONS"},
9559    {"bits": [6, 6], "name": "ORDER_MODE"},
9560    {"bits": [7, 9], "name": "DISPATCH_CACHE_CNTL"},
9561    {"bits": [10, 10], "name": "SCALAR_L1_INV_VOL"},
9562    {"bits": [11, 11], "name": "VECTOR_L1_INV_VOL"},
9563    {"bits": [12, 12], "name": "DATA_ATC"},
9564    {"bits": [14, 14], "name": "RESTORE"}
9565   ]
9566  },
9567  "COMPUTE_MISC_RESERVED": {
9568   "fields": [
9569    {"bits": [0, 1], "name": "SEND_SEID"},
9570    {"bits": [2, 2], "name": "RESERVED2"},
9571    {"bits": [3, 3], "name": "RESERVED3"},
9572    {"bits": [4, 4], "name": "RESERVED4"},
9573    {"bits": [5, 16], "name": "WAVE_ID_BASE"}
9574   ]
9575  },
9576  "COMPUTE_NUM_THREAD_X": {
9577   "fields": [
9578    {"bits": [0, 15], "name": "NUM_THREAD_FULL"},
9579    {"bits": [16, 31], "name": "NUM_THREAD_PARTIAL"}
9580   ]
9581  },
9582  "COMPUTE_PERFCOUNT_ENABLE": {
9583   "fields": [
9584    {"bits": [0, 0], "name": "PERFCOUNT_ENABLE"}
9585   ]
9586  },
9587  "COMPUTE_PGM_HI": {
9588   "fields": [
9589    {"bits": [0, 7], "name": "DATA"},
9590    {"bits": [8, 8], "name": "INST_ATC"}
9591   ]
9592  },
9593  "COMPUTE_PGM_RSRC1": {
9594   "fields": [
9595    {"bits": [0, 5], "name": "VGPRS"},
9596    {"bits": [6, 9], "name": "SGPRS"},
9597    {"bits": [10, 11], "name": "PRIORITY"},
9598    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
9599    {"bits": [20, 20], "name": "PRIV"},
9600    {"bits": [21, 21], "name": "DX10_CLAMP"},
9601    {"bits": [22, 22], "name": "DEBUG_MODE"},
9602    {"bits": [23, 23], "name": "IEEE_MODE"},
9603    {"bits": [24, 24], "name": "BULKY"},
9604    {"bits": [25, 25], "name": "CDBG_USER"}
9605   ]
9606  },
9607  "COMPUTE_PGM_RSRC2": {
9608   "fields": [
9609    {"bits": [0, 0], "name": "SCRATCH_EN"},
9610    {"bits": [1, 5], "name": "USER_SGPR"},
9611    {"bits": [6, 6], "name": "TRAP_PRESENT"},
9612    {"bits": [7, 7], "name": "TGID_X_EN"},
9613    {"bits": [8, 8], "name": "TGID_Y_EN"},
9614    {"bits": [9, 9], "name": "TGID_Z_EN"},
9615    {"bits": [10, 10], "name": "TG_SIZE_EN"},
9616    {"bits": [11, 12], "name": "TIDIG_COMP_CNT"},
9617    {"bits": [13, 14], "name": "EXCP_EN_MSB"},
9618    {"bits": [15, 23], "name": "LDS_SIZE"},
9619    {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
9620   ]
9621  },
9622  "COMPUTE_PIPELINESTAT_ENABLE": {
9623   "fields": [
9624    {"bits": [0, 0], "name": "PIPELINESTAT_ENABLE"}
9625   ]
9626  },
9627  "COMPUTE_RELAUNCH": {
9628   "fields": [
9629    {"bits": [0, 29], "name": "PAYLOAD"},
9630    {"bits": [30, 30], "name": "IS_EVENT"},
9631    {"bits": [31, 31], "name": "IS_STATE"}
9632   ]
9633  },
9634  "COMPUTE_RESOURCE_LIMITS": {
9635   "fields": [
9636    {"bits": [0, 9], "name": "WAVES_PER_SH"},
9637    {"bits": [12, 15], "name": "TG_PER_CU"},
9638    {"bits": [16, 21], "name": "LOCK_THRESHOLD"},
9639    {"bits": [22, 22], "name": "SIMD_DEST_CNTL"},
9640    {"bits": [23, 23], "name": "FORCE_SIMD_DIST"},
9641    {"bits": [24, 26], "name": "CU_GROUP_COUNT"}
9642   ]
9643  },
9644  "COMPUTE_STATIC_THREAD_MGMT_SE0": {
9645   "fields": [
9646    {"bits": [0, 15], "name": "SH0_CU_EN"},
9647    {"bits": [16, 31], "name": "SH1_CU_EN"}
9648   ]
9649  },
9650  "COMPUTE_TBA_HI": {
9651   "fields": [
9652    {"bits": [0, 7], "name": "DATA"}
9653   ]
9654  },
9655  "COMPUTE_THREAD_TRACE_ENABLE": {
9656   "fields": [
9657    {"bits": [0, 0], "name": "THREAD_TRACE_ENABLE"}
9658   ]
9659  },
9660  "COMPUTE_TMPRING_SIZE": {
9661   "fields": [
9662    {"bits": [0, 11], "name": "WAVES"},
9663    {"bits": [12, 24], "name": "WAVESIZE"}
9664   ]
9665  },
9666  "COMPUTE_VMID": {
9667   "fields": [
9668    {"bits": [0, 3], "name": "DATA"}
9669   ]
9670  },
9671  "COMPUTE_WAVE_RESTORE_ADDR_HI": {
9672   "fields": [
9673    {"bits": [0, 15], "name": "ADDR"}
9674   ]
9675  },
9676  "COMPUTE_WAVE_RESTORE_CONTROL": {
9677   "fields": [
9678    {"bits": [0, 0], "name": "ATC"},
9679    {"bits": [1, 2], "name": "MTYPE"}
9680   ]
9681  },
9682  "CPG_PERFCOUNTER0_SELECT": {
9683   "fields": [
9684    {"bits": [0, 5], "name": "PERF_SEL"},
9685    {"bits": [10, 15], "name": "PERF_SEL1"},
9686    {"bits": [20, 23], "name": "CNTR_MODE"}
9687   ]
9688  },
9689  "CPG_PERFCOUNTER0_SELECT1": {
9690   "fields": [
9691    {"bits": [0, 5], "name": "PERF_SEL2"},
9692    {"bits": [10, 15], "name": "PERF_SEL3"}
9693   ]
9694  },
9695  "CPG_PERFCOUNTER1_SELECT": {
9696   "fields": [
9697    {"bits": [0, 5], "name": "PERF_SEL"}
9698   ]
9699  },
9700  "CP_APPEND_ADDR_HI": {
9701   "fields": [
9702    {"bits": [0, 15], "name": "MEM_ADDR_HI"},
9703    {"bits": [16, 16], "name": "CS_PS_SEL"},
9704    {"bits": [25, 25], "name": "CACHE_POLICY"},
9705    {"bits": [27, 28], "name": "MTYPE"},
9706    {"bits": [29, 31], "name": "COMMAND"}
9707   ]
9708  },
9709  "CP_APPEND_ADDR_LO": {
9710   "fields": [
9711    {"bits": [2, 31], "name": "MEM_ADDR_LO"}
9712   ]
9713  },
9714  "CP_CE_IB1_BASE_HI": {
9715   "fields": [
9716    {"bits": [0, 15], "name": "IB1_BASE_HI"}
9717   ]
9718  },
9719  "CP_CE_IB1_BASE_LO": {
9720   "fields": [
9721    {"bits": [2, 31], "name": "IB1_BASE_LO"}
9722   ]
9723  },
9724  "CP_CE_IB1_BUFSZ": {
9725   "fields": [
9726    {"bits": [0, 19], "name": "IB1_BUFSZ"}
9727   ]
9728  },
9729  "CP_CE_IB2_BASE_HI": {
9730   "fields": [
9731    {"bits": [0, 15], "name": "IB2_BASE_HI"}
9732   ]
9733  },
9734  "CP_CE_IB2_BASE_LO": {
9735   "fields": [
9736    {"bits": [2, 31], "name": "IB2_BASE_LO"}
9737   ]
9738  },
9739  "CP_CE_IB2_BUFSZ": {
9740   "fields": [
9741    {"bits": [0, 19], "name": "IB2_BUFSZ"}
9742   ]
9743  },
9744  "CP_CE_INIT_BASE_HI": {
9745   "fields": [
9746    {"bits": [0, 15], "name": "INIT_BASE_HI"}
9747   ]
9748  },
9749  "CP_CE_INIT_BASE_LO": {
9750   "fields": [
9751    {"bits": [5, 31], "name": "INIT_BASE_LO"}
9752   ]
9753  },
9754  "CP_CE_INIT_BUFSZ": {
9755   "fields": [
9756    {"bits": [0, 11], "name": "INIT_BUFSZ"}
9757   ]
9758  },
9759  "CP_COHER_BASE_HI": {
9760   "fields": [
9761    {"bits": [0, 7], "name": "COHER_BASE_HI_256B"}
9762   ]
9763  },
9764  "CP_COHER_CNTL": {
9765   "fields": [
9766    {"bits": [0, 0], "name": "DEST_BASE_0_ENA"},
9767    {"bits": [1, 1], "name": "DEST_BASE_1_ENA"},
9768    {"bits": [2, 2], "name": "TC_SD_ACTION_ENA"},
9769    {"bits": [3, 3], "name": "TC_NC_ACTION_ENA"},
9770    {"bits": [6, 6], "name": "CB0_DEST_BASE_ENA"},
9771    {"bits": [7, 7], "name": "CB1_DEST_BASE_ENA"},
9772    {"bits": [8, 8], "name": "CB2_DEST_BASE_ENA"},
9773    {"bits": [9, 9], "name": "CB3_DEST_BASE_ENA"},
9774    {"bits": [10, 10], "name": "CB4_DEST_BASE_ENA"},
9775    {"bits": [11, 11], "name": "CB5_DEST_BASE_ENA"},
9776    {"bits": [12, 12], "name": "CB6_DEST_BASE_ENA"},
9777    {"bits": [13, 13], "name": "CB7_DEST_BASE_ENA"},
9778    {"bits": [14, 14], "name": "DB_DEST_BASE_ENA"},
9779    {"bits": [15, 15], "name": "TCL1_VOL_ACTION_ENA"},
9780    {"bits": [18, 18], "name": "TC_WB_ACTION_ENA"},
9781    {"bits": [19, 19], "name": "DEST_BASE_2_ENA"},
9782    {"bits": [21, 21], "name": "DEST_BASE_3_ENA"},
9783    {"bits": [22, 22], "name": "TCL1_ACTION_ENA"},
9784    {"bits": [23, 23], "name": "TC_ACTION_ENA"},
9785    {"bits": [25, 25], "name": "CB_ACTION_ENA"},
9786    {"bits": [26, 26], "name": "DB_ACTION_ENA"},
9787    {"bits": [27, 27], "name": "SH_KCACHE_ACTION_ENA"},
9788    {"bits": [28, 28], "name": "SH_KCACHE_VOL_ACTION_ENA"},
9789    {"bits": [29, 29], "name": "SH_ICACHE_ACTION_ENA"},
9790    {"bits": [30, 30], "name": "SH_KCACHE_WB_ACTION_ENA"},
9791    {"bits": [31, 31], "name": "SH_SD_ACTION_ENA"}
9792   ]
9793  },
9794  "CP_COHER_SIZE_HI": {
9795   "fields": [
9796    {"bits": [0, 7], "name": "COHER_SIZE_HI_256B"}
9797   ]
9798  },
9799  "CP_COHER_START_DELAY": {
9800   "fields": [
9801    {"bits": [0, 5], "name": "START_DELAY_COUNT"}
9802   ]
9803  },
9804  "CP_COHER_STATUS": {
9805   "fields": [
9806    {"bits": [0, 7], "name": "MATCHING_GFX_CNTX"},
9807    {"bits": [24, 25], "name": "MEID"},
9808    {"bits": [30, 30], "name": "PHASE1_STATUS"},
9809    {"bits": [31, 31], "name": "STATUS"}
9810   ]
9811  },
9812  "CP_CPC_BUSY_STAT": {
9813   "fields": [
9814    {"bits": [0, 0], "name": "MEC1_LOAD_BUSY"},
9815    {"bits": [1, 1], "name": "MEC1_SEMAPOHRE_BUSY"},
9816    {"bits": [2, 2], "name": "MEC1_MUTEX_BUSY"},
9817    {"bits": [3, 3], "name": "MEC1_MESSAGE_BUSY"},
9818    {"bits": [4, 4], "name": "MEC1_EOP_QUEUE_BUSY"},
9819    {"bits": [5, 5], "name": "MEC1_IQ_QUEUE_BUSY"},
9820    {"bits": [6, 6], "name": "MEC1_IB_QUEUE_BUSY"},
9821    {"bits": [7, 7], "name": "MEC1_TC_BUSY"},
9822    {"bits": [8, 8], "name": "MEC1_DMA_BUSY"},
9823    {"bits": [9, 9], "name": "MEC1_PARTIAL_FLUSH_BUSY"},
9824    {"bits": [10, 10], "name": "MEC1_PIPE0_BUSY"},
9825    {"bits": [11, 11], "name": "MEC1_PIPE1_BUSY"},
9826    {"bits": [12, 12], "name": "MEC1_PIPE2_BUSY"},
9827    {"bits": [13, 13], "name": "MEC1_PIPE3_BUSY"},
9828    {"bits": [16, 16], "name": "MEC2_LOAD_BUSY"},
9829    {"bits": [17, 17], "name": "MEC2_SEMAPOHRE_BUSY"},
9830    {"bits": [18, 18], "name": "MEC2_MUTEX_BUSY"},
9831    {"bits": [19, 19], "name": "MEC2_MESSAGE_BUSY"},
9832    {"bits": [20, 20], "name": "MEC2_EOP_QUEUE_BUSY"},
9833    {"bits": [21, 21], "name": "MEC2_IQ_QUEUE_BUSY"},
9834    {"bits": [22, 22], "name": "MEC2_IB_QUEUE_BUSY"},
9835    {"bits": [23, 23], "name": "MEC2_TC_BUSY"},
9836    {"bits": [24, 24], "name": "MEC2_DMA_BUSY"},
9837    {"bits": [25, 25], "name": "MEC2_PARTIAL_FLUSH_BUSY"},
9838    {"bits": [26, 26], "name": "MEC2_PIPE0_BUSY"},
9839    {"bits": [27, 27], "name": "MEC2_PIPE1_BUSY"},
9840    {"bits": [28, 28], "name": "MEC2_PIPE2_BUSY"},
9841    {"bits": [29, 29], "name": "MEC2_PIPE3_BUSY"}
9842   ]
9843  },
9844  "CP_CPC_GRBM_FREE_COUNT": {
9845   "fields": [
9846    {"bits": [0, 5], "name": "FREE_COUNT"}
9847   ]
9848  },
9849  "CP_CPC_HALT_HYST_COUNT": {
9850   "fields": [
9851    {"bits": [0, 3], "name": "COUNT"}
9852   ]
9853  },
9854  "CP_CPC_SCRATCH_INDEX": {
9855   "fields": [
9856    {"bits": [0, 8], "name": "SCRATCH_INDEX"}
9857   ]
9858  },
9859  "CP_CPC_STALLED_STAT1": {
9860   "fields": [
9861    {"bits": [3, 3], "name": "RCIU_TX_FREE_STALL"},
9862    {"bits": [4, 4], "name": "RCIU_PRIV_VIOLATION"},
9863    {"bits": [6, 6], "name": "TCIU_TX_FREE_STALL"},
9864    {"bits": [8, 8], "name": "MEC1_DECODING_PACKET"},
9865    {"bits": [9, 9], "name": "MEC1_WAIT_ON_RCIU"},
9866    {"bits": [10, 10], "name": "MEC1_WAIT_ON_RCIU_READ"},
9867    {"bits": [13, 13], "name": "MEC1_WAIT_ON_ROQ_DATA"},
9868    {"bits": [16, 16], "name": "MEC2_DECODING_PACKET"},
9869    {"bits": [17, 17], "name": "MEC2_WAIT_ON_RCIU"},
9870    {"bits": [18, 18], "name": "MEC2_WAIT_ON_RCIU_READ"},
9871    {"bits": [21, 21], "name": "MEC2_WAIT_ON_ROQ_DATA"},
9872    {"bits": [22, 22], "name": "ATCL2IU_WAITING_ON_FREE"},
9873    {"bits": [23, 23], "name": "ATCL2IU_WAITING_ON_TAGS"},
9874    {"bits": [24, 24], "name": "ATCL1_WAITING_ON_TRANS"}
9875   ]
9876  },
9877  "CP_CPC_STATUS": {
9878   "fields": [
9879    {"bits": [0, 0], "name": "MEC1_BUSY"},
9880    {"bits": [1, 1], "name": "MEC2_BUSY"},
9881    {"bits": [2, 2], "name": "DC0_BUSY"},
9882    {"bits": [3, 3], "name": "DC1_BUSY"},
9883    {"bits": [4, 4], "name": "RCIU1_BUSY"},
9884    {"bits": [5, 5], "name": "RCIU2_BUSY"},
9885    {"bits": [6, 6], "name": "ROQ1_BUSY"},
9886    {"bits": [7, 7], "name": "ROQ2_BUSY"},
9887    {"bits": [10, 10], "name": "TCIU_BUSY"},
9888    {"bits": [11, 11], "name": "SCRATCH_RAM_BUSY"},
9889    {"bits": [12, 12], "name": "QU_BUSY"},
9890    {"bits": [13, 13], "name": "ATCL2IU_BUSY"},
9891    {"bits": [29, 29], "name": "CPG_CPC_BUSY"},
9892    {"bits": [30, 30], "name": "CPF_CPC_BUSY"},
9893    {"bits": [31, 31], "name": "CPC_BUSY"}
9894   ]
9895  },
9896  "CP_CPF_BUSY_STAT": {
9897   "fields": [
9898    {"bits": [0, 0], "name": "REG_BUS_FIFO_BUSY"},
9899    {"bits": [1, 1], "name": "CSF_RING_BUSY"},
9900    {"bits": [2, 2], "name": "CSF_INDIRECT1_BUSY"},
9901    {"bits": [3, 3], "name": "CSF_INDIRECT2_BUSY"},
9902    {"bits": [4, 4], "name": "CSF_STATE_BUSY"},
9903    {"bits": [5, 5], "name": "CSF_CE_INDR1_BUSY"},
9904    {"bits": [6, 6], "name": "CSF_CE_INDR2_BUSY"},
9905    {"bits": [7, 7], "name": "CSF_ARBITER_BUSY"},
9906    {"bits": [8, 8], "name": "CSF_INPUT_BUSY"},
9907    {"bits": [9, 9], "name": "OUTSTANDING_READ_TAGS"},
9908    {"bits": [11, 11], "name": "HPD_PROCESSING_EOP_BUSY"},
9909    {"bits": [12, 12], "name": "HQD_DISPATCH_BUSY"},
9910    {"bits": [13, 13], "name": "HQD_IQ_TIMER_BUSY"},
9911    {"bits": [14, 14], "name": "HQD_DMA_OFFLOAD_BUSY"},
9912    {"bits": [15, 15], "name": "HQD_WAIT_SEMAPHORE_BUSY"},
9913    {"bits": [16, 16], "name": "HQD_SIGNAL_SEMAPHORE_BUSY"},
9914    {"bits": [17, 17], "name": "HQD_MESSAGE_BUSY"},
9915    {"bits": [18, 18], "name": "HQD_PQ_FETCHER_BUSY"},
9916    {"bits": [19, 19], "name": "HQD_IB_FETCHER_BUSY"},
9917    {"bits": [20, 20], "name": "HQD_IQ_FETCHER_BUSY"},
9918    {"bits": [21, 21], "name": "HQD_EOP_FETCHER_BUSY"},
9919    {"bits": [22, 22], "name": "HQD_CONSUMED_RPTR_BUSY"},
9920    {"bits": [23, 23], "name": "HQD_FETCHER_ARB_BUSY"},
9921    {"bits": [24, 24], "name": "HQD_ROQ_ALIGN_BUSY"},
9922    {"bits": [25, 25], "name": "HQD_ROQ_EOP_BUSY"},
9923    {"bits": [26, 26], "name": "HQD_ROQ_IQ_BUSY"},
9924    {"bits": [27, 27], "name": "HQD_ROQ_PQ_BUSY"},
9925    {"bits": [28, 28], "name": "HQD_ROQ_IB_BUSY"},
9926    {"bits": [29, 29], "name": "HQD_WPTR_POLL_BUSY"},
9927    {"bits": [30, 30], "name": "HQD_PQ_BUSY"},
9928    {"bits": [31, 31], "name": "HQD_IB_BUSY"}
9929   ]
9930  },
9931  "CP_CPF_STALLED_STAT1": {
9932   "fields": [
9933    {"bits": [0, 0], "name": "RING_FETCHING_DATA"},
9934    {"bits": [1, 1], "name": "INDR1_FETCHING_DATA"},
9935    {"bits": [2, 2], "name": "INDR2_FETCHING_DATA"},
9936    {"bits": [3, 3], "name": "STATE_FETCHING_DATA"},
9937    {"bits": [5, 5], "name": "TCIU_WAITING_ON_FREE"},
9938    {"bits": [6, 6], "name": "TCIU_WAITING_ON_TAGS"},
9939    {"bits": [7, 7], "name": "ATCL2IU_WAITING_ON_FREE"},
9940    {"bits": [8, 8], "name": "ATCL2IU_WAITING_ON_TAGS"},
9941    {"bits": [9, 9], "name": "ATCL1_WAITING_ON_TRANS"}
9942   ]
9943  },
9944  "CP_CPF_STATUS": {
9945   "fields": [
9946    {"bits": [0, 0], "name": "POST_WPTR_GFX_BUSY"},
9947    {"bits": [1, 1], "name": "CSF_BUSY"},
9948    {"bits": [4, 4], "name": "ROQ_ALIGN_BUSY"},
9949    {"bits": [5, 5], "name": "ROQ_RING_BUSY"},
9950    {"bits": [6, 6], "name": "ROQ_INDIRECT1_BUSY"},
9951    {"bits": [7, 7], "name": "ROQ_INDIRECT2_BUSY"},
9952    {"bits": [8, 8], "name": "ROQ_STATE_BUSY"},
9953    {"bits": [9, 9], "name": "ROQ_CE_RING_BUSY"},
9954    {"bits": [10, 10], "name": "ROQ_CE_INDIRECT1_BUSY"},
9955    {"bits": [11, 11], "name": "ROQ_CE_INDIRECT2_BUSY"},
9956    {"bits": [12, 12], "name": "SEMAPHORE_BUSY"},
9957    {"bits": [13, 13], "name": "INTERRUPT_BUSY"},
9958    {"bits": [14, 14], "name": "TCIU_BUSY"},
9959    {"bits": [15, 15], "name": "HQD_BUSY"},
9960    {"bits": [16, 16], "name": "PRT_BUSY"},
9961    {"bits": [17, 17], "name": "ATCL2IU_BUSY"},
9962    {"bits": [26, 26], "name": "CPF_GFX_BUSY"},
9963    {"bits": [27, 27], "name": "CPF_CMP_BUSY"},
9964    {"bits": [28, 29], "name": "GRBM_CPF_STAT_BUSY"},
9965    {"bits": [30, 30], "name": "CPC_CPF_BUSY"},
9966    {"bits": [31, 31], "name": "CPF_BUSY"}
9967   ]
9968  },
9969  "CP_DMA_CNTL": {
9970   "fields": [
9971    {"bits": [4, 5], "name": "MIN_AVAILSZ"},
9972    {"bits": [16, 19], "name": "BUFFER_DEPTH"},
9973    {"bits": [28, 28], "name": "PIO_FIFO_EMPTY"},
9974    {"bits": [29, 29], "name": "PIO_FIFO_FULL"},
9975    {"bits": [30, 31], "name": "PIO_COUNT"}
9976   ]
9977  },
9978  "CP_DMA_ME_COMMAND": {
9979   "fields": [
9980    {"bits": [0, 20], "name": "BYTE_COUNT"},
9981    {"bits": [21, 21], "name": "DIS_WC"},
9982    {"bits": [22, 23], "name": "SRC_SWAP"},
9983    {"bits": [24, 25], "name": "DST_SWAP"},
9984    {"bits": [26, 26], "name": "SAS"},
9985    {"bits": [27, 27], "name": "DAS"},
9986    {"bits": [28, 28], "name": "SAIC"},
9987    {"bits": [29, 29], "name": "DAIC"},
9988    {"bits": [30, 30], "name": "RAW_WAIT"}
9989   ]
9990  },
9991  "CP_DMA_ME_CONTROL": {
9992   "fields": [
9993    {"bits": [10, 11], "name": "SRC_MTYPE"},
9994    {"bits": [12, 12], "name": "SRC_ATC"},
9995    {"bits": [13, 13], "name": "SRC_CACHE_POLICY"},
9996    {"bits": [20, 21], "name": "DST_SELECT"},
9997    {"bits": [22, 23], "name": "DST_MTYPE"},
9998    {"bits": [24, 24], "name": "DST_ATC"},
9999    {"bits": [25, 25], "name": "DST_CACHE_POLICY"},
10000    {"bits": [29, 30], "name": "SRC_SELECT"}
10001   ]
10002  },
10003  "CP_DMA_ME_DST_ADDR_HI": {
10004   "fields": [
10005    {"bits": [0, 15], "name": "DST_ADDR_HI"}
10006   ]
10007  },
10008  "CP_DMA_ME_SRC_ADDR_HI": {
10009   "fields": [
10010    {"bits": [0, 15], "name": "SRC_ADDR_HI"}
10011   ]
10012  },
10013  "CP_DMA_READ_TAGS": {
10014   "fields": [
10015    {"bits": [0, 25], "name": "DMA_READ_TAG"},
10016    {"bits": [28, 28], "name": "DMA_READ_TAG_VALID"}
10017   ]
10018  },
10019  "CP_DRAW_OBJECT_COUNTER": {
10020   "fields": [
10021    {"bits": [0, 15], "name": "COUNT"}
10022   ]
10023  },
10024  "CP_DRAW_WINDOW_CNTL": {
10025   "fields": [
10026    {"bits": [0, 0], "name": "DISABLE_DRAW_WINDOW_LO_MAX"},
10027    {"bits": [1, 1], "name": "DISABLE_DRAW_WINDOW_LO_MIN"},
10028    {"bits": [2, 2], "name": "DISABLE_DRAW_WINDOW_HI"},
10029    {"bits": [8, 8], "name": "MODE"}
10030   ]
10031  },
10032  "CP_DRAW_WINDOW_LO": {
10033   "fields": [
10034    {"bits": [0, 15], "name": "MIN"},
10035    {"bits": [16, 31], "name": "MAX"}
10036   ]
10037  },
10038  "CP_EOP_DONE_ADDR_HI": {
10039   "fields": [
10040    {"bits": [0, 15], "name": "ADDR_HI"}
10041   ]
10042  },
10043  "CP_EOP_DONE_ADDR_LO": {
10044   "fields": [
10045    {"bits": [2, 31], "name": "ADDR_LO"}
10046   ]
10047  },
10048  "CP_EOP_DONE_CNTX_ID": {
10049   "fields": [
10050    {"bits": [0, 27], "name": "CNTX_ID"}
10051   ]
10052  },
10053  "CP_EOP_DONE_DATA_CNTL": {
10054   "fields": [
10055    {"bits": [0, 15], "name": "CNTX_ID"},
10056    {"bits": [16, 17], "name": "DST_SEL"},
10057    {"bits": [24, 26], "name": "INT_SEL"},
10058    {"bits": [29, 31], "name": "DATA_SEL"}
10059   ]
10060  },
10061  "CP_EOP_DONE_EVENT_CNTL": {
10062   "fields": [
10063    {"bits": [0, 6], "name": "WBINV_TC_OP"},
10064    {"bits": [12, 17], "name": "WBINV_ACTION_ENA"},
10065    {"bits": [25, 25], "name": "CACHE_CONTROL"},
10066    {"bits": [27, 28], "name": "MTYPE"}
10067   ]
10068  },
10069  "CP_IB1_OFFSET": {
10070   "fields": [
10071    {"bits": [0, 19], "name": "IB1_OFFSET"}
10072   ]
10073  },
10074  "CP_IB1_PREAMBLE_BEGIN": {
10075   "fields": [
10076    {"bits": [0, 19], "name": "IB1_PREAMBLE_BEGIN"}
10077   ]
10078  },
10079  "CP_IB1_PREAMBLE_END": {
10080   "fields": [
10081    {"bits": [0, 19], "name": "IB1_PREAMBLE_END"}
10082   ]
10083  },
10084  "CP_IB2_OFFSET": {
10085   "fields": [
10086    {"bits": [0, 19], "name": "IB2_OFFSET"}
10087   ]
10088  },
10089  "CP_IB2_PREAMBLE_BEGIN": {
10090   "fields": [
10091    {"bits": [0, 19], "name": "IB2_PREAMBLE_BEGIN"}
10092   ]
10093  },
10094  "CP_IB2_PREAMBLE_END": {
10095   "fields": [
10096    {"bits": [0, 19], "name": "IB2_PREAMBLE_END"}
10097   ]
10098  },
10099  "CP_INDEX_TYPE": {
10100   "fields": [
10101    {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}
10102   ]
10103  },
10104  "CP_ME_MC_RADDR_HI": {
10105   "fields": [
10106    {"bits": [0, 15], "name": "ME_MC_RADDR_HI"},
10107    {"bits": [20, 21], "name": "MTYPE"},
10108    {"bits": [22, 22], "name": "CACHE_POLICY"}
10109   ]
10110  },
10111  "CP_ME_MC_RADDR_LO": {
10112   "fields": [
10113    {"bits": [0, 1], "name": "ME_MC_RADDR_SWAP"},
10114    {"bits": [2, 31], "name": "ME_MC_RADDR_LO"}
10115   ]
10116  },
10117  "CP_ME_MC_WADDR_HI": {
10118   "fields": [
10119    {"bits": [0, 15], "name": "ME_MC_WADDR_HI"},
10120    {"bits": [20, 21], "name": "MTYPE"},
10121    {"bits": [22, 22], "name": "CACHE_POLICY"}
10122   ]
10123  },
10124  "CP_ME_MC_WADDR_LO": {
10125   "fields": [
10126    {"bits": [0, 1], "name": "ME_MC_WADDR_SWAP"},
10127    {"bits": [2, 31], "name": "ME_MC_WADDR_LO"}
10128   ]
10129  },
10130  "CP_PERFMON_CNTL": {
10131   "fields": [
10132    {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"},
10133    {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"},
10134    {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"},
10135    {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"}
10136   ]
10137  },
10138  "CP_PERFMON_CNTX_CNTL": {
10139   "fields": [
10140    {"bits": [31, 31], "name": "PERFMON_ENABLE"}
10141   ]
10142  },
10143  "CP_PFP_COMPLETION_STATUS": {
10144   "fields": [
10145    {"bits": [0, 1], "name": "STATUS"}
10146   ]
10147  },
10148  "CP_PFP_IB_CONTROL": {
10149   "fields": [
10150    {"bits": [0, 7], "name": "IB_EN"}
10151   ]
10152  },
10153  "CP_PFP_LOAD_CONTROL": {
10154   "fields": [
10155    {"bits": [0, 0], "name": "CONFIG_REG_EN"},
10156    {"bits": [1, 1], "name": "CNTX_REG_EN"},
10157    {"bits": [16, 16], "name": "SH_GFX_REG_EN"},
10158    {"bits": [24, 24], "name": "SH_CS_REG_EN"}
10159   ]
10160  },
10161  "CP_PIPE_STATS_ADDR_HI": {
10162   "fields": [
10163    {"bits": [0, 15], "name": "PIPE_STATS_ADDR_HI"}
10164   ]
10165  },
10166  "CP_PIPE_STATS_ADDR_LO": {
10167   "fields": [
10168    {"bits": [2, 31], "name": "PIPE_STATS_ADDR_LO"}
10169   ]
10170  },
10171  "CP_PIPE_STATS_CONTROL": {
10172   "fields": [
10173    {"bits": [25, 25], "name": "CACHE_CONTROL"},
10174    {"bits": [27, 28], "name": "MTYPE"}
10175   ]
10176  },
10177  "CP_PRED_NOT_VISIBLE": {
10178   "fields": [
10179    {"bits": [0, 0], "name": "NOT_VISIBLE"}
10180   ]
10181  },
10182  "CP_RB_OFFSET": {
10183   "fields": [
10184    {"bits": [0, 19], "name": "RB_OFFSET"}
10185   ]
10186  },
10187  "CP_RINGID": {
10188   "fields": [
10189    {"bits": [0, 1], "name": "RINGID"}
10190   ]
10191  },
10192  "CP_SAMPLE_STATUS": {
10193   "fields": [
10194    {"bits": [0, 0], "name": "Z_PASS_ACITVE"},
10195    {"bits": [1, 1], "name": "STREAMOUT_ACTIVE"},
10196    {"bits": [2, 2], "name": "PIPELINE_ACTIVE"},
10197    {"bits": [3, 3], "name": "STIPPLE_ACTIVE"},
10198    {"bits": [4, 4], "name": "VGT_BUFFERS_ACTIVE"},
10199    {"bits": [5, 5], "name": "SCREEN_EXT_ACTIVE"},
10200    {"bits": [6, 6], "name": "DRAW_INDIRECT_ACTIVE"},
10201    {"bits": [7, 7], "name": "DISP_INDIRECT_ACTIVE"}
10202   ]
10203  },
10204  "CP_SCRATCH_INDEX": {
10205   "fields": [
10206    {"bits": [0, 7], "name": "SCRATCH_INDEX"}
10207   ]
10208  },
10209  "CP_SIG_SEM_ADDR_HI": {
10210   "fields": [
10211    {"bits": [0, 15], "name": "SEM_ADDR_HI"},
10212    {"bits": [16, 16], "name": "SEM_USE_MAILBOX"},
10213    {"bits": [20, 20], "name": "SEM_SIGNAL_TYPE"},
10214    {"bits": [24, 25], "name": "SEM_CLIENT_CODE"},
10215    {"bits": [29, 31], "name": "SEM_SELECT"}
10216   ]
10217  },
10218  "CP_SIG_SEM_ADDR_LO": {
10219   "fields": [
10220    {"bits": [0, 1], "name": "SEM_ADDR_SWAP"},
10221    {"bits": [3, 31], "name": "SEM_ADDR_LO"}
10222   ]
10223  },
10224  "CP_STREAM_OUT_ADDR_HI": {
10225   "fields": [
10226    {"bits": [0, 15], "name": "STREAM_OUT_ADDR_HI"}
10227   ]
10228  },
10229  "CP_STREAM_OUT_ADDR_LO": {
10230   "fields": [
10231    {"bits": [2, 31], "name": "STREAM_OUT_ADDR_LO"}
10232   ]
10233  },
10234  "CP_STRMOUT_CNTL": {
10235   "fields": [
10236    {"bits": [0, 0], "name": "OFFSET_UPDATE_DONE"}
10237   ]
10238  },
10239  "CP_ST_BASE_HI": {
10240   "fields": [
10241    {"bits": [0, 15], "name": "ST_BASE_HI"}
10242   ]
10243  },
10244  "CP_ST_BASE_LO": {
10245   "fields": [
10246    {"bits": [2, 31], "name": "ST_BASE_LO"}
10247   ]
10248  },
10249  "CP_ST_BUFSZ": {
10250   "fields": [
10251    {"bits": [0, 19], "name": "ST_BUFSZ"}
10252   ]
10253  },
10254  "CP_VMID": {
10255   "fields": [
10256    {"bits": [0, 3], "name": "VMID"}
10257   ]
10258  },
10259  "CS_COPY_STATE": {
10260   "fields": [
10261    {"bits": [0, 2], "name": "SRC_STATE_ID"}
10262   ]
10263  },
10264  "DB_ALPHA_TO_MASK": {
10265   "fields": [
10266    {"bits": [0, 0], "name": "ALPHA_TO_MASK_ENABLE"},
10267    {"bits": [8, 9], "name": "ALPHA_TO_MASK_OFFSET0"},
10268    {"bits": [10, 11], "name": "ALPHA_TO_MASK_OFFSET1"},
10269    {"bits": [12, 13], "name": "ALPHA_TO_MASK_OFFSET2"},
10270    {"bits": [14, 15], "name": "ALPHA_TO_MASK_OFFSET3"},
10271    {"bits": [16, 16], "name": "OFFSET_ROUND"}
10272   ]
10273  },
10274  "DB_COUNT_CONTROL": {
10275   "fields": [
10276    {"bits": [0, 0], "name": "ZPASS_INCREMENT_DISABLE"},
10277    {"bits": [1, 1], "name": "PERFECT_ZPASS_COUNTS"},
10278    {"bits": [4, 6], "name": "SAMPLE_RATE"},
10279    {"bits": [8, 11], "name": "ZPASS_ENABLE"},
10280    {"bits": [12, 15], "name": "ZFAIL_ENABLE"},
10281    {"bits": [16, 19], "name": "SFAIL_ENABLE"},
10282    {"bits": [20, 23], "name": "DBFAIL_ENABLE"},
10283    {"bits": [24, 27], "name": "SLICE_EVEN_ENABLE"},
10284    {"bits": [28, 31], "name": "SLICE_ODD_ENABLE"}
10285   ]
10286  },
10287  "DB_DEPTH_CONTROL": {
10288   "fields": [
10289    {"bits": [0, 0], "name": "STENCIL_ENABLE"},
10290    {"bits": [1, 1], "name": "Z_ENABLE"},
10291    {"bits": [2, 2], "name": "Z_WRITE_ENABLE"},
10292    {"bits": [3, 3], "name": "DEPTH_BOUNDS_ENABLE"},
10293    {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"},
10294    {"bits": [7, 7], "name": "BACKFACE_ENABLE"},
10295    {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"},
10296    {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"},
10297    {"bits": [30, 30], "name": "ENABLE_COLOR_WRITES_ON_DEPTH_FAIL"},
10298    {"bits": [31, 31], "name": "DISABLE_COLOR_WRITES_ON_DEPTH_PASS"}
10299   ]
10300  },
10301  "DB_DEPTH_INFO": {
10302   "fields": [
10303    {"bits": [0, 3], "name": "ADDR5_SWIZZLE_MASK"},
10304    {"bits": [4, 7], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"},
10305    {"bits": [8, 12], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"},
10306    {"bits": [13, 14], "enum_ref": "BankWidth", "name": "BANK_WIDTH"},
10307    {"bits": [15, 16], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"},
10308    {"bits": [17, 18], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"},
10309    {"bits": [19, 20], "enum_ref": "NumBanks", "name": "NUM_BANKS"}
10310   ]
10311  },
10312  "DB_DEPTH_SIZE": {
10313   "fields": [
10314    {"bits": [0, 10], "name": "PITCH_TILE_MAX"},
10315    {"bits": [11, 21], "name": "HEIGHT_TILE_MAX"}
10316   ]
10317  },
10318  "DB_DEPTH_SLICE": {
10319   "fields": [
10320    {"bits": [0, 21], "name": "SLICE_TILE_MAX"}
10321   ]
10322  },
10323  "DB_DEPTH_VIEW": {
10324   "fields": [
10325    {"bits": [0, 10], "name": "SLICE_START"},
10326    {"bits": [13, 23], "name": "SLICE_MAX"},
10327    {"bits": [24, 24], "name": "Z_READ_ONLY"},
10328    {"bits": [25, 25], "name": "STENCIL_READ_ONLY"}
10329   ]
10330  },
10331  "DB_EQAA": {
10332   "fields": [
10333    {"bits": [0, 2], "name": "MAX_ANCHOR_SAMPLES"},
10334    {"bits": [4, 6], "name": "PS_ITER_SAMPLES"},
10335    {"bits": [8, 10], "name": "MASK_EXPORT_NUM_SAMPLES"},
10336    {"bits": [12, 14], "name": "ALPHA_TO_MASK_NUM_SAMPLES"},
10337    {"bits": [16, 16], "name": "HIGH_QUALITY_INTERSECTIONS"},
10338    {"bits": [17, 17], "name": "INCOHERENT_EQAA_READS"},
10339    {"bits": [18, 18], "name": "INTERPOLATE_COMP_Z"},
10340    {"bits": [19, 19], "name": "INTERPOLATE_SRC_Z"},
10341    {"bits": [20, 20], "name": "STATIC_ANCHOR_ASSOCIATIONS"},
10342    {"bits": [21, 21], "name": "ALPHA_TO_MASK_EQAA_DISABLE"},
10343    {"bits": [24, 26], "name": "OVERRASTERIZATION_AMOUNT"},
10344    {"bits": [27, 27], "name": "ENABLE_POSTZ_OVERRASTERIZATION"}
10345   ]
10346  },
10347  "DB_HTILE_SURFACE": {
10348   "fields": [
10349    {"bits": [0, 0], "name": "LINEAR"},
10350    {"bits": [1, 1], "name": "FULL_CACHE"},
10351    {"bits": [2, 2], "name": "HTILE_USES_PRELOAD_WIN"},
10352    {"bits": [3, 3], "name": "PRELOAD"},
10353    {"bits": [4, 9], "name": "PREFETCH_WIDTH"},
10354    {"bits": [10, 15], "name": "PREFETCH_HEIGHT"},
10355    {"bits": [16, 16], "name": "DST_OUTSIDE_ZERO_TO_ONE"},
10356    {"bits": [17, 17], "name": "TC_COMPATIBLE"}
10357   ]
10358  },
10359  "DB_PERFCOUNTER0_SELECT": {
10360   "fields": [
10361    {"bits": [0, 9], "name": "PERF_SEL"},
10362    {"bits": [10, 19], "name": "PERF_SEL1"},
10363    {"bits": [20, 23], "name": "CNTR_MODE"},
10364    {"bits": [24, 27], "name": "PERF_MODE1"},
10365    {"bits": [28, 31], "name": "PERF_MODE"}
10366   ]
10367  },
10368  "DB_PERFCOUNTER0_SELECT1": {
10369   "fields": [
10370    {"bits": [0, 9], "name": "PERF_SEL2"},
10371    {"bits": [10, 19], "name": "PERF_SEL3"},
10372    {"bits": [24, 27], "name": "PERF_MODE3"},
10373    {"bits": [28, 31], "name": "PERF_MODE2"}
10374   ]
10375  },
10376  "DB_PRELOAD_CONTROL": {
10377   "fields": [
10378    {"bits": [0, 7], "name": "START_X"},
10379    {"bits": [8, 15], "name": "START_Y"},
10380    {"bits": [16, 23], "name": "MAX_X"},
10381    {"bits": [24, 31], "name": "MAX_Y"}
10382   ]
10383  },
10384  "DB_RENDER_CONTROL": {
10385   "fields": [
10386    {"bits": [0, 0], "name": "DEPTH_CLEAR_ENABLE"},
10387    {"bits": [1, 1], "name": "STENCIL_CLEAR_ENABLE"},
10388    {"bits": [2, 2], "name": "DEPTH_COPY"},
10389    {"bits": [3, 3], "name": "STENCIL_COPY"},
10390    {"bits": [4, 4], "name": "RESUMMARIZE_ENABLE"},
10391    {"bits": [5, 5], "name": "STENCIL_COMPRESS_DISABLE"},
10392    {"bits": [6, 6], "name": "DEPTH_COMPRESS_DISABLE"},
10393    {"bits": [7, 7], "name": "COPY_CENTROID"},
10394    {"bits": [8, 11], "name": "COPY_SAMPLE"},
10395    {"bits": [12, 12], "name": "DECOMPRESS_ENABLE"}
10396   ]
10397  },
10398  "DB_RENDER_OVERRIDE": {
10399   "fields": [
10400    {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"},
10401    {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"},
10402    {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"},
10403    {"bits": [6, 6], "name": "FORCE_SHADER_Z_ORDER"},
10404    {"bits": [7, 7], "name": "FAST_Z_DISABLE"},
10405    {"bits": [8, 8], "name": "FAST_STENCIL_DISABLE"},
10406    {"bits": [9, 9], "name": "NOOP_CULL_DISABLE"},
10407    {"bits": [10, 10], "name": "FORCE_COLOR_KILL"},
10408    {"bits": [11, 11], "name": "FORCE_Z_READ"},
10409    {"bits": [12, 12], "name": "FORCE_STENCIL_READ"},
10410    {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"},
10411    {"bits": [15, 15], "name": "FORCE_QC_SMASK_CONFLICT"},
10412    {"bits": [16, 16], "name": "DISABLE_VIEWPORT_CLAMP"},
10413    {"bits": [17, 17], "name": "IGNORE_SC_ZRANGE"},
10414    {"bits": [18, 18], "name": "DISABLE_FULLY_COVERED"},
10415    {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"},
10416    {"bits": [21, 25], "name": "MAX_TILES_IN_DTT"},
10417    {"bits": [26, 26], "name": "DISABLE_TILE_RATE_TILES"},
10418    {"bits": [27, 27], "name": "FORCE_Z_DIRTY"},
10419    {"bits": [28, 28], "name": "FORCE_STENCIL_DIRTY"},
10420    {"bits": [29, 29], "name": "FORCE_Z_VALID"},
10421    {"bits": [30, 30], "name": "FORCE_STENCIL_VALID"},
10422    {"bits": [31, 31], "name": "PRESERVE_COMPRESSION"}
10423   ]
10424  },
10425  "DB_RENDER_OVERRIDE2": {
10426   "fields": [
10427    {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"},
10428    {"bits": [2, 4], "name": "PARTIAL_SQUAD_LAUNCH_COUNTDOWN"},
10429    {"bits": [5, 5], "name": "DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION"},
10430    {"bits": [6, 6], "name": "DISABLE_SMEM_EXPCLEAR_OPTIMIZATION"},
10431    {"bits": [7, 7], "name": "DISABLE_COLOR_ON_VALIDATION"},
10432    {"bits": [8, 8], "name": "DECOMPRESS_Z_ON_FLUSH"},
10433    {"bits": [9, 9], "name": "DISABLE_REG_SNOOP"},
10434    {"bits": [10, 10], "name": "DEPTH_BOUNDS_HIER_DEPTH_DISABLE"},
10435    {"bits": [11, 11], "name": "SEPARATE_HIZS_FUNC_ENABLE"},
10436    {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"},
10437    {"bits": [15, 17], "name": "HIS_SFUNC_FF"},
10438    {"bits": [18, 20], "name": "HIS_SFUNC_BF"},
10439    {"bits": [21, 21], "name": "PRESERVE_ZRANGE"},
10440    {"bits": [22, 22], "name": "PRESERVE_SRESULTS"},
10441    {"bits": [23, 23], "name": "DISABLE_FAST_PASS"}
10442   ]
10443  },
10444  "DB_SHADER_CONTROL": {
10445   "fields": [
10446    {"bits": [0, 0], "name": "Z_EXPORT_ENABLE"},
10447    {"bits": [1, 1], "name": "STENCIL_TEST_VAL_EXPORT_ENABLE"},
10448    {"bits": [2, 2], "name": "STENCIL_OP_VAL_EXPORT_ENABLE"},
10449    {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"},
10450    {"bits": [6, 6], "name": "KILL_ENABLE"},
10451    {"bits": [7, 7], "name": "COVERAGE_TO_MASK_ENABLE"},
10452    {"bits": [8, 8], "name": "MASK_EXPORT_ENABLE"},
10453    {"bits": [9, 9], "name": "EXEC_ON_HIER_FAIL"},
10454    {"bits": [10, 10], "name": "EXEC_ON_NOOP"},
10455    {"bits": [11, 11], "name": "ALPHA_TO_MASK_DISABLE"},
10456    {"bits": [12, 12], "name": "DEPTH_BEFORE_SHADER"},
10457    {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"},
10458    {"bits": [15, 15], "name": "DUAL_QUAD_DISABLE"}
10459   ]
10460  },
10461  "DB_SRESULTS_COMPARE_STATE0": {
10462   "fields": [
10463    {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"},
10464    {"bits": [4, 11], "name": "COMPAREVALUE0"},
10465    {"bits": [12, 19], "name": "COMPAREMASK0"},
10466    {"bits": [24, 24], "name": "ENABLE0"}
10467   ]
10468  },
10469  "DB_SRESULTS_COMPARE_STATE1": {
10470   "fields": [
10471    {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"},
10472    {"bits": [4, 11], "name": "COMPAREVALUE1"},
10473    {"bits": [12, 19], "name": "COMPAREMASK1"},
10474    {"bits": [24, 24], "name": "ENABLE1"}
10475   ]
10476  },
10477  "DB_STENCILREFMASK": {
10478   "fields": [
10479    {"bits": [0, 7], "name": "STENCILTESTVAL"},
10480    {"bits": [8, 15], "name": "STENCILMASK"},
10481    {"bits": [16, 23], "name": "STENCILWRITEMASK"},
10482    {"bits": [24, 31], "name": "STENCILOPVAL"}
10483   ]
10484  },
10485  "DB_STENCILREFMASK_BF": {
10486   "fields": [
10487    {"bits": [0, 7], "name": "STENCILTESTVAL_BF"},
10488    {"bits": [8, 15], "name": "STENCILMASK_BF"},
10489    {"bits": [16, 23], "name": "STENCILWRITEMASK_BF"},
10490    {"bits": [24, 31], "name": "STENCILOPVAL_BF"}
10491   ]
10492  },
10493  "DB_STENCIL_CLEAR": {
10494   "fields": [
10495    {"bits": [0, 7], "name": "CLEAR"}
10496   ]
10497  },
10498  "DB_STENCIL_CONTROL": {
10499   "fields": [
10500    {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"},
10501    {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"},
10502    {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"},
10503    {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"},
10504    {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"},
10505    {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"}
10506   ]
10507  },
10508  "DB_STENCIL_INFO": {
10509   "fields": [
10510    {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"},
10511    {"bits": [13, 15], "enum_ref": "TileSplit", "name": "TILE_SPLIT"},
10512    {"bits": [20, 22], "name": "TILE_MODE_INDEX"},
10513    {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"},
10514    {"bits": [29, 29], "name": "TILE_STENCIL_DISABLE"},
10515    {"bits": [30, 30], "name": "CLEAR_DISALLOWED"}
10516   ]
10517  },
10518  "DB_ZPASS_COUNT_HI": {
10519   "fields": [
10520    {"bits": [0, 30], "name": "COUNT_HI"}
10521   ]
10522  },
10523  "DB_Z_INFO": {
10524   "fields": [
10525    {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"},
10526    {"bits": [2, 3], "name": "NUM_SAMPLES"},
10527    {"bits": [13, 15], "enum_ref": "TileSplit", "name": "TILE_SPLIT"},
10528    {"bits": [20, 22], "name": "TILE_MODE_INDEX"},
10529    {"bits": [23, 26], "name": "DECOMPRESS_ON_N_ZPLANES"},
10530    {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"},
10531    {"bits": [28, 28], "name": "READ_SIZE"},
10532    {"bits": [29, 29], "name": "TILE_SURFACE_ENABLE"},
10533    {"bits": [30, 30], "name": "CLEAR_DISALLOWED"},
10534    {"bits": [31, 31], "name": "ZRANGE_PRECISION"}
10535   ]
10536  },
10537  "GB_ADDR_CONFIG": {
10538   "fields": [
10539    {"bits": [0, 2], "name": "NUM_PIPES"},
10540    {"bits": [4, 6], "name": "PIPE_INTERLEAVE_SIZE"},
10541    {"bits": [8, 10], "name": "BANK_INTERLEAVE_SIZE"},
10542    {"bits": [12, 13], "name": "NUM_SHADER_ENGINES"},
10543    {"bits": [16, 18], "name": "SHADER_ENGINE_TILE_SIZE"},
10544    {"bits": [20, 22], "name": "NUM_GPUS"},
10545    {"bits": [24, 25], "name": "MULTI_GPU_TILE_SIZE"},
10546    {"bits": [28, 29], "name": "ROW_SIZE"},
10547    {"bits": [30, 30], "name": "NUM_LOWER_PIPES"}
10548   ]
10549  },
10550  "GB_MACROTILE_MODE0": {
10551   "fields": [
10552    {"bits": [0, 1], "enum_ref": "BankWidth", "name": "BANK_WIDTH"},
10553    {"bits": [2, 3], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"},
10554    {"bits": [4, 5], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"},
10555    {"bits": [6, 7], "enum_ref": "NumBanks", "name": "NUM_BANKS"}
10556   ]
10557  },
10558  "GB_TILE_MODE0": {
10559   "fields": [
10560    {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"},
10561    {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"},
10562    {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"},
10563    {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"},
10564    {"bits": [25, 26], "name": "SAMPLE_SPLIT"}
10565   ]
10566  },
10567  "GDS_ATOM_BASE": {
10568   "fields": [
10569    {"bits": [0, 15], "name": "BASE"},
10570    {"bits": [16, 31], "name": "UNUSED"}
10571   ]
10572  },
10573  "GDS_ATOM_CNTL": {
10574   "fields": [
10575    {"bits": [0, 5], "name": "AINC"},
10576    {"bits": [6, 7], "name": "UNUSED1"},
10577    {"bits": [8, 9], "name": "DMODE"},
10578    {"bits": [10, 31], "name": "UNUSED2"}
10579   ]
10580  },
10581  "GDS_ATOM_COMPLETE": {
10582   "fields": [
10583    {"bits": [0, 0], "name": "COMPLETE"},
10584    {"bits": [1, 31], "name": "UNUSED"}
10585   ]
10586  },
10587  "GDS_ATOM_OFFSET0": {
10588   "fields": [
10589    {"bits": [0, 7], "name": "OFFSET0"},
10590    {"bits": [8, 31], "name": "UNUSED"}
10591   ]
10592  },
10593  "GDS_ATOM_OFFSET1": {
10594   "fields": [
10595    {"bits": [0, 7], "name": "OFFSET1"},
10596    {"bits": [8, 31], "name": "UNUSED"}
10597   ]
10598  },
10599  "GDS_ATOM_OP": {
10600   "fields": [
10601    {"bits": [0, 7], "name": "OP"},
10602    {"bits": [8, 31], "name": "UNUSED"}
10603   ]
10604  },
10605  "GDS_ATOM_SIZE": {
10606   "fields": [
10607    {"bits": [0, 15], "name": "SIZE"},
10608    {"bits": [16, 31], "name": "UNUSED"}
10609   ]
10610  },
10611  "GDS_GWS_RESOURCE": {
10612   "fields": [
10613    {"bits": [0, 0], "name": "FLAG"},
10614    {"bits": [1, 12], "name": "COUNTER"},
10615    {"bits": [13, 13], "name": "TYPE"},
10616    {"bits": [14, 14], "name": "DED"},
10617    {"bits": [15, 15], "name": "RELEASE_ALL"},
10618    {"bits": [16, 27], "name": "HEAD_QUEUE"},
10619    {"bits": [28, 28], "name": "HEAD_VALID"},
10620    {"bits": [29, 29], "name": "HEAD_FLAG"},
10621    {"bits": [30, 31], "name": "UNUSED1"}
10622   ]
10623  },
10624  "GDS_GWS_RESOURCE_CNT": {
10625   "fields": [
10626    {"bits": [0, 15], "name": "RESOURCE_CNT"},
10627    {"bits": [16, 31], "name": "UNUSED"}
10628   ]
10629  },
10630  "GDS_GWS_RESOURCE_CNTL": {
10631   "fields": [
10632    {"bits": [0, 5], "name": "INDEX"},
10633    {"bits": [6, 31], "name": "UNUSED"}
10634   ]
10635  },
10636  "GDS_OA_ADDRESS": {
10637   "fields": [
10638    {"bits": [0, 15], "name": "DS_ADDRESS"},
10639    {"bits": [16, 19], "name": "CRAWLER"},
10640    {"bits": [20, 21], "name": "CRAWLER_TYPE"},
10641    {"bits": [22, 29], "name": "UNUSED"},
10642    {"bits": [30, 30], "name": "NO_ALLOC"},
10643    {"bits": [31, 31], "name": "ENABLE"}
10644   ]
10645  },
10646  "GDS_OA_CNTL": {
10647   "fields": [
10648    {"bits": [0, 3], "name": "INDEX"},
10649    {"bits": [4, 31], "name": "UNUSED"}
10650   ]
10651  },
10652  "GDS_OA_INCDEC": {
10653   "fields": [
10654    {"bits": [0, 30], "name": "VALUE"},
10655    {"bits": [31, 31], "name": "INCDEC"}
10656   ]
10657  },
10658  "GRBM_GFX_INDEX": {
10659   "fields": [
10660    {"bits": [0, 7], "name": "INSTANCE_INDEX"},
10661    {"bits": [8, 15], "name": "SH_INDEX"},
10662    {"bits": [16, 23], "name": "SE_INDEX"},
10663    {"bits": [29, 29], "name": "SH_BROADCAST_WRITES"},
10664    {"bits": [30, 30], "name": "INSTANCE_BROADCAST_WRITES"},
10665    {"bits": [31, 31], "name": "SE_BROADCAST_WRITES"}
10666   ]
10667  },
10668  "GRBM_PERFCOUNTER0_SELECT": {
10669   "fields": [
10670    {"bits": [0, 5], "name": "PERF_SEL"},
10671    {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"},
10672    {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"},
10673    {"bits": [12, 12], "name": "VGT_BUSY_USER_DEFINED_MASK"},
10674    {"bits": [13, 13], "name": "TA_BUSY_USER_DEFINED_MASK"},
10675    {"bits": [14, 14], "name": "SX_BUSY_USER_DEFINED_MASK"},
10676    {"bits": [16, 16], "name": "SPI_BUSY_USER_DEFINED_MASK"},
10677    {"bits": [17, 17], "name": "SC_BUSY_USER_DEFINED_MASK"},
10678    {"bits": [18, 18], "name": "PA_BUSY_USER_DEFINED_MASK"},
10679    {"bits": [19, 19], "name": "GRBM_BUSY_USER_DEFINED_MASK"},
10680    {"bits": [20, 20], "name": "DB_BUSY_USER_DEFINED_MASK"},
10681    {"bits": [21, 21], "name": "CB_BUSY_USER_DEFINED_MASK"},
10682    {"bits": [22, 22], "name": "CP_BUSY_USER_DEFINED_MASK"},
10683    {"bits": [23, 23], "name": "IA_BUSY_USER_DEFINED_MASK"},
10684    {"bits": [24, 24], "name": "GDS_BUSY_USER_DEFINED_MASK"},
10685    {"bits": [25, 25], "name": "BCI_BUSY_USER_DEFINED_MASK"},
10686    {"bits": [26, 26], "name": "RLC_BUSY_USER_DEFINED_MASK"},
10687    {"bits": [27, 27], "name": "TC_BUSY_USER_DEFINED_MASK"},
10688    {"bits": [28, 28], "name": "WD_BUSY_USER_DEFINED_MASK"}
10689   ]
10690  },
10691  "GRBM_SE0_PERFCOUNTER_SELECT": {
10692   "fields": [
10693    {"bits": [0, 5], "name": "PERF_SEL"},
10694    {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"},
10695    {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"},
10696    {"bits": [12, 12], "name": "TA_BUSY_USER_DEFINED_MASK"},
10697    {"bits": [13, 13], "name": "SX_BUSY_USER_DEFINED_MASK"},
10698    {"bits": [15, 15], "name": "SPI_BUSY_USER_DEFINED_MASK"},
10699    {"bits": [16, 16], "name": "SC_BUSY_USER_DEFINED_MASK"},
10700    {"bits": [17, 17], "name": "DB_BUSY_USER_DEFINED_MASK"},
10701    {"bits": [18, 18], "name": "CB_BUSY_USER_DEFINED_MASK"},
10702    {"bits": [19, 19], "name": "VGT_BUSY_USER_DEFINED_MASK"},
10703    {"bits": [20, 20], "name": "PA_BUSY_USER_DEFINED_MASK"},
10704    {"bits": [21, 21], "name": "BCI_BUSY_USER_DEFINED_MASK"}
10705   ]
10706  },
10707  "GRBM_STATUS": {
10708   "fields": [
10709    {"bits": [0, 3], "name": "ME0PIPE0_CMDFIFO_AVAIL"},
10710    {"bits": [5, 5], "name": "SRBM_RQ_PENDING"},
10711    {"bits": [7, 7], "name": "ME0PIPE0_CF_RQ_PENDING"},
10712    {"bits": [8, 8], "name": "ME0PIPE0_PF_RQ_PENDING"},
10713    {"bits": [9, 9], "name": "GDS_DMA_RQ_PENDING"},
10714    {"bits": [12, 12], "name": "DB_CLEAN"},
10715    {"bits": [13, 13], "name": "CB_CLEAN"},
10716    {"bits": [14, 14], "name": "TA_BUSY"},
10717    {"bits": [15, 15], "name": "GDS_BUSY"},
10718    {"bits": [16, 16], "name": "WD_BUSY_NO_DMA"},
10719    {"bits": [17, 17], "name": "VGT_BUSY"},
10720    {"bits": [18, 18], "name": "IA_BUSY_NO_DMA"},
10721    {"bits": [19, 19], "name": "IA_BUSY"},
10722    {"bits": [20, 20], "name": "SX_BUSY"},
10723    {"bits": [21, 21], "name": "WD_BUSY"},
10724    {"bits": [22, 22], "name": "SPI_BUSY"},
10725    {"bits": [23, 23], "name": "BCI_BUSY"},
10726    {"bits": [24, 24], "name": "SC_BUSY"},
10727    {"bits": [25, 25], "name": "PA_BUSY"},
10728    {"bits": [26, 26], "name": "DB_BUSY"},
10729    {"bits": [28, 28], "name": "CP_COHERENCY_BUSY"},
10730    {"bits": [29, 29], "name": "CP_BUSY"},
10731    {"bits": [30, 30], "name": "CB_BUSY"},
10732    {"bits": [31, 31], "name": "GUI_ACTIVE"}
10733   ]
10734  },
10735  "GRBM_STATUS2": {
10736   "fields": [
10737    {"bits": [0, 3], "name": "ME0PIPE1_CMDFIFO_AVAIL"},
10738    {"bits": [4, 4], "name": "ME0PIPE1_CF_RQ_PENDING"},
10739    {"bits": [5, 5], "name": "ME0PIPE1_PF_RQ_PENDING"},
10740    {"bits": [6, 6], "name": "ME1PIPE0_RQ_PENDING"},
10741    {"bits": [7, 7], "name": "ME1PIPE1_RQ_PENDING"},
10742    {"bits": [8, 8], "name": "ME1PIPE2_RQ_PENDING"},
10743    {"bits": [9, 9], "name": "ME1PIPE3_RQ_PENDING"},
10744    {"bits": [10, 10], "name": "ME2PIPE0_RQ_PENDING"},
10745    {"bits": [11, 11], "name": "ME2PIPE1_RQ_PENDING"},
10746    {"bits": [12, 12], "name": "ME2PIPE2_RQ_PENDING"},
10747    {"bits": [13, 13], "name": "ME2PIPE3_RQ_PENDING"},
10748    {"bits": [14, 14], "name": "RLC_RQ_PENDING"},
10749    {"bits": [24, 24], "name": "RLC_BUSY"},
10750    {"bits": [25, 25], "name": "TC_BUSY"},
10751    {"bits": [26, 26], "name": "TCC_CC_RESIDENT"},
10752    {"bits": [28, 28], "name": "CPF_BUSY"},
10753    {"bits": [29, 29], "name": "CPC_BUSY"},
10754    {"bits": [30, 30], "name": "CPG_BUSY"}
10755   ]
10756  },
10757  "GRBM_STATUS_SE0": {
10758   "fields": [
10759    {"bits": [1, 1], "name": "DB_CLEAN"},
10760    {"bits": [2, 2], "name": "CB_CLEAN"},
10761    {"bits": [22, 22], "name": "BCI_BUSY"},
10762    {"bits": [23, 23], "name": "VGT_BUSY"},
10763    {"bits": [24, 24], "name": "PA_BUSY"},
10764    {"bits": [25, 25], "name": "TA_BUSY"},
10765    {"bits": [26, 26], "name": "SX_BUSY"},
10766    {"bits": [27, 27], "name": "SPI_BUSY"},
10767    {"bits": [29, 29], "name": "SC_BUSY"},
10768    {"bits": [30, 30], "name": "DB_BUSY"},
10769    {"bits": [31, 31], "name": "CB_BUSY"}
10770   ]
10771  },
10772  "IA_MULTI_VGT_PARAM": {
10773   "fields": [
10774    {"bits": [0, 15], "name": "PRIMGROUP_SIZE"},
10775    {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"},
10776    {"bits": [17, 17], "name": "SWITCH_ON_EOP"},
10777    {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"},
10778    {"bits": [19, 19], "name": "SWITCH_ON_EOI"},
10779    {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"},
10780    {"bits": [28, 31], "name": "MAX_PRIMGRP_IN_WAVE"}
10781   ]
10782  },
10783  "PA_CL_CLIP_CNTL": {
10784   "fields": [
10785    {"bits": [0, 0], "name": "UCP_ENA_0"},
10786    {"bits": [1, 1], "name": "UCP_ENA_1"},
10787    {"bits": [2, 2], "name": "UCP_ENA_2"},
10788    {"bits": [3, 3], "name": "UCP_ENA_3"},
10789    {"bits": [4, 4], "name": "UCP_ENA_4"},
10790    {"bits": [5, 5], "name": "UCP_ENA_5"},
10791    {"bits": [13, 13], "name": "PS_UCP_Y_SCALE_NEG"},
10792    {"bits": [14, 15], "name": "PS_UCP_MODE"},
10793    {"bits": [16, 16], "name": "CLIP_DISABLE"},
10794    {"bits": [17, 17], "name": "UCP_CULL_ONLY_ENA"},
10795    {"bits": [18, 18], "name": "BOUNDARY_EDGE_FLAG_ENA"},
10796    {"bits": [19, 19], "name": "DX_CLIP_SPACE_DEF"},
10797    {"bits": [20, 20], "name": "DIS_CLIP_ERR_DETECT"},
10798    {"bits": [21, 21], "name": "VTX_KILL_OR"},
10799    {"bits": [22, 22], "name": "DX_RASTERIZATION_KILL"},
10800    {"bits": [24, 24], "name": "DX_LINEAR_ATTR_CLIP_ENA"},
10801    {"bits": [25, 25], "name": "VTE_VPORT_PROVOKE_DISABLE"},
10802    {"bits": [26, 26], "name": "ZCLIP_NEAR_DISABLE"},
10803    {"bits": [27, 27], "name": "ZCLIP_FAR_DISABLE"}
10804   ]
10805  },
10806  "PA_CL_NANINF_CNTL": {
10807   "fields": [
10808    {"bits": [0, 0], "name": "VTE_XY_INF_DISCARD"},
10809    {"bits": [1, 1], "name": "VTE_Z_INF_DISCARD"},
10810    {"bits": [2, 2], "name": "VTE_W_INF_DISCARD"},
10811    {"bits": [3, 3], "name": "VTE_0XNANINF_IS_0"},
10812    {"bits": [4, 4], "name": "VTE_XY_NAN_RETAIN"},
10813    {"bits": [5, 5], "name": "VTE_Z_NAN_RETAIN"},
10814    {"bits": [6, 6], "name": "VTE_W_NAN_RETAIN"},
10815    {"bits": [7, 7], "name": "VTE_W_RECIP_NAN_IS_0"},
10816    {"bits": [8, 8], "name": "VS_XY_NAN_TO_INF"},
10817    {"bits": [9, 9], "name": "VS_XY_INF_RETAIN"},
10818    {"bits": [10, 10], "name": "VS_Z_NAN_TO_INF"},
10819    {"bits": [11, 11], "name": "VS_Z_INF_RETAIN"},
10820    {"bits": [12, 12], "name": "VS_W_NAN_TO_INF"},
10821    {"bits": [13, 13], "name": "VS_W_INF_RETAIN"},
10822    {"bits": [14, 14], "name": "VS_CLIP_DIST_INF_DISCARD"},
10823    {"bits": [20, 20], "name": "VTE_NO_OUTPUT_NEG_0"}
10824   ]
10825  },
10826  "PA_CL_VS_OUT_CNTL": {
10827   "fields": [
10828    {"bits": [0, 0], "name": "CLIP_DIST_ENA_0"},
10829    {"bits": [1, 1], "name": "CLIP_DIST_ENA_1"},
10830    {"bits": [2, 2], "name": "CLIP_DIST_ENA_2"},
10831    {"bits": [3, 3], "name": "CLIP_DIST_ENA_3"},
10832    {"bits": [4, 4], "name": "CLIP_DIST_ENA_4"},
10833    {"bits": [5, 5], "name": "CLIP_DIST_ENA_5"},
10834    {"bits": [6, 6], "name": "CLIP_DIST_ENA_6"},
10835    {"bits": [7, 7], "name": "CLIP_DIST_ENA_7"},
10836    {"bits": [8, 8], "name": "CULL_DIST_ENA_0"},
10837    {"bits": [9, 9], "name": "CULL_DIST_ENA_1"},
10838    {"bits": [10, 10], "name": "CULL_DIST_ENA_2"},
10839    {"bits": [11, 11], "name": "CULL_DIST_ENA_3"},
10840    {"bits": [12, 12], "name": "CULL_DIST_ENA_4"},
10841    {"bits": [13, 13], "name": "CULL_DIST_ENA_5"},
10842    {"bits": [14, 14], "name": "CULL_DIST_ENA_6"},
10843    {"bits": [15, 15], "name": "CULL_DIST_ENA_7"},
10844    {"bits": [16, 16], "name": "USE_VTX_POINT_SIZE"},
10845    {"bits": [17, 17], "name": "USE_VTX_EDGE_FLAG"},
10846    {"bits": [18, 18], "name": "USE_VTX_RENDER_TARGET_INDX"},
10847    {"bits": [19, 19], "name": "USE_VTX_VIEWPORT_INDX"},
10848    {"bits": [20, 20], "name": "USE_VTX_KILL_FLAG"},
10849    {"bits": [21, 21], "name": "VS_OUT_MISC_VEC_ENA"},
10850    {"bits": [22, 22], "name": "VS_OUT_CCDIST0_VEC_ENA"},
10851    {"bits": [23, 23], "name": "VS_OUT_CCDIST1_VEC_ENA"},
10852    {"bits": [24, 24], "name": "VS_OUT_MISC_SIDE_BUS_ENA"},
10853    {"bits": [25, 25], "name": "USE_VTX_GS_CUT_FLAG"},
10854    {"bits": [26, 26], "name": "USE_VTX_LINE_WIDTH"}
10855   ]
10856  },
10857  "PA_CL_VTE_CNTL": {
10858   "fields": [
10859    {"bits": [0, 0], "name": "VPORT_X_SCALE_ENA"},
10860    {"bits": [1, 1], "name": "VPORT_X_OFFSET_ENA"},
10861    {"bits": [2, 2], "name": "VPORT_Y_SCALE_ENA"},
10862    {"bits": [3, 3], "name": "VPORT_Y_OFFSET_ENA"},
10863    {"bits": [4, 4], "name": "VPORT_Z_SCALE_ENA"},
10864    {"bits": [5, 5], "name": "VPORT_Z_OFFSET_ENA"},
10865    {"bits": [8, 8], "name": "VTX_XY_FMT"},
10866    {"bits": [9, 9], "name": "VTX_Z_FMT"},
10867    {"bits": [10, 10], "name": "VTX_W0_FMT"},
10868    {"bits": [11, 11], "name": "PERFCOUNTER_REF"}
10869   ]
10870  },
10871  "PA_SC_AA_CONFIG": {
10872   "fields": [
10873    {"bits": [0, 2], "name": "MSAA_NUM_SAMPLES"},
10874    {"bits": [4, 4], "name": "AA_MASK_CENTROID_DTMN"},
10875    {"bits": [13, 16], "name": "MAX_SAMPLE_DIST"},
10876    {"bits": [20, 22], "name": "MSAA_EXPOSED_SAMPLES"},
10877    {"bits": [24, 25], "name": "DETAIL_TO_EXPOSED_MODE"}
10878   ]
10879  },
10880  "PA_SC_AA_MASK_X0Y0_X1Y0": {
10881   "fields": [
10882    {"bits": [0, 15], "name": "AA_MASK_X0Y0"},
10883    {"bits": [16, 31], "name": "AA_MASK_X1Y0"}
10884   ]
10885  },
10886  "PA_SC_AA_MASK_X0Y1_X1Y1": {
10887   "fields": [
10888    {"bits": [0, 15], "name": "AA_MASK_X0Y1"},
10889    {"bits": [16, 31], "name": "AA_MASK_X1Y1"}
10890   ]
10891  },
10892  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0": {
10893   "fields": [
10894    {"bits": [0, 3], "name": "S0_X"},
10895    {"bits": [4, 7], "name": "S0_Y"},
10896    {"bits": [8, 11], "name": "S1_X"},
10897    {"bits": [12, 15], "name": "S1_Y"},
10898    {"bits": [16, 19], "name": "S2_X"},
10899    {"bits": [20, 23], "name": "S2_Y"},
10900    {"bits": [24, 27], "name": "S3_X"},
10901    {"bits": [28, 31], "name": "S3_Y"}
10902   ]
10903  },
10904  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1": {
10905   "fields": [
10906    {"bits": [0, 3], "name": "S4_X"},
10907    {"bits": [4, 7], "name": "S4_Y"},
10908    {"bits": [8, 11], "name": "S5_X"},
10909    {"bits": [12, 15], "name": "S5_Y"},
10910    {"bits": [16, 19], "name": "S6_X"},
10911    {"bits": [20, 23], "name": "S6_Y"},
10912    {"bits": [24, 27], "name": "S7_X"},
10913    {"bits": [28, 31], "name": "S7_Y"}
10914   ]
10915  },
10916  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2": {
10917   "fields": [
10918    {"bits": [0, 3], "name": "S8_X"},
10919    {"bits": [4, 7], "name": "S8_Y"},
10920    {"bits": [8, 11], "name": "S9_X"},
10921    {"bits": [12, 15], "name": "S9_Y"},
10922    {"bits": [16, 19], "name": "S10_X"},
10923    {"bits": [20, 23], "name": "S10_Y"},
10924    {"bits": [24, 27], "name": "S11_X"},
10925    {"bits": [28, 31], "name": "S11_Y"}
10926   ]
10927  },
10928  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3": {
10929   "fields": [
10930    {"bits": [0, 3], "name": "S12_X"},
10931    {"bits": [4, 7], "name": "S12_Y"},
10932    {"bits": [8, 11], "name": "S13_X"},
10933    {"bits": [12, 15], "name": "S13_Y"},
10934    {"bits": [16, 19], "name": "S14_X"},
10935    {"bits": [20, 23], "name": "S14_Y"},
10936    {"bits": [24, 27], "name": "S15_X"},
10937    {"bits": [28, 31], "name": "S15_Y"}
10938   ]
10939  },
10940  "PA_SC_CENTROID_PRIORITY_0": {
10941   "fields": [
10942    {"bits": [0, 3], "name": "DISTANCE_0"},
10943    {"bits": [4, 7], "name": "DISTANCE_1"},
10944    {"bits": [8, 11], "name": "DISTANCE_2"},
10945    {"bits": [12, 15], "name": "DISTANCE_3"},
10946    {"bits": [16, 19], "name": "DISTANCE_4"},
10947    {"bits": [20, 23], "name": "DISTANCE_5"},
10948    {"bits": [24, 27], "name": "DISTANCE_6"},
10949    {"bits": [28, 31], "name": "DISTANCE_7"}
10950   ]
10951  },
10952  "PA_SC_CENTROID_PRIORITY_1": {
10953   "fields": [
10954    {"bits": [0, 3], "name": "DISTANCE_8"},
10955    {"bits": [4, 7], "name": "DISTANCE_9"},
10956    {"bits": [8, 11], "name": "DISTANCE_10"},
10957    {"bits": [12, 15], "name": "DISTANCE_11"},
10958    {"bits": [16, 19], "name": "DISTANCE_12"},
10959    {"bits": [20, 23], "name": "DISTANCE_13"},
10960    {"bits": [24, 27], "name": "DISTANCE_14"},
10961    {"bits": [28, 31], "name": "DISTANCE_15"}
10962   ]
10963  },
10964  "PA_SC_CLIPRECT_0_BR": {
10965   "fields": [
10966    {"bits": [0, 14], "name": "BR_X"},
10967    {"bits": [16, 30], "name": "BR_Y"}
10968   ]
10969  },
10970  "PA_SC_CLIPRECT_0_TL": {
10971   "fields": [
10972    {"bits": [0, 14], "name": "TL_X"},
10973    {"bits": [16, 30], "name": "TL_Y"}
10974   ]
10975  },
10976  "PA_SC_CLIPRECT_RULE": {
10977   "fields": [
10978    {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"}
10979   ]
10980  },
10981  "PA_SC_EDGERULE": {
10982   "fields": [
10983    {"bits": [0, 3], "name": "ER_TRI"},
10984    {"bits": [4, 7], "name": "ER_POINT"},
10985    {"bits": [8, 11], "name": "ER_RECT"},
10986    {"bits": [12, 17], "name": "ER_LINE_LR"},
10987    {"bits": [18, 23], "name": "ER_LINE_RL"},
10988    {"bits": [24, 27], "name": "ER_LINE_TB"},
10989    {"bits": [28, 31], "name": "ER_LINE_BT"}
10990   ]
10991  },
10992  "PA_SC_GENERIC_SCISSOR_TL": {
10993   "fields": [
10994    {"bits": [0, 14], "name": "TL_X"},
10995    {"bits": [16, 30], "name": "TL_Y"},
10996    {"bits": [31, 31], "name": "WINDOW_OFFSET_DISABLE"}
10997   ]
10998  },
10999  "PA_SC_LINE_CNTL": {
11000   "fields": [
11001    {"bits": [9, 9], "name": "EXPAND_LINE_WIDTH"},
11002    {"bits": [10, 10], "name": "LAST_PIXEL"},
11003    {"bits": [11, 11], "name": "PERPENDICULAR_ENDCAP_ENA"},
11004    {"bits": [12, 12], "name": "DX10_DIAMOND_TEST_ENA"}
11005   ]
11006  },
11007  "PA_SC_LINE_STIPPLE": {
11008   "fields": [
11009    {"bits": [0, 15], "name": "LINE_PATTERN"},
11010    {"bits": [16, 23], "name": "REPEAT_COUNT"},
11011    {"bits": [28, 28], "name": "PATTERN_BIT_ORDER"},
11012    {"bits": [29, 30], "name": "AUTO_RESET_CNTL"}
11013   ]
11014  },
11015  "PA_SC_LINE_STIPPLE_STATE": {
11016   "fields": [
11017    {"bits": [0, 3], "name": "CURRENT_PTR"},
11018    {"bits": [8, 15], "name": "CURRENT_COUNT"}
11019   ]
11020  },
11021  "PA_SC_MODE_CNTL_0": {
11022   "fields": [
11023    {"bits": [0, 0], "name": "MSAA_ENABLE"},
11024    {"bits": [1, 1], "name": "VPORT_SCISSOR_ENABLE"},
11025    {"bits": [2, 2], "name": "LINE_STIPPLE_ENABLE"},
11026    {"bits": [3, 3], "name": "SEND_UNLIT_STILES_TO_PKR"}
11027   ]
11028  },
11029  "PA_SC_MODE_CNTL_1": {
11030   "fields": [
11031    {"bits": [0, 0], "name": "WALK_SIZE"},
11032    {"bits": [1, 1], "name": "WALK_ALIGNMENT"},
11033    {"bits": [2, 2], "name": "WALK_ALIGN8_PRIM_FITS_ST"},
11034    {"bits": [3, 3], "name": "WALK_FENCE_ENABLE"},
11035    {"bits": [4, 6], "name": "WALK_FENCE_SIZE"},
11036    {"bits": [7, 7], "name": "SUPERTILE_WALK_ORDER_ENABLE"},
11037    {"bits": [8, 8], "name": "TILE_WALK_ORDER_ENABLE"},
11038    {"bits": [9, 9], "name": "TILE_COVER_DISABLE"},
11039    {"bits": [10, 10], "name": "TILE_COVER_NO_SCISSOR"},
11040    {"bits": [11, 11], "name": "ZMM_LINE_EXTENT"},
11041    {"bits": [12, 12], "name": "ZMM_LINE_OFFSET"},
11042    {"bits": [13, 13], "name": "ZMM_RECT_EXTENT"},
11043    {"bits": [14, 14], "name": "KILL_PIX_POST_HI_Z"},
11044    {"bits": [15, 15], "name": "KILL_PIX_POST_DETAIL_MASK"},
11045    {"bits": [16, 16], "name": "PS_ITER_SAMPLE"},
11046    {"bits": [17, 17], "name": "MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE"},
11047    {"bits": [18, 18], "name": "MULTI_GPU_SUPERTILE_ENABLE"},
11048    {"bits": [19, 19], "name": "GPU_ID_OVERRIDE_ENABLE"},
11049    {"bits": [20, 23], "name": "GPU_ID_OVERRIDE"},
11050    {"bits": [24, 24], "name": "MULTI_GPU_PRIM_DISCARD_ENABLE"},
11051    {"bits": [25, 25], "name": "FORCE_EOV_CNTDWN_ENABLE"},
11052    {"bits": [26, 26], "name": "FORCE_EOV_REZ_ENABLE"},
11053    {"bits": [27, 27], "name": "OUT_OF_ORDER_PRIMITIVE_ENABLE"},
11054    {"bits": [28, 30], "name": "OUT_OF_ORDER_WATER_MARK"}
11055   ]
11056  },
11057  "PA_SC_P3D_TRAP_SCREEN_H": {
11058   "fields": [
11059    {"bits": [0, 13], "name": "X_COORD"}
11060   ]
11061  },
11062  "PA_SC_P3D_TRAP_SCREEN_HV_EN": {
11063   "fields": [
11064    {"bits": [0, 0], "name": "ENABLE_HV_PRE_SHADER"},
11065    {"bits": [1, 1], "name": "FORCE_PRE_SHADER_ALL_PIXELS"}
11066   ]
11067  },
11068  "PA_SC_P3D_TRAP_SCREEN_V": {
11069   "fields": [
11070    {"bits": [0, 13], "name": "Y_COORD"}
11071   ]
11072  },
11073  "PA_SC_PERFCOUNTER1_SELECT": {
11074   "fields": [
11075    {"bits": [0, 9], "name": "PERF_SEL"}
11076   ]
11077  },
11078  "PA_SC_RASTER_CONFIG": {
11079   "fields": [
11080    {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"},
11081    {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"},
11082    {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"},
11083    {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"},
11084    {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"},
11085    {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"},
11086    {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"},
11087    {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"},
11088    {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"},
11089    {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"},
11090    {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"},
11091    {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"},
11092    {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"},
11093    {"bits": [26, 27], "enum_ref": "SeXsel", "name": "SE_XSEL"},
11094    {"bits": [28, 29], "enum_ref": "SeYsel", "name": "SE_YSEL"}
11095   ]
11096  },
11097  "PA_SC_RASTER_CONFIG_1": {
11098   "fields": [
11099    {"bits": [0, 1], "enum_ref": "SePairMap", "name": "SE_PAIR_MAP"},
11100    {"bits": [2, 3], "enum_ref": "SePairXsel", "name": "SE_PAIR_XSEL"},
11101    {"bits": [4, 5], "enum_ref": "SePairYsel", "name": "SE_PAIR_YSEL"}
11102   ]
11103  },
11104  "PA_SC_SCREEN_EXTENT_CONTROL": {
11105   "fields": [
11106    {"bits": [0, 1], "name": "SLICE_EVEN_ENABLE"},
11107    {"bits": [2, 3], "name": "SLICE_ODD_ENABLE"}
11108   ]
11109  },
11110  "PA_SC_SCREEN_EXTENT_MIN_0": {
11111   "fields": [
11112    {"bits": [0, 15], "name": "X"},
11113    {"bits": [16, 31], "name": "Y"}
11114   ]
11115  },
11116  "PA_SC_SCREEN_SCISSOR_BR": {
11117   "fields": [
11118    {"bits": [0, 15], "name": "BR_X"},
11119    {"bits": [16, 31], "name": "BR_Y"}
11120   ]
11121  },
11122  "PA_SC_SCREEN_SCISSOR_TL": {
11123   "fields": [
11124    {"bits": [0, 15], "name": "TL_X"},
11125    {"bits": [16, 31], "name": "TL_Y"}
11126   ]
11127  },
11128  "PA_SC_SHADER_CONTROL": {
11129   "fields": [
11130    {"bits": [0, 1], "name": "REALIGN_DQUADS_AFTER_N_WAVES"}
11131   ]
11132  },
11133  "PA_SC_WINDOW_OFFSET": {
11134   "fields": [
11135    {"bits": [0, 15], "name": "WINDOW_X_OFFSET"},
11136    {"bits": [16, 31], "name": "WINDOW_Y_OFFSET"}
11137   ]
11138  },
11139  "PA_SU_HARDWARE_SCREEN_OFFSET": {
11140   "fields": [
11141    {"bits": [0, 8], "name": "HW_SCREEN_OFFSET_X"},
11142    {"bits": [16, 24], "name": "HW_SCREEN_OFFSET_Y"}
11143   ]
11144  },
11145  "PA_SU_LINE_CNTL": {
11146   "fields": [
11147    {"bits": [0, 15], "name": "WIDTH"}
11148   ]
11149  },
11150  "PA_SU_LINE_STIPPLE_CNTL": {
11151   "fields": [
11152    {"bits": [0, 1], "name": "LINE_STIPPLE_RESET"},
11153    {"bits": [2, 2], "name": "EXPAND_FULL_LENGTH"},
11154    {"bits": [3, 3], "name": "FRACTIONAL_ACCUM"},
11155    {"bits": [4, 4], "name": "DIAMOND_ADJUST"}
11156   ]
11157  },
11158  "PA_SU_LINE_STIPPLE_VALUE": {
11159   "fields": [
11160    {"bits": [0, 23], "name": "LINE_STIPPLE_VALUE"}
11161   ]
11162  },
11163  "PA_SU_PERFCOUNTER0_HI": {
11164   "fields": [
11165    {"bits": [0, 15], "name": "PERFCOUNTER_HI"}
11166   ]
11167  },
11168  "PA_SU_PERFCOUNTER0_SELECT": {
11169   "fields": [
11170    {"bits": [0, 9], "name": "PERF_SEL"},
11171    {"bits": [10, 19], "name": "PERF_SEL1"},
11172    {"bits": [20, 23], "name": "CNTR_MODE"}
11173   ]
11174  },
11175  "PA_SU_PERFCOUNTER0_SELECT1": {
11176   "fields": [
11177    {"bits": [0, 9], "name": "PERF_SEL2"},
11178    {"bits": [10, 19], "name": "PERF_SEL3"}
11179   ]
11180  },
11181  "PA_SU_PERFCOUNTER2_SELECT": {
11182   "fields": [
11183    {"bits": [0, 9], "name": "PERF_SEL"},
11184    {"bits": [20, 23], "name": "CNTR_MODE"}
11185   ]
11186  },
11187  "PA_SU_POINT_MINMAX": {
11188   "fields": [
11189    {"bits": [0, 15], "name": "MIN_SIZE"},
11190    {"bits": [16, 31], "name": "MAX_SIZE"}
11191   ]
11192  },
11193  "PA_SU_POINT_SIZE": {
11194   "fields": [
11195    {"bits": [0, 15], "name": "HEIGHT"},
11196    {"bits": [16, 31], "name": "WIDTH"}
11197   ]
11198  },
11199  "PA_SU_POLY_OFFSET_DB_FMT_CNTL": {
11200   "fields": [
11201    {"bits": [0, 7], "name": "POLY_OFFSET_NEG_NUM_DB_BITS"},
11202    {"bits": [8, 8], "name": "POLY_OFFSET_DB_IS_FLOAT_FMT"}
11203   ]
11204  },
11205  "PA_SU_PRIM_FILTER_CNTL": {
11206   "fields": [
11207    {"bits": [0, 0], "name": "TRIANGLE_FILTER_DISABLE"},
11208    {"bits": [1, 1], "name": "LINE_FILTER_DISABLE"},
11209    {"bits": [2, 2], "name": "POINT_FILTER_DISABLE"},
11210    {"bits": [3, 3], "name": "RECTANGLE_FILTER_DISABLE"},
11211    {"bits": [4, 4], "name": "TRIANGLE_EXPAND_ENA"},
11212    {"bits": [5, 5], "name": "LINE_EXPAND_ENA"},
11213    {"bits": [6, 6], "name": "POINT_EXPAND_ENA"},
11214    {"bits": [7, 7], "name": "RECTANGLE_EXPAND_ENA"},
11215    {"bits": [8, 15], "name": "PRIM_EXPAND_CONSTANT"},
11216    {"bits": [30, 30], "name": "XMAX_RIGHT_EXCLUSION"},
11217    {"bits": [31, 31], "name": "YMAX_BOTTOM_EXCLUSION"}
11218   ]
11219  },
11220  "PA_SU_SC_MODE_CNTL": {
11221   "fields": [
11222    {"bits": [0, 0], "name": "CULL_FRONT"},
11223    {"bits": [1, 1], "name": "CULL_BACK"},
11224    {"bits": [2, 2], "name": "FACE"},
11225    {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"},
11226    {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_FRONT_PTYPE"},
11227    {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_BACK_PTYPE"},
11228    {"bits": [11, 11], "name": "POLY_OFFSET_FRONT_ENABLE"},
11229    {"bits": [12, 12], "name": "POLY_OFFSET_BACK_ENABLE"},
11230    {"bits": [13, 13], "name": "POLY_OFFSET_PARA_ENABLE"},
11231    {"bits": [16, 16], "name": "VTX_WINDOW_OFFSET_ENABLE"},
11232    {"bits": [19, 19], "name": "PROVOKING_VTX_LAST"},
11233    {"bits": [20, 20], "name": "PERSP_CORR_DIS"},
11234    {"bits": [21, 21], "name": "MULTI_PRIM_IB_ENA"}
11235   ]
11236  },
11237  "PA_SU_VTX_CNTL": {
11238   "fields": [
11239    {"bits": [0, 0], "name": "PIX_CENTER"},
11240    {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"},
11241    {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"}
11242   ]
11243  },
11244  "RLC_PERFCOUNTER0_SELECT": {
11245   "fields": [
11246    {"bits": [0, 7], "name": "PERFCOUNTER_SELECT"}
11247   ]
11248  },
11249  "RLC_PERFMON_CLK_CNTL": {
11250   "fields": [
11251    {"bits": [0, 0], "name": "PERFMON_CLOCK_STATE"}
11252   ]
11253  },
11254  "RLC_PERFMON_CNTL": {
11255   "fields": [
11256    {"bits": [0, 2], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"},
11257    {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"}
11258   ]
11259  },
11260  "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY": {
11261   "fields": [
11262    {"bits": [0, 7], "name": "PERFMON_SAMPLE_DELAY"},
11263    {"bits": [8, 31], "name": "RESERVED"}
11264   ]
11265  },
11266  "RLC_SPM_PERFMON_CNTL": {
11267   "fields": [
11268    {"bits": [0, 11], "name": "RESERVED1"},
11269    {"bits": [12, 13], "name": "PERFMON_RING_MODE"},
11270    {"bits": [14, 15], "name": "RESERVED"},
11271    {"bits": [16, 31], "name": "PERFMON_SAMPLE_INTERVAL"}
11272   ]
11273  },
11274  "RLC_SPM_PERFMON_RING_BASE_HI": {
11275   "fields": [
11276    {"bits": [0, 15], "name": "RING_BASE_HI"},
11277    {"bits": [16, 31], "name": "RESERVED"}
11278   ]
11279  },
11280  "RLC_SPM_PERFMON_SEGMENT_SIZE": {
11281   "fields": [
11282    {"bits": [0, 7], "name": "PERFMON_SEGMENT_SIZE"},
11283    {"bits": [8, 10], "name": "RESERVED1"},
11284    {"bits": [11, 15], "name": "GLOBAL_NUM_LINE"},
11285    {"bits": [16, 20], "name": "SE0_NUM_LINE"},
11286    {"bits": [21, 25], "name": "SE1_NUM_LINE"},
11287    {"bits": [26, 30], "name": "SE2_NUM_LINE"},
11288    {"bits": [31, 31], "name": "RESERVED"}
11289   ]
11290  },
11291  "SCRATCH_UMSK": {
11292   "fields": [
11293    {"bits": [0, 7], "name": "OBSOLETE_UMSK"},
11294    {"bits": [16, 17], "name": "OBSOLETE_SWAP"}
11295   ]
11296  },
11297  "SPI_BARYC_CNTL": {
11298   "fields": [
11299    {"bits": [0, 0], "name": "PERSP_CENTER_CNTL"},
11300    {"bits": [4, 4], "name": "PERSP_CENTROID_CNTL"},
11301    {"bits": [8, 8], "name": "LINEAR_CENTER_CNTL"},
11302    {"bits": [12, 12], "name": "LINEAR_CENTROID_CNTL"},
11303    {"bits": [16, 17], "name": "POS_FLOAT_LOCATION"},
11304    {"bits": [20, 20], "name": "POS_FLOAT_ULC"},
11305    {"bits": [24, 24], "name": "FRONT_FACE_ALL_BITS"}
11306   ]
11307  },
11308  "SPI_CONFIG_CNTL": {
11309   "fields": [
11310    {"bits": [0, 20], "name": "GPR_WRITE_PRIORITY"},
11311    {"bits": [21, 23], "name": "EXP_PRIORITY_ORDER"},
11312    {"bits": [24, 24], "name": "ENABLE_SQG_TOP_EVENTS"},
11313    {"bits": [25, 25], "name": "ENABLE_SQG_BOP_EVENTS"},
11314    {"bits": [26, 26], "name": "RSRC_MGMT_RESET"},
11315    {"bits": [27, 27], "name": "TTRACE_STALL_ALL"}
11316   ]
11317  },
11318  "SPI_INTERP_CONTROL_0": {
11319   "fields": [
11320    {"bits": [0, 0], "name": "FLAT_SHADE_ENA"},
11321    {"bits": [1, 1], "name": "PNT_SPRITE_ENA"},
11322    {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"},
11323    {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"},
11324    {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"},
11325    {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"},
11326    {"bits": [14, 14], "name": "PNT_SPRITE_TOP_1"}
11327   ]
11328  },
11329  "SPI_PERFCOUNTER4_SELECT": {
11330   "fields": [
11331    {"bits": [0, 7], "name": "PERF_SEL"}
11332   ]
11333  },
11334  "SPI_PERFCOUNTER_BINS": {
11335   "fields": [
11336    {"bits": [0, 3], "name": "BIN0_MIN"},
11337    {"bits": [4, 7], "name": "BIN0_MAX"},
11338    {"bits": [8, 11], "name": "BIN1_MIN"},
11339    {"bits": [12, 15], "name": "BIN1_MAX"},
11340    {"bits": [16, 19], "name": "BIN2_MIN"},
11341    {"bits": [20, 23], "name": "BIN2_MAX"},
11342    {"bits": [24, 27], "name": "BIN3_MIN"},
11343    {"bits": [28, 31], "name": "BIN3_MAX"}
11344   ]
11345  },
11346  "SPI_PS_INPUT_CNTL_0": {
11347   "fields": [
11348    {"bits": [0, 5], "name": "OFFSET"},
11349    {"bits": [8, 9], "name": "DEFAULT_VAL"},
11350    {"bits": [10, 10], "name": "FLAT_SHADE"},
11351    {"bits": [13, 16], "name": "CYL_WRAP"},
11352    {"bits": [17, 17], "name": "PT_SPRITE_TEX"},
11353    {"bits": [18, 18], "name": "DUP"},
11354    {"bits": [19, 19], "name": "FP16_INTERP_MODE"},
11355    {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"},
11356    {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"},
11357    {"bits": [23, 23], "name": "PT_SPRITE_TEX_ATTR1"},
11358    {"bits": [24, 24], "name": "ATTR0_VALID"},
11359    {"bits": [25, 25], "name": "ATTR1_VALID"}
11360   ]
11361  },
11362  "SPI_PS_INPUT_CNTL_20": {
11363   "fields": [
11364    {"bits": [0, 5], "name": "OFFSET"},
11365    {"bits": [8, 9], "name": "DEFAULT_VAL"},
11366    {"bits": [10, 10], "name": "FLAT_SHADE"},
11367    {"bits": [18, 18], "name": "DUP"},
11368    {"bits": [19, 19], "name": "FP16_INTERP_MODE"},
11369    {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"},
11370    {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"},
11371    {"bits": [24, 24], "name": "ATTR0_VALID"},
11372    {"bits": [25, 25], "name": "ATTR1_VALID"}
11373   ]
11374  },
11375  "SPI_PS_INPUT_ENA": {
11376   "fields": [
11377    {"bits": [0, 0], "name": "PERSP_SAMPLE_ENA"},
11378    {"bits": [1, 1], "name": "PERSP_CENTER_ENA"},
11379    {"bits": [2, 2], "name": "PERSP_CENTROID_ENA"},
11380    {"bits": [3, 3], "name": "PERSP_PULL_MODEL_ENA"},
11381    {"bits": [4, 4], "name": "LINEAR_SAMPLE_ENA"},
11382    {"bits": [5, 5], "name": "LINEAR_CENTER_ENA"},
11383    {"bits": [6, 6], "name": "LINEAR_CENTROID_ENA"},
11384    {"bits": [7, 7], "name": "LINE_STIPPLE_TEX_ENA"},
11385    {"bits": [8, 8], "name": "POS_X_FLOAT_ENA"},
11386    {"bits": [9, 9], "name": "POS_Y_FLOAT_ENA"},
11387    {"bits": [10, 10], "name": "POS_Z_FLOAT_ENA"},
11388    {"bits": [11, 11], "name": "POS_W_FLOAT_ENA"},
11389    {"bits": [12, 12], "name": "FRONT_FACE_ENA"},
11390    {"bits": [13, 13], "name": "ANCILLARY_ENA"},
11391    {"bits": [14, 14], "name": "SAMPLE_COVERAGE_ENA"},
11392    {"bits": [15, 15], "name": "POS_FIXED_PT_ENA"}
11393   ]
11394  },
11395  "SPI_PS_IN_CONTROL": {
11396   "fields": [
11397    {"bits": [0, 5], "name": "NUM_INTERP"},
11398    {"bits": [6, 6], "name": "PARAM_GEN"},
11399    {"bits": [14, 14], "name": "BC_OPTIMIZE_DISABLE"}
11400   ]
11401  },
11402  "SPI_SHADER_COL_FORMAT": {
11403   "fields": [
11404    {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"},
11405    {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"},
11406    {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"},
11407    {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"},
11408    {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"},
11409    {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"},
11410    {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"},
11411    {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"}
11412   ]
11413  },
11414  "SPI_SHADER_LATE_ALLOC_VS": {
11415   "fields": [
11416    {"bits": [0, 5], "name": "LIMIT"}
11417   ]
11418  },
11419  "SPI_SHADER_PGM_RSRC1_GS": {
11420   "fields": [
11421    {"bits": [0, 5], "name": "VGPRS"},
11422    {"bits": [6, 9], "name": "SGPRS"},
11423    {"bits": [10, 11], "name": "PRIORITY"},
11424    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
11425    {"bits": [20, 20], "name": "PRIV"},
11426    {"bits": [21, 21], "name": "DX10_CLAMP"},
11427    {"bits": [22, 22], "name": "DEBUG_MODE"},
11428    {"bits": [23, 23], "name": "IEEE_MODE"},
11429    {"bits": [24, 24], "name": "CU_GROUP_ENABLE"},
11430    {"bits": [25, 27], "name": "CACHE_CTL"},
11431    {"bits": [28, 28], "name": "CDBG_USER"}
11432   ]
11433  },
11434  "SPI_SHADER_PGM_RSRC1_HS": {
11435   "fields": [
11436    {"bits": [0, 5], "name": "VGPRS"},
11437    {"bits": [6, 9], "name": "SGPRS"},
11438    {"bits": [10, 11], "name": "PRIORITY"},
11439    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
11440    {"bits": [20, 20], "name": "PRIV"},
11441    {"bits": [21, 21], "name": "DX10_CLAMP"},
11442    {"bits": [22, 22], "name": "DEBUG_MODE"},
11443    {"bits": [23, 23], "name": "IEEE_MODE"},
11444    {"bits": [24, 26], "name": "CACHE_CTL"},
11445    {"bits": [27, 27], "name": "CDBG_USER"}
11446   ]
11447  },
11448  "SPI_SHADER_PGM_RSRC1_LS": {
11449   "fields": [
11450    {"bits": [0, 5], "name": "VGPRS"},
11451    {"bits": [6, 9], "name": "SGPRS"},
11452    {"bits": [10, 11], "name": "PRIORITY"},
11453    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
11454    {"bits": [20, 20], "name": "PRIV"},
11455    {"bits": [21, 21], "name": "DX10_CLAMP"},
11456    {"bits": [22, 22], "name": "DEBUG_MODE"},
11457    {"bits": [23, 23], "name": "IEEE_MODE"},
11458    {"bits": [24, 25], "name": "VGPR_COMP_CNT"},
11459    {"bits": [26, 28], "name": "CACHE_CTL"},
11460    {"bits": [29, 29], "name": "CDBG_USER"}
11461   ]
11462  },
11463  "SPI_SHADER_PGM_RSRC1_PS": {
11464   "fields": [
11465    {"bits": [0, 5], "name": "VGPRS"},
11466    {"bits": [6, 9], "name": "SGPRS"},
11467    {"bits": [10, 11], "name": "PRIORITY"},
11468    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
11469    {"bits": [20, 20], "name": "PRIV"},
11470    {"bits": [21, 21], "name": "DX10_CLAMP"},
11471    {"bits": [22, 22], "name": "DEBUG_MODE"},
11472    {"bits": [23, 23], "name": "IEEE_MODE"},
11473    {"bits": [24, 24], "name": "CU_GROUP_DISABLE"},
11474    {"bits": [25, 27], "name": "CACHE_CTL"},
11475    {"bits": [28, 28], "name": "CDBG_USER"}
11476   ]
11477  },
11478  "SPI_SHADER_PGM_RSRC1_VS": {
11479   "fields": [
11480    {"bits": [0, 5], "name": "VGPRS"},
11481    {"bits": [6, 9], "name": "SGPRS"},
11482    {"bits": [10, 11], "name": "PRIORITY"},
11483    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
11484    {"bits": [20, 20], "name": "PRIV"},
11485    {"bits": [21, 21], "name": "DX10_CLAMP"},
11486    {"bits": [22, 22], "name": "DEBUG_MODE"},
11487    {"bits": [23, 23], "name": "IEEE_MODE"},
11488    {"bits": [24, 25], "name": "VGPR_COMP_CNT"},
11489    {"bits": [26, 26], "name": "CU_GROUP_ENABLE"},
11490    {"bits": [27, 29], "name": "CACHE_CTL"},
11491    {"bits": [30, 30], "name": "CDBG_USER"}
11492   ]
11493  },
11494  "SPI_SHADER_PGM_RSRC2_ES_VS": {
11495   "fields": [
11496    {"bits": [0, 0], "name": "SCRATCH_EN"},
11497    {"bits": [1, 5], "name": "USER_SGPR"},
11498    {"bits": [6, 6], "name": "TRAP_PRESENT"},
11499    {"bits": [7, 7], "name": "OC_LDS_EN"},
11500    {"bits": [8, 16], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
11501    {"bits": [20, 28], "name": "LDS_SIZE"}
11502   ]
11503  },
11504  "SPI_SHADER_PGM_RSRC2_GS": {
11505   "fields": [
11506    {"bits": [0, 0], "name": "SCRATCH_EN"},
11507    {"bits": [1, 5], "name": "USER_SGPR"},
11508    {"bits": [6, 6], "name": "TRAP_PRESENT"},
11509    {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
11510   ]
11511  },
11512  "SPI_SHADER_PGM_RSRC2_HS": {
11513   "fields": [
11514    {"bits": [0, 0], "name": "SCRATCH_EN"},
11515    {"bits": [1, 5], "name": "USER_SGPR"},
11516    {"bits": [6, 6], "name": "TRAP_PRESENT"},
11517    {"bits": [7, 7], "name": "OC_LDS_EN"},
11518    {"bits": [8, 8], "name": "TG_SIZE_EN"},
11519    {"bits": [9, 17], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
11520   ]
11521  },
11522  "SPI_SHADER_PGM_RSRC2_LS_VS": {
11523   "fields": [
11524    {"bits": [0, 0], "name": "SCRATCH_EN"},
11525    {"bits": [1, 5], "name": "USER_SGPR"},
11526    {"bits": [6, 6], "name": "TRAP_PRESENT"},
11527    {"bits": [7, 15], "name": "LDS_SIZE"},
11528    {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
11529   ]
11530  },
11531  "SPI_SHADER_PGM_RSRC2_PS": {
11532   "fields": [
11533    {"bits": [0, 0], "name": "SCRATCH_EN"},
11534    {"bits": [1, 5], "name": "USER_SGPR"},
11535    {"bits": [6, 6], "name": "TRAP_PRESENT"},
11536    {"bits": [7, 7], "name": "WAVE_CNT_EN"},
11537    {"bits": [8, 15], "name": "EXTRA_LDS_SIZE"},
11538    {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
11539   ]
11540  },
11541  "SPI_SHADER_PGM_RSRC2_VS": {
11542   "fields": [
11543    {"bits": [0, 0], "name": "SCRATCH_EN"},
11544    {"bits": [1, 5], "name": "USER_SGPR"},
11545    {"bits": [6, 6], "name": "TRAP_PRESENT"},
11546    {"bits": [7, 7], "name": "OC_LDS_EN"},
11547    {"bits": [8, 8], "name": "SO_BASE0_EN"},
11548    {"bits": [9, 9], "name": "SO_BASE1_EN"},
11549    {"bits": [10, 10], "name": "SO_BASE2_EN"},
11550    {"bits": [11, 11], "name": "SO_BASE3_EN"},
11551    {"bits": [12, 12], "name": "SO_EN"},
11552    {"bits": [13, 21], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
11553    {"bits": [24, 24], "name": "DISPATCH_DRAW_EN"}
11554   ]
11555  },
11556  "SPI_SHADER_PGM_RSRC3_GS": {
11557   "fields": [
11558    {"bits": [0, 15], "name": "CU_EN"},
11559    {"bits": [16, 21], "name": "WAVE_LIMIT"},
11560    {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"},
11561    {"bits": [26, 31], "name": "GROUP_FIFO_DEPTH"}
11562   ]
11563  },
11564  "SPI_SHADER_PGM_RSRC3_HS": {
11565   "fields": [
11566    {"bits": [0, 5], "name": "WAVE_LIMIT"},
11567    {"bits": [6, 9], "name": "LOCK_LOW_THRESHOLD"},
11568    {"bits": [10, 15], "name": "GROUP_FIFO_DEPTH"}
11569   ]
11570  },
11571  "SPI_SHADER_PGM_RSRC3_PS": {
11572   "fields": [
11573    {"bits": [0, 15], "name": "CU_EN"},
11574    {"bits": [16, 21], "name": "WAVE_LIMIT"},
11575    {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"}
11576   ]
11577  },
11578  "SPI_SHADER_POS_FORMAT": {
11579   "fields": [
11580    {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"},
11581    {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"},
11582    {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"},
11583    {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"}
11584   ]
11585  },
11586  "SPI_SHADER_TBA_HI_PS": {
11587   "fields": [
11588    {"bits": [0, 7], "name": "MEM_BASE"}
11589   ]
11590  },
11591  "SPI_SHADER_Z_FORMAT": {
11592   "fields": [
11593    {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"}
11594   ]
11595  },
11596  "SPI_VS_OUT_CONFIG": {
11597   "fields": [
11598    {"bits": [1, 5], "name": "VS_EXPORT_COUNT"},
11599    {"bits": [6, 6], "name": "VS_HALF_PACK"}
11600   ]
11601  },
11602  "SQC_CACHES": {
11603   "fields": [
11604    {"bits": [0, 0], "name": "TARGET_INST"},
11605    {"bits": [1, 1], "name": "TARGET_DATA"},
11606    {"bits": [2, 2], "name": "INVALIDATE"},
11607    {"bits": [3, 3], "name": "WRITEBACK"},
11608    {"bits": [4, 4], "name": "VOL"},
11609    {"bits": [16, 16], "name": "COMPLETE"}
11610   ]
11611  },
11612  "SQC_WRITEBACK": {
11613   "fields": [
11614    {"bits": [0, 0], "name": "DWB"},
11615    {"bits": [1, 1], "name": "DIRTY"}
11616   ]
11617  },
11618  "SQ_BUF_RSRC_WORD1": {
11619   "fields": [
11620    {"bits": [0, 15], "name": "BASE_ADDRESS_HI"},
11621    {"bits": [16, 29], "name": "STRIDE"},
11622    {"bits": [30, 30], "name": "CACHE_SWIZZLE"},
11623    {"bits": [31, 31], "name": "SWIZZLE_ENABLE"}
11624   ]
11625  },
11626  "SQ_BUF_RSRC_WORD3": {
11627   "fields": [
11628    {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"},
11629    {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"},
11630    {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"},
11631    {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"},
11632    {"bits": [12, 14], "enum_ref": "BUF_NUM_FORMAT", "name": "NUM_FORMAT"},
11633    {"bits": [15, 18], "enum_ref": "BUF_DATA_FORMAT", "name": "DATA_FORMAT"},
11634    {"bits": [19, 20], "name": "ELEMENT_SIZE"},
11635    {"bits": [21, 22], "name": "INDEX_STRIDE"},
11636    {"bits": [23, 23], "name": "ADD_TID_ENABLE"},
11637    {"bits": [24, 24], "name": "ATC"},
11638    {"bits": [25, 25], "name": "HASH_ENABLE"},
11639    {"bits": [26, 26], "name": "HEAP"},
11640    {"bits": [27, 29], "name": "MTYPE"},
11641    {"bits": [30, 31], "enum_ref": "SQ_RSRC_BUF_TYPE", "name": "TYPE"}
11642   ]
11643  },
11644  "SQ_IMG_RSRC_WORD1": {
11645   "fields": [
11646    {"bits": [0, 7], "name": "BASE_ADDRESS_HI"},
11647    {"bits": [8, 19], "name": "MIN_LOD"},
11648    {"bits": [20, 25], "enum_ref": "IMG_DATA_FORMAT", "name": "DATA_FORMAT"},
11649    {"bits": [26, 29], "enum_ref": "IMG_NUM_FORMAT", "name": "NUM_FORMAT"},
11650    {"bits": [30, 31], "name": "MTYPE"}
11651   ]
11652  },
11653  "SQ_IMG_RSRC_WORD2": {
11654   "fields": [
11655    {"bits": [0, 13], "name": "WIDTH"},
11656    {"bits": [14, 27], "name": "HEIGHT"},
11657    {"bits": [28, 30], "name": "PERF_MOD"},
11658    {"bits": [31, 31], "name": "INTERLACED"}
11659   ]
11660  },
11661  "SQ_IMG_RSRC_WORD3": {
11662   "fields": [
11663    {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"},
11664    {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"},
11665    {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"},
11666    {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"},
11667    {"bits": [12, 15], "name": "BASE_LEVEL"},
11668    {"bits": [16, 19], "name": "LAST_LEVEL"},
11669    {"bits": [20, 24], "name": "TILING_INDEX"},
11670    {"bits": [25, 25], "name": "POW2_PAD"},
11671    {"bits": [26, 26], "name": "MTYPE"},
11672    {"bits": [27, 27], "name": "ATC"},
11673    {"bits": [28, 31], "enum_ref": "SQ_RSRC_IMG_TYPE", "name": "TYPE"}
11674   ]
11675  },
11676  "SQ_IMG_RSRC_WORD4": {
11677   "fields": [
11678    {"bits": [0, 12], "name": "DEPTH"},
11679    {"bits": [13, 26], "name": "PITCH"}
11680   ]
11681  },
11682  "SQ_IMG_RSRC_WORD5": {
11683   "fields": [
11684    {"bits": [0, 12], "name": "BASE_ARRAY"},
11685    {"bits": [13, 25], "name": "LAST_ARRAY"}
11686   ]
11687  },
11688  "SQ_IMG_RSRC_WORD6": {
11689   "fields": [
11690    {"bits": [0, 11], "name": "MIN_LOD_WARN"},
11691    {"bits": [12, 19], "name": "COUNTER_BANK_ID"},
11692    {"bits": [20, 20], "name": "LOD_HDW_CNT_EN"},
11693    {"bits": [21, 21], "name": "COMPRESSION_EN"},
11694    {"bits": [22, 22], "name": "ALPHA_IS_ON_MSB"},
11695    {"bits": [23, 23], "name": "COLOR_TRANSFORM"},
11696    {"bits": [24, 27], "name": "LOST_ALPHA_BITS"},
11697    {"bits": [28, 31], "name": "LOST_COLOR_BITS"}
11698   ]
11699  },
11700  "SQ_IMG_SAMP_WORD0": {
11701   "fields": [
11702    {"bits": [0, 2], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_X"},
11703    {"bits": [3, 5], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Y"},
11704    {"bits": [6, 8], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Z"},
11705    {"bits": [9, 11], "name": "MAX_ANISO_RATIO"},
11706    {"bits": [12, 14], "enum_ref": "SQ_TEX_DEPTH_COMPARE", "name": "DEPTH_COMPARE_FUNC"},
11707    {"bits": [15, 15], "name": "FORCE_UNNORMALIZED"},
11708    {"bits": [16, 18], "name": "ANISO_THRESHOLD"},
11709    {"bits": [19, 19], "name": "MC_COORD_TRUNC"},
11710    {"bits": [20, 20], "name": "FORCE_DEGAMMA"},
11711    {"bits": [21, 26], "name": "ANISO_BIAS"},
11712    {"bits": [27, 27], "name": "TRUNC_COORD"},
11713    {"bits": [28, 28], "name": "DISABLE_CUBE_WRAP"},
11714    {"bits": [29, 30], "enum_ref": "SQ_IMG_FILTER_TYPE", "name": "FILTER_MODE"},
11715    {"bits": [31, 31], "name": "COMPAT_MODE"}
11716   ]
11717  },
11718  "SQ_IMG_SAMP_WORD1": {
11719   "fields": [
11720    {"bits": [0, 11], "name": "MIN_LOD"},
11721    {"bits": [12, 23], "name": "MAX_LOD"},
11722    {"bits": [24, 27], "name": "PERF_MIP"},
11723    {"bits": [28, 31], "name": "PERF_Z"}
11724   ]
11725  },
11726  "SQ_IMG_SAMP_WORD2": {
11727   "fields": [
11728    {"bits": [0, 13], "name": "LOD_BIAS"},
11729    {"bits": [14, 19], "name": "LOD_BIAS_SEC"},
11730    {"bits": [20, 21], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MAG_FILTER"},
11731    {"bits": [22, 23], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MIN_FILTER"},
11732    {"bits": [24, 25], "enum_ref": "SQ_TEX_Z_FILTER", "name": "Z_FILTER"},
11733    {"bits": [26, 27], "enum_ref": "SQ_TEX_MIP_FILTER", "name": "MIP_FILTER"},
11734    {"bits": [28, 28], "name": "MIP_POINT_PRECLAMP"},
11735    {"bits": [29, 29], "name": "DISABLE_LSB_CEIL"},
11736    {"bits": [30, 30], "name": "FILTER_PREC_FIX"},
11737    {"bits": [31, 31], "name": "ANISO_OVERRIDE"}
11738   ]
11739  },
11740  "SQ_IMG_SAMP_WORD3": {
11741   "fields": [
11742    {"bits": [0, 11], "name": "BORDER_COLOR_PTR"},
11743    {"bits": [29, 29], "name": "UPGRADED_DEPTH"},
11744    {"bits": [30, 31], "enum_ref": "SQ_TEX_BORDER_COLOR", "name": "BORDER_COLOR_TYPE"}
11745   ]
11746  },
11747  "SQ_PERFCOUNTER0_SELECT": {
11748   "fields": [
11749    {"bits": [0, 8], "name": "PERF_SEL"},
11750    {"bits": [12, 15], "name": "SQC_BANK_MASK"},
11751    {"bits": [16, 19], "name": "SQC_CLIENT_MASK"},
11752    {"bits": [20, 23], "name": "SPM_MODE"},
11753    {"bits": [24, 27], "name": "SIMD_MASK"},
11754    {"bits": [28, 31], "name": "PERF_MODE"}
11755   ]
11756  },
11757  "SQ_PERFCOUNTER_CTRL": {
11758   "fields": [
11759    {"bits": [0, 0], "name": "PS_EN"},
11760    {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"},
11761    {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},
11762    {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"},
11763    {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},
11764    {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"},
11765    {"bits": [6, 6], "name": "CS_EN"},
11766    {"bits": [8, 12], "name": "CNTR_RATE"},
11767    {"bits": [13, 13], "name": "DISABLE_FLUSH"}
11768   ]
11769  },
11770  "SQ_PERFCOUNTER_CTRL2": {
11771   "fields": [
11772    {"bits": [0, 0], "name": "FORCE_EN"}
11773   ]
11774  },
11775  "SQ_PERFCOUNTER_MASK": {
11776   "fields": [
11777    {"bits": [0, 15], "name": "SH0_MASK"},
11778    {"bits": [16, 31], "name": "SH1_MASK"}
11779   ]
11780  },
11781  "SQ_THREAD_TRACE_BASE2": {
11782   "fields": [
11783    {"bits": [0, 3], "name": "ADDR_HI"}
11784   ]
11785  },
11786  "SQ_THREAD_TRACE_CTRL": {
11787   "fields": [
11788    {"bits": [31, 31], "name": "RESET_BUFFER"}
11789   ]
11790  },
11791  "SQ_THREAD_TRACE_HIWATER": {
11792   "fields": [
11793    {"bits": [0, 2], "name": "HIWATER"}
11794   ]
11795  },
11796  "SQ_THREAD_TRACE_MASK": {
11797   "fields": [
11798    {"bits": [0, 4], "name": "CU_SEL"},
11799    {"bits": [5, 5], "name": "SH_SEL"},
11800    {"bits": [7, 7], "name": "REG_STALL_EN"},
11801    {"bits": [8, 11], "name": "SIMD_EN"},
11802    {"bits": [12, 13], "name": "VM_ID_MASK"},
11803    {"bits": [14, 14], "name": "SPI_STALL_EN"},
11804    {"bits": [15, 15], "name": "SQ_STALL_EN"},
11805    {"bits": [16, 31], "name": "RANDOM_SEED"}
11806   ]
11807  },
11808  "SQ_THREAD_TRACE_MODE": {
11809   "fields": [
11810    {"bits": [0, 2], "name": "MASK_PS"},
11811    {"bits": [3, 5], "name": "MASK_VS"},
11812    {"bits": [6, 8], "name": "MASK_GS"},
11813    {"bits": [9, 11], "name": "MASK_ES"},
11814    {"bits": [12, 14], "name": "MASK_HS"},
11815    {"bits": [15, 17], "name": "MASK_LS"},
11816    {"bits": [18, 20], "name": "MASK_CS"},
11817    {"bits": [21, 22], "name": "MODE"},
11818    {"bits": [23, 24], "name": "CAPTURE_MODE"},
11819    {"bits": [25, 25], "name": "AUTOFLUSH_EN"},
11820    {"bits": [26, 26], "name": "PRIV"},
11821    {"bits": [27, 28], "name": "ISSUE_MASK"},
11822    {"bits": [29, 29], "name": "TEST_MODE"},
11823    {"bits": [30, 30], "name": "INTERRUPT_EN"},
11824    {"bits": [31, 31], "name": "WRAP"}
11825   ]
11826  },
11827  "SQ_THREAD_TRACE_SIZE": {
11828   "fields": [
11829    {"bits": [0, 21], "name": "SIZE"}
11830   ]
11831  },
11832  "SQ_THREAD_TRACE_STATUS": {
11833   "fields": [
11834    {"bits": [0, 9], "name": "FINISH_PENDING"},
11835    {"bits": [16, 25], "name": "FINISH_DONE"},
11836    {"bits": [29, 29], "name": "NEW_BUF"},
11837    {"bits": [30, 30], "name": "BUSY"},
11838    {"bits": [31, 31], "name": "FULL"}
11839   ]
11840  },
11841  "SQ_THREAD_TRACE_TOKEN_MASK": {
11842   "fields": [
11843    {"bits": [0, 15], "name": "TOKEN_MASK"},
11844    {"bits": [16, 23], "name": "REG_MASK"},
11845    {"bits": [24, 24], "name": "REG_DROP_ON_STALL"}
11846   ]
11847  },
11848  "SQ_THREAD_TRACE_WPTR": {
11849   "fields": [
11850    {"bits": [0, 29], "name": "WPTR"},
11851    {"bits": [30, 31], "name": "READ_OFFSET"}
11852   ]
11853  },
11854  "SQ_WAVE_GPR_ALLOC": {
11855   "fields": [
11856    {"bits": [0, 5], "name": "VGPR_BASE"},
11857    {"bits": [8, 13], "name": "VGPR_SIZE"},
11858    {"bits": [16, 21], "name": "SGPR_BASE"},
11859    {"bits": [24, 27], "name": "SGPR_SIZE"}
11860   ]
11861  },
11862  "SQ_WAVE_HW_ID": {
11863   "fields": [
11864    {"bits": [0, 3], "name": "WAVE_ID"},
11865    {"bits": [4, 5], "name": "SIMD_ID"},
11866    {"bits": [6, 7], "name": "PIPE_ID"},
11867    {"bits": [8, 11], "name": "CU_ID"},
11868    {"bits": [12, 12], "name": "SH_ID"},
11869    {"bits": [13, 14], "name": "SE_ID"},
11870    {"bits": [16, 19], "name": "TG_ID"},
11871    {"bits": [20, 23], "name": "VM_ID"},
11872    {"bits": [24, 26], "name": "QUEUE_ID"},
11873    {"bits": [27, 29], "name": "STATE_ID"},
11874    {"bits": [30, 31], "name": "ME_ID"}
11875   ]
11876  },
11877  "SQ_WAVE_IB_DBG0": {
11878   "fields": [
11879    {"bits": [0, 2], "name": "IBUF_ST"},
11880    {"bits": [3, 3], "name": "PC_INVALID"},
11881    {"bits": [4, 4], "name": "NEED_NEXT_DW"},
11882    {"bits": [5, 7], "name": "NO_PREFETCH_CNT"},
11883    {"bits": [8, 9], "name": "IBUF_RPTR"},
11884    {"bits": [10, 11], "name": "IBUF_WPTR"},
11885    {"bits": [16, 19], "name": "INST_STR_ST"},
11886    {"bits": [20, 23], "name": "MISC_CNT"},
11887    {"bits": [24, 25], "name": "ECC_ST"},
11888    {"bits": [26, 26], "name": "IS_HYB"},
11889    {"bits": [27, 28], "name": "HYB_CNT"},
11890    {"bits": [29, 29], "name": "KILL"},
11891    {"bits": [30, 30], "name": "NEED_KILL_IFETCH"}
11892   ]
11893  },
11894  "SQ_WAVE_IB_DBG1": {
11895   "fields": [
11896    {"bits": [0, 0], "name": "IXNACK"},
11897    {"bits": [1, 1], "name": "XNACK"},
11898    {"bits": [2, 2], "name": "TA_NEED_RESET"},
11899    {"bits": [4, 7], "name": "XCNT"},
11900    {"bits": [8, 11], "name": "QCNT"}
11901   ]
11902  },
11903  "SQ_WAVE_IB_STS": {
11904   "fields": [
11905    {"bits": [0, 3], "name": "VM_CNT"},
11906    {"bits": [4, 6], "name": "EXP_CNT"},
11907    {"bits": [8, 11], "name": "LGKM_CNT"},
11908    {"bits": [12, 14], "name": "VALU_CNT"},
11909    {"bits": [15, 15], "name": "FIRST_REPLAY"},
11910    {"bits": [16, 19], "name": "RCNT"}
11911   ]
11912  },
11913  "SQ_WAVE_LDS_ALLOC": {
11914   "fields": [
11915    {"bits": [0, 7], "name": "LDS_BASE"},
11916    {"bits": [12, 20], "name": "LDS_SIZE"}
11917   ]
11918  },
11919  "SQ_WAVE_MODE": {
11920   "fields": [
11921    {"bits": [0, 3], "name": "FP_ROUND"},
11922    {"bits": [4, 7], "name": "FP_DENORM"},
11923    {"bits": [8, 8], "name": "DX10_CLAMP"},
11924    {"bits": [9, 9], "name": "IEEE"},
11925    {"bits": [10, 10], "name": "LOD_CLAMPED"},
11926    {"bits": [11, 11], "name": "DEBUG_EN"},
11927    {"bits": [12, 20], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
11928    {"bits": [27, 27], "name": "GPR_IDX_EN"},
11929    {"bits": [28, 28], "name": "VSKIP"},
11930    {"bits": [29, 31], "name": "CSP"}
11931   ]
11932  },
11933  "SQ_WAVE_PC_HI": {
11934   "fields": [
11935    {"bits": [0, 15], "name": "PC_HI"}
11936   ]
11937  },
11938  "SQ_WAVE_STATUS": {
11939   "fields": [
11940    {"bits": [0, 0], "name": "SCC"},
11941    {"bits": [1, 2], "name": "SPI_PRIO"},
11942    {"bits": [3, 4], "name": "USER_PRIO"},
11943    {"bits": [5, 5], "name": "PRIV"},
11944    {"bits": [6, 6], "name": "TRAP_EN"},
11945    {"bits": [7, 7], "name": "TTRACE_EN"},
11946    {"bits": [8, 8], "name": "EXPORT_RDY"},
11947    {"bits": [9, 9], "name": "EXECZ"},
11948    {"bits": [10, 10], "name": "VCCZ"},
11949    {"bits": [11, 11], "name": "IN_TG"},
11950    {"bits": [12, 12], "name": "IN_BARRIER"},
11951    {"bits": [13, 13], "name": "HALT"},
11952    {"bits": [14, 14], "name": "TRAP"},
11953    {"bits": [15, 15], "name": "TTRACE_CU_EN"},
11954    {"bits": [16, 16], "name": "VALID"},
11955    {"bits": [17, 17], "name": "ECC_ERR"},
11956    {"bits": [18, 18], "name": "SKIP_EXPORT"},
11957    {"bits": [19, 19], "name": "PERF_EN"},
11958    {"bits": [20, 20], "name": "COND_DBG_USER"},
11959    {"bits": [21, 21], "name": "COND_DBG_SYS"},
11960    {"bits": [22, 22], "name": "ALLOW_REPLAY"},
11961    {"bits": [23, 23], "name": "INST_ATC"},
11962    {"bits": [27, 27], "name": "MUST_EXPORT"}
11963   ]
11964  },
11965  "SQ_WAVE_TBA_HI": {
11966   "fields": [
11967    {"bits": [0, 7], "name": "ADDR_HI"}
11968   ]
11969  },
11970  "SQ_WAVE_TRAPSTS": {
11971   "fields": [
11972    {"bits": [0, 8], "enum_ref": "EXCP_EN", "name": "EXCP"},
11973    {"bits": [10, 10], "name": "SAVECTX"},
11974    {"bits": [16, 21], "name": "EXCP_CYCLE"},
11975    {"bits": [29, 31], "name": "DP_RATE"}
11976   ]
11977  },
11978  "SX_BLEND_OPT_CONTROL": {
11979   "fields": [
11980    {"bits": [0, 0], "name": "MRT0_COLOR_OPT_DISABLE"},
11981    {"bits": [1, 1], "name": "MRT0_ALPHA_OPT_DISABLE"},
11982    {"bits": [4, 4], "name": "MRT1_COLOR_OPT_DISABLE"},
11983    {"bits": [5, 5], "name": "MRT1_ALPHA_OPT_DISABLE"},
11984    {"bits": [8, 8], "name": "MRT2_COLOR_OPT_DISABLE"},
11985    {"bits": [9, 9], "name": "MRT2_ALPHA_OPT_DISABLE"},
11986    {"bits": [12, 12], "name": "MRT3_COLOR_OPT_DISABLE"},
11987    {"bits": [13, 13], "name": "MRT3_ALPHA_OPT_DISABLE"},
11988    {"bits": [16, 16], "name": "MRT4_COLOR_OPT_DISABLE"},
11989    {"bits": [17, 17], "name": "MRT4_ALPHA_OPT_DISABLE"},
11990    {"bits": [20, 20], "name": "MRT5_COLOR_OPT_DISABLE"},
11991    {"bits": [21, 21], "name": "MRT5_ALPHA_OPT_DISABLE"},
11992    {"bits": [24, 24], "name": "MRT6_COLOR_OPT_DISABLE"},
11993    {"bits": [25, 25], "name": "MRT6_ALPHA_OPT_DISABLE"},
11994    {"bits": [28, 28], "name": "MRT7_COLOR_OPT_DISABLE"},
11995    {"bits": [29, 29], "name": "MRT7_ALPHA_OPT_DISABLE"},
11996    {"bits": [31, 31], "name": "PIXEN_ZERO_OPT_DISABLE"}
11997   ]
11998  },
11999  "SX_BLEND_OPT_EPSILON": {
12000   "fields": [
12001    {"bits": [0, 3], "enum_ref": "SX_BLEND_OPT_EPSILON__MRT0_EPSILON", "name": "MRT0_EPSILON"},
12002    {"bits": [4, 7], "name": "MRT1_EPSILON"},
12003    {"bits": [8, 11], "name": "MRT2_EPSILON"},
12004    {"bits": [12, 15], "name": "MRT3_EPSILON"},
12005    {"bits": [16, 19], "name": "MRT4_EPSILON"},
12006    {"bits": [20, 23], "name": "MRT5_EPSILON"},
12007    {"bits": [24, 27], "name": "MRT6_EPSILON"},
12008    {"bits": [28, 31], "name": "MRT7_EPSILON"}
12009   ]
12010  },
12011  "SX_MRT0_BLEND_OPT": {
12012   "fields": [
12013    {"bits": [0, 2], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_SRC_OPT"},
12014    {"bits": [4, 6], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_DST_OPT"},
12015    {"bits": [8, 10], "enum_ref": "SX_OPT_COMB_FCN", "name": "COLOR_COMB_FCN"},
12016    {"bits": [16, 18], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_SRC_OPT"},
12017    {"bits": [20, 22], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_DST_OPT"},
12018    {"bits": [24, 26], "enum_ref": "SX_OPT_COMB_FCN", "name": "ALPHA_COMB_FCN"}
12019   ]
12020  },
12021  "SX_PERFCOUNTER0_SELECT": {
12022   "fields": [
12023    {"bits": [0, 9], "name": "PERFCOUNTER_SELECT"},
12024    {"bits": [10, 19], "name": "PERFCOUNTER_SELECT1"},
12025    {"bits": [20, 23], "name": "CNTR_MODE"}
12026   ]
12027  },
12028  "SX_PERFCOUNTER0_SELECT1": {
12029   "fields": [
12030    {"bits": [0, 9], "name": "PERFCOUNTER_SELECT2"},
12031    {"bits": [10, 19], "name": "PERFCOUNTER_SELECT3"}
12032   ]
12033  },
12034  "SX_PS_DOWNCONVERT": {
12035   "fields": [
12036    {"bits": [0, 3], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT0"},
12037    {"bits": [4, 7], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT1"},
12038    {"bits": [8, 11], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT2"},
12039    {"bits": [12, 15], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT3"},
12040    {"bits": [16, 19], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT4"},
12041    {"bits": [20, 23], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT5"},
12042    {"bits": [24, 27], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT6"},
12043    {"bits": [28, 31], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT7"}
12044   ]
12045  },
12046  "TA_BC_BASE_ADDR_HI": {
12047   "fields": [
12048    {"bits": [0, 7], "name": "ADDRESS"}
12049   ]
12050  },
12051  "TCC_PERFCOUNTER0_SELECT1": {
12052   "fields": [
12053    {"bits": [0, 9], "name": "PERF_SEL2"},
12054    {"bits": [10, 19], "name": "PERF_SEL3"},
12055    {"bits": [24, 27], "name": "PERF_MODE2"},
12056    {"bits": [28, 31], "name": "PERF_MODE3"}
12057   ]
12058  },
12059  "TCC_PERFCOUNTER2_SELECT": {
12060   "fields": [
12061    {"bits": [0, 9], "name": "PERF_SEL"},
12062    {"bits": [20, 23], "name": "CNTR_MODE"},
12063    {"bits": [28, 31], "name": "PERF_MODE"}
12064   ]
12065  },
12066  "TD_PERFCOUNTER0_SELECT": {
12067   "fields": [
12068    {"bits": [0, 7], "name": "PERF_SEL"},
12069    {"bits": [10, 17], "name": "PERF_SEL1"},
12070    {"bits": [20, 23], "name": "CNTR_MODE"},
12071    {"bits": [24, 27], "name": "PERF_MODE1"},
12072    {"bits": [28, 31], "name": "PERF_MODE"}
12073   ]
12074  },
12075  "TD_PERFCOUNTER0_SELECT1": {
12076   "fields": [
12077    {"bits": [0, 7], "name": "PERF_SEL2"},
12078    {"bits": [10, 17], "name": "PERF_SEL3"},
12079    {"bits": [24, 27], "name": "PERF_MODE3"},
12080    {"bits": [28, 31], "name": "PERF_MODE2"}
12081   ]
12082  },
12083  "VGT_DMA_BASE_HI": {
12084   "fields": [
12085    {"bits": [0, 7], "name": "BASE_ADDR"}
12086   ]
12087  },
12088  "VGT_DMA_INDEX_TYPE": {
12089   "fields": [
12090    {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"},
12091    {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"},
12092    {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"},
12093    {"bits": [6, 6], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"},
12094    {"bits": [9, 9], "name": "NOT_EOP"},
12095    {"bits": [10, 10], "name": "REQ_PATH"},
12096    {"bits": [11, 12], "name": "MTYPE"}
12097   ]
12098  },
12099  "VGT_DRAW_INITIATOR": {
12100   "fields": [
12101    {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"},
12102    {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"},
12103    {"bits": [4, 4], "name": "SPRITE_EN_R6XX"},
12104    {"bits": [5, 5], "name": "NOT_EOP"},
12105    {"bits": [6, 6], "name": "USE_OPAQUE"}
12106   ]
12107  },
12108  "VGT_ESGS_RING_ITEMSIZE": {
12109   "fields": [
12110    {"bits": [0, 14], "name": "ITEMSIZE"}
12111   ]
12112  },
12113  "VGT_ES_PER_GS": {
12114   "fields": [
12115    {"bits": [0, 10], "name": "ES_PER_GS"}
12116   ]
12117  },
12118  "VGT_EVENT_ADDRESS_REG": {
12119   "fields": [
12120    {"bits": [0, 27], "name": "ADDRESS_LOW"}
12121   ]
12122  },
12123  "VGT_EVENT_INITIATOR": {
12124   "fields": [
12125    {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"},
12126    {"bits": [18, 26], "name": "ADDRESS_HI"},
12127    {"bits": [27, 27], "name": "EXTENDED_EVENT"}
12128   ]
12129  },
12130  "VGT_GROUP_DECR": {
12131   "fields": [
12132    {"bits": [0, 3], "name": "DECR"}
12133   ]
12134  },
12135  "VGT_GROUP_FIRST_DECR": {
12136   "fields": [
12137    {"bits": [0, 3], "name": "FIRST_DECR"}
12138   ]
12139  },
12140  "VGT_GROUP_PRIM_TYPE": {
12141   "fields": [
12142    {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"},
12143    {"bits": [14, 14], "name": "RETAIN_ORDER"},
12144    {"bits": [15, 15], "name": "RETAIN_QUADS"},
12145    {"bits": [16, 18], "name": "PRIM_ORDER"}
12146   ]
12147  },
12148  "VGT_GROUP_VECT_0_CNTL": {
12149   "fields": [
12150    {"bits": [0, 0], "name": "COMP_X_EN"},
12151    {"bits": [1, 1], "name": "COMP_Y_EN"},
12152    {"bits": [2, 2], "name": "COMP_Z_EN"},
12153    {"bits": [3, 3], "name": "COMP_W_EN"},
12154    {"bits": [8, 15], "name": "STRIDE"},
12155    {"bits": [16, 23], "name": "SHIFT"}
12156   ]
12157  },
12158  "VGT_GROUP_VECT_0_FMT_CNTL": {
12159   "fields": [
12160    {"bits": [0, 3], "name": "X_CONV"},
12161    {"bits": [4, 7], "name": "X_OFFSET"},
12162    {"bits": [8, 11], "name": "Y_CONV"},
12163    {"bits": [12, 15], "name": "Y_OFFSET"},
12164    {"bits": [16, 19], "name": "Z_CONV"},
12165    {"bits": [20, 23], "name": "Z_OFFSET"},
12166    {"bits": [24, 27], "name": "W_CONV"},
12167    {"bits": [28, 31], "name": "W_OFFSET"}
12168   ]
12169  },
12170  "VGT_GSVS_RING_OFFSET_1": {
12171   "fields": [
12172    {"bits": [0, 14], "name": "OFFSET"}
12173   ]
12174  },
12175  "VGT_GS_INSTANCE_CNT": {
12176   "fields": [
12177    {"bits": [0, 0], "name": "ENABLE"},
12178    {"bits": [2, 8], "name": "CNT"}
12179   ]
12180  },
12181  "VGT_GS_MAX_VERT_OUT": {
12182   "fields": [
12183    {"bits": [0, 10], "name": "MAX_VERT_OUT"}
12184   ]
12185  },
12186  "VGT_GS_MODE": {
12187   "fields": [
12188    {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"},
12189    {"bits": [3, 3], "name": "RESERVED_0"},
12190    {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"},
12191    {"bits": [6, 10], "name": "RESERVED_1"},
12192    {"bits": [11, 11], "name": "GS_C_PACK_EN"},
12193    {"bits": [12, 12], "name": "RESERVED_2"},
12194    {"bits": [13, 13], "name": "ES_PASSTHRU"},
12195    {"bits": [14, 14], "name": "RESERVED_3"},
12196    {"bits": [15, 15], "name": "RESERVED_4"},
12197    {"bits": [16, 16], "name": "RESERVED_5"},
12198    {"bits": [17, 17], "name": "PARTIAL_THD_AT_EOI"},
12199    {"bits": [18, 18], "name": "SUPPRESS_CUTS"},
12200    {"bits": [19, 19], "name": "ES_WRITE_OPTIMIZE"},
12201    {"bits": [20, 20], "name": "GS_WRITE_OPTIMIZE"},
12202    {"bits": [21, 22], "name": "ONCHIP"}
12203   ]
12204  },
12205  "VGT_GS_ONCHIP_CNTL": {
12206   "fields": [
12207    {"bits": [0, 10], "name": "ES_VERTS_PER_SUBGRP"},
12208    {"bits": [11, 21], "name": "GS_PRIMS_PER_SUBGRP"}
12209   ]
12210  },
12211  "VGT_GS_OUT_PRIM_TYPE": {
12212   "fields": [
12213    {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"},
12214    {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"},
12215    {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"},
12216    {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"},
12217    {"bits": [31, 31], "name": "UNIQUE_TYPE_PER_STREAM"}
12218   ]
12219  },
12220  "VGT_GS_PER_ES": {
12221   "fields": [
12222    {"bits": [0, 10], "name": "GS_PER_ES"}
12223   ]
12224  },
12225  "VGT_GS_PER_VS": {
12226   "fields": [
12227    {"bits": [0, 3], "name": "GS_PER_VS"}
12228   ]
12229  },
12230  "VGT_HOS_CNTL": {
12231   "fields": [
12232    {"bits": [0, 1], "name": "TESS_MODE"}
12233   ]
12234  },
12235  "VGT_HOS_REUSE_DEPTH": {
12236   "fields": [
12237    {"bits": [0, 7], "name": "REUSE_DEPTH"}
12238   ]
12239  },
12240  "VGT_HS_OFFCHIP_PARAM": {
12241   "fields": [
12242    {"bits": [0, 8], "name": "OFFCHIP_BUFFERING"},
12243    {"bits": [9, 10], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP_GRANULARITY"}
12244   ]
12245  },
12246  "VGT_LS_HS_CONFIG": {
12247   "fields": [
12248    {"bits": [0, 7], "name": "NUM_PATCHES"},
12249    {"bits": [8, 13], "name": "HS_NUM_INPUT_CP"},
12250    {"bits": [14, 19], "name": "HS_NUM_OUTPUT_CP"}
12251   ]
12252  },
12253  "VGT_MULTI_PRIM_IB_RESET_EN": {
12254   "fields": [
12255    {"bits": [0, 0], "name": "RESET_EN"}
12256   ]
12257  },
12258  "VGT_OUTPUT_PATH_CNTL": {
12259   "fields": [
12260    {"bits": [0, 2], "name": "PATH_SELECT"}
12261   ]
12262  },
12263  "VGT_OUT_DEALLOC_CNTL": {
12264   "fields": [
12265    {"bits": [0, 6], "name": "DEALLOC_DIST"}
12266   ]
12267  },
12268  "VGT_PERFCOUNTER2_SELECT": {
12269   "fields": [
12270    {"bits": [0, 7], "name": "PERF_SEL"},
12271    {"bits": [28, 31], "name": "PERF_MODE"}
12272   ]
12273  },
12274  "VGT_PERFCOUNTER_SEID_MASK": {
12275   "fields": [
12276    {"bits": [0, 7], "name": "PERF_SEID_IGNORE_MASK"}
12277   ]
12278  },
12279  "VGT_PRIMITIVEID_EN": {
12280   "fields": [
12281    {"bits": [0, 0], "name": "PRIMITIVEID_EN"},
12282    {"bits": [1, 1], "name": "DISABLE_RESET_ON_EOI"}
12283   ]
12284  },
12285  "VGT_PRIMITIVE_TYPE": {
12286   "fields": [
12287    {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}
12288   ]
12289  },
12290  "VGT_REUSE_OFF": {
12291   "fields": [
12292    {"bits": [0, 0], "name": "REUSE_OFF"}
12293   ]
12294  },
12295  "VGT_SHADER_STAGES_EN": {
12296   "fields": [
12297    {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"},
12298    {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},
12299    {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"},
12300    {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},
12301    {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"},
12302    {"bits": [8, 8], "name": "DYNAMIC_HS"},
12303    {"bits": [9, 9], "name": "DISPATCH_DRAW_EN"},
12304    {"bits": [10, 10], "name": "DIS_DEALLOC_ACCUM_0"},
12305    {"bits": [11, 11], "name": "DIS_DEALLOC_ACCUM_1"},
12306    {"bits": [12, 12], "name": "VS_WAVE_ID_EN"}
12307   ]
12308  },
12309  "VGT_STRMOUT_BUFFER_CONFIG": {
12310   "fields": [
12311    {"bits": [0, 3], "name": "STREAM_0_BUFFER_EN"},
12312    {"bits": [4, 7], "name": "STREAM_1_BUFFER_EN"},
12313    {"bits": [8, 11], "name": "STREAM_2_BUFFER_EN"},
12314    {"bits": [12, 15], "name": "STREAM_3_BUFFER_EN"}
12315   ]
12316  },
12317  "VGT_STRMOUT_CONFIG": {
12318   "fields": [
12319    {"bits": [0, 0], "name": "STREAMOUT_0_EN"},
12320    {"bits": [1, 1], "name": "STREAMOUT_1_EN"},
12321    {"bits": [2, 2], "name": "STREAMOUT_2_EN"},
12322    {"bits": [3, 3], "name": "STREAMOUT_3_EN"},
12323    {"bits": [4, 6], "name": "RAST_STREAM"},
12324    {"bits": [8, 11], "name": "RAST_STREAM_MASK"},
12325    {"bits": [31, 31], "name": "USE_RAST_STREAM_MASK"}
12326   ]
12327  },
12328  "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE": {
12329   "fields": [
12330    {"bits": [0, 8], "name": "VERTEX_STRIDE"}
12331   ]
12332  },
12333  "VGT_STRMOUT_VTX_STRIDE_0": {
12334   "fields": [
12335    {"bits": [0, 9], "name": "STRIDE"}
12336   ]
12337  },
12338  "VGT_TESS_DISTRIBUTION": {
12339   "fields": [
12340    {"bits": [0, 7], "name": "ACCUM_ISOLINE"},
12341    {"bits": [8, 15], "name": "ACCUM_TRI"},
12342    {"bits": [16, 23], "name": "ACCUM_QUAD"},
12343    {"bits": [24, 31], "name": "DONUT_SPLIT"}
12344   ]
12345  },
12346  "VGT_TF_PARAM": {
12347   "fields": [
12348    {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"},
12349    {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"},
12350    {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"},
12351    {"bits": [8, 8], "name": "RESERVED_REDUC_AXIS"},
12352    {"bits": [9, 9], "name": "DEPRECATED"},
12353    {"bits": [10, 13], "name": "NUM_DS_WAVES_PER_SIMD"},
12354    {"bits": [14, 14], "name": "DISABLE_DONUTS"},
12355    {"bits": [15, 15], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"},
12356    {"bits": [17, 18], "enum_ref": "VGT_DIST_MODE", "name": "DISTRIBUTION_MODE"},
12357    {"bits": [19, 20], "name": "MTYPE"}
12358   ]
12359  },
12360  "VGT_TF_RING_SIZE": {
12361   "fields": [
12362    {"bits": [0, 15], "name": "SIZE"}
12363   ]
12364  },
12365  "VGT_VERTEX_REUSE_BLOCK_CNTL": {
12366   "fields": [
12367    {"bits": [0, 7], "name": "VTX_REUSE_DEPTH"}
12368   ]
12369  },
12370  "VGT_VTX_CNT_EN": {
12371   "fields": [
12372    {"bits": [0, 0], "name": "VTX_CNT_EN"}
12373   ]
12374  }
12375 }
12376}
12377