1{
2 "enums": {
3  "BinMapMode": {
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6    {"name": "BIN_MAP_MODE_RTA_INDEX", "value": 1},
7    {"name": "BIN_MAP_MODE_POPS", "value": 2}
8   ]
9  },
10  "BinSizeExtend": {
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13    {"name": "BIN_SIZE_64_PIXELS", "value": 1},
14    {"name": "BIN_SIZE_128_PIXELS", "value": 2},
15    {"name": "BIN_SIZE_256_PIXELS", "value": 3},
16    {"name": "BIN_SIZE_512_PIXELS", "value": 4}
17   ]
18  },
19  "BinningMode": {
20   "entries": [
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22    {"name": "FORCE_BINNING_ON", "value": 1},
23    {"name": "DISABLE_BINNING_USE_NEW_SC", "value": 2},
24    {"name": "DISABLE_BINNING_USE_LEGACY_SC", "value": 3}
25   ]
26  },
27  "BlendOp": {
28   "entries": [
29    {"name": "BLEND_ZERO", "value": 0},
30    {"name": "BLEND_ONE", "value": 1},
31    {"name": "BLEND_SRC_COLOR", "value": 2},
32    {"name": "BLEND_ONE_MINUS_SRC_COLOR", "value": 3},
33    {"name": "BLEND_SRC_ALPHA", "value": 4},
34    {"name": "BLEND_ONE_MINUS_SRC_ALPHA", "value": 5},
35    {"name": "BLEND_DST_ALPHA", "value": 6},
36    {"name": "BLEND_ONE_MINUS_DST_ALPHA", "value": 7},
37    {"name": "BLEND_DST_COLOR", "value": 8},
38    {"name": "BLEND_ONE_MINUS_DST_COLOR", "value": 9},
39    {"name": "BLEND_SRC_ALPHA_SATURATE", "value": 10},
40    {"name": "BLEND_BOTH_SRC_ALPHA", "value": 11},
41    {"name": "BLEND_BOTH_INV_SRC_ALPHA", "value": 12},
42    {"name": "BLEND_CONSTANT_COLOR", "value": 13},
43    {"name": "BLEND_ONE_MINUS_CONSTANT_COLOR", "value": 14},
44    {"name": "BLEND_SRC1_COLOR", "value": 15},
45    {"name": "BLEND_INV_SRC1_COLOR", "value": 16},
46    {"name": "BLEND_SRC1_ALPHA", "value": 17},
47    {"name": "BLEND_INV_SRC1_ALPHA", "value": 18},
48    {"name": "BLEND_CONSTANT_ALPHA", "value": 19},
49    {"name": "BLEND_ONE_MINUS_CONSTANT_ALPHA", "value": 20}
50   ]
51  },
52  "BlendOpt": {
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55    {"name": "FORCE_OPT_DISABLE", "value": 1},
56    {"name": "FORCE_OPT_ENABLE_IF_SRC_A_0", "value": 2},
57    {"name": "FORCE_OPT_ENABLE_IF_SRC_RGB_0", "value": 3},
58    {"name": "FORCE_OPT_ENABLE_IF_SRC_ARGB_0", "value": 4},
59    {"name": "FORCE_OPT_ENABLE_IF_SRC_A_1", "value": 5},
60    {"name": "FORCE_OPT_ENABLE_IF_SRC_RGB_1", "value": 6},
61    {"name": "FORCE_OPT_ENABLE_IF_SRC_ARGB_1", "value": 7}
62   ]
63  },
64  "CBMode": {
65   "entries": [
66    {"name": "CB_DISABLE", "value": 0},
67    {"name": "CB_NORMAL", "value": 1},
68    {"name": "CB_ELIMINATE_FAST_CLEAR", "value": 2},
69    {"name": "CB_RESOLVE", "value": 3},
70    {"name": "CB_DECOMPRESS", "value": 4},
71    {"name": "CB_FMASK_DECOMPRESS", "value": 5},
72    {"name": "CB_DCC_DECOMPRESS", "value": 6},
73    {"name": "CB_RESERVED", "value": 7}
74   ]
75  },
76  "CBPerfClearFilterSel": {
77   "entries": [
78    {"name": "CB_PERF_CLEAR_FILTER_SEL_NONCLEAR", "value": 0},
79    {"name": "CB_PERF_CLEAR_FILTER_SEL_CLEAR", "value": 1}
80   ]
81  },
82  "CBPerfOpFilterSel": {
83   "entries": [
84    {"name": "CB_PERF_OP_FILTER_SEL_WRITE_ONLY", "value": 0},
85    {"name": "CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION", "value": 1},
86    {"name": "CB_PERF_OP_FILTER_SEL_RESOLVE", "value": 2},
87    {"name": "CB_PERF_OP_FILTER_SEL_DECOMPRESS", "value": 3},
88    {"name": "CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS", "value": 4},
89    {"name": "CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR", "value": 5}
90   ]
91  },
92  "CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE": {
93   "entries": [
94    {"name": "MAX_BLOCK_SIZE_64B", "value": 0},
95    {"name": "MAX_BLOCK_SIZE_128B", "value": 1},
96    {"name": "MAX_BLOCK_SIZE_256B", "value": 2}
97   ]
98  },
99  "CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE": {
100   "entries": [
101    {"name": "MIN_BLOCK_SIZE_32B", "value": 0},
102    {"name": "MIN_BLOCK_SIZE_64B", "value": 1}
103   ]
104  },
105  "CLIP_RULE": {
106   "entries": [
107    {"name": "OUT", "value": 1},
108    {"name": "IN_0", "value": 2},
109    {"name": "IN_1", "value": 4},
110    {"name": "IN_10", "value": 8},
111    {"name": "IN_2", "value": 16},
112    {"name": "IN_20", "value": 32},
113    {"name": "IN_21", "value": 64},
114    {"name": "IN_210", "value": 128},
115    {"name": "IN_3", "value": 256},
116    {"name": "IN_30", "value": 512},
117    {"name": "IN_31", "value": 1024},
118    {"name": "IN_310", "value": 2048},
119    {"name": "IN_32", "value": 4096},
120    {"name": "IN_320", "value": 8192},
121    {"name": "IN_321", "value": 16384},
122    {"name": "IN_3210", "value": 32768}
123   ]
124  },
125  "CP_PERFMON_ENABLE_MODE": {
126   "entries": [
127    {"name": "CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT", "value": 0},
128    {"name": "CP_PERFMON_ENABLE_MODE_RESERVED_1", "value": 1},
129    {"name": "CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE", "value": 2},
130    {"name": "CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE", "value": 3}
131   ]
132  },
133  "CP_PERFMON_STATE": {
134   "entries": [
135    {"name": "CP_PERFMON_STATE_DISABLE_AND_RESET", "value": 0},
136    {"name": "CP_PERFMON_STATE_START_COUNTING", "value": 1},
137    {"name": "CP_PERFMON_STATE_STOP_COUNTING", "value": 2},
138    {"name": "CP_PERFMON_STATE_RESERVED_3", "value": 3},
139    {"name": "CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM", "value": 4},
140    {"name": "CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM", "value": 5}
141   ]
142  },
143  "CmaskAddr": {
144   "entries": [
145    {"name": "CMASK_ADDR_TILED", "value": 0},
146    {"name": "CMASK_ADDR_LINEAR", "value": 1},
147    {"name": "CMASK_ADDR_COMPATIBLE", "value": 2}
148   ]
149  },
150  "ColorFormat": {
151   "entries": [
152    {"name": "COLOR_INVALID", "value": 0},
153    {"name": "COLOR_8", "value": 1},
154    {"name": "COLOR_16", "value": 2},
155    {"name": "COLOR_8_8", "value": 3},
156    {"name": "COLOR_32", "value": 4},
157    {"name": "COLOR_16_16", "value": 5},
158    {"name": "COLOR_10_11_11", "value": 6},
159    {"name": "COLOR_11_11_10", "value": 7},
160    {"name": "COLOR_10_10_10_2", "value": 8},
161    {"name": "COLOR_2_10_10_10", "value": 9},
162    {"name": "COLOR_8_8_8_8", "value": 10},
163    {"name": "COLOR_32_32", "value": 11},
164    {"name": "COLOR_16_16_16_16", "value": 12},
165    {"name": "COLOR_32_32_32_32", "value": 14},
166    {"name": "COLOR_5_6_5", "value": 16},
167    {"name": "COLOR_1_5_5_5", "value": 17},
168    {"name": "COLOR_5_5_5_1", "value": 18},
169    {"name": "COLOR_4_4_4_4", "value": 19},
170    {"name": "COLOR_8_24", "value": 20},
171    {"name": "COLOR_24_8", "value": 21},
172    {"name": "COLOR_X24_8_32_FLOAT", "value": 22},
173    {"name": "COLOR_5_9_9_9", "value": 24}
174   ]
175  },
176  "CombFunc": {
177   "entries": [
178    {"name": "COMB_DST_PLUS_SRC", "value": 0},
179    {"name": "COMB_SRC_MINUS_DST", "value": 1},
180    {"name": "COMB_MIN_DST_SRC", "value": 2},
181    {"name": "COMB_MAX_DST_SRC", "value": 3},
182    {"name": "COMB_DST_MINUS_SRC", "value": 4}
183   ]
184  },
185  "CompareFrag": {
186   "entries": [
187    {"name": "FRAG_NEVER", "value": 0},
188    {"name": "FRAG_LESS", "value": 1},
189    {"name": "FRAG_EQUAL", "value": 2},
190    {"name": "FRAG_LEQUAL", "value": 3},
191    {"name": "FRAG_GREATER", "value": 4},
192    {"name": "FRAG_NOTEQUAL", "value": 5},
193    {"name": "FRAG_GEQUAL", "value": 6},
194    {"name": "FRAG_ALWAYS", "value": 7}
195   ]
196  },
197  "ConservativeZExport": {
198   "entries": [
199    {"name": "EXPORT_ANY_Z", "value": 0},
200    {"name": "EXPORT_LESS_THAN_Z", "value": 1},
201    {"name": "EXPORT_GREATER_THAN_Z", "value": 2},
202    {"name": "EXPORT_RESERVED", "value": 3}
203   ]
204  },
205  "CovToShaderSel": {
206   "entries": [
207    {"name": "INPUT_COVERAGE", "value": 0},
208    {"name": "INPUT_INNER_COVERAGE", "value": 1},
209    {"name": "INPUT_DEPTH_COVERAGE", "value": 2},
210    {"name": "RAW", "value": 3}
211   ]
212  },
213  "DB_DFSM_CONTROL__PUNCHOUT_MODE": {
214   "entries": [
215    {"name": "AUTO", "value": 0},
216    {"name": "FORCE_ON", "value": 1},
217    {"name": "FORCE_OFF", "value": 2},
218    {"name": "RESERVED", "value": 3}
219   ]
220  },
221  "DbPRTFaultBehavior": {
222   "entries": [
223    {"name": "FAULT_ZERO", "value": 0},
224    {"name": "FAULT_ONE", "value": 1},
225    {"name": "FAULT_FAIL", "value": 2},
226    {"name": "FAULT_PASS", "value": 3}
227   ]
228  },
229  "DbPSLControl": {
230   "entries": [
231    {"name": "PSLC_AUTO", "value": 0},
232    {"name": "PSLC_ON_HANG_ONLY", "value": 1},
233    {"name": "PSLC_ASAP", "value": 2},
234    {"name": "PSLC_COUNTDOWN", "value": 3}
235   ]
236  },
237  "EXCP_EN": {
238   "entries": [
239    {"name": "INVALID", "value": 1},
240    {"name": "INPUT_DENORMAL", "value": 2},
241    {"name": "DIVIDE_BY_ZERO", "value": 4},
242    {"name": "OVERFLOW", "value": 8},
243    {"name": "UNDERFLOW", "value": 16},
244    {"name": "INEXACT", "value": 32},
245    {"name": "INT_DIVIDE_BY_ZERO", "value": 64},
246    {"name": "ADDRESS_WATCH", "value": 128},
247    {"name": "MEMORY_VIOLATION", "value": 256}
248   ]
249  },
250  "FLOAT_MODE": {
251   "entries": [
252    {"name": "FP_32_ROUND_TOWARDS_ZERO", "value": 3},
253    {"name": "FP_16_64_ROUND_TOWARDS_ZERO", "value": 12},
254    {"name": "FP_32_DENORMS", "value": 48},
255    {"name": "FP_16_64_DENORMS", "value": 192}
256   ]
257  },
258  "ForceControl": {
259   "entries": [
260    {"name": "FORCE_OFF", "value": 0},
261    {"name": "FORCE_ENABLE", "value": 1},
262    {"name": "FORCE_DISABLE", "value": 2},
263    {"name": "FORCE_RESERVED", "value": 3}
264   ]
265  },
266  "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE": {
267   "entries": [
268    {"name": "X_DRAW_POINTS", "value": 0},
269    {"name": "X_DRAW_LINES", "value": 1},
270    {"name": "X_DRAW_TRIANGLES", "value": 2}
271   ]
272  },
273  "PA_SU_SC_MODE_CNTL__POLY_MODE": {
274   "entries": [
275    {"name": "X_DISABLE_POLY_MODE", "value": 0},
276    {"name": "X_DUAL_MODE", "value": 1}
277   ]
278  },
279  "PA_SU_VTX_CNTL__ROUND_MODE": {
280   "entries": [
281    {"name": "X_TRUNCATE", "value": 0},
282    {"name": "X_ROUND", "value": 1},
283    {"name": "X_ROUND_TO_EVEN", "value": 2},
284    {"name": "X_ROUND_TO_ODD", "value": 3}
285   ]
286  },
287  "PkrMap": {
288   "entries": [
289    {"name": "RASTER_CONFIG_PKR_MAP_0", "value": 0},
290    {"name": "RASTER_CONFIG_PKR_MAP_1", "value": 1},
291    {"name": "RASTER_CONFIG_PKR_MAP_2", "value": 2},
292    {"name": "RASTER_CONFIG_PKR_MAP_3", "value": 3}
293   ]
294  },
295  "PkrXsel": {
296   "entries": [
297    {"name": "RASTER_CONFIG_PKR_XSEL_0", "value": 0},
298    {"name": "RASTER_CONFIG_PKR_XSEL_1", "value": 1},
299    {"name": "RASTER_CONFIG_PKR_XSEL_2", "value": 2},
300    {"name": "RASTER_CONFIG_PKR_XSEL_3", "value": 3}
301   ]
302  },
303  "PkrXsel2": {
304   "entries": [
305    {"name": "RASTER_CONFIG_PKR_XSEL2_0", "value": 0},
306    {"name": "RASTER_CONFIG_PKR_XSEL2_1", "value": 1},
307    {"name": "RASTER_CONFIG_PKR_XSEL2_2", "value": 2},
308    {"name": "RASTER_CONFIG_PKR_XSEL2_3", "value": 3}
309   ]
310  },
311  "PkrYsel": {
312   "entries": [
313    {"name": "RASTER_CONFIG_PKR_YSEL_0", "value": 0},
314    {"name": "RASTER_CONFIG_PKR_YSEL_1", "value": 1},
315    {"name": "RASTER_CONFIG_PKR_YSEL_2", "value": 2},
316    {"name": "RASTER_CONFIG_PKR_YSEL_3", "value": 3}
317   ]
318  },
319  "QUANT_MODE": {
320   "entries": [
321    {"name": "X_16_8_FIXED_POINT_1_16TH", "value": 0},
322    {"name": "X_16_8_FIXED_POINT_1_8TH", "value": 1},
323    {"name": "X_16_8_FIXED_POINT_1_4TH", "value": 2},
324    {"name": "X_16_8_FIXED_POINT_1_2", "value": 3},
325    {"name": "X_16_8_FIXED_POINT_1", "value": 4},
326    {"name": "X_16_8_FIXED_POINT_1_256TH", "value": 5},
327    {"name": "X_14_10_FIXED_POINT_1_1024TH", "value": 6},
328    {"name": "X_12_12_FIXED_POINT_1_4096TH", "value": 7}
329   ]
330  },
331  "ROP3": {
332   "entries": [
333    {"name": "ROP3_CLEAR", "value": 0},
334    {"name": "X_0X05", "value": 5},
335    {"name": "X_0X0A", "value": 10},
336    {"name": "X_0X0F", "value": 15},
337    {"name": "ROP3_NOR", "value": 17},
338    {"name": "ROP3_AND_INVERTED", "value": 34},
339    {"name": "ROP3_COPY_INVERTED", "value": 51},
340    {"name": "ROP3_AND_REVERSE", "value": 68},
341    {"name": "X_0X50", "value": 80},
342    {"name": "ROP3_INVERT", "value": 85},
343    {"name": "X_0X5A", "value": 90},
344    {"name": "X_0X5F", "value": 95},
345    {"name": "ROP3_XOR", "value": 102},
346    {"name": "ROP3_NAND", "value": 119},
347    {"name": "ROP3_AND", "value": 136},
348    {"name": "ROP3_EQUIVALENT", "value": 153},
349    {"name": "X_0XA0", "value": 160},
350    {"name": "X_0XA5", "value": 165},
351    {"name": "ROP3_NO_OP", "value": 170},
352    {"name": "X_0XAF", "value": 175},
353    {"name": "ROP3_OR_INVERTED", "value": 187},
354    {"name": "ROP3_COPY", "value": 204},
355    {"name": "ROP3_OR_REVERSE", "value": 221},
356    {"name": "ROP3_OR", "value": 238},
357    {"name": "X_0XF0", "value": 240},
358    {"name": "X_0XF5", "value": 245},
359    {"name": "X_0XFA", "value": 250},
360    {"name": "ROP3_SET", "value": 255}
361   ]
362  },
363  "RbMap": {
364   "entries": [
365    {"name": "RASTER_CONFIG_RB_MAP_0", "value": 0},
366    {"name": "RASTER_CONFIG_RB_MAP_1", "value": 1},
367    {"name": "RASTER_CONFIG_RB_MAP_2", "value": 2},
368    {"name": "RASTER_CONFIG_RB_MAP_3", "value": 3}
369   ]
370  },
371  "RbXsel": {
372   "entries": [
373    {"name": "RASTER_CONFIG_RB_XSEL_0", "value": 0},
374    {"name": "RASTER_CONFIG_RB_XSEL_1", "value": 1}
375   ]
376  },
377  "RbXsel2": {
378   "entries": [
379    {"name": "RASTER_CONFIG_RB_XSEL2_0", "value": 0},
380    {"name": "RASTER_CONFIG_RB_XSEL2_1", "value": 1},
381    {"name": "RASTER_CONFIG_RB_XSEL2_2", "value": 2},
382    {"name": "RASTER_CONFIG_RB_XSEL2_3", "value": 3}
383   ]
384  },
385  "RbYsel": {
386   "entries": [
387    {"name": "RASTER_CONFIG_RB_YSEL_0", "value": 0},
388    {"name": "RASTER_CONFIG_RB_YSEL_1", "value": 1}
389   ]
390  },
391  "ReadPolicy": {
392   "entries": [
393    {"name": "CACHE_LRU_RD", "value": 0},
394    {"name": "CACHE_NOA", "value": 1},
395    {"name": "UNCACHED_RD", "value": 2},
396    {"name": "RESERVED_RDPOLICY", "value": 3}
397   ]
398  },
399  "SPI_PNT_SPRITE_OVERRIDE": {
400   "entries": [
401    {"name": "SPI_PNT_SPRITE_SEL_0", "value": 0},
402    {"name": "SPI_PNT_SPRITE_SEL_1", "value": 1},
403    {"name": "SPI_PNT_SPRITE_SEL_S", "value": 2},
404    {"name": "SPI_PNT_SPRITE_SEL_T", "value": 3},
405    {"name": "SPI_PNT_SPRITE_SEL_NONE", "value": 4}
406   ]
407  },
408  "SPI_SHADER_EX_FORMAT": {
409   "entries": [
410    {"name": "SPI_SHADER_ZERO", "value": 0},
411    {"name": "SPI_SHADER_32_R", "value": 1},
412    {"name": "SPI_SHADER_32_GR", "value": 2},
413    {"name": "SPI_SHADER_32_AR", "value": 3},
414    {"name": "SPI_SHADER_FP16_ABGR", "value": 4},
415    {"name": "SPI_SHADER_UNORM16_ABGR", "value": 5},
416    {"name": "SPI_SHADER_SNORM16_ABGR", "value": 6},
417    {"name": "SPI_SHADER_UINT16_ABGR", "value": 7},
418    {"name": "SPI_SHADER_SINT16_ABGR", "value": 8},
419    {"name": "SPI_SHADER_32_ABGR", "value": 9}
420   ]
421  },
422  "SPI_SHADER_FORMAT": {
423   "entries": [
424    {"name": "SPI_SHADER_NONE", "value": 0},
425    {"name": "SPI_SHADER_1COMP", "value": 1},
426    {"name": "SPI_SHADER_2COMP", "value": 2},
427    {"name": "SPI_SHADER_4COMPRESS", "value": 3},
428    {"name": "SPI_SHADER_4COMP", "value": 4}
429   ]
430  },
431  "SPM_PERFMON_STATE": {
432   "entries": [
433    {"name": "STRM_PERFMON_STATE_DISABLE_AND_RESET", "value": 0},
434    {"name": "STRM_PERFMON_STATE_START_COUNTING", "value": 1},
435    {"name": "STRM_PERFMON_STATE_STOP_COUNTING", "value": 2},
436    {"name": "STRM_PERFMON_STATE_RESERVED_3", "value": 3},
437    {"name": "STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM", "value": 4},
438    {"name": "STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM", "value": 5}
439   ]
440  },
441  "SX_BLEND_OPT": {
442   "entries": [
443    {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_ALL", "value": 0},
444    {"name": "BLEND_OPT_PRESERVE_ALL_IGNORE_NONE", "value": 1},
445    {"name": "BLEND_OPT_PRESERVE_C1_IGNORE_C0", "value": 2},
446    {"name": "BLEND_OPT_PRESERVE_C0_IGNORE_C1", "value": 3},
447    {"name": "BLEND_OPT_PRESERVE_A1_IGNORE_A0", "value": 4},
448    {"name": "BLEND_OPT_PRESERVE_A0_IGNORE_A1", "value": 5},
449    {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_A0", "value": 6},
450    {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_NONE", "value": 7}
451   ]
452  },
453  "SX_BLEND_OPT_EPSILON__MRT0_EPSILON": {
454   "entries": [
455    {"name": "EXACT", "value": 0},
456    {"name": "11BIT_FORMAT", "value": 1},
457    {"name": "10BIT_FORMAT", "value": 3},
458    {"name": "8BIT_FORMAT", "value": 6},
459    {"name": "6BIT_FORMAT", "value": 11},
460    {"name": "5BIT_FORMAT", "value": 13},
461    {"name": "4BIT_FORMAT", "value": 15}
462   ]
463  },
464  "SX_DOWNCONVERT_FORMAT": {
465   "entries": [
466    {"name": "SX_RT_EXPORT_NO_CONVERSION", "value": 0},
467    {"name": "SX_RT_EXPORT_32_R", "value": 1},
468    {"name": "SX_RT_EXPORT_32_A", "value": 2},
469    {"name": "SX_RT_EXPORT_10_11_11", "value": 3},
470    {"name": "SX_RT_EXPORT_2_10_10_10", "value": 4},
471    {"name": "SX_RT_EXPORT_8_8_8_8", "value": 5},
472    {"name": "SX_RT_EXPORT_5_6_5", "value": 6},
473    {"name": "SX_RT_EXPORT_1_5_5_5", "value": 7},
474    {"name": "SX_RT_EXPORT_4_4_4_4", "value": 8},
475    {"name": "SX_RT_EXPORT_16_16_GR", "value": 9},
476    {"name": "SX_RT_EXPORT_16_16_AR", "value": 10},
477    {"name": "SX_RT_EXPORT_9_9_9_E5", "value": 11}
478   ]
479  },
480  "SX_OPT_COMB_FCN": {
481   "entries": [
482    {"name": "OPT_COMB_NONE", "value": 0},
483    {"name": "OPT_COMB_ADD", "value": 1},
484    {"name": "OPT_COMB_SUBTRACT", "value": 2},
485    {"name": "OPT_COMB_MIN", "value": 3},
486    {"name": "OPT_COMB_MAX", "value": 4},
487    {"name": "OPT_COMB_REVSUBTRACT", "value": 5},
488    {"name": "OPT_COMB_BLEND_DISABLED", "value": 6},
489    {"name": "OPT_COMB_SAFE_ADD", "value": 7}
490   ]
491  },
492  "ScMap": {
493   "entries": [
494    {"name": "RASTER_CONFIG_SC_MAP_0", "value": 0},
495    {"name": "RASTER_CONFIG_SC_MAP_1", "value": 1},
496    {"name": "RASTER_CONFIG_SC_MAP_2", "value": 2},
497    {"name": "RASTER_CONFIG_SC_MAP_3", "value": 3}
498   ]
499  },
500  "ScUncertaintyRegionMode": {
501   "entries": [
502    {"name": "SC_HALF_LSB", "value": 0},
503    {"name": "SC_LSB_ONE_SIDED", "value": 1},
504    {"name": "SC_LSB_TWO_SIDED", "value": 2}
505   ]
506  },
507  "ScXsel": {
508   "entries": [
509    {"name": "RASTER_CONFIG_SC_XSEL_8_WIDE_TILE", "value": 0},
510    {"name": "RASTER_CONFIG_SC_XSEL_16_WIDE_TILE", "value": 1},
511    {"name": "RASTER_CONFIG_SC_XSEL_32_WIDE_TILE", "value": 2},
512    {"name": "RASTER_CONFIG_SC_XSEL_64_WIDE_TILE", "value": 3}
513   ]
514  },
515  "ScYsel": {
516   "entries": [
517    {"name": "RASTER_CONFIG_SC_YSEL_8_WIDE_TILE", "value": 0},
518    {"name": "RASTER_CONFIG_SC_YSEL_16_WIDE_TILE", "value": 1},
519    {"name": "RASTER_CONFIG_SC_YSEL_32_WIDE_TILE", "value": 2},
520    {"name": "RASTER_CONFIG_SC_YSEL_64_WIDE_TILE", "value": 3}
521   ]
522  },
523  "SeMap": {
524   "entries": [
525    {"name": "RASTER_CONFIG_SE_MAP_0", "value": 0},
526    {"name": "RASTER_CONFIG_SE_MAP_1", "value": 1},
527    {"name": "RASTER_CONFIG_SE_MAP_2", "value": 2},
528    {"name": "RASTER_CONFIG_SE_MAP_3", "value": 3}
529   ]
530  },
531  "SePairMap": {
532   "entries": [
533    {"name": "RASTER_CONFIG_SE_PAIR_MAP_0", "value": 0},
534    {"name": "RASTER_CONFIG_SE_PAIR_MAP_1", "value": 1},
535    {"name": "RASTER_CONFIG_SE_PAIR_MAP_2", "value": 2},
536    {"name": "RASTER_CONFIG_SE_PAIR_MAP_3", "value": 3}
537   ]
538  },
539  "SePairXsel": {
540   "entries": [
541    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE", "value": 0},
542    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE", "value": 1},
543    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE", "value": 2},
544    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE", "value": 3}
545   ]
546  },
547  "SePairYsel": {
548   "entries": [
549    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE", "value": 0},
550    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE", "value": 1},
551    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE", "value": 2},
552    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE", "value": 3}
553   ]
554  },
555  "SeXsel": {
556   "entries": [
557    {"name": "RASTER_CONFIG_SE_XSEL_8_WIDE_TILE", "value": 0},
558    {"name": "RASTER_CONFIG_SE_XSEL_16_WIDE_TILE", "value": 1},
559    {"name": "RASTER_CONFIG_SE_XSEL_32_WIDE_TILE", "value": 2},
560    {"name": "RASTER_CONFIG_SE_XSEL_64_WIDE_TILE", "value": 3}
561   ]
562  },
563  "SeYsel": {
564   "entries": [
565    {"name": "RASTER_CONFIG_SE_YSEL_8_WIDE_TILE", "value": 0},
566    {"name": "RASTER_CONFIG_SE_YSEL_16_WIDE_TILE", "value": 1},
567    {"name": "RASTER_CONFIG_SE_YSEL_32_WIDE_TILE", "value": 2},
568    {"name": "RASTER_CONFIG_SE_YSEL_64_WIDE_TILE", "value": 3}
569   ]
570  },
571  "StencilFormat": {
572   "entries": [
573    {"name": "STENCIL_INVALID", "value": 0},
574    {"name": "STENCIL_8", "value": 1}
575   ]
576  },
577  "StencilOp": {
578   "entries": [
579    {"name": "STENCIL_KEEP", "value": 0},
580    {"name": "STENCIL_ZERO", "value": 1},
581    {"name": "STENCIL_ONES", "value": 2},
582    {"name": "STENCIL_REPLACE_TEST", "value": 3},
583    {"name": "STENCIL_REPLACE_OP", "value": 4},
584    {"name": "STENCIL_ADD_CLAMP", "value": 5},
585    {"name": "STENCIL_SUB_CLAMP", "value": 6},
586    {"name": "STENCIL_INVERT", "value": 7},
587    {"name": "STENCIL_ADD_WRAP", "value": 8},
588    {"name": "STENCIL_SUB_WRAP", "value": 9},
589    {"name": "STENCIL_AND", "value": 10},
590    {"name": "STENCIL_OR", "value": 11},
591    {"name": "STENCIL_XOR", "value": 12},
592    {"name": "STENCIL_NAND", "value": 13},
593    {"name": "STENCIL_NOR", "value": 14},
594    {"name": "STENCIL_XNOR", "value": 15}
595   ]
596  },
597  "SurfaceEndian": {
598   "entries": [
599    {"name": "ENDIAN_NONE", "value": 0},
600    {"name": "ENDIAN_8IN16", "value": 1},
601    {"name": "ENDIAN_8IN32", "value": 2},
602    {"name": "ENDIAN_8IN64", "value": 3}
603   ]
604  },
605  "SurfaceNumber": {
606   "entries": [
607    {"name": "NUMBER_UNORM", "value": 0},
608    {"name": "NUMBER_SNORM", "value": 1},
609    {"name": "NUMBER_USCALED", "value": 2},
610    {"name": "NUMBER_SSCALED", "value": 3},
611    {"name": "NUMBER_UINT", "value": 4},
612    {"name": "NUMBER_SINT", "value": 5},
613    {"name": "NUMBER_SRGB", "value": 6},
614    {"name": "NUMBER_FLOAT", "value": 7}
615   ]
616  },
617  "SurfaceSwap": {
618   "entries": [
619    {"name": "SWAP_STD", "value": 0},
620    {"name": "SWAP_ALT", "value": 1},
621    {"name": "SWAP_STD_REV", "value": 2},
622    {"name": "SWAP_ALT_REV", "value": 3}
623   ]
624  },
625  "ThreadTraceRegInclude": {
626   "entries": [
627    {"name": "REG_INCLUDE_SQDEC", "value": 1},
628    {"name": "REG_INCLUDE_SHDEC", "value": 2},
629    {"name": "REG_INCLUDE_GFXUDEC", "value": 4},
630    {"name": "REG_INCLUDE_COMP", "value": 8},
631    {"name": "REG_INCLUDE_CONTEXT", "value": 16},
632    {"name": "REG_INCLUDE_CONFIG", "value": 32},
633    {"name": "REG_INCLUDE_OTHER", "value": 64},
634    {"name": "REG_INCLUDE_READS", "value": 128}
635   ]
636  },
637  "ThreadTraceTokenExclude": {
638   "entries": [
639    {"name": "TOKEN_EXCLUDE_VMEMEXEC", "value": 1},
640    {"name": "TOKEN_EXCLUDE_ALUEXEC", "value": 2},
641    {"name": "TOKEN_EXCLUDE_VALUINST", "value": 4},
642    {"name": "TOKEN_EXCLUDE_WAVERDY", "value": 8},
643    {"name": "TOKEN_EXCLUDE_IMMED1", "value": 16},
644    {"name": "TOKEN_EXCLUDE_IMMEDIATE", "value": 32},
645    {"name": "TOKEN_EXCLUDE_REG", "value": 64},
646    {"name": "TOKEN_EXCLUDE_EVENT", "value": 128},
647    {"name": "TOKEN_EXCLUDE_INST", "value": 256},
648    {"name": "TOKEN_EXCLUDE_UTILCTR", "value": 512},
649    {"name": "TOKEN_EXCLUDE_WAVEALLOC", "value": 1024},
650    {"name": "TOKEN_EXCLUDE_PERF", "value": 2048}
651   ]
652  },
653  "VGT_DETECT_ONE": {
654   "entries": [
655    {"name": "PRE_CLAMP_TF1", "value": 0},
656    {"name": "POST_CLAMP_TF1", "value": 1},
657    {"name": "DISABLE_TF1", "value": 2}
658   ]
659  },
660  "VGT_DETECT_ZERO": {
661   "entries": [
662    {"name": "PRE_CLAMP_TF0", "value": 0},
663    {"name": "POST_CLAMP_TF0", "value": 1},
664    {"name": "DISABLE_TF0", "value": 2}
665   ]
666  },
667  "VGT_DIST_MODE": {
668   "entries": [
669    {"name": "NO_DIST", "value": 0},
670    {"name": "PATCHES", "value": 1},
671    {"name": "DONUTS", "value": 2},
672    {"name": "TRAPEZOIDS", "value": 3}
673   ]
674  },
675  "VGT_DI_MAJOR_MODE_SELECT": {
676   "entries": [
677    {"name": "DI_MAJOR_MODE_0", "value": 0},
678    {"name": "DI_MAJOR_MODE_1", "value": 1}
679   ]
680  },
681  "VGT_DI_PRIM_TYPE": {
682   "entries": [
683    {"name": "DI_PT_NONE", "value": 0},
684    {"name": "DI_PT_POINTLIST", "value": 1},
685    {"name": "DI_PT_LINELIST", "value": 2},
686    {"name": "DI_PT_LINESTRIP", "value": 3},
687    {"name": "DI_PT_TRILIST", "value": 4},
688    {"name": "DI_PT_TRIFAN", "value": 5},
689    {"name": "DI_PT_TRISTRIP", "value": 6},
690    {"name": "DI_PT_2D_RECTANGLE", "value": 7},
691    {"name": "DI_PT_UNUSED_1", "value": 8},
692    {"name": "DI_PT_PATCH", "value": 9},
693    {"name": "DI_PT_LINELIST_ADJ", "value": 10},
694    {"name": "DI_PT_LINESTRIP_ADJ", "value": 11},
695    {"name": "DI_PT_TRILIST_ADJ", "value": 12},
696    {"name": "DI_PT_TRISTRIP_ADJ", "value": 13},
697    {"name": "DI_PT_UNUSED_3", "value": 14},
698    {"name": "DI_PT_UNUSED_4", "value": 15},
699    {"name": "DI_PT_TRI_WITH_WFLAGS", "value": 16},
700    {"name": "DI_PT_RECTLIST", "value": 17},
701    {"name": "DI_PT_LINELOOP", "value": 18},
702    {"name": "DI_PT_QUADLIST", "value": 19},
703    {"name": "DI_PT_QUADSTRIP", "value": 20},
704    {"name": "DI_PT_POLYGON", "value": 21}
705   ]
706  },
707  "VGT_DI_SOURCE_SELECT": {
708   "entries": [
709    {"name": "DI_SRC_SEL_DMA", "value": 0},
710    {"name": "DI_SRC_SEL_IMMEDIATE", "value": 1},
711    {"name": "DI_SRC_SEL_AUTO_INDEX", "value": 2},
712    {"name": "DI_SRC_SEL_RESERVED", "value": 3}
713   ]
714  },
715  "VGT_DMA_BUF_TYPE": {
716   "entries": [
717    {"name": "VGT_DMA_BUF_MEM", "value": 0},
718    {"name": "VGT_DMA_BUF_RING", "value": 1},
719    {"name": "VGT_DMA_BUF_SETUP", "value": 2},
720    {"name": "VGT_DMA_PTR_UPDATE", "value": 3}
721   ]
722  },
723  "VGT_DMA_SWAP_MODE": {
724   "entries": [
725    {"name": "VGT_DMA_SWAP_NONE", "value": 0},
726    {"name": "VGT_DMA_SWAP_16_BIT", "value": 1},
727    {"name": "VGT_DMA_SWAP_32_BIT", "value": 2},
728    {"name": "VGT_DMA_SWAP_WORD", "value": 3}
729   ]
730  },
731  "VGT_EVENT_TYPE": {
732   "entries": [
733    {"name": "Reserved_0x00", "value": 0},
734    {"name": "SAMPLE_STREAMOUTSTATS1", "value": 1},
735    {"name": "SAMPLE_STREAMOUTSTATS2", "value": 2},
736    {"name": "SAMPLE_STREAMOUTSTATS3", "value": 3},
737    {"name": "CACHE_FLUSH_TS", "value": 4},
738    {"name": "CONTEXT_DONE", "value": 5},
739    {"name": "CACHE_FLUSH", "value": 6},
740    {"name": "CS_PARTIAL_FLUSH", "value": 7},
741    {"name": "VGT_STREAMOUT_SYNC", "value": 8},
742    {"name": "SET_FE_ID", "value": 9},
743    {"name": "VGT_STREAMOUT_RESET", "value": 10},
744    {"name": "END_OF_PIPE_INCR_DE", "value": 11},
745    {"name": "END_OF_PIPE_IB_END", "value": 12},
746    {"name": "RST_PIX_CNT", "value": 13},
747    {"name": "BREAK_BATCH", "value": 14},
748    {"name": "VS_PARTIAL_FLUSH", "value": 15},
749    {"name": "PS_PARTIAL_FLUSH", "value": 16},
750    {"name": "FLUSH_HS_OUTPUT", "value": 17},
751    {"name": "FLUSH_DFSM", "value": 18},
752    {"name": "RESET_TO_LOWEST_VGT", "value": 19},
753    {"name": "CACHE_FLUSH_AND_INV_TS_EVENT", "value": 20},
754    {"name": "ZPASS_DONE", "value": 21},
755    {"name": "CACHE_FLUSH_AND_INV_EVENT", "value": 22},
756    {"name": "PERFCOUNTER_START", "value": 23},
757    {"name": "PERFCOUNTER_STOP", "value": 24},
758    {"name": "PIPELINESTAT_START", "value": 25},
759    {"name": "PIPELINESTAT_STOP", "value": 26},
760    {"name": "PERFCOUNTER_SAMPLE", "value": 27},
761    {"name": "FLUSH_ES_OUTPUT", "value": 28},
762    {"name": "BIN_CONF_OVERRIDE_CHECK", "value": 29},
763    {"name": "SAMPLE_PIPELINESTAT", "value": 30},
764    {"name": "SO_VGTSTREAMOUT_FLUSH", "value": 31},
765    {"name": "SAMPLE_STREAMOUTSTATS", "value": 32},
766    {"name": "RESET_VTX_CNT", "value": 33},
767    {"name": "BLOCK_CONTEXT_DONE", "value": 34},
768    {"name": "CS_CONTEXT_DONE", "value": 35},
769    {"name": "VGT_FLUSH", "value": 36},
770    {"name": "TGID_ROLLOVER", "value": 37},
771    {"name": "SQ_NON_EVENT", "value": 38},
772    {"name": "SC_SEND_DB_VPZ", "value": 39},
773    {"name": "BOTTOM_OF_PIPE_TS", "value": 40},
774    {"name": "FLUSH_SX_TS", "value": 41},
775    {"name": "DB_CACHE_FLUSH_AND_INV", "value": 42},
776    {"name": "FLUSH_AND_INV_DB_DATA_TS", "value": 43},
777    {"name": "FLUSH_AND_INV_DB_META", "value": 44},
778    {"name": "FLUSH_AND_INV_CB_DATA_TS", "value": 45},
779    {"name": "FLUSH_AND_INV_CB_META", "value": 46},
780    {"name": "CS_DONE", "value": 47},
781    {"name": "PS_DONE", "value": 48},
782    {"name": "FLUSH_AND_INV_CB_PIXEL_DATA", "value": 49},
783    {"name": "SX_CB_RAT_ACK_REQUEST", "value": 50},
784    {"name": "THREAD_TRACE_START", "value": 51},
785    {"name": "THREAD_TRACE_STOP", "value": 52},
786    {"name": "THREAD_TRACE_MARKER", "value": 53},
787    {"name": "THREAD_TRACE_DRAW", "value": 54},
788    {"name": "THREAD_TRACE_FINISH", "value": 55},
789    {"name": "PIXEL_PIPE_STAT_CONTROL", "value": 56},
790    {"name": "PIXEL_PIPE_STAT_DUMP", "value": 57},
791    {"name": "PIXEL_PIPE_STAT_RESET", "value": 58},
792    {"name": "CONTEXT_SUSPEND", "value": 59},
793    {"name": "OFFCHIP_HS_DEALLOC", "value": 60},
794    {"name": "ENABLE_NGG_PIPELINE", "value": 61},
795    {"name": "ENABLE_LEGACY_PIPELINE", "value": 62},
796    {"name": "DRAW_DONE", "value": 63}
797   ]
798  },
799  "VGT_GS_CUT_MODE": {
800   "entries": [
801    {"name": "GS_CUT_1024", "value": 0},
802    {"name": "GS_CUT_512", "value": 1},
803    {"name": "GS_CUT_256", "value": 2},
804    {"name": "GS_CUT_128", "value": 3}
805   ]
806  },
807  "VGT_GS_MODE_TYPE": {
808   "entries": [
809    {"name": "GS_OFF", "value": 0},
810    {"name": "GS_SCENARIO_A", "value": 1},
811    {"name": "GS_SCENARIO_B", "value": 2},
812    {"name": "GS_SCENARIO_G", "value": 3},
813    {"name": "GS_SCENARIO_C", "value": 4},
814    {"name": "SPRITE_EN", "value": 5}
815   ]
816  },
817  "VGT_GS_OUTPRIM_TYPE": {
818   "entries": [
819    {"name": "POINTLIST", "value": 0},
820    {"name": "LINESTRIP", "value": 1},
821    {"name": "TRISTRIP", "value": 2},
822    {"name": "RECTLIST", "value": 3}
823   ]
824  },
825  "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY": {
826   "entries": [
827    {"name": "X_8K_DWORDS", "value": 0},
828    {"name": "X_4K_DWORDS", "value": 1},
829    {"name": "X_2K_DWORDS", "value": 2},
830    {"name": "X_1K_DWORDS", "value": 3}
831   ]
832  },
833  "VGT_INDEX_TYPE_MODE": {
834   "entries": [
835    {"name": "VGT_INDEX_16", "value": 0},
836    {"name": "VGT_INDEX_32", "value": 1},
837    {"name": "VGT_INDEX_8", "value": 2}
838   ]
839  },
840  "VGT_RDREQ_POLICY": {
841   "entries": [
842    {"name": "VGT_POLICY_LRU", "value": 0},
843    {"name": "VGT_POLICY_STREAM", "value": 1},
844    {"name": "VGT_POLICY_BYPASS", "value": 2}
845   ]
846  },
847  "VGT_STAGES_ES_EN": {
848   "entries": [
849    {"name": "ES_STAGE_OFF", "value": 0},
850    {"name": "ES_STAGE_DS", "value": 1},
851    {"name": "ES_STAGE_REAL", "value": 2},
852    {"name": "RESERVED_ES", "value": 3}
853   ]
854  },
855  "VGT_STAGES_GS_EN": {
856   "entries": [
857    {"name": "GS_STAGE_OFF", "value": 0},
858    {"name": "GS_STAGE_ON", "value": 1}
859   ]
860  },
861  "VGT_STAGES_HS_EN": {
862   "entries": [
863    {"name": "HS_STAGE_OFF", "value": 0},
864    {"name": "HS_STAGE_ON", "value": 1}
865   ]
866  },
867  "VGT_STAGES_LS_EN": {
868   "entries": [
869    {"name": "LS_STAGE_OFF", "value": 0},
870    {"name": "LS_STAGE_ON", "value": 1},
871    {"name": "CS_STAGE_ON", "value": 2},
872    {"name": "RESERVED_LS", "value": 3}
873   ]
874  },
875  "VGT_STAGES_VS_EN": {
876   "entries": [
877    {"name": "VS_STAGE_REAL", "value": 0},
878    {"name": "VS_STAGE_DS", "value": 1},
879    {"name": "VS_STAGE_COPY_SHADER", "value": 2},
880    {"name": "RESERVED_VS", "value": 3}
881   ]
882  },
883  "VGT_TESS_PARTITION": {
884   "entries": [
885    {"name": "PART_INTEGER", "value": 0},
886    {"name": "PART_POW2", "value": 1},
887    {"name": "PART_FRAC_ODD", "value": 2},
888    {"name": "PART_FRAC_EVEN", "value": 3}
889   ]
890  },
891  "VGT_TESS_TOPOLOGY": {
892   "entries": [
893    {"name": "OUTPUT_POINT", "value": 0},
894    {"name": "OUTPUT_LINE", "value": 1},
895    {"name": "OUTPUT_TRIANGLE_CW", "value": 2},
896    {"name": "OUTPUT_TRIANGLE_CCW", "value": 3}
897   ]
898  },
899  "VGT_TESS_TYPE": {
900   "entries": [
901    {"name": "TESS_ISOLINE", "value": 0},
902    {"name": "TESS_TRIANGLE", "value": 1},
903    {"name": "TESS_QUAD", "value": 2}
904   ]
905  },
906  "VRSCombinerModeSC": {
907   "entries": [
908    {"name": "VRS_COMB_MODE_PASSTHRU", "value": 0},
909    {"name": "VRS_COMB_MODE_OVERRIDE", "value": 1},
910    {"name": "VRS_COMB_MODE_MIN", "value": 2},
911    {"name": "VRS_COMB_MODE_MAX", "value": 3},
912    {"name": "VRS_COMB_MODE_SATURATE", "value": 4}
913   ]
914  },
915  "VRSHtileEncoding": {
916   "entries": [
917    {"name": "VRS_HTILE_DISABLE", "value": 0},
918    {"name": "VRS_HTILE_2BIT_ENCODING", "value": 1},
919    {"name": "VRS_HTILE_4BIT_ENCODING", "value": 2}
920   ]
921  },
922  "WritePolicy": {
923   "entries": [
924    {"name": "CACHE_LRU_WR", "value": 0},
925    {"name": "CACHE_STREAM", "value": 1},
926    {"name": "CACHE_BYPASS", "value": 2},
927    {"name": "UNCACHED_WR", "value": 3}
928   ]
929  },
930  "ZFormat": {
931   "entries": [
932    {"name": "Z_INVALID", "value": 0},
933    {"name": "Z_16", "value": 1},
934    {"name": "Z_24", "value": 2},
935    {"name": "Z_32_FLOAT", "value": 3}
936   ]
937  },
938  "ZLimitSumm": {
939   "entries": [
940    {"name": "FORCE_SUMM_OFF", "value": 0},
941    {"name": "FORCE_SUMM_MINZ", "value": 1},
942    {"name": "FORCE_SUMM_MAXZ", "value": 2},
943    {"name": "FORCE_SUMM_BOTH", "value": 3}
944   ]
945  },
946  "ZOrder": {
947   "entries": [
948    {"name": "LATE_Z", "value": 0},
949    {"name": "EARLY_Z_THEN_LATE_Z", "value": 1},
950    {"name": "RE_Z", "value": 2},
951    {"name": "EARLY_Z_THEN_RE_Z", "value": 3}
952   ]
953  }
954 },
955 "register_mappings": [
956  {
957   "chips": ["gfx103"],
958   "map": {"at": 40, "to": "mm"},
959   "name": "SQ_WAVE_ACTIVE",
960   "type_ref": "SQ_WAVE_ACTIVE"
961  },
962  {
963   "chips": ["gfx103"],
964   "map": {"at": 44, "to": "mm"},
965   "name": "SQ_WAVE_VALID_AND_IDLE",
966   "type_ref": "SQ_WAVE_ACTIVE"
967  },
968  {
969   "chips": ["gfx103"],
970   "map": {"at": 1028, "to": "mm"},
971   "name": "SQ_WAVE_MODE",
972   "type_ref": "SQ_WAVE_MODE"
973  },
974  {
975   "chips": ["gfx103"],
976   "map": {"at": 1032, "to": "mm"},
977   "name": "SQ_WAVE_STATUS",
978   "type_ref": "SQ_WAVE_STATUS"
979  },
980  {
981   "chips": ["gfx103"],
982   "map": {"at": 1036, "to": "mm"},
983   "name": "SQ_WAVE_TRAPSTS",
984   "type_ref": "SQ_WAVE_TRAPSTS"
985  },
986  {
987   "chips": ["gfx103"],
988   "map": {"at": 1040, "to": "mm"},
989   "name": "SQ_WAVE_HW_ID_LEGACY",
990   "type_ref": "SQ_WAVE_HW_ID_LEGACY"
991  },
992  {
993   "chips": ["gfx103"],
994   "map": {"at": 1044, "to": "mm"},
995   "name": "SQ_WAVE_GPR_ALLOC",
996   "type_ref": "SQ_WAVE_GPR_ALLOC"
997  },
998  {
999   "chips": ["gfx103"],
1000   "map": {"at": 1048, "to": "mm"},
1001   "name": "SQ_WAVE_LDS_ALLOC",
1002   "type_ref": "SQ_WAVE_LDS_ALLOC"
1003  },
1004  {
1005   "chips": ["gfx103"],
1006   "map": {"at": 1052, "to": "mm"},
1007   "name": "SQ_WAVE_IB_STS",
1008   "type_ref": "SQ_WAVE_IB_STS"
1009  },
1010  {
1011   "chips": ["gfx103"],
1012   "map": {"at": 1056, "to": "mm"},
1013   "name": "SQ_WAVE_PC_LO"
1014  },
1015  {
1016   "chips": ["gfx103"],
1017   "map": {"at": 1060, "to": "mm"},
1018   "name": "SQ_WAVE_PC_HI",
1019   "type_ref": "SQ_WAVE_PC_HI"
1020  },
1021  {
1022   "chips": ["gfx103"],
1023   "map": {"at": 1064, "to": "mm"},
1024   "name": "SQ_WAVE_INST_DW0"
1025  },
1026  {
1027   "chips": ["gfx103"],
1028   "map": {"at": 1076, "to": "mm"},
1029   "name": "SQ_WAVE_IB_DBG1",
1030   "type_ref": "SQ_WAVE_IB_DBG1"
1031  },
1032  {
1033   "chips": ["gfx103"],
1034   "map": {"at": 1080, "to": "mm"},
1035   "name": "SQ_WAVE_FLUSH_IB"
1036  },
1037  {
1038   "chips": ["gfx103"],
1039   "map": {"at": 1104, "to": "mm"},
1040   "name": "SQ_WAVE_FLAT_SCRATCH_LO"
1041  },
1042  {
1043   "chips": ["gfx103"],
1044   "map": {"at": 1108, "to": "mm"},
1045   "name": "SQ_WAVE_FLAT_SCRATCH_HI"
1046  },
1047  {
1048   "chips": ["gfx103"],
1049   "map": {"at": 1116, "to": "mm"},
1050   "name": "SQ_WAVE_HW_ID1",
1051   "type_ref": "SQ_WAVE_HW_ID1"
1052  },
1053  {
1054   "chips": ["gfx103"],
1055   "map": {"at": 1120, "to": "mm"},
1056   "name": "SQ_WAVE_HW_ID2",
1057   "type_ref": "SQ_WAVE_HW_ID2"
1058  },
1059  {
1060   "chips": ["gfx103"],
1061   "map": {"at": 1124, "to": "mm"},
1062   "name": "SQ_WAVE_POPS_PACKER",
1063   "type_ref": "SQ_WAVE_POPS_PACKER"
1064  },
1065  {
1066   "chips": ["gfx103"],
1067   "map": {"at": 1128, "to": "mm"},
1068   "name": "SQ_WAVE_SCHED_MODE",
1069   "type_ref": "SQ_WAVE_SCHED_MODE"
1070  },
1071  {
1072   "chips": ["gfx103"],
1073   "map": {"at": 1132, "to": "mm"},
1074   "name": "SQ_WAVE_VGPR_OFFSET",
1075   "type_ref": "SQ_WAVE_VGPR_OFFSET"
1076  },
1077  {
1078   "chips": ["gfx103"],
1079   "map": {"at": 1136, "to": "mm"},
1080   "name": "SQ_WAVE_IB_STS2",
1081   "type_ref": "SQ_WAVE_IB_STS2"
1082  },
1083  {
1084   "chips": ["gfx103"],
1085   "map": {"at": 1140, "to": "mm"},
1086   "name": "SQ_WAVE_SHADER_CYCLES",
1087   "type_ref": "SQ_WAVE_SHADER_CYCLES"
1088  },
1089  {
1090   "chips": ["gfx103"],
1091   "map": {"at": 2480, "to": "mm"},
1092   "name": "SQ_WAVE_TTMP0"
1093  },
1094  {
1095   "chips": ["gfx103"],
1096   "map": {"at": 2484, "to": "mm"},
1097   "name": "SQ_WAVE_TTMP1"
1098  },
1099  {
1100   "chips": ["gfx103"],
1101   "map": {"at": 2488, "to": "mm"},
1102   "name": "SQ_WAVE_TTMP2"
1103  },
1104  {
1105   "chips": ["gfx103"],
1106   "map": {"at": 2492, "to": "mm"},
1107   "name": "SQ_WAVE_TTMP3"
1108  },
1109  {
1110   "chips": ["gfx103"],
1111   "map": {"at": 2496, "to": "mm"},
1112   "name": "SQ_WAVE_TTMP4"
1113  },
1114  {
1115   "chips": ["gfx103"],
1116   "map": {"at": 2500, "to": "mm"},
1117   "name": "SQ_WAVE_TTMP5"
1118  },
1119  {
1120   "chips": ["gfx103"],
1121   "map": {"at": 2504, "to": "mm"},
1122   "name": "SQ_WAVE_TTMP6"
1123  },
1124  {
1125   "chips": ["gfx103"],
1126   "map": {"at": 2508, "to": "mm"},
1127   "name": "SQ_WAVE_TTMP7"
1128  },
1129  {
1130   "chips": ["gfx103"],
1131   "map": {"at": 2512, "to": "mm"},
1132   "name": "SQ_WAVE_TTMP8"
1133  },
1134  {
1135   "chips": ["gfx103"],
1136   "map": {"at": 2516, "to": "mm"},
1137   "name": "SQ_WAVE_TTMP9"
1138  },
1139  {
1140   "chips": ["gfx103"],
1141   "map": {"at": 2520, "to": "mm"},
1142   "name": "SQ_WAVE_TTMP10"
1143  },
1144  {
1145   "chips": ["gfx103"],
1146   "map": {"at": 2524, "to": "mm"},
1147   "name": "SQ_WAVE_TTMP11"
1148  },
1149  {
1150   "chips": ["gfx103"],
1151   "map": {"at": 2528, "to": "mm"},
1152   "name": "SQ_WAVE_TTMP12"
1153  },
1154  {
1155   "chips": ["gfx103"],
1156   "map": {"at": 2532, "to": "mm"},
1157   "name": "SQ_WAVE_TTMP13"
1158  },
1159  {
1160   "chips": ["gfx103"],
1161   "map": {"at": 2536, "to": "mm"},
1162   "name": "SQ_WAVE_TTMP14"
1163  },
1164  {
1165   "chips": ["gfx103"],
1166   "map": {"at": 2540, "to": "mm"},
1167   "name": "SQ_WAVE_TTMP15"
1168  },
1169  {
1170   "chips": ["gfx103"],
1171   "map": {"at": 2544, "to": "mm"},
1172   "name": "SQ_WAVE_M0"
1173  },
1174  {
1175   "chips": ["gfx103"],
1176   "map": {"at": 2552, "to": "mm"},
1177   "name": "SQ_WAVE_EXEC_LO"
1178  },
1179  {
1180   "chips": ["gfx103"],
1181   "map": {"at": 2556, "to": "mm"},
1182   "name": "SQ_WAVE_EXEC_HI"
1183  },
1184  {
1185   "chips": ["gfx103"],
1186   "map": {"at": 32776, "to": "mm"},
1187   "name": "GRBM_STATUS2",
1188   "type_ref": "GRBM_STATUS2"
1189  },
1190  {
1191   "chips": ["gfx103"],
1192   "map": {"at": 32784, "to": "mm"},
1193   "name": "GRBM_STATUS",
1194   "type_ref": "GRBM_STATUS"
1195  },
1196  {
1197   "chips": ["gfx103"],
1198   "map": {"at": 32788, "to": "mm"},
1199   "name": "GRBM_STATUS_SE0",
1200   "type_ref": "GRBM_STATUS_SE0"
1201  },
1202  {
1203   "chips": ["gfx103"],
1204   "map": {"at": 32792, "to": "mm"},
1205   "name": "GRBM_STATUS_SE1",
1206   "type_ref": "GRBM_STATUS_SE0"
1207  },
1208  {
1209   "chips": ["gfx103"],
1210   "map": {"at": 32796, "to": "mm"},
1211   "name": "GRBM_STATUS3",
1212   "type_ref": "GRBM_STATUS3"
1213  },
1214  {
1215   "chips": ["gfx103"],
1216   "map": {"at": 32824, "to": "mm"},
1217   "name": "GRBM_STATUS_SE2",
1218   "type_ref": "GRBM_STATUS_SE0"
1219  },
1220  {
1221   "chips": ["gfx103"],
1222   "map": {"at": 32828, "to": "mm"},
1223   "name": "GRBM_STATUS_SE3",
1224   "type_ref": "GRBM_STATUS_SE0"
1225  },
1226  {
1227   "chips": ["gfx103"],
1228   "map": {"at": 33296, "to": "mm"},
1229   "name": "CP_CPC_STATUS",
1230   "type_ref": "CP_CPC_STATUS"
1231  },
1232  {
1233   "chips": ["gfx103"],
1234   "map": {"at": 33300, "to": "mm"},
1235   "name": "CP_CPC_BUSY_STAT",
1236   "type_ref": "CP_CPC_BUSY_STAT"
1237  },
1238  {
1239   "chips": ["gfx103"],
1240   "map": {"at": 33304, "to": "mm"},
1241   "name": "CP_CPC_STALLED_STAT1",
1242   "type_ref": "CP_CPC_STALLED_STAT1"
1243  },
1244  {
1245   "chips": ["gfx103"],
1246   "map": {"at": 33308, "to": "mm"},
1247   "name": "CP_CPF_STATUS",
1248   "type_ref": "CP_CPF_STATUS"
1249  },
1250  {
1251   "chips": ["gfx103"],
1252   "map": {"at": 33312, "to": "mm"},
1253   "name": "CP_CPF_BUSY_STAT",
1254   "type_ref": "CP_CPF_BUSY_STAT"
1255  },
1256  {
1257   "chips": ["gfx103"],
1258   "map": {"at": 33316, "to": "mm"},
1259   "name": "CP_CPF_STALLED_STAT1",
1260   "type_ref": "CP_CPF_STALLED_STAT1"
1261  },
1262  {
1263   "chips": ["gfx103"],
1264   "map": {"at": 33320, "to": "mm"},
1265   "name": "CP_CPC_BUSY_STAT2",
1266   "type_ref": "CP_CPC_BUSY_STAT2"
1267  },
1268  {
1269   "chips": ["gfx103"],
1270   "map": {"at": 33324, "to": "mm"},
1271   "name": "CP_CPC_GRBM_FREE_COUNT",
1272   "type_ref": "CP_CPC_GRBM_FREE_COUNT"
1273  },
1274  {
1275   "chips": ["gfx103"],
1276   "map": {"at": 33328, "to": "mm"},
1277   "name": "CP_CPC_PRIV_VIOLATION_ADDR",
1278   "type_ref": "CP_CPC_PRIV_VIOLATION_ADDR"
1279  },
1280  {
1281   "chips": ["gfx103"],
1282   "map": {"at": 33344, "to": "mm"},
1283   "name": "CP_CPC_SCRATCH_INDEX",
1284   "type_ref": "CP_CPC_SCRATCH_INDEX"
1285  },
1286  {
1287   "chips": ["gfx103"],
1288   "map": {"at": 33348, "to": "mm"},
1289   "name": "CP_CPC_SCRATCH_DATA"
1290  },
1291  {
1292   "chips": ["gfx103"],
1293   "map": {"at": 33352, "to": "mm"},
1294   "name": "CP_CPF_GRBM_FREE_COUNT",
1295   "type_ref": "CP_CPF_GRBM_FREE_COUNT"
1296  },
1297  {
1298   "chips": ["gfx103"],
1299   "map": {"at": 33356, "to": "mm"},
1300   "name": "CP_CPF_BUSY_STAT2",
1301   "type_ref": "CP_CPF_BUSY_STAT2"
1302  },
1303  {
1304   "chips": ["gfx103"],
1305   "map": {"at": 33436, "to": "mm"},
1306   "name": "CP_CPC_HALT_HYST_COUNT",
1307   "type_ref": "CP_CPC_HALT_HYST_COUNT"
1308  },
1309  {
1310   "chips": ["gfx103"],
1311   "map": {"at": 36096, "to": "mm"},
1312   "name": "SQ_THREAD_TRACE_BUF0_BASE"
1313  },
1314  {
1315   "chips": ["gfx103"],
1316   "map": {"at": 36100, "to": "mm"},
1317   "name": "SQ_THREAD_TRACE_BUF0_SIZE",
1318   "type_ref": "SQ_THREAD_TRACE_BUF0_SIZE"
1319  },
1320  {
1321   "chips": ["gfx103"],
1322   "map": {"at": 36104, "to": "mm"},
1323   "name": "SQ_THREAD_TRACE_BUF1_BASE"
1324  },
1325  {
1326   "chips": ["gfx103"],
1327   "map": {"at": 36108, "to": "mm"},
1328   "name": "SQ_THREAD_TRACE_BUF1_SIZE",
1329   "type_ref": "SQ_THREAD_TRACE_BUF0_SIZE"
1330  },
1331  {
1332   "chips": ["gfx103"],
1333   "map": {"at": 36112, "to": "mm"},
1334   "name": "SQ_THREAD_TRACE_WPTR",
1335   "type_ref": "SQ_THREAD_TRACE_WPTR"
1336  },
1337  {
1338   "chips": ["gfx103"],
1339   "map": {"at": 36116, "to": "mm"},
1340   "name": "SQ_THREAD_TRACE_MASK",
1341   "type_ref": "SQ_THREAD_TRACE_MASK"
1342  },
1343  {
1344   "chips": ["gfx103"],
1345   "map": {"at": 36120, "to": "mm"},
1346   "name": "SQ_THREAD_TRACE_TOKEN_MASK",
1347   "type_ref": "SQ_THREAD_TRACE_TOKEN_MASK"
1348  },
1349  {
1350   "chips": ["gfx103"],
1351   "map": {"at": 36124, "to": "mm"},
1352   "name": "SQ_THREAD_TRACE_CTRL",
1353   "type_ref": "SQ_THREAD_TRACE_CTRL"
1354  },
1355  {
1356   "chips": ["gfx103"],
1357   "map": {"at": 36128, "to": "mm"},
1358   "name": "SQ_THREAD_TRACE_STATUS",
1359   "type_ref": "SQ_THREAD_TRACE_STATUS"
1360  },
1361  {
1362   "chips": ["gfx103"],
1363   "map": {"at": 36132, "to": "mm"},
1364   "name": "SQ_THREAD_TRACE_DROPPED_CNTR"
1365  },
1366  {
1367   "chips": ["gfx103"],
1368   "map": {"at": 36140, "to": "mm"},
1369   "name": "SQ_THREAD_TRACE_GFX_DRAW_CNTR"
1370  },
1371  {
1372   "chips": ["gfx103"],
1373   "map": {"at": 36144, "to": "mm"},
1374   "name": "SQ_THREAD_TRACE_GFX_MARKER_CNTR"
1375  },
1376  {
1377   "chips": ["gfx103"],
1378   "map": {"at": 36148, "to": "mm"},
1379   "name": "SQ_THREAD_TRACE_HP3D_DRAW_CNTR"
1380  },
1381  {
1382   "chips": ["gfx103"],
1383   "map": {"at": 36152, "to": "mm"},
1384   "name": "SQ_THREAD_TRACE_HP3D_MARKER_CNTR"
1385  },
1386  {
1387   "chips": ["gfx103"],
1388   "map": {"at": 36156, "to": "mm"},
1389   "name": "SQ_THREAD_TRACE_STATUS2",
1390   "type_ref": "SQ_THREAD_TRACE_STATUS2"
1391  },
1392  {
1393   "chips": ["gfx103"],
1394   "map": {"at": 37168, "to": "mm"},
1395   "name": "SPI_CONFIG_CNTL",
1396   "type_ref": "SPI_CONFIG_CNTL"
1397  },
1398  {
1399   "chips": ["gfx103"],
1400   "map": {"at": 39160, "to": "mm"},
1401   "name": "GB_ADDR_CONFIG",
1402   "type_ref": "GB_ADDR_CONFIG"
1403  },
1404  {
1405   "chips": ["gfx103"],
1406   "map": {"at": 45060, "to": "mm"},
1407   "name": "SPI_SHADER_PGM_RSRC4_PS",
1408   "type_ref": "SPI_SHADER_PGM_RSRC4_PS"
1409  },
1410  {
1411   "chips": ["gfx103"],
1412   "map": {"at": 45080, "to": "mm"},
1413   "name": "SPI_SHADER_PGM_CHKSUM_PS"
1414  },
1415  {
1416   "chips": ["gfx103"],
1417   "map": {"at": 45084, "to": "mm"},
1418   "name": "SPI_SHADER_PGM_RSRC3_PS",
1419   "type_ref": "SPI_SHADER_PGM_RSRC3_PS"
1420  },
1421  {
1422   "chips": ["gfx103"],
1423   "map": {"at": 45088, "to": "mm"},
1424   "name": "SPI_SHADER_PGM_LO_PS"
1425  },
1426  {
1427   "chips": ["gfx103"],
1428   "map": {"at": 45092, "to": "mm"},
1429   "name": "SPI_SHADER_PGM_HI_PS",
1430   "type_ref": "SPI_SHADER_PGM_HI_PS"
1431  },
1432  {
1433   "chips": ["gfx103"],
1434   "map": {"at": 45096, "to": "mm"},
1435   "name": "SPI_SHADER_PGM_RSRC1_PS",
1436   "type_ref": "SPI_SHADER_PGM_RSRC1_PS"
1437  },
1438  {
1439   "chips": ["gfx103"],
1440   "map": {"at": 45100, "to": "mm"},
1441   "name": "SPI_SHADER_PGM_RSRC2_PS",
1442   "type_ref": "SPI_SHADER_PGM_RSRC2_PS"
1443  },
1444  {
1445   "chips": ["gfx103"],
1446   "map": {"at": 45104, "to": "mm"},
1447   "name": "SPI_SHADER_USER_DATA_PS_0"
1448  },
1449  {
1450   "chips": ["gfx103"],
1451   "map": {"at": 45108, "to": "mm"},
1452   "name": "SPI_SHADER_USER_DATA_PS_1"
1453  },
1454  {
1455   "chips": ["gfx103"],
1456   "map": {"at": 45112, "to": "mm"},
1457   "name": "SPI_SHADER_USER_DATA_PS_2"
1458  },
1459  {
1460   "chips": ["gfx103"],
1461   "map": {"at": 45116, "to": "mm"},
1462   "name": "SPI_SHADER_USER_DATA_PS_3"
1463  },
1464  {
1465   "chips": ["gfx103"],
1466   "map": {"at": 45120, "to": "mm"},
1467   "name": "SPI_SHADER_USER_DATA_PS_4"
1468  },
1469  {
1470   "chips": ["gfx103"],
1471   "map": {"at": 45124, "to": "mm"},
1472   "name": "SPI_SHADER_USER_DATA_PS_5"
1473  },
1474  {
1475   "chips": ["gfx103"],
1476   "map": {"at": 45128, "to": "mm"},
1477   "name": "SPI_SHADER_USER_DATA_PS_6"
1478  },
1479  {
1480   "chips": ["gfx103"],
1481   "map": {"at": 45132, "to": "mm"},
1482   "name": "SPI_SHADER_USER_DATA_PS_7"
1483  },
1484  {
1485   "chips": ["gfx103"],
1486   "map": {"at": 45136, "to": "mm"},
1487   "name": "SPI_SHADER_USER_DATA_PS_8"
1488  },
1489  {
1490   "chips": ["gfx103"],
1491   "map": {"at": 45140, "to": "mm"},
1492   "name": "SPI_SHADER_USER_DATA_PS_9"
1493  },
1494  {
1495   "chips": ["gfx103"],
1496   "map": {"at": 45144, "to": "mm"},
1497   "name": "SPI_SHADER_USER_DATA_PS_10"
1498  },
1499  {
1500   "chips": ["gfx103"],
1501   "map": {"at": 45148, "to": "mm"},
1502   "name": "SPI_SHADER_USER_DATA_PS_11"
1503  },
1504  {
1505   "chips": ["gfx103"],
1506   "map": {"at": 45152, "to": "mm"},
1507   "name": "SPI_SHADER_USER_DATA_PS_12"
1508  },
1509  {
1510   "chips": ["gfx103"],
1511   "map": {"at": 45156, "to": "mm"},
1512   "name": "SPI_SHADER_USER_DATA_PS_13"
1513  },
1514  {
1515   "chips": ["gfx103"],
1516   "map": {"at": 45160, "to": "mm"},
1517   "name": "SPI_SHADER_USER_DATA_PS_14"
1518  },
1519  {
1520   "chips": ["gfx103"],
1521   "map": {"at": 45164, "to": "mm"},
1522   "name": "SPI_SHADER_USER_DATA_PS_15"
1523  },
1524  {
1525   "chips": ["gfx103"],
1526   "map": {"at": 45168, "to": "mm"},
1527   "name": "SPI_SHADER_USER_DATA_PS_16"
1528  },
1529  {
1530   "chips": ["gfx103"],
1531   "map": {"at": 45172, "to": "mm"},
1532   "name": "SPI_SHADER_USER_DATA_PS_17"
1533  },
1534  {
1535   "chips": ["gfx103"],
1536   "map": {"at": 45176, "to": "mm"},
1537   "name": "SPI_SHADER_USER_DATA_PS_18"
1538  },
1539  {
1540   "chips": ["gfx103"],
1541   "map": {"at": 45180, "to": "mm"},
1542   "name": "SPI_SHADER_USER_DATA_PS_19"
1543  },
1544  {
1545   "chips": ["gfx103"],
1546   "map": {"at": 45184, "to": "mm"},
1547   "name": "SPI_SHADER_USER_DATA_PS_20"
1548  },
1549  {
1550   "chips": ["gfx103"],
1551   "map": {"at": 45188, "to": "mm"},
1552   "name": "SPI_SHADER_USER_DATA_PS_21"
1553  },
1554  {
1555   "chips": ["gfx103"],
1556   "map": {"at": 45192, "to": "mm"},
1557   "name": "SPI_SHADER_USER_DATA_PS_22"
1558  },
1559  {
1560   "chips": ["gfx103"],
1561   "map": {"at": 45196, "to": "mm"},
1562   "name": "SPI_SHADER_USER_DATA_PS_23"
1563  },
1564  {
1565   "chips": ["gfx103"],
1566   "map": {"at": 45200, "to": "mm"},
1567   "name": "SPI_SHADER_USER_DATA_PS_24"
1568  },
1569  {
1570   "chips": ["gfx103"],
1571   "map": {"at": 45204, "to": "mm"},
1572   "name": "SPI_SHADER_USER_DATA_PS_25"
1573  },
1574  {
1575   "chips": ["gfx103"],
1576   "map": {"at": 45208, "to": "mm"},
1577   "name": "SPI_SHADER_USER_DATA_PS_26"
1578  },
1579  {
1580   "chips": ["gfx103"],
1581   "map": {"at": 45212, "to": "mm"},
1582   "name": "SPI_SHADER_USER_DATA_PS_27"
1583  },
1584  {
1585   "chips": ["gfx103"],
1586   "map": {"at": 45216, "to": "mm"},
1587   "name": "SPI_SHADER_USER_DATA_PS_28"
1588  },
1589  {
1590   "chips": ["gfx103"],
1591   "map": {"at": 45220, "to": "mm"},
1592   "name": "SPI_SHADER_USER_DATA_PS_29"
1593  },
1594  {
1595   "chips": ["gfx103"],
1596   "map": {"at": 45224, "to": "mm"},
1597   "name": "SPI_SHADER_USER_DATA_PS_30"
1598  },
1599  {
1600   "chips": ["gfx103"],
1601   "map": {"at": 45228, "to": "mm"},
1602   "name": "SPI_SHADER_USER_DATA_PS_31"
1603  },
1604  {
1605   "chips": ["gfx103"],
1606   "map": {"at": 45248, "to": "mm"},
1607   "name": "SPI_SHADER_REQ_CTRL_PS",
1608   "type_ref": "SPI_SHADER_REQ_CTRL_PS"
1609  },
1610  {
1611   "chips": ["gfx103"],
1612   "map": {"at": 45256, "to": "mm"},
1613   "name": "SPI_SHADER_USER_ACCUM_PS_0",
1614   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
1615  },
1616  {
1617   "chips": ["gfx103"],
1618   "map": {"at": 45260, "to": "mm"},
1619   "name": "SPI_SHADER_USER_ACCUM_PS_1",
1620   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
1621  },
1622  {
1623   "chips": ["gfx103"],
1624   "map": {"at": 45264, "to": "mm"},
1625   "name": "SPI_SHADER_USER_ACCUM_PS_2",
1626   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
1627  },
1628  {
1629   "chips": ["gfx103"],
1630   "map": {"at": 45268, "to": "mm"},
1631   "name": "SPI_SHADER_USER_ACCUM_PS_3",
1632   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
1633  },
1634  {
1635   "chips": ["gfx103"],
1636   "map": {"at": 45316, "to": "mm"},
1637   "name": "SPI_SHADER_PGM_RSRC4_VS",
1638   "type_ref": "SPI_SHADER_PGM_RSRC4_PS"
1639  },
1640  {
1641   "chips": ["gfx103"],
1642   "map": {"at": 45332, "to": "mm"},
1643   "name": "SPI_SHADER_PGM_CHKSUM_VS"
1644  },
1645  {
1646   "chips": ["gfx103"],
1647   "map": {"at": 45336, "to": "mm"},
1648   "name": "SPI_SHADER_PGM_RSRC3_VS",
1649   "type_ref": "SPI_SHADER_PGM_RSRC3_PS"
1650  },
1651  {
1652   "chips": ["gfx103"],
1653   "map": {"at": 45340, "to": "mm"},
1654   "name": "SPI_SHADER_LATE_ALLOC_VS",
1655   "type_ref": "SPI_SHADER_LATE_ALLOC_VS"
1656  },
1657  {
1658   "chips": ["gfx103"],
1659   "map": {"at": 45344, "to": "mm"},
1660   "name": "SPI_SHADER_PGM_LO_VS"
1661  },
1662  {
1663   "chips": ["gfx103"],
1664   "map": {"at": 45348, "to": "mm"},
1665   "name": "SPI_SHADER_PGM_HI_VS",
1666   "type_ref": "SPI_SHADER_PGM_HI_PS"
1667  },
1668  {
1669   "chips": ["gfx103"],
1670   "map": {"at": 45352, "to": "mm"},
1671   "name": "SPI_SHADER_PGM_RSRC1_VS",
1672   "type_ref": "SPI_SHADER_PGM_RSRC1_VS"
1673  },
1674  {
1675   "chips": ["gfx103"],
1676   "map": {"at": 45356, "to": "mm"},
1677   "name": "SPI_SHADER_PGM_RSRC2_VS",
1678   "type_ref": "SPI_SHADER_PGM_RSRC2_VS"
1679  },
1680  {
1681   "chips": ["gfx103"],
1682   "map": {"at": 45360, "to": "mm"},
1683   "name": "SPI_SHADER_USER_DATA_VS_0"
1684  },
1685  {
1686   "chips": ["gfx103"],
1687   "map": {"at": 45364, "to": "mm"},
1688   "name": "SPI_SHADER_USER_DATA_VS_1"
1689  },
1690  {
1691   "chips": ["gfx103"],
1692   "map": {"at": 45368, "to": "mm"},
1693   "name": "SPI_SHADER_USER_DATA_VS_2"
1694  },
1695  {
1696   "chips": ["gfx103"],
1697   "map": {"at": 45372, "to": "mm"},
1698   "name": "SPI_SHADER_USER_DATA_VS_3"
1699  },
1700  {
1701   "chips": ["gfx103"],
1702   "map": {"at": 45376, "to": "mm"},
1703   "name": "SPI_SHADER_USER_DATA_VS_4"
1704  },
1705  {
1706   "chips": ["gfx103"],
1707   "map": {"at": 45380, "to": "mm"},
1708   "name": "SPI_SHADER_USER_DATA_VS_5"
1709  },
1710  {
1711   "chips": ["gfx103"],
1712   "map": {"at": 45384, "to": "mm"},
1713   "name": "SPI_SHADER_USER_DATA_VS_6"
1714  },
1715  {
1716   "chips": ["gfx103"],
1717   "map": {"at": 45388, "to": "mm"},
1718   "name": "SPI_SHADER_USER_DATA_VS_7"
1719  },
1720  {
1721   "chips": ["gfx103"],
1722   "map": {"at": 45392, "to": "mm"},
1723   "name": "SPI_SHADER_USER_DATA_VS_8"
1724  },
1725  {
1726   "chips": ["gfx103"],
1727   "map": {"at": 45396, "to": "mm"},
1728   "name": "SPI_SHADER_USER_DATA_VS_9"
1729  },
1730  {
1731   "chips": ["gfx103"],
1732   "map": {"at": 45400, "to": "mm"},
1733   "name": "SPI_SHADER_USER_DATA_VS_10"
1734  },
1735  {
1736   "chips": ["gfx103"],
1737   "map": {"at": 45404, "to": "mm"},
1738   "name": "SPI_SHADER_USER_DATA_VS_11"
1739  },
1740  {
1741   "chips": ["gfx103"],
1742   "map": {"at": 45408, "to": "mm"},
1743   "name": "SPI_SHADER_USER_DATA_VS_12"
1744  },
1745  {
1746   "chips": ["gfx103"],
1747   "map": {"at": 45412, "to": "mm"},
1748   "name": "SPI_SHADER_USER_DATA_VS_13"
1749  },
1750  {
1751   "chips": ["gfx103"],
1752   "map": {"at": 45416, "to": "mm"},
1753   "name": "SPI_SHADER_USER_DATA_VS_14"
1754  },
1755  {
1756   "chips": ["gfx103"],
1757   "map": {"at": 45420, "to": "mm"},
1758   "name": "SPI_SHADER_USER_DATA_VS_15"
1759  },
1760  {
1761   "chips": ["gfx103"],
1762   "map": {"at": 45424, "to": "mm"},
1763   "name": "SPI_SHADER_USER_DATA_VS_16"
1764  },
1765  {
1766   "chips": ["gfx103"],
1767   "map": {"at": 45428, "to": "mm"},
1768   "name": "SPI_SHADER_USER_DATA_VS_17"
1769  },
1770  {
1771   "chips": ["gfx103"],
1772   "map": {"at": 45432, "to": "mm"},
1773   "name": "SPI_SHADER_USER_DATA_VS_18"
1774  },
1775  {
1776   "chips": ["gfx103"],
1777   "map": {"at": 45436, "to": "mm"},
1778   "name": "SPI_SHADER_USER_DATA_VS_19"
1779  },
1780  {
1781   "chips": ["gfx103"],
1782   "map": {"at": 45440, "to": "mm"},
1783   "name": "SPI_SHADER_USER_DATA_VS_20"
1784  },
1785  {
1786   "chips": ["gfx103"],
1787   "map": {"at": 45444, "to": "mm"},
1788   "name": "SPI_SHADER_USER_DATA_VS_21"
1789  },
1790  {
1791   "chips": ["gfx103"],
1792   "map": {"at": 45448, "to": "mm"},
1793   "name": "SPI_SHADER_USER_DATA_VS_22"
1794  },
1795  {
1796   "chips": ["gfx103"],
1797   "map": {"at": 45452, "to": "mm"},
1798   "name": "SPI_SHADER_USER_DATA_VS_23"
1799  },
1800  {
1801   "chips": ["gfx103"],
1802   "map": {"at": 45456, "to": "mm"},
1803   "name": "SPI_SHADER_USER_DATA_VS_24"
1804  },
1805  {
1806   "chips": ["gfx103"],
1807   "map": {"at": 45460, "to": "mm"},
1808   "name": "SPI_SHADER_USER_DATA_VS_25"
1809  },
1810  {
1811   "chips": ["gfx103"],
1812   "map": {"at": 45464, "to": "mm"},
1813   "name": "SPI_SHADER_USER_DATA_VS_26"
1814  },
1815  {
1816   "chips": ["gfx103"],
1817   "map": {"at": 45468, "to": "mm"},
1818   "name": "SPI_SHADER_USER_DATA_VS_27"
1819  },
1820  {
1821   "chips": ["gfx103"],
1822   "map": {"at": 45472, "to": "mm"},
1823   "name": "SPI_SHADER_USER_DATA_VS_28"
1824  },
1825  {
1826   "chips": ["gfx103"],
1827   "map": {"at": 45476, "to": "mm"},
1828   "name": "SPI_SHADER_USER_DATA_VS_29"
1829  },
1830  {
1831   "chips": ["gfx103"],
1832   "map": {"at": 45480, "to": "mm"},
1833   "name": "SPI_SHADER_USER_DATA_VS_30"
1834  },
1835  {
1836   "chips": ["gfx103"],
1837   "map": {"at": 45484, "to": "mm"},
1838   "name": "SPI_SHADER_USER_DATA_VS_31"
1839  },
1840  {
1841   "chips": ["gfx103"],
1842   "map": {"at": 45504, "to": "mm"},
1843   "name": "SPI_SHADER_REQ_CTRL_VS",
1844   "type_ref": "SPI_SHADER_REQ_CTRL_PS"
1845  },
1846  {
1847   "chips": ["gfx103"],
1848   "map": {"at": 45512, "to": "mm"},
1849   "name": "SPI_SHADER_USER_ACCUM_VS_0",
1850   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
1851  },
1852  {
1853   "chips": ["gfx103"],
1854   "map": {"at": 45516, "to": "mm"},
1855   "name": "SPI_SHADER_USER_ACCUM_VS_1",
1856   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
1857  },
1858  {
1859   "chips": ["gfx103"],
1860   "map": {"at": 45520, "to": "mm"},
1861   "name": "SPI_SHADER_USER_ACCUM_VS_2",
1862   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
1863  },
1864  {
1865   "chips": ["gfx103"],
1866   "map": {"at": 45524, "to": "mm"},
1867   "name": "SPI_SHADER_USER_ACCUM_VS_3",
1868   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
1869  },
1870  {
1871   "chips": ["gfx103"],
1872   "map": {"at": 45548, "to": "mm"},
1873   "name": "SPI_SHADER_PGM_RSRC2_GS_VS",
1874   "type_ref": "SPI_SHADER_PGM_RSRC2_GS_VS"
1875  },
1876  {
1877   "chips": ["gfx103"],
1878   "map": {"at": 45568, "to": "mm"},
1879   "name": "SPI_SHADER_PGM_CHKSUM_GS"
1880  },
1881  {
1882   "chips": ["gfx103"],
1883   "map": {"at": 45572, "to": "mm"},
1884   "name": "SPI_SHADER_PGM_RSRC4_GS",
1885   "type_ref": "SPI_SHADER_PGM_RSRC4_GS"
1886  },
1887  {
1888   "chips": ["gfx103"],
1889   "map": {"at": 45576, "to": "mm"},
1890   "name": "SPI_SHADER_USER_DATA_ADDR_LO_GS"
1891  },
1892  {
1893   "chips": ["gfx103"],
1894   "map": {"at": 45580, "to": "mm"},
1895   "name": "SPI_SHADER_USER_DATA_ADDR_HI_GS"
1896  },
1897  {
1898   "chips": ["gfx103"],
1899   "map": {"at": 45584, "to": "mm"},
1900   "name": "SPI_SHADER_PGM_LO_ES_GS"
1901  },
1902  {
1903   "chips": ["gfx103"],
1904   "map": {"at": 45588, "to": "mm"},
1905   "name": "SPI_SHADER_PGM_HI_ES_GS",
1906   "type_ref": "SPI_SHADER_PGM_HI_PS"
1907  },
1908  {
1909   "chips": ["gfx103"],
1910   "map": {"at": 45596, "to": "mm"},
1911   "name": "SPI_SHADER_PGM_RSRC3_GS",
1912   "type_ref": "SPI_SHADER_PGM_RSRC3_GS"
1913  },
1914  {
1915   "chips": ["gfx103"],
1916   "map": {"at": 45600, "to": "mm"},
1917   "name": "SPI_SHADER_PGM_LO_GS"
1918  },
1919  {
1920   "chips": ["gfx103"],
1921   "map": {"at": 45604, "to": "mm"},
1922   "name": "SPI_SHADER_PGM_HI_GS",
1923   "type_ref": "SPI_SHADER_PGM_HI_PS"
1924  },
1925  {
1926   "chips": ["gfx103"],
1927   "map": {"at": 45608, "to": "mm"},
1928   "name": "SPI_SHADER_PGM_RSRC1_GS",
1929   "type_ref": "SPI_SHADER_PGM_RSRC1_GS"
1930  },
1931  {
1932   "chips": ["gfx103"],
1933   "map": {"at": 45612, "to": "mm"},
1934   "name": "SPI_SHADER_PGM_RSRC2_GS",
1935   "type_ref": "SPI_SHADER_PGM_RSRC2_GS"
1936  },
1937  {
1938   "chips": ["gfx103"],
1939   "map": {"at": 45616, "to": "mm"},
1940   "name": "SPI_SHADER_USER_DATA_GS_0"
1941  },
1942  {
1943   "chips": ["gfx103"],
1944   "map": {"at": 45620, "to": "mm"},
1945   "name": "SPI_SHADER_USER_DATA_GS_1"
1946  },
1947  {
1948   "chips": ["gfx103"],
1949   "map": {"at": 45624, "to": "mm"},
1950   "name": "SPI_SHADER_USER_DATA_GS_2"
1951  },
1952  {
1953   "chips": ["gfx103"],
1954   "map": {"at": 45628, "to": "mm"},
1955   "name": "SPI_SHADER_USER_DATA_GS_3"
1956  },
1957  {
1958   "chips": ["gfx103"],
1959   "map": {"at": 45632, "to": "mm"},
1960   "name": "SPI_SHADER_USER_DATA_GS_4"
1961  },
1962  {
1963   "chips": ["gfx103"],
1964   "map": {"at": 45636, "to": "mm"},
1965   "name": "SPI_SHADER_USER_DATA_GS_5"
1966  },
1967  {
1968   "chips": ["gfx103"],
1969   "map": {"at": 45640, "to": "mm"},
1970   "name": "SPI_SHADER_USER_DATA_GS_6"
1971  },
1972  {
1973   "chips": ["gfx103"],
1974   "map": {"at": 45644, "to": "mm"},
1975   "name": "SPI_SHADER_USER_DATA_GS_7"
1976  },
1977  {
1978   "chips": ["gfx103"],
1979   "map": {"at": 45648, "to": "mm"},
1980   "name": "SPI_SHADER_USER_DATA_GS_8"
1981  },
1982  {
1983   "chips": ["gfx103"],
1984   "map": {"at": 45652, "to": "mm"},
1985   "name": "SPI_SHADER_USER_DATA_GS_9"
1986  },
1987  {
1988   "chips": ["gfx103"],
1989   "map": {"at": 45656, "to": "mm"},
1990   "name": "SPI_SHADER_USER_DATA_GS_10"
1991  },
1992  {
1993   "chips": ["gfx103"],
1994   "map": {"at": 45660, "to": "mm"},
1995   "name": "SPI_SHADER_USER_DATA_GS_11"
1996  },
1997  {
1998   "chips": ["gfx103"],
1999   "map": {"at": 45664, "to": "mm"},
2000   "name": "SPI_SHADER_USER_DATA_GS_12"
2001  },
2002  {
2003   "chips": ["gfx103"],
2004   "map": {"at": 45668, "to": "mm"},
2005   "name": "SPI_SHADER_USER_DATA_GS_13"
2006  },
2007  {
2008   "chips": ["gfx103"],
2009   "map": {"at": 45672, "to": "mm"},
2010   "name": "SPI_SHADER_USER_DATA_GS_14"
2011  },
2012  {
2013   "chips": ["gfx103"],
2014   "map": {"at": 45676, "to": "mm"},
2015   "name": "SPI_SHADER_USER_DATA_GS_15"
2016  },
2017  {
2018   "chips": ["gfx103"],
2019   "map": {"at": 45680, "to": "mm"},
2020   "name": "SPI_SHADER_USER_DATA_GS_16"
2021  },
2022  {
2023   "chips": ["gfx103"],
2024   "map": {"at": 45684, "to": "mm"},
2025   "name": "SPI_SHADER_USER_DATA_GS_17"
2026  },
2027  {
2028   "chips": ["gfx103"],
2029   "map": {"at": 45688, "to": "mm"},
2030   "name": "SPI_SHADER_USER_DATA_GS_18"
2031  },
2032  {
2033   "chips": ["gfx103"],
2034   "map": {"at": 45692, "to": "mm"},
2035   "name": "SPI_SHADER_USER_DATA_GS_19"
2036  },
2037  {
2038   "chips": ["gfx103"],
2039   "map": {"at": 45696, "to": "mm"},
2040   "name": "SPI_SHADER_USER_DATA_GS_20"
2041  },
2042  {
2043   "chips": ["gfx103"],
2044   "map": {"at": 45700, "to": "mm"},
2045   "name": "SPI_SHADER_USER_DATA_GS_21"
2046  },
2047  {
2048   "chips": ["gfx103"],
2049   "map": {"at": 45704, "to": "mm"},
2050   "name": "SPI_SHADER_USER_DATA_GS_22"
2051  },
2052  {
2053   "chips": ["gfx103"],
2054   "map": {"at": 45708, "to": "mm"},
2055   "name": "SPI_SHADER_USER_DATA_GS_23"
2056  },
2057  {
2058   "chips": ["gfx103"],
2059   "map": {"at": 45712, "to": "mm"},
2060   "name": "SPI_SHADER_USER_DATA_GS_24"
2061  },
2062  {
2063   "chips": ["gfx103"],
2064   "map": {"at": 45716, "to": "mm"},
2065   "name": "SPI_SHADER_USER_DATA_GS_25"
2066  },
2067  {
2068   "chips": ["gfx103"],
2069   "map": {"at": 45720, "to": "mm"},
2070   "name": "SPI_SHADER_USER_DATA_GS_26"
2071  },
2072  {
2073   "chips": ["gfx103"],
2074   "map": {"at": 45724, "to": "mm"},
2075   "name": "SPI_SHADER_USER_DATA_GS_27"
2076  },
2077  {
2078   "chips": ["gfx103"],
2079   "map": {"at": 45728, "to": "mm"},
2080   "name": "SPI_SHADER_USER_DATA_GS_28"
2081  },
2082  {
2083   "chips": ["gfx103"],
2084   "map": {"at": 45732, "to": "mm"},
2085   "name": "SPI_SHADER_USER_DATA_GS_29"
2086  },
2087  {
2088   "chips": ["gfx103"],
2089   "map": {"at": 45736, "to": "mm"},
2090   "name": "SPI_SHADER_USER_DATA_GS_30"
2091  },
2092  {
2093   "chips": ["gfx103"],
2094   "map": {"at": 45740, "to": "mm"},
2095   "name": "SPI_SHADER_USER_DATA_GS_31"
2096  },
2097  {
2098   "chips": ["gfx103"],
2099   "map": {"at": 45760, "to": "mm"},
2100   "name": "SPI_SHADER_REQ_CTRL_ESGS",
2101   "type_ref": "SPI_SHADER_REQ_CTRL_PS"
2102  },
2103  {
2104   "chips": ["gfx103"],
2105   "map": {"at": 45768, "to": "mm"},
2106   "name": "SPI_SHADER_USER_ACCUM_ESGS_0",
2107   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2108  },
2109  {
2110   "chips": ["gfx103"],
2111   "map": {"at": 45772, "to": "mm"},
2112   "name": "SPI_SHADER_USER_ACCUM_ESGS_1",
2113   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2114  },
2115  {
2116   "chips": ["gfx103"],
2117   "map": {"at": 45776, "to": "mm"},
2118   "name": "SPI_SHADER_USER_ACCUM_ESGS_2",
2119   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2120  },
2121  {
2122   "chips": ["gfx103"],
2123   "map": {"at": 45780, "to": "mm"},
2124   "name": "SPI_SHADER_USER_ACCUM_ESGS_3",
2125   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2126  },
2127  {
2128   "chips": ["gfx103"],
2129   "map": {"at": 45856, "to": "mm"},
2130   "name": "SPI_SHADER_PGM_LO_ES"
2131  },
2132  {
2133   "chips": ["gfx103"],
2134   "map": {"at": 45860, "to": "mm"},
2135   "name": "SPI_SHADER_PGM_HI_ES",
2136   "type_ref": "SPI_SHADER_PGM_HI_PS"
2137  },
2138  {
2139   "chips": ["gfx103"],
2140   "map": {"at": 46080, "to": "mm"},
2141   "name": "SPI_SHADER_PGM_CHKSUM_HS"
2142  },
2143  {
2144   "chips": ["gfx103"],
2145   "map": {"at": 46084, "to": "mm"},
2146   "name": "SPI_SHADER_PGM_RSRC4_HS",
2147   "type_ref": "SPI_SHADER_PGM_RSRC4_PS"
2148  },
2149  {
2150   "chips": ["gfx103"],
2151   "map": {"at": 46088, "to": "mm"},
2152   "name": "SPI_SHADER_USER_DATA_ADDR_LO_HS"
2153  },
2154  {
2155   "chips": ["gfx103"],
2156   "map": {"at": 46092, "to": "mm"},
2157   "name": "SPI_SHADER_USER_DATA_ADDR_HI_HS"
2158  },
2159  {
2160   "chips": ["gfx103"],
2161   "map": {"at": 46096, "to": "mm"},
2162   "name": "SPI_SHADER_PGM_LO_LS_HS"
2163  },
2164  {
2165   "chips": ["gfx103"],
2166   "map": {"at": 46100, "to": "mm"},
2167   "name": "SPI_SHADER_PGM_HI_LS_HS",
2168   "type_ref": "SPI_SHADER_PGM_HI_PS"
2169  },
2170  {
2171   "chips": ["gfx103"],
2172   "map": {"at": 46108, "to": "mm"},
2173   "name": "SPI_SHADER_PGM_RSRC3_HS",
2174   "type_ref": "SPI_SHADER_PGM_RSRC3_HS"
2175  },
2176  {
2177   "chips": ["gfx103"],
2178   "map": {"at": 46112, "to": "mm"},
2179   "name": "SPI_SHADER_PGM_LO_HS"
2180  },
2181  {
2182   "chips": ["gfx103"],
2183   "map": {"at": 46116, "to": "mm"},
2184   "name": "SPI_SHADER_PGM_HI_HS",
2185   "type_ref": "SPI_SHADER_PGM_HI_PS"
2186  },
2187  {
2188   "chips": ["gfx103"],
2189   "map": {"at": 46120, "to": "mm"},
2190   "name": "SPI_SHADER_PGM_RSRC1_HS",
2191   "type_ref": "SPI_SHADER_PGM_RSRC1_HS"
2192  },
2193  {
2194   "chips": ["gfx103"],
2195   "map": {"at": 46124, "to": "mm"},
2196   "name": "SPI_SHADER_PGM_RSRC2_HS",
2197   "type_ref": "SPI_SHADER_PGM_RSRC2_HS"
2198  },
2199  {
2200   "chips": ["gfx103"],
2201   "map": {"at": 46128, "to": "mm"},
2202   "name": "SPI_SHADER_USER_DATA_HS_0"
2203  },
2204  {
2205   "chips": ["gfx103"],
2206   "map": {"at": 46132, "to": "mm"},
2207   "name": "SPI_SHADER_USER_DATA_HS_1"
2208  },
2209  {
2210   "chips": ["gfx103"],
2211   "map": {"at": 46136, "to": "mm"},
2212   "name": "SPI_SHADER_USER_DATA_HS_2"
2213  },
2214  {
2215   "chips": ["gfx103"],
2216   "map": {"at": 46140, "to": "mm"},
2217   "name": "SPI_SHADER_USER_DATA_HS_3"
2218  },
2219  {
2220   "chips": ["gfx103"],
2221   "map": {"at": 46144, "to": "mm"},
2222   "name": "SPI_SHADER_USER_DATA_HS_4"
2223  },
2224  {
2225   "chips": ["gfx103"],
2226   "map": {"at": 46148, "to": "mm"},
2227   "name": "SPI_SHADER_USER_DATA_HS_5"
2228  },
2229  {
2230   "chips": ["gfx103"],
2231   "map": {"at": 46152, "to": "mm"},
2232   "name": "SPI_SHADER_USER_DATA_HS_6"
2233  },
2234  {
2235   "chips": ["gfx103"],
2236   "map": {"at": 46156, "to": "mm"},
2237   "name": "SPI_SHADER_USER_DATA_HS_7"
2238  },
2239  {
2240   "chips": ["gfx103"],
2241   "map": {"at": 46160, "to": "mm"},
2242   "name": "SPI_SHADER_USER_DATA_HS_8"
2243  },
2244  {
2245   "chips": ["gfx103"],
2246   "map": {"at": 46164, "to": "mm"},
2247   "name": "SPI_SHADER_USER_DATA_HS_9"
2248  },
2249  {
2250   "chips": ["gfx103"],
2251   "map": {"at": 46168, "to": "mm"},
2252   "name": "SPI_SHADER_USER_DATA_HS_10"
2253  },
2254  {
2255   "chips": ["gfx103"],
2256   "map": {"at": 46172, "to": "mm"},
2257   "name": "SPI_SHADER_USER_DATA_HS_11"
2258  },
2259  {
2260   "chips": ["gfx103"],
2261   "map": {"at": 46176, "to": "mm"},
2262   "name": "SPI_SHADER_USER_DATA_HS_12"
2263  },
2264  {
2265   "chips": ["gfx103"],
2266   "map": {"at": 46180, "to": "mm"},
2267   "name": "SPI_SHADER_USER_DATA_HS_13"
2268  },
2269  {
2270   "chips": ["gfx103"],
2271   "map": {"at": 46184, "to": "mm"},
2272   "name": "SPI_SHADER_USER_DATA_HS_14"
2273  },
2274  {
2275   "chips": ["gfx103"],
2276   "map": {"at": 46188, "to": "mm"},
2277   "name": "SPI_SHADER_USER_DATA_HS_15"
2278  },
2279  {
2280   "chips": ["gfx103"],
2281   "map": {"at": 46192, "to": "mm"},
2282   "name": "SPI_SHADER_USER_DATA_HS_16"
2283  },
2284  {
2285   "chips": ["gfx103"],
2286   "map": {"at": 46196, "to": "mm"},
2287   "name": "SPI_SHADER_USER_DATA_HS_17"
2288  },
2289  {
2290   "chips": ["gfx103"],
2291   "map": {"at": 46200, "to": "mm"},
2292   "name": "SPI_SHADER_USER_DATA_HS_18"
2293  },
2294  {
2295   "chips": ["gfx103"],
2296   "map": {"at": 46204, "to": "mm"},
2297   "name": "SPI_SHADER_USER_DATA_HS_19"
2298  },
2299  {
2300   "chips": ["gfx103"],
2301   "map": {"at": 46208, "to": "mm"},
2302   "name": "SPI_SHADER_USER_DATA_HS_20"
2303  },
2304  {
2305   "chips": ["gfx103"],
2306   "map": {"at": 46212, "to": "mm"},
2307   "name": "SPI_SHADER_USER_DATA_HS_21"
2308  },
2309  {
2310   "chips": ["gfx103"],
2311   "map": {"at": 46216, "to": "mm"},
2312   "name": "SPI_SHADER_USER_DATA_HS_22"
2313  },
2314  {
2315   "chips": ["gfx103"],
2316   "map": {"at": 46220, "to": "mm"},
2317   "name": "SPI_SHADER_USER_DATA_HS_23"
2318  },
2319  {
2320   "chips": ["gfx103"],
2321   "map": {"at": 46224, "to": "mm"},
2322   "name": "SPI_SHADER_USER_DATA_HS_24"
2323  },
2324  {
2325   "chips": ["gfx103"],
2326   "map": {"at": 46228, "to": "mm"},
2327   "name": "SPI_SHADER_USER_DATA_HS_25"
2328  },
2329  {
2330   "chips": ["gfx103"],
2331   "map": {"at": 46232, "to": "mm"},
2332   "name": "SPI_SHADER_USER_DATA_HS_26"
2333  },
2334  {
2335   "chips": ["gfx103"],
2336   "map": {"at": 46236, "to": "mm"},
2337   "name": "SPI_SHADER_USER_DATA_HS_27"
2338  },
2339  {
2340   "chips": ["gfx103"],
2341   "map": {"at": 46240, "to": "mm"},
2342   "name": "SPI_SHADER_USER_DATA_HS_28"
2343  },
2344  {
2345   "chips": ["gfx103"],
2346   "map": {"at": 46244, "to": "mm"},
2347   "name": "SPI_SHADER_USER_DATA_HS_29"
2348  },
2349  {
2350   "chips": ["gfx103"],
2351   "map": {"at": 46248, "to": "mm"},
2352   "name": "SPI_SHADER_USER_DATA_HS_30"
2353  },
2354  {
2355   "chips": ["gfx103"],
2356   "map": {"at": 46252, "to": "mm"},
2357   "name": "SPI_SHADER_USER_DATA_HS_31"
2358  },
2359  {
2360   "chips": ["gfx103"],
2361   "map": {"at": 46272, "to": "mm"},
2362   "name": "SPI_SHADER_REQ_CTRL_LSHS",
2363   "type_ref": "SPI_SHADER_REQ_CTRL_PS"
2364  },
2365  {
2366   "chips": ["gfx103"],
2367   "map": {"at": 46280, "to": "mm"},
2368   "name": "SPI_SHADER_USER_ACCUM_LSHS_0",
2369   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2370  },
2371  {
2372   "chips": ["gfx103"],
2373   "map": {"at": 46284, "to": "mm"},
2374   "name": "SPI_SHADER_USER_ACCUM_LSHS_1",
2375   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2376  },
2377  {
2378   "chips": ["gfx103"],
2379   "map": {"at": 46288, "to": "mm"},
2380   "name": "SPI_SHADER_USER_ACCUM_LSHS_2",
2381   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2382  },
2383  {
2384   "chips": ["gfx103"],
2385   "map": {"at": 46292, "to": "mm"},
2386   "name": "SPI_SHADER_USER_ACCUM_LSHS_3",
2387   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2388  },
2389  {
2390   "chips": ["gfx103"],
2391   "map": {"at": 46368, "to": "mm"},
2392   "name": "SPI_SHADER_PGM_LO_LS"
2393  },
2394  {
2395   "chips": ["gfx103"],
2396   "map": {"at": 46372, "to": "mm"},
2397   "name": "SPI_SHADER_PGM_HI_LS",
2398   "type_ref": "SPI_SHADER_PGM_HI_PS"
2399  },
2400  {
2401   "chips": ["gfx103"],
2402   "map": {"at": 47104, "to": "mm"},
2403   "name": "COMPUTE_DISPATCH_INITIATOR",
2404   "type_ref": "COMPUTE_DISPATCH_INITIATOR"
2405  },
2406  {
2407   "chips": ["gfx103"],
2408   "map": {"at": 47108, "to": "mm"},
2409   "name": "COMPUTE_DIM_X"
2410  },
2411  {
2412   "chips": ["gfx103"],
2413   "map": {"at": 47112, "to": "mm"},
2414   "name": "COMPUTE_DIM_Y"
2415  },
2416  {
2417   "chips": ["gfx103"],
2418   "map": {"at": 47116, "to": "mm"},
2419   "name": "COMPUTE_DIM_Z"
2420  },
2421  {
2422   "chips": ["gfx103"],
2423   "map": {"at": 47120, "to": "mm"},
2424   "name": "COMPUTE_START_X"
2425  },
2426  {
2427   "chips": ["gfx103"],
2428   "map": {"at": 47124, "to": "mm"},
2429   "name": "COMPUTE_START_Y"
2430  },
2431  {
2432   "chips": ["gfx103"],
2433   "map": {"at": 47128, "to": "mm"},
2434   "name": "COMPUTE_START_Z"
2435  },
2436  {
2437   "chips": ["gfx103"],
2438   "map": {"at": 47132, "to": "mm"},
2439   "name": "COMPUTE_NUM_THREAD_X",
2440   "type_ref": "COMPUTE_NUM_THREAD_X"
2441  },
2442  {
2443   "chips": ["gfx103"],
2444   "map": {"at": 47136, "to": "mm"},
2445   "name": "COMPUTE_NUM_THREAD_Y",
2446   "type_ref": "COMPUTE_NUM_THREAD_X"
2447  },
2448  {
2449   "chips": ["gfx103"],
2450   "map": {"at": 47140, "to": "mm"},
2451   "name": "COMPUTE_NUM_THREAD_Z",
2452   "type_ref": "COMPUTE_NUM_THREAD_X"
2453  },
2454  {
2455   "chips": ["gfx103"],
2456   "map": {"at": 47144, "to": "mm"},
2457   "name": "COMPUTE_PIPELINESTAT_ENABLE",
2458   "type_ref": "COMPUTE_PIPELINESTAT_ENABLE"
2459  },
2460  {
2461   "chips": ["gfx103"],
2462   "map": {"at": 47148, "to": "mm"},
2463   "name": "COMPUTE_PERFCOUNT_ENABLE",
2464   "type_ref": "COMPUTE_PERFCOUNT_ENABLE"
2465  },
2466  {
2467   "chips": ["gfx103"],
2468   "map": {"at": 47152, "to": "mm"},
2469   "name": "COMPUTE_PGM_LO"
2470  },
2471  {
2472   "chips": ["gfx103"],
2473   "map": {"at": 47156, "to": "mm"},
2474   "name": "COMPUTE_PGM_HI",
2475   "type_ref": "COMPUTE_PGM_HI"
2476  },
2477  {
2478   "chips": ["gfx103"],
2479   "map": {"at": 47160, "to": "mm"},
2480   "name": "COMPUTE_DISPATCH_PKT_ADDR_LO"
2481  },
2482  {
2483   "chips": ["gfx103"],
2484   "map": {"at": 47164, "to": "mm"},
2485   "name": "COMPUTE_DISPATCH_PKT_ADDR_HI",
2486   "type_ref": "COMPUTE_PGM_HI"
2487  },
2488  {
2489   "chips": ["gfx103"],
2490   "map": {"at": 47168, "to": "mm"},
2491   "name": "COMPUTE_DISPATCH_SCRATCH_BASE_LO"
2492  },
2493  {
2494   "chips": ["gfx103"],
2495   "map": {"at": 47172, "to": "mm"},
2496   "name": "COMPUTE_DISPATCH_SCRATCH_BASE_HI",
2497   "type_ref": "COMPUTE_PGM_HI"
2498  },
2499  {
2500   "chips": ["gfx103"],
2501   "map": {"at": 47176, "to": "mm"},
2502   "name": "COMPUTE_PGM_RSRC1",
2503   "type_ref": "COMPUTE_PGM_RSRC1"
2504  },
2505  {
2506   "chips": ["gfx103"],
2507   "map": {"at": 47180, "to": "mm"},
2508   "name": "COMPUTE_PGM_RSRC2",
2509   "type_ref": "COMPUTE_PGM_RSRC2"
2510  },
2511  {
2512   "chips": ["gfx103"],
2513   "map": {"at": 47184, "to": "mm"},
2514   "name": "COMPUTE_VMID",
2515   "type_ref": "COMPUTE_VMID"
2516  },
2517  {
2518   "chips": ["gfx103"],
2519   "map": {"at": 47188, "to": "mm"},
2520   "name": "COMPUTE_RESOURCE_LIMITS",
2521   "type_ref": "COMPUTE_RESOURCE_LIMITS"
2522  },
2523  {
2524   "chips": ["gfx103"],
2525   "map": {"at": 47192, "to": "mm"},
2526   "name": "COMPUTE_DESTINATION_EN_SE0"
2527  },
2528  {
2529   "chips": ["gfx103"],
2530   "map": {"at": 47196, "to": "mm"},
2531   "name": "COMPUTE_DESTINATION_EN_SE1"
2532  },
2533  {
2534   "chips": ["gfx103"],
2535   "map": {"at": 47200, "to": "mm"},
2536   "name": "COMPUTE_TMPRING_SIZE",
2537   "type_ref": "COMPUTE_TMPRING_SIZE"
2538  },
2539  {
2540   "chips": ["gfx103"],
2541   "map": {"at": 47204, "to": "mm"},
2542   "name": "COMPUTE_DESTINATION_EN_SE2"
2543  },
2544  {
2545   "chips": ["gfx103"],
2546   "map": {"at": 47208, "to": "mm"},
2547   "name": "COMPUTE_DESTINATION_EN_SE3"
2548  },
2549  {
2550   "chips": ["gfx103"],
2551   "map": {"at": 47212, "to": "mm"},
2552   "name": "COMPUTE_RESTART_X"
2553  },
2554  {
2555   "chips": ["gfx103"],
2556   "map": {"at": 47216, "to": "mm"},
2557   "name": "COMPUTE_RESTART_Y"
2558  },
2559  {
2560   "chips": ["gfx103"],
2561   "map": {"at": 47220, "to": "mm"},
2562   "name": "COMPUTE_RESTART_Z"
2563  },
2564  {
2565   "chips": ["gfx103"],
2566   "map": {"at": 47224, "to": "mm"},
2567   "name": "COMPUTE_THREAD_TRACE_ENABLE",
2568   "type_ref": "COMPUTE_THREAD_TRACE_ENABLE"
2569  },
2570  {
2571   "chips": ["gfx103"],
2572   "map": {"at": 47228, "to": "mm"},
2573   "name": "COMPUTE_MISC_RESERVED",
2574   "type_ref": "COMPUTE_MISC_RESERVED"
2575  },
2576  {
2577   "chips": ["gfx103"],
2578   "map": {"at": 47232, "to": "mm"},
2579   "name": "COMPUTE_DISPATCH_ID"
2580  },
2581  {
2582   "chips": ["gfx103"],
2583   "map": {"at": 47236, "to": "mm"},
2584   "name": "COMPUTE_THREADGROUP_ID"
2585  },
2586  {
2587   "chips": ["gfx103"],
2588   "map": {"at": 47240, "to": "mm"},
2589   "name": "COMPUTE_REQ_CTRL",
2590   "type_ref": "COMPUTE_REQ_CTRL"
2591  },
2592  {
2593   "chips": ["gfx103"],
2594   "map": {"at": 47248, "to": "mm"},
2595   "name": "COMPUTE_USER_ACCUM_0",
2596   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2597  },
2598  {
2599   "chips": ["gfx103"],
2600   "map": {"at": 47252, "to": "mm"},
2601   "name": "COMPUTE_USER_ACCUM_1",
2602   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2603  },
2604  {
2605   "chips": ["gfx103"],
2606   "map": {"at": 47256, "to": "mm"},
2607   "name": "COMPUTE_USER_ACCUM_2",
2608   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2609  },
2610  {
2611   "chips": ["gfx103"],
2612   "map": {"at": 47260, "to": "mm"},
2613   "name": "COMPUTE_USER_ACCUM_3",
2614   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2615  },
2616  {
2617   "chips": ["gfx103"],
2618   "map": {"at": 47264, "to": "mm"},
2619   "name": "COMPUTE_PGM_RSRC3",
2620   "type_ref": "COMPUTE_PGM_RSRC3"
2621  },
2622  {
2623   "chips": ["gfx103"],
2624   "map": {"at": 47268, "to": "mm"},
2625   "name": "COMPUTE_DDID_INDEX",
2626   "type_ref": "COMPUTE_DDID_INDEX"
2627  },
2628  {
2629   "chips": ["gfx103"],
2630   "map": {"at": 47272, "to": "mm"},
2631   "name": "COMPUTE_SHADER_CHKSUM"
2632  },
2633  {
2634   "chips": ["gfx103"],
2635   "map": {"at": 47276, "to": "mm"},
2636   "name": "COMPUTE_RELAUNCH",
2637   "type_ref": "COMPUTE_RELAUNCH"
2638  },
2639  {
2640   "chips": ["gfx103"],
2641   "map": {"at": 47280, "to": "mm"},
2642   "name": "COMPUTE_WAVE_RESTORE_ADDR_LO"
2643  },
2644  {
2645   "chips": ["gfx103"],
2646   "map": {"at": 47284, "to": "mm"},
2647   "name": "COMPUTE_WAVE_RESTORE_ADDR_HI",
2648   "type_ref": "COMPUTE_WAVE_RESTORE_ADDR_HI"
2649  },
2650  {
2651   "chips": ["gfx103"],
2652   "map": {"at": 47288, "to": "mm"},
2653   "name": "COMPUTE_RELAUNCH2",
2654   "type_ref": "COMPUTE_RELAUNCH"
2655  },
2656  {
2657   "chips": ["gfx103"],
2658   "map": {"at": 47360, "to": "mm"},
2659   "name": "COMPUTE_USER_DATA_0"
2660  },
2661  {
2662   "chips": ["gfx103"],
2663   "map": {"at": 47364, "to": "mm"},
2664   "name": "COMPUTE_USER_DATA_1"
2665  },
2666  {
2667   "chips": ["gfx103"],
2668   "map": {"at": 47368, "to": "mm"},
2669   "name": "COMPUTE_USER_DATA_2"
2670  },
2671  {
2672   "chips": ["gfx103"],
2673   "map": {"at": 47372, "to": "mm"},
2674   "name": "COMPUTE_USER_DATA_3"
2675  },
2676  {
2677   "chips": ["gfx103"],
2678   "map": {"at": 47376, "to": "mm"},
2679   "name": "COMPUTE_USER_DATA_4"
2680  },
2681  {
2682   "chips": ["gfx103"],
2683   "map": {"at": 47380, "to": "mm"},
2684   "name": "COMPUTE_USER_DATA_5"
2685  },
2686  {
2687   "chips": ["gfx103"],
2688   "map": {"at": 47384, "to": "mm"},
2689   "name": "COMPUTE_USER_DATA_6"
2690  },
2691  {
2692   "chips": ["gfx103"],
2693   "map": {"at": 47388, "to": "mm"},
2694   "name": "COMPUTE_USER_DATA_7"
2695  },
2696  {
2697   "chips": ["gfx103"],
2698   "map": {"at": 47392, "to": "mm"},
2699   "name": "COMPUTE_USER_DATA_8"
2700  },
2701  {
2702   "chips": ["gfx103"],
2703   "map": {"at": 47396, "to": "mm"},
2704   "name": "COMPUTE_USER_DATA_9"
2705  },
2706  {
2707   "chips": ["gfx103"],
2708   "map": {"at": 47400, "to": "mm"},
2709   "name": "COMPUTE_USER_DATA_10"
2710  },
2711  {
2712   "chips": ["gfx103"],
2713   "map": {"at": 47404, "to": "mm"},
2714   "name": "COMPUTE_USER_DATA_11"
2715  },
2716  {
2717   "chips": ["gfx103"],
2718   "map": {"at": 47408, "to": "mm"},
2719   "name": "COMPUTE_USER_DATA_12"
2720  },
2721  {
2722   "chips": ["gfx103"],
2723   "map": {"at": 47412, "to": "mm"},
2724   "name": "COMPUTE_USER_DATA_13"
2725  },
2726  {
2727   "chips": ["gfx103"],
2728   "map": {"at": 47416, "to": "mm"},
2729   "name": "COMPUTE_USER_DATA_14"
2730  },
2731  {
2732   "chips": ["gfx103"],
2733   "map": {"at": 47420, "to": "mm"},
2734   "name": "COMPUTE_USER_DATA_15"
2735  },
2736  {
2737   "chips": ["gfx103"],
2738   "map": {"at": 47604, "to": "mm"},
2739   "name": "COMPUTE_DISPATCH_TUNNEL",
2740   "type_ref": "COMPUTE_DISPATCH_TUNNEL"
2741  },
2742  {
2743   "chips": ["gfx103"],
2744   "map": {"at": 47608, "to": "mm"},
2745   "name": "COMPUTE_DISPATCH_END"
2746  },
2747  {
2748   "chips": ["gfx103"],
2749   "map": {"at": 47612, "to": "mm"},
2750   "name": "COMPUTE_NOWHERE"
2751  },
2752  {
2753   "chips": ["gfx103"],
2754   "map": {"at": 47616, "to": "mm"},
2755   "name": "SH_RESERVED_REG0"
2756  },
2757  {
2758   "chips": ["gfx103"],
2759   "map": {"at": 47620, "to": "mm"},
2760   "name": "SH_RESERVED_REG1"
2761  },
2762  {
2763   "chips": ["gfx103"],
2764   "map": {"at": 163840, "to": "mm"},
2765   "name": "DB_RENDER_CONTROL",
2766   "type_ref": "DB_RENDER_CONTROL"
2767  },
2768  {
2769   "chips": ["gfx103"],
2770   "map": {"at": 163844, "to": "mm"},
2771   "name": "DB_COUNT_CONTROL",
2772   "type_ref": "DB_COUNT_CONTROL"
2773  },
2774  {
2775   "chips": ["gfx103"],
2776   "map": {"at": 163848, "to": "mm"},
2777   "name": "DB_DEPTH_VIEW",
2778   "type_ref": "DB_DEPTH_VIEW"
2779  },
2780  {
2781   "chips": ["gfx103"],
2782   "map": {"at": 163852, "to": "mm"},
2783   "name": "DB_RENDER_OVERRIDE",
2784   "type_ref": "DB_RENDER_OVERRIDE"
2785  },
2786  {
2787   "chips": ["gfx103"],
2788   "map": {"at": 163856, "to": "mm"},
2789   "name": "DB_RENDER_OVERRIDE2",
2790   "type_ref": "DB_RENDER_OVERRIDE2"
2791  },
2792  {
2793   "chips": ["gfx103"],
2794   "map": {"at": 163860, "to": "mm"},
2795   "name": "DB_HTILE_DATA_BASE"
2796  },
2797  {
2798   "chips": ["gfx103"],
2799   "map": {"at": 163868, "to": "mm"},
2800   "name": "DB_DEPTH_SIZE_XY",
2801   "type_ref": "DB_DEPTH_SIZE_XY"
2802  },
2803  {
2804   "chips": ["gfx103"],
2805   "map": {"at": 163872, "to": "mm"},
2806   "name": "DB_DEPTH_BOUNDS_MIN"
2807  },
2808  {
2809   "chips": ["gfx103"],
2810   "map": {"at": 163876, "to": "mm"},
2811   "name": "DB_DEPTH_BOUNDS_MAX"
2812  },
2813  {
2814   "chips": ["gfx103"],
2815   "map": {"at": 163880, "to": "mm"},
2816   "name": "DB_STENCIL_CLEAR",
2817   "type_ref": "DB_STENCIL_CLEAR"
2818  },
2819  {
2820   "chips": ["gfx103"],
2821   "map": {"at": 163884, "to": "mm"},
2822   "name": "DB_DEPTH_CLEAR"
2823  },
2824  {
2825   "chips": ["gfx103"],
2826   "map": {"at": 163888, "to": "mm"},
2827   "name": "PA_SC_SCREEN_SCISSOR_TL",
2828   "type_ref": "PA_SC_SCREEN_SCISSOR_TL"
2829  },
2830  {
2831   "chips": ["gfx103"],
2832   "map": {"at": 163892, "to": "mm"},
2833   "name": "PA_SC_SCREEN_SCISSOR_BR",
2834   "type_ref": "PA_SC_SCREEN_SCISSOR_BR"
2835  },
2836  {
2837   "chips": ["gfx103"],
2838   "map": {"at": 163896, "to": "mm"},
2839   "name": "DB_DFSM_CONTROL",
2840   "type_ref": "DB_DFSM_CONTROL"
2841  },
2842  {
2843   "chips": ["gfx103"],
2844   "map": {"at": 163900, "to": "mm"},
2845   "name": "DB_RESERVED_REG_2",
2846   "type_ref": "DB_RESERVED_REG_2"
2847  },
2848  {
2849   "chips": ["gfx103"],
2850   "map": {"at": 163904, "to": "mm"},
2851   "name": "DB_Z_INFO",
2852   "type_ref": "DB_Z_INFO"
2853  },
2854  {
2855   "chips": ["gfx103"],
2856   "map": {"at": 163908, "to": "mm"},
2857   "name": "DB_STENCIL_INFO",
2858   "type_ref": "DB_STENCIL_INFO"
2859  },
2860  {
2861   "chips": ["gfx103"],
2862   "map": {"at": 163912, "to": "mm"},
2863   "name": "DB_Z_READ_BASE"
2864  },
2865  {
2866   "chips": ["gfx103"],
2867   "map": {"at": 163916, "to": "mm"},
2868   "name": "DB_STENCIL_READ_BASE"
2869  },
2870  {
2871   "chips": ["gfx103"],
2872   "map": {"at": 163920, "to": "mm"},
2873   "name": "DB_Z_WRITE_BASE"
2874  },
2875  {
2876   "chips": ["gfx103"],
2877   "map": {"at": 163924, "to": "mm"},
2878   "name": "DB_STENCIL_WRITE_BASE"
2879  },
2880  {
2881   "chips": ["gfx103"],
2882   "map": {"at": 163928, "to": "mm"},
2883   "name": "DB_RESERVED_REG_1",
2884   "type_ref": "DB_RESERVED_REG_1"
2885  },
2886  {
2887   "chips": ["gfx103"],
2888   "map": {"at": 163932, "to": "mm"},
2889   "name": "DB_RESERVED_REG_3",
2890   "type_ref": "DB_RESERVED_REG_3"
2891  },
2892  {
2893   "chips": ["gfx103"],
2894   "map": {"at": 163940, "to": "mm"},
2895   "name": "DB_VRS_OVERRIDE_CNTL",
2896   "type_ref": "DB_VRS_OVERRIDE_CNTL"
2897  },
2898  {
2899   "chips": ["gfx103"],
2900   "map": {"at": 163944, "to": "mm"},
2901   "name": "DB_Z_READ_BASE_HI",
2902   "type_ref": "DB_Z_READ_BASE_HI"
2903  },
2904  {
2905   "chips": ["gfx103"],
2906   "map": {"at": 163948, "to": "mm"},
2907   "name": "DB_STENCIL_READ_BASE_HI",
2908   "type_ref": "DB_Z_READ_BASE_HI"
2909  },
2910  {
2911   "chips": ["gfx103"],
2912   "map": {"at": 163952, "to": "mm"},
2913   "name": "DB_Z_WRITE_BASE_HI",
2914   "type_ref": "DB_Z_READ_BASE_HI"
2915  },
2916  {
2917   "chips": ["gfx103"],
2918   "map": {"at": 163956, "to": "mm"},
2919   "name": "DB_STENCIL_WRITE_BASE_HI",
2920   "type_ref": "DB_Z_READ_BASE_HI"
2921  },
2922  {
2923   "chips": ["gfx103"],
2924   "map": {"at": 163960, "to": "mm"},
2925   "name": "DB_HTILE_DATA_BASE_HI",
2926   "type_ref": "DB_Z_READ_BASE_HI"
2927  },
2928  {
2929   "chips": ["gfx103"],
2930   "map": {"at": 163964, "to": "mm"},
2931   "name": "DB_RMI_L2_CACHE_CONTROL",
2932   "type_ref": "DB_RMI_L2_CACHE_CONTROL"
2933  },
2934  {
2935   "chips": ["gfx103"],
2936   "map": {"at": 163968, "to": "mm"},
2937   "name": "TA_BC_BASE_ADDR"
2938  },
2939  {
2940   "chips": ["gfx103"],
2941   "map": {"at": 163972, "to": "mm"},
2942   "name": "TA_BC_BASE_ADDR_HI",
2943   "type_ref": "TA_BC_BASE_ADDR_HI"
2944  },
2945  {
2946   "chips": ["gfx103"],
2947   "map": {"at": 164328, "to": "mm"},
2948   "name": "COHER_DEST_BASE_HI_0",
2949   "type_ref": "COHER_DEST_BASE_HI_0"
2950  },
2951  {
2952   "chips": ["gfx103"],
2953   "map": {"at": 164332, "to": "mm"},
2954   "name": "COHER_DEST_BASE_HI_1",
2955   "type_ref": "COHER_DEST_BASE_HI_0"
2956  },
2957  {
2958   "chips": ["gfx103"],
2959   "map": {"at": 164336, "to": "mm"},
2960   "name": "COHER_DEST_BASE_HI_2",
2961   "type_ref": "COHER_DEST_BASE_HI_0"
2962  },
2963  {
2964   "chips": ["gfx103"],
2965   "map": {"at": 164340, "to": "mm"},
2966   "name": "COHER_DEST_BASE_HI_3",
2967   "type_ref": "COHER_DEST_BASE_HI_0"
2968  },
2969  {
2970   "chips": ["gfx103"],
2971   "map": {"at": 164344, "to": "mm"},
2972   "name": "COHER_DEST_BASE_2"
2973  },
2974  {
2975   "chips": ["gfx103"],
2976   "map": {"at": 164348, "to": "mm"},
2977   "name": "COHER_DEST_BASE_3"
2978  },
2979  {
2980   "chips": ["gfx103"],
2981   "map": {"at": 164352, "to": "mm"},
2982   "name": "PA_SC_WINDOW_OFFSET",
2983   "type_ref": "PA_SC_WINDOW_OFFSET"
2984  },
2985  {
2986   "chips": ["gfx103"],
2987   "map": {"at": 164356, "to": "mm"},
2988   "name": "PA_SC_WINDOW_SCISSOR_TL",
2989   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
2990  },
2991  {
2992   "chips": ["gfx103"],
2993   "map": {"at": 164360, "to": "mm"},
2994   "name": "PA_SC_WINDOW_SCISSOR_BR",
2995   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
2996  },
2997  {
2998   "chips": ["gfx103"],
2999   "map": {"at": 164364, "to": "mm"},
3000   "name": "PA_SC_CLIPRECT_RULE",
3001   "type_ref": "PA_SC_CLIPRECT_RULE"
3002  },
3003  {
3004   "chips": ["gfx103"],
3005   "map": {"at": 164368, "to": "mm"},
3006   "name": "PA_SC_CLIPRECT_0_TL",
3007   "type_ref": "PA_SC_CLIPRECT_0_TL"
3008  },
3009  {
3010   "chips": ["gfx103"],
3011   "map": {"at": 164372, "to": "mm"},
3012   "name": "PA_SC_CLIPRECT_0_BR",
3013   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3014  },
3015  {
3016   "chips": ["gfx103"],
3017   "map": {"at": 164376, "to": "mm"},
3018   "name": "PA_SC_CLIPRECT_1_TL",
3019   "type_ref": "PA_SC_CLIPRECT_0_TL"
3020  },
3021  {
3022   "chips": ["gfx103"],
3023   "map": {"at": 164380, "to": "mm"},
3024   "name": "PA_SC_CLIPRECT_1_BR",
3025   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3026  },
3027  {
3028   "chips": ["gfx103"],
3029   "map": {"at": 164384, "to": "mm"},
3030   "name": "PA_SC_CLIPRECT_2_TL",
3031   "type_ref": "PA_SC_CLIPRECT_0_TL"
3032  },
3033  {
3034   "chips": ["gfx103"],
3035   "map": {"at": 164388, "to": "mm"},
3036   "name": "PA_SC_CLIPRECT_2_BR",
3037   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3038  },
3039  {
3040   "chips": ["gfx103"],
3041   "map": {"at": 164392, "to": "mm"},
3042   "name": "PA_SC_CLIPRECT_3_TL",
3043   "type_ref": "PA_SC_CLIPRECT_0_TL"
3044  },
3045  {
3046   "chips": ["gfx103"],
3047   "map": {"at": 164396, "to": "mm"},
3048   "name": "PA_SC_CLIPRECT_3_BR",
3049   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3050  },
3051  {
3052   "chips": ["gfx103"],
3053   "map": {"at": 164400, "to": "mm"},
3054   "name": "PA_SC_EDGERULE",
3055   "type_ref": "PA_SC_EDGERULE"
3056  },
3057  {
3058   "chips": ["gfx103"],
3059   "map": {"at": 164404, "to": "mm"},
3060   "name": "PA_SU_HARDWARE_SCREEN_OFFSET",
3061   "type_ref": "PA_SU_HARDWARE_SCREEN_OFFSET"
3062  },
3063  {
3064   "chips": ["gfx103"],
3065   "map": {"at": 164408, "to": "mm"},
3066   "name": "CB_TARGET_MASK",
3067   "type_ref": "CB_TARGET_MASK"
3068  },
3069  {
3070   "chips": ["gfx103"],
3071   "map": {"at": 164412, "to": "mm"},
3072   "name": "CB_SHADER_MASK",
3073   "type_ref": "CB_SHADER_MASK"
3074  },
3075  {
3076   "chips": ["gfx103"],
3077   "map": {"at": 164416, "to": "mm"},
3078   "name": "PA_SC_GENERIC_SCISSOR_TL",
3079   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3080  },
3081  {
3082   "chips": ["gfx103"],
3083   "map": {"at": 164420, "to": "mm"},
3084   "name": "PA_SC_GENERIC_SCISSOR_BR",
3085   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3086  },
3087  {
3088   "chips": ["gfx103"],
3089   "map": {"at": 164424, "to": "mm"},
3090   "name": "COHER_DEST_BASE_0"
3091  },
3092  {
3093   "chips": ["gfx103"],
3094   "map": {"at": 164428, "to": "mm"},
3095   "name": "COHER_DEST_BASE_1"
3096  },
3097  {
3098   "chips": ["gfx103"],
3099   "map": {"at": 164432, "to": "mm"},
3100   "name": "PA_SC_VPORT_SCISSOR_0_TL",
3101   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3102  },
3103  {
3104   "chips": ["gfx103"],
3105   "map": {"at": 164436, "to": "mm"},
3106   "name": "PA_SC_VPORT_SCISSOR_0_BR",
3107   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3108  },
3109  {
3110   "chips": ["gfx103"],
3111   "map": {"at": 164440, "to": "mm"},
3112   "name": "PA_SC_VPORT_SCISSOR_1_TL",
3113   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3114  },
3115  {
3116   "chips": ["gfx103"],
3117   "map": {"at": 164444, "to": "mm"},
3118   "name": "PA_SC_VPORT_SCISSOR_1_BR",
3119   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3120  },
3121  {
3122   "chips": ["gfx103"],
3123   "map": {"at": 164448, "to": "mm"},
3124   "name": "PA_SC_VPORT_SCISSOR_2_TL",
3125   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3126  },
3127  {
3128   "chips": ["gfx103"],
3129   "map": {"at": 164452, "to": "mm"},
3130   "name": "PA_SC_VPORT_SCISSOR_2_BR",
3131   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3132  },
3133  {
3134   "chips": ["gfx103"],
3135   "map": {"at": 164456, "to": "mm"},
3136   "name": "PA_SC_VPORT_SCISSOR_3_TL",
3137   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3138  },
3139  {
3140   "chips": ["gfx103"],
3141   "map": {"at": 164460, "to": "mm"},
3142   "name": "PA_SC_VPORT_SCISSOR_3_BR",
3143   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3144  },
3145  {
3146   "chips": ["gfx103"],
3147   "map": {"at": 164464, "to": "mm"},
3148   "name": "PA_SC_VPORT_SCISSOR_4_TL",
3149   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3150  },
3151  {
3152   "chips": ["gfx103"],
3153   "map": {"at": 164468, "to": "mm"},
3154   "name": "PA_SC_VPORT_SCISSOR_4_BR",
3155   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3156  },
3157  {
3158   "chips": ["gfx103"],
3159   "map": {"at": 164472, "to": "mm"},
3160   "name": "PA_SC_VPORT_SCISSOR_5_TL",
3161   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3162  },
3163  {
3164   "chips": ["gfx103"],
3165   "map": {"at": 164476, "to": "mm"},
3166   "name": "PA_SC_VPORT_SCISSOR_5_BR",
3167   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3168  },
3169  {
3170   "chips": ["gfx103"],
3171   "map": {"at": 164480, "to": "mm"},
3172   "name": "PA_SC_VPORT_SCISSOR_6_TL",
3173   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3174  },
3175  {
3176   "chips": ["gfx103"],
3177   "map": {"at": 164484, "to": "mm"},
3178   "name": "PA_SC_VPORT_SCISSOR_6_BR",
3179   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3180  },
3181  {
3182   "chips": ["gfx103"],
3183   "map": {"at": 164488, "to": "mm"},
3184   "name": "PA_SC_VPORT_SCISSOR_7_TL",
3185   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3186  },
3187  {
3188   "chips": ["gfx103"],
3189   "map": {"at": 164492, "to": "mm"},
3190   "name": "PA_SC_VPORT_SCISSOR_7_BR",
3191   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3192  },
3193  {
3194   "chips": ["gfx103"],
3195   "map": {"at": 164496, "to": "mm"},
3196   "name": "PA_SC_VPORT_SCISSOR_8_TL",
3197   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3198  },
3199  {
3200   "chips": ["gfx103"],
3201   "map": {"at": 164500, "to": "mm"},
3202   "name": "PA_SC_VPORT_SCISSOR_8_BR",
3203   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3204  },
3205  {
3206   "chips": ["gfx103"],
3207   "map": {"at": 164504, "to": "mm"},
3208   "name": "PA_SC_VPORT_SCISSOR_9_TL",
3209   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3210  },
3211  {
3212   "chips": ["gfx103"],
3213   "map": {"at": 164508, "to": "mm"},
3214   "name": "PA_SC_VPORT_SCISSOR_9_BR",
3215   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3216  },
3217  {
3218   "chips": ["gfx103"],
3219   "map": {"at": 164512, "to": "mm"},
3220   "name": "PA_SC_VPORT_SCISSOR_10_TL",
3221   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3222  },
3223  {
3224   "chips": ["gfx103"],
3225   "map": {"at": 164516, "to": "mm"},
3226   "name": "PA_SC_VPORT_SCISSOR_10_BR",
3227   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3228  },
3229  {
3230   "chips": ["gfx103"],
3231   "map": {"at": 164520, "to": "mm"},
3232   "name": "PA_SC_VPORT_SCISSOR_11_TL",
3233   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3234  },
3235  {
3236   "chips": ["gfx103"],
3237   "map": {"at": 164524, "to": "mm"},
3238   "name": "PA_SC_VPORT_SCISSOR_11_BR",
3239   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3240  },
3241  {
3242   "chips": ["gfx103"],
3243   "map": {"at": 164528, "to": "mm"},
3244   "name": "PA_SC_VPORT_SCISSOR_12_TL",
3245   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3246  },
3247  {
3248   "chips": ["gfx103"],
3249   "map": {"at": 164532, "to": "mm"},
3250   "name": "PA_SC_VPORT_SCISSOR_12_BR",
3251   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3252  },
3253  {
3254   "chips": ["gfx103"],
3255   "map": {"at": 164536, "to": "mm"},
3256   "name": "PA_SC_VPORT_SCISSOR_13_TL",
3257   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3258  },
3259  {
3260   "chips": ["gfx103"],
3261   "map": {"at": 164540, "to": "mm"},
3262   "name": "PA_SC_VPORT_SCISSOR_13_BR",
3263   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3264  },
3265  {
3266   "chips": ["gfx103"],
3267   "map": {"at": 164544, "to": "mm"},
3268   "name": "PA_SC_VPORT_SCISSOR_14_TL",
3269   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3270  },
3271  {
3272   "chips": ["gfx103"],
3273   "map": {"at": 164548, "to": "mm"},
3274   "name": "PA_SC_VPORT_SCISSOR_14_BR",
3275   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3276  },
3277  {
3278   "chips": ["gfx103"],
3279   "map": {"at": 164552, "to": "mm"},
3280   "name": "PA_SC_VPORT_SCISSOR_15_TL",
3281   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3282  },
3283  {
3284   "chips": ["gfx103"],
3285   "map": {"at": 164556, "to": "mm"},
3286   "name": "PA_SC_VPORT_SCISSOR_15_BR",
3287   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3288  },
3289  {
3290   "chips": ["gfx103"],
3291   "map": {"at": 164560, "to": "mm"},
3292   "name": "PA_SC_VPORT_ZMIN_0"
3293  },
3294  {
3295   "chips": ["gfx103"],
3296   "map": {"at": 164564, "to": "mm"},
3297   "name": "PA_SC_VPORT_ZMAX_0"
3298  },
3299  {
3300   "chips": ["gfx103"],
3301   "map": {"at": 164568, "to": "mm"},
3302   "name": "PA_SC_VPORT_ZMIN_1"
3303  },
3304  {
3305   "chips": ["gfx103"],
3306   "map": {"at": 164572, "to": "mm"},
3307   "name": "PA_SC_VPORT_ZMAX_1"
3308  },
3309  {
3310   "chips": ["gfx103"],
3311   "map": {"at": 164576, "to": "mm"},
3312   "name": "PA_SC_VPORT_ZMIN_2"
3313  },
3314  {
3315   "chips": ["gfx103"],
3316   "map": {"at": 164580, "to": "mm"},
3317   "name": "PA_SC_VPORT_ZMAX_2"
3318  },
3319  {
3320   "chips": ["gfx103"],
3321   "map": {"at": 164584, "to": "mm"},
3322   "name": "PA_SC_VPORT_ZMIN_3"
3323  },
3324  {
3325   "chips": ["gfx103"],
3326   "map": {"at": 164588, "to": "mm"},
3327   "name": "PA_SC_VPORT_ZMAX_3"
3328  },
3329  {
3330   "chips": ["gfx103"],
3331   "map": {"at": 164592, "to": "mm"},
3332   "name": "PA_SC_VPORT_ZMIN_4"
3333  },
3334  {
3335   "chips": ["gfx103"],
3336   "map": {"at": 164596, "to": "mm"},
3337   "name": "PA_SC_VPORT_ZMAX_4"
3338  },
3339  {
3340   "chips": ["gfx103"],
3341   "map": {"at": 164600, "to": "mm"},
3342   "name": "PA_SC_VPORT_ZMIN_5"
3343  },
3344  {
3345   "chips": ["gfx103"],
3346   "map": {"at": 164604, "to": "mm"},
3347   "name": "PA_SC_VPORT_ZMAX_5"
3348  },
3349  {
3350   "chips": ["gfx103"],
3351   "map": {"at": 164608, "to": "mm"},
3352   "name": "PA_SC_VPORT_ZMIN_6"
3353  },
3354  {
3355   "chips": ["gfx103"],
3356   "map": {"at": 164612, "to": "mm"},
3357   "name": "PA_SC_VPORT_ZMAX_6"
3358  },
3359  {
3360   "chips": ["gfx103"],
3361   "map": {"at": 164616, "to": "mm"},
3362   "name": "PA_SC_VPORT_ZMIN_7"
3363  },
3364  {
3365   "chips": ["gfx103"],
3366   "map": {"at": 164620, "to": "mm"},
3367   "name": "PA_SC_VPORT_ZMAX_7"
3368  },
3369  {
3370   "chips": ["gfx103"],
3371   "map": {"at": 164624, "to": "mm"},
3372   "name": "PA_SC_VPORT_ZMIN_8"
3373  },
3374  {
3375   "chips": ["gfx103"],
3376   "map": {"at": 164628, "to": "mm"},
3377   "name": "PA_SC_VPORT_ZMAX_8"
3378  },
3379  {
3380   "chips": ["gfx103"],
3381   "map": {"at": 164632, "to": "mm"},
3382   "name": "PA_SC_VPORT_ZMIN_9"
3383  },
3384  {
3385   "chips": ["gfx103"],
3386   "map": {"at": 164636, "to": "mm"},
3387   "name": "PA_SC_VPORT_ZMAX_9"
3388  },
3389  {
3390   "chips": ["gfx103"],
3391   "map": {"at": 164640, "to": "mm"},
3392   "name": "PA_SC_VPORT_ZMIN_10"
3393  },
3394  {
3395   "chips": ["gfx103"],
3396   "map": {"at": 164644, "to": "mm"},
3397   "name": "PA_SC_VPORT_ZMAX_10"
3398  },
3399  {
3400   "chips": ["gfx103"],
3401   "map": {"at": 164648, "to": "mm"},
3402   "name": "PA_SC_VPORT_ZMIN_11"
3403  },
3404  {
3405   "chips": ["gfx103"],
3406   "map": {"at": 164652, "to": "mm"},
3407   "name": "PA_SC_VPORT_ZMAX_11"
3408  },
3409  {
3410   "chips": ["gfx103"],
3411   "map": {"at": 164656, "to": "mm"},
3412   "name": "PA_SC_VPORT_ZMIN_12"
3413  },
3414  {
3415   "chips": ["gfx103"],
3416   "map": {"at": 164660, "to": "mm"},
3417   "name": "PA_SC_VPORT_ZMAX_12"
3418  },
3419  {
3420   "chips": ["gfx103"],
3421   "map": {"at": 164664, "to": "mm"},
3422   "name": "PA_SC_VPORT_ZMIN_13"
3423  },
3424  {
3425   "chips": ["gfx103"],
3426   "map": {"at": 164668, "to": "mm"},
3427   "name": "PA_SC_VPORT_ZMAX_13"
3428  },
3429  {
3430   "chips": ["gfx103"],
3431   "map": {"at": 164672, "to": "mm"},
3432   "name": "PA_SC_VPORT_ZMIN_14"
3433  },
3434  {
3435   "chips": ["gfx103"],
3436   "map": {"at": 164676, "to": "mm"},
3437   "name": "PA_SC_VPORT_ZMAX_14"
3438  },
3439  {
3440   "chips": ["gfx103"],
3441   "map": {"at": 164680, "to": "mm"},
3442   "name": "PA_SC_VPORT_ZMIN_15"
3443  },
3444  {
3445   "chips": ["gfx103"],
3446   "map": {"at": 164684, "to": "mm"},
3447   "name": "PA_SC_VPORT_ZMAX_15"
3448  },
3449  {
3450   "chips": ["gfx103"],
3451   "map": {"at": 164688, "to": "mm"},
3452   "name": "PA_SC_RASTER_CONFIG",
3453   "type_ref": "PA_SC_RASTER_CONFIG"
3454  },
3455  {
3456   "chips": ["gfx103"],
3457   "map": {"at": 164692, "to": "mm"},
3458   "name": "PA_SC_RASTER_CONFIG_1",
3459   "type_ref": "PA_SC_RASTER_CONFIG_1"
3460  },
3461  {
3462   "chips": ["gfx103"],
3463   "map": {"at": 164696, "to": "mm"},
3464   "name": "PA_SC_SCREEN_EXTENT_CONTROL",
3465   "type_ref": "PA_SC_SCREEN_EXTENT_CONTROL"
3466  },
3467  {
3468   "chips": ["gfx103"],
3469   "map": {"at": 164700, "to": "mm"},
3470   "name": "PA_SC_TILE_STEERING_OVERRIDE",
3471   "type_ref": "PA_SC_TILE_STEERING_OVERRIDE"
3472  },
3473  {
3474   "chips": ["gfx103"],
3475   "map": {"at": 164704, "to": "mm"},
3476   "name": "CP_PERFMON_CNTX_CNTL",
3477   "type_ref": "CP_PERFMON_CNTX_CNTL"
3478  },
3479  {
3480   "chips": ["gfx103"],
3481   "map": {"at": 164708, "to": "mm"},
3482   "name": "CP_PIPEID",
3483   "type_ref": "CP_PIPEID"
3484  },
3485  {
3486   "chips": ["gfx103"],
3487   "map": {"at": 164712, "to": "mm"},
3488   "name": "CP_VMID",
3489   "type_ref": "CP_VMID"
3490  },
3491  {
3492   "chips": ["gfx103"],
3493   "map": {"at": 164716, "to": "mm"},
3494   "name": "CONTEXT_RESERVED_REG0"
3495  },
3496  {
3497   "chips": ["gfx103"],
3498   "map": {"at": 164720, "to": "mm"},
3499   "name": "CONTEXT_RESERVED_REG1"
3500  },
3501  {
3502   "chips": ["gfx103"],
3503   "map": {"at": 164864, "to": "mm"},
3504   "name": "VGT_MAX_VTX_INDX"
3505  },
3506  {
3507   "chips": ["gfx103"],
3508   "map": {"at": 164868, "to": "mm"},
3509   "name": "VGT_MIN_VTX_INDX"
3510  },
3511  {
3512   "chips": ["gfx103"],
3513   "map": {"at": 164872, "to": "mm"},
3514   "name": "VGT_INDX_OFFSET"
3515  },
3516  {
3517   "chips": ["gfx103"],
3518   "map": {"at": 164876, "to": "mm"},
3519   "name": "VGT_MULTI_PRIM_IB_RESET_INDX"
3520  },
3521  {
3522   "chips": ["gfx103"],
3523   "map": {"at": 164880, "to": "mm"},
3524   "name": "CB_RMI_GL2_CACHE_CONTROL",
3525   "type_ref": "CB_RMI_GL2_CACHE_CONTROL"
3526  },
3527  {
3528   "chips": ["gfx103"],
3529   "map": {"at": 164884, "to": "mm"},
3530   "name": "CB_BLEND_RED"
3531  },
3532  {
3533   "chips": ["gfx103"],
3534   "map": {"at": 164888, "to": "mm"},
3535   "name": "CB_BLEND_GREEN"
3536  },
3537  {
3538   "chips": ["gfx103"],
3539   "map": {"at": 164892, "to": "mm"},
3540   "name": "CB_BLEND_BLUE"
3541  },
3542  {
3543   "chips": ["gfx103"],
3544   "map": {"at": 164896, "to": "mm"},
3545   "name": "CB_BLEND_ALPHA"
3546  },
3547  {
3548   "chips": ["gfx103"],
3549   "map": {"at": 164900, "to": "mm"},
3550   "name": "CB_DCC_CONTROL",
3551   "type_ref": "CB_DCC_CONTROL"
3552  },
3553  {
3554   "chips": ["gfx103"],
3555   "map": {"at": 164904, "to": "mm"},
3556   "name": "CB_COVERAGE_OUT_CONTROL",
3557   "type_ref": "CB_COVERAGE_OUT_CONTROL"
3558  },
3559  {
3560   "chips": ["gfx103"],
3561   "map": {"at": 164908, "to": "mm"},
3562   "name": "DB_STENCIL_CONTROL",
3563   "type_ref": "DB_STENCIL_CONTROL"
3564  },
3565  {
3566   "chips": ["gfx103"],
3567   "map": {"at": 164912, "to": "mm"},
3568   "name": "DB_STENCILREFMASK",
3569   "type_ref": "DB_STENCILREFMASK"
3570  },
3571  {
3572   "chips": ["gfx103"],
3573   "map": {"at": 164916, "to": "mm"},
3574   "name": "DB_STENCILREFMASK_BF",
3575   "type_ref": "DB_STENCILREFMASK_BF"
3576  },
3577  {
3578   "chips": ["gfx103"],
3579   "map": {"at": 164924, "to": "mm"},
3580   "name": "PA_CL_VPORT_XSCALE"
3581  },
3582  {
3583   "chips": ["gfx103"],
3584   "map": {"at": 164928, "to": "mm"},
3585   "name": "PA_CL_VPORT_XOFFSET"
3586  },
3587  {
3588   "chips": ["gfx103"],
3589   "map": {"at": 164932, "to": "mm"},
3590   "name": "PA_CL_VPORT_YSCALE"
3591  },
3592  {
3593   "chips": ["gfx103"],
3594   "map": {"at": 164936, "to": "mm"},
3595   "name": "PA_CL_VPORT_YOFFSET"
3596  },
3597  {
3598   "chips": ["gfx103"],
3599   "map": {"at": 164940, "to": "mm"},
3600   "name": "PA_CL_VPORT_ZSCALE"
3601  },
3602  {
3603   "chips": ["gfx103"],
3604   "map": {"at": 164944, "to": "mm"},
3605   "name": "PA_CL_VPORT_ZOFFSET"
3606  },
3607  {
3608   "chips": ["gfx103"],
3609   "map": {"at": 164948, "to": "mm"},
3610   "name": "PA_CL_VPORT_XSCALE_1"
3611  },
3612  {
3613   "chips": ["gfx103"],
3614   "map": {"at": 164952, "to": "mm"},
3615   "name": "PA_CL_VPORT_XOFFSET_1"
3616  },
3617  {
3618   "chips": ["gfx103"],
3619   "map": {"at": 164956, "to": "mm"},
3620   "name": "PA_CL_VPORT_YSCALE_1"
3621  },
3622  {
3623   "chips": ["gfx103"],
3624   "map": {"at": 164960, "to": "mm"},
3625   "name": "PA_CL_VPORT_YOFFSET_1"
3626  },
3627  {
3628   "chips": ["gfx103"],
3629   "map": {"at": 164964, "to": "mm"},
3630   "name": "PA_CL_VPORT_ZSCALE_1"
3631  },
3632  {
3633   "chips": ["gfx103"],
3634   "map": {"at": 164968, "to": "mm"},
3635   "name": "PA_CL_VPORT_ZOFFSET_1"
3636  },
3637  {
3638   "chips": ["gfx103"],
3639   "map": {"at": 164972, "to": "mm"},
3640   "name": "PA_CL_VPORT_XSCALE_2"
3641  },
3642  {
3643   "chips": ["gfx103"],
3644   "map": {"at": 164976, "to": "mm"},
3645   "name": "PA_CL_VPORT_XOFFSET_2"
3646  },
3647  {
3648   "chips": ["gfx103"],
3649   "map": {"at": 164980, "to": "mm"},
3650   "name": "PA_CL_VPORT_YSCALE_2"
3651  },
3652  {
3653   "chips": ["gfx103"],
3654   "map": {"at": 164984, "to": "mm"},
3655   "name": "PA_CL_VPORT_YOFFSET_2"
3656  },
3657  {
3658   "chips": ["gfx103"],
3659   "map": {"at": 164988, "to": "mm"},
3660   "name": "PA_CL_VPORT_ZSCALE_2"
3661  },
3662  {
3663   "chips": ["gfx103"],
3664   "map": {"at": 164992, "to": "mm"},
3665   "name": "PA_CL_VPORT_ZOFFSET_2"
3666  },
3667  {
3668   "chips": ["gfx103"],
3669   "map": {"at": 164996, "to": "mm"},
3670   "name": "PA_CL_VPORT_XSCALE_3"
3671  },
3672  {
3673   "chips": ["gfx103"],
3674   "map": {"at": 165000, "to": "mm"},
3675   "name": "PA_CL_VPORT_XOFFSET_3"
3676  },
3677  {
3678   "chips": ["gfx103"],
3679   "map": {"at": 165004, "to": "mm"},
3680   "name": "PA_CL_VPORT_YSCALE_3"
3681  },
3682  {
3683   "chips": ["gfx103"],
3684   "map": {"at": 165008, "to": "mm"},
3685   "name": "PA_CL_VPORT_YOFFSET_3"
3686  },
3687  {
3688   "chips": ["gfx103"],
3689   "map": {"at": 165012, "to": "mm"},
3690   "name": "PA_CL_VPORT_ZSCALE_3"
3691  },
3692  {
3693   "chips": ["gfx103"],
3694   "map": {"at": 165016, "to": "mm"},
3695   "name": "PA_CL_VPORT_ZOFFSET_3"
3696  },
3697  {
3698   "chips": ["gfx103"],
3699   "map": {"at": 165020, "to": "mm"},
3700   "name": "PA_CL_VPORT_XSCALE_4"
3701  },
3702  {
3703   "chips": ["gfx103"],
3704   "map": {"at": 165024, "to": "mm"},
3705   "name": "PA_CL_VPORT_XOFFSET_4"
3706  },
3707  {
3708   "chips": ["gfx103"],
3709   "map": {"at": 165028, "to": "mm"},
3710   "name": "PA_CL_VPORT_YSCALE_4"
3711  },
3712  {
3713   "chips": ["gfx103"],
3714   "map": {"at": 165032, "to": "mm"},
3715   "name": "PA_CL_VPORT_YOFFSET_4"
3716  },
3717  {
3718   "chips": ["gfx103"],
3719   "map": {"at": 165036, "to": "mm"},
3720   "name": "PA_CL_VPORT_ZSCALE_4"
3721  },
3722  {
3723   "chips": ["gfx103"],
3724   "map": {"at": 165040, "to": "mm"},
3725   "name": "PA_CL_VPORT_ZOFFSET_4"
3726  },
3727  {
3728   "chips": ["gfx103"],
3729   "map": {"at": 165044, "to": "mm"},
3730   "name": "PA_CL_VPORT_XSCALE_5"
3731  },
3732  {
3733   "chips": ["gfx103"],
3734   "map": {"at": 165048, "to": "mm"},
3735   "name": "PA_CL_VPORT_XOFFSET_5"
3736  },
3737  {
3738   "chips": ["gfx103"],
3739   "map": {"at": 165052, "to": "mm"},
3740   "name": "PA_CL_VPORT_YSCALE_5"
3741  },
3742  {
3743   "chips": ["gfx103"],
3744   "map": {"at": 165056, "to": "mm"},
3745   "name": "PA_CL_VPORT_YOFFSET_5"
3746  },
3747  {
3748   "chips": ["gfx103"],
3749   "map": {"at": 165060, "to": "mm"},
3750   "name": "PA_CL_VPORT_ZSCALE_5"
3751  },
3752  {
3753   "chips": ["gfx103"],
3754   "map": {"at": 165064, "to": "mm"},
3755   "name": "PA_CL_VPORT_ZOFFSET_5"
3756  },
3757  {
3758   "chips": ["gfx103"],
3759   "map": {"at": 165068, "to": "mm"},
3760   "name": "PA_CL_VPORT_XSCALE_6"
3761  },
3762  {
3763   "chips": ["gfx103"],
3764   "map": {"at": 165072, "to": "mm"},
3765   "name": "PA_CL_VPORT_XOFFSET_6"
3766  },
3767  {
3768   "chips": ["gfx103"],
3769   "map": {"at": 165076, "to": "mm"},
3770   "name": "PA_CL_VPORT_YSCALE_6"
3771  },
3772  {
3773   "chips": ["gfx103"],
3774   "map": {"at": 165080, "to": "mm"},
3775   "name": "PA_CL_VPORT_YOFFSET_6"
3776  },
3777  {
3778   "chips": ["gfx103"],
3779   "map": {"at": 165084, "to": "mm"},
3780   "name": "PA_CL_VPORT_ZSCALE_6"
3781  },
3782  {
3783   "chips": ["gfx103"],
3784   "map": {"at": 165088, "to": "mm"},
3785   "name": "PA_CL_VPORT_ZOFFSET_6"
3786  },
3787  {
3788   "chips": ["gfx103"],
3789   "map": {"at": 165092, "to": "mm"},
3790   "name": "PA_CL_VPORT_XSCALE_7"
3791  },
3792  {
3793   "chips": ["gfx103"],
3794   "map": {"at": 165096, "to": "mm"},
3795   "name": "PA_CL_VPORT_XOFFSET_7"
3796  },
3797  {
3798   "chips": ["gfx103"],
3799   "map": {"at": 165100, "to": "mm"},
3800   "name": "PA_CL_VPORT_YSCALE_7"
3801  },
3802  {
3803   "chips": ["gfx103"],
3804   "map": {"at": 165104, "to": "mm"},
3805   "name": "PA_CL_VPORT_YOFFSET_7"
3806  },
3807  {
3808   "chips": ["gfx103"],
3809   "map": {"at": 165108, "to": "mm"},
3810   "name": "PA_CL_VPORT_ZSCALE_7"
3811  },
3812  {
3813   "chips": ["gfx103"],
3814   "map": {"at": 165112, "to": "mm"},
3815   "name": "PA_CL_VPORT_ZOFFSET_7"
3816  },
3817  {
3818   "chips": ["gfx103"],
3819   "map": {"at": 165116, "to": "mm"},
3820   "name": "PA_CL_VPORT_XSCALE_8"
3821  },
3822  {
3823   "chips": ["gfx103"],
3824   "map": {"at": 165120, "to": "mm"},
3825   "name": "PA_CL_VPORT_XOFFSET_8"
3826  },
3827  {
3828   "chips": ["gfx103"],
3829   "map": {"at": 165124, "to": "mm"},
3830   "name": "PA_CL_VPORT_YSCALE_8"
3831  },
3832  {
3833   "chips": ["gfx103"],
3834   "map": {"at": 165128, "to": "mm"},
3835   "name": "PA_CL_VPORT_YOFFSET_8"
3836  },
3837  {
3838   "chips": ["gfx103"],
3839   "map": {"at": 165132, "to": "mm"},
3840   "name": "PA_CL_VPORT_ZSCALE_8"
3841  },
3842  {
3843   "chips": ["gfx103"],
3844   "map": {"at": 165136, "to": "mm"},
3845   "name": "PA_CL_VPORT_ZOFFSET_8"
3846  },
3847  {
3848   "chips": ["gfx103"],
3849   "map": {"at": 165140, "to": "mm"},
3850   "name": "PA_CL_VPORT_XSCALE_9"
3851  },
3852  {
3853   "chips": ["gfx103"],
3854   "map": {"at": 165144, "to": "mm"},
3855   "name": "PA_CL_VPORT_XOFFSET_9"
3856  },
3857  {
3858   "chips": ["gfx103"],
3859   "map": {"at": 165148, "to": "mm"},
3860   "name": "PA_CL_VPORT_YSCALE_9"
3861  },
3862  {
3863   "chips": ["gfx103"],
3864   "map": {"at": 165152, "to": "mm"},
3865   "name": "PA_CL_VPORT_YOFFSET_9"
3866  },
3867  {
3868   "chips": ["gfx103"],
3869   "map": {"at": 165156, "to": "mm"},
3870   "name": "PA_CL_VPORT_ZSCALE_9"
3871  },
3872  {
3873   "chips": ["gfx103"],
3874   "map": {"at": 165160, "to": "mm"},
3875   "name": "PA_CL_VPORT_ZOFFSET_9"
3876  },
3877  {
3878   "chips": ["gfx103"],
3879   "map": {"at": 165164, "to": "mm"},
3880   "name": "PA_CL_VPORT_XSCALE_10"
3881  },
3882  {
3883   "chips": ["gfx103"],
3884   "map": {"at": 165168, "to": "mm"},
3885   "name": "PA_CL_VPORT_XOFFSET_10"
3886  },
3887  {
3888   "chips": ["gfx103"],
3889   "map": {"at": 165172, "to": "mm"},
3890   "name": "PA_CL_VPORT_YSCALE_10"
3891  },
3892  {
3893   "chips": ["gfx103"],
3894   "map": {"at": 165176, "to": "mm"},
3895   "name": "PA_CL_VPORT_YOFFSET_10"
3896  },
3897  {
3898   "chips": ["gfx103"],
3899   "map": {"at": 165180, "to": "mm"},
3900   "name": "PA_CL_VPORT_ZSCALE_10"
3901  },
3902  {
3903   "chips": ["gfx103"],
3904   "map": {"at": 165184, "to": "mm"},
3905   "name": "PA_CL_VPORT_ZOFFSET_10"
3906  },
3907  {
3908   "chips": ["gfx103"],
3909   "map": {"at": 165188, "to": "mm"},
3910   "name": "PA_CL_VPORT_XSCALE_11"
3911  },
3912  {
3913   "chips": ["gfx103"],
3914   "map": {"at": 165192, "to": "mm"},
3915   "name": "PA_CL_VPORT_XOFFSET_11"
3916  },
3917  {
3918   "chips": ["gfx103"],
3919   "map": {"at": 165196, "to": "mm"},
3920   "name": "PA_CL_VPORT_YSCALE_11"
3921  },
3922  {
3923   "chips": ["gfx103"],
3924   "map": {"at": 165200, "to": "mm"},
3925   "name": "PA_CL_VPORT_YOFFSET_11"
3926  },
3927  {
3928   "chips": ["gfx103"],
3929   "map": {"at": 165204, "to": "mm"},
3930   "name": "PA_CL_VPORT_ZSCALE_11"
3931  },
3932  {
3933   "chips": ["gfx103"],
3934   "map": {"at": 165208, "to": "mm"},
3935   "name": "PA_CL_VPORT_ZOFFSET_11"
3936  },
3937  {
3938   "chips": ["gfx103"],
3939   "map": {"at": 165212, "to": "mm"},
3940   "name": "PA_CL_VPORT_XSCALE_12"
3941  },
3942  {
3943   "chips": ["gfx103"],
3944   "map": {"at": 165216, "to": "mm"},
3945   "name": "PA_CL_VPORT_XOFFSET_12"
3946  },
3947  {
3948   "chips": ["gfx103"],
3949   "map": {"at": 165220, "to": "mm"},
3950   "name": "PA_CL_VPORT_YSCALE_12"
3951  },
3952  {
3953   "chips": ["gfx103"],
3954   "map": {"at": 165224, "to": "mm"},
3955   "name": "PA_CL_VPORT_YOFFSET_12"
3956  },
3957  {
3958   "chips": ["gfx103"],
3959   "map": {"at": 165228, "to": "mm"},
3960   "name": "PA_CL_VPORT_ZSCALE_12"
3961  },
3962  {
3963   "chips": ["gfx103"],
3964   "map": {"at": 165232, "to": "mm"},
3965   "name": "PA_CL_VPORT_ZOFFSET_12"
3966  },
3967  {
3968   "chips": ["gfx103"],
3969   "map": {"at": 165236, "to": "mm"},
3970   "name": "PA_CL_VPORT_XSCALE_13"
3971  },
3972  {
3973   "chips": ["gfx103"],
3974   "map": {"at": 165240, "to": "mm"},
3975   "name": "PA_CL_VPORT_XOFFSET_13"
3976  },
3977  {
3978   "chips": ["gfx103"],
3979   "map": {"at": 165244, "to": "mm"},
3980   "name": "PA_CL_VPORT_YSCALE_13"
3981  },
3982  {
3983   "chips": ["gfx103"],
3984   "map": {"at": 165248, "to": "mm"},
3985   "name": "PA_CL_VPORT_YOFFSET_13"
3986  },
3987  {
3988   "chips": ["gfx103"],
3989   "map": {"at": 165252, "to": "mm"},
3990   "name": "PA_CL_VPORT_ZSCALE_13"
3991  },
3992  {
3993   "chips": ["gfx103"],
3994   "map": {"at": 165256, "to": "mm"},
3995   "name": "PA_CL_VPORT_ZOFFSET_13"
3996  },
3997  {
3998   "chips": ["gfx103"],
3999   "map": {"at": 165260, "to": "mm"},
4000   "name": "PA_CL_VPORT_XSCALE_14"
4001  },
4002  {
4003   "chips": ["gfx103"],
4004   "map": {"at": 165264, "to": "mm"},
4005   "name": "PA_CL_VPORT_XOFFSET_14"
4006  },
4007  {
4008   "chips": ["gfx103"],
4009   "map": {"at": 165268, "to": "mm"},
4010   "name": "PA_CL_VPORT_YSCALE_14"
4011  },
4012  {
4013   "chips": ["gfx103"],
4014   "map": {"at": 165272, "to": "mm"},
4015   "name": "PA_CL_VPORT_YOFFSET_14"
4016  },
4017  {
4018   "chips": ["gfx103"],
4019   "map": {"at": 165276, "to": "mm"},
4020   "name": "PA_CL_VPORT_ZSCALE_14"
4021  },
4022  {
4023   "chips": ["gfx103"],
4024   "map": {"at": 165280, "to": "mm"},
4025   "name": "PA_CL_VPORT_ZOFFSET_14"
4026  },
4027  {
4028   "chips": ["gfx103"],
4029   "map": {"at": 165284, "to": "mm"},
4030   "name": "PA_CL_VPORT_XSCALE_15"
4031  },
4032  {
4033   "chips": ["gfx103"],
4034   "map": {"at": 165288, "to": "mm"},
4035   "name": "PA_CL_VPORT_XOFFSET_15"
4036  },
4037  {
4038   "chips": ["gfx103"],
4039   "map": {"at": 165292, "to": "mm"},
4040   "name": "PA_CL_VPORT_YSCALE_15"
4041  },
4042  {
4043   "chips": ["gfx103"],
4044   "map": {"at": 165296, "to": "mm"},
4045   "name": "PA_CL_VPORT_YOFFSET_15"
4046  },
4047  {
4048   "chips": ["gfx103"],
4049   "map": {"at": 165300, "to": "mm"},
4050   "name": "PA_CL_VPORT_ZSCALE_15"
4051  },
4052  {
4053   "chips": ["gfx103"],
4054   "map": {"at": 165304, "to": "mm"},
4055   "name": "PA_CL_VPORT_ZOFFSET_15"
4056  },
4057  {
4058   "chips": ["gfx103"],
4059   "map": {"at": 165308, "to": "mm"},
4060   "name": "PA_CL_UCP_0_X"
4061  },
4062  {
4063   "chips": ["gfx103"],
4064   "map": {"at": 165312, "to": "mm"},
4065   "name": "PA_CL_UCP_0_Y"
4066  },
4067  {
4068   "chips": ["gfx103"],
4069   "map": {"at": 165316, "to": "mm"},
4070   "name": "PA_CL_UCP_0_Z"
4071  },
4072  {
4073   "chips": ["gfx103"],
4074   "map": {"at": 165320, "to": "mm"},
4075   "name": "PA_CL_UCP_0_W"
4076  },
4077  {
4078   "chips": ["gfx103"],
4079   "map": {"at": 165324, "to": "mm"},
4080   "name": "PA_CL_UCP_1_X"
4081  },
4082  {
4083   "chips": ["gfx103"],
4084   "map": {"at": 165328, "to": "mm"},
4085   "name": "PA_CL_UCP_1_Y"
4086  },
4087  {
4088   "chips": ["gfx103"],
4089   "map": {"at": 165332, "to": "mm"},
4090   "name": "PA_CL_UCP_1_Z"
4091  },
4092  {
4093   "chips": ["gfx103"],
4094   "map": {"at": 165336, "to": "mm"},
4095   "name": "PA_CL_UCP_1_W"
4096  },
4097  {
4098   "chips": ["gfx103"],
4099   "map": {"at": 165340, "to": "mm"},
4100   "name": "PA_CL_UCP_2_X"
4101  },
4102  {
4103   "chips": ["gfx103"],
4104   "map": {"at": 165344, "to": "mm"},
4105   "name": "PA_CL_UCP_2_Y"
4106  },
4107  {
4108   "chips": ["gfx103"],
4109   "map": {"at": 165348, "to": "mm"},
4110   "name": "PA_CL_UCP_2_Z"
4111  },
4112  {
4113   "chips": ["gfx103"],
4114   "map": {"at": 165352, "to": "mm"},
4115   "name": "PA_CL_UCP_2_W"
4116  },
4117  {
4118   "chips": ["gfx103"],
4119   "map": {"at": 165356, "to": "mm"},
4120   "name": "PA_CL_UCP_3_X"
4121  },
4122  {
4123   "chips": ["gfx103"],
4124   "map": {"at": 165360, "to": "mm"},
4125   "name": "PA_CL_UCP_3_Y"
4126  },
4127  {
4128   "chips": ["gfx103"],
4129   "map": {"at": 165364, "to": "mm"},
4130   "name": "PA_CL_UCP_3_Z"
4131  },
4132  {
4133   "chips": ["gfx103"],
4134   "map": {"at": 165368, "to": "mm"},
4135   "name": "PA_CL_UCP_3_W"
4136  },
4137  {
4138   "chips": ["gfx103"],
4139   "map": {"at": 165372, "to": "mm"},
4140   "name": "PA_CL_UCP_4_X"
4141  },
4142  {
4143   "chips": ["gfx103"],
4144   "map": {"at": 165376, "to": "mm"},
4145   "name": "PA_CL_UCP_4_Y"
4146  },
4147  {
4148   "chips": ["gfx103"],
4149   "map": {"at": 165380, "to": "mm"},
4150   "name": "PA_CL_UCP_4_Z"
4151  },
4152  {
4153   "chips": ["gfx103"],
4154   "map": {"at": 165384, "to": "mm"},
4155   "name": "PA_CL_UCP_4_W"
4156  },
4157  {
4158   "chips": ["gfx103"],
4159   "map": {"at": 165388, "to": "mm"},
4160   "name": "PA_CL_UCP_5_X"
4161  },
4162  {
4163   "chips": ["gfx103"],
4164   "map": {"at": 165392, "to": "mm"},
4165   "name": "PA_CL_UCP_5_Y"
4166  },
4167  {
4168   "chips": ["gfx103"],
4169   "map": {"at": 165396, "to": "mm"},
4170   "name": "PA_CL_UCP_5_Z"
4171  },
4172  {
4173   "chips": ["gfx103"],
4174   "map": {"at": 165400, "to": "mm"},
4175   "name": "PA_CL_UCP_5_W"
4176  },
4177  {
4178   "chips": ["gfx103"],
4179   "map": {"at": 165404, "to": "mm"},
4180   "name": "PA_CL_PROG_NEAR_CLIP_Z"
4181  },
4182  {
4183   "chips": ["gfx103"],
4184   "map": {"at": 165444, "to": "mm"},
4185   "name": "SPI_PS_INPUT_CNTL_0",
4186   "type_ref": "SPI_PS_INPUT_CNTL_0"
4187  },
4188  {
4189   "chips": ["gfx103"],
4190   "map": {"at": 165448, "to": "mm"},
4191   "name": "SPI_PS_INPUT_CNTL_1",
4192   "type_ref": "SPI_PS_INPUT_CNTL_0"
4193  },
4194  {
4195   "chips": ["gfx103"],
4196   "map": {"at": 165452, "to": "mm"},
4197   "name": "SPI_PS_INPUT_CNTL_2",
4198   "type_ref": "SPI_PS_INPUT_CNTL_0"
4199  },
4200  {
4201   "chips": ["gfx103"],
4202   "map": {"at": 165456, "to": "mm"},
4203   "name": "SPI_PS_INPUT_CNTL_3",
4204   "type_ref": "SPI_PS_INPUT_CNTL_0"
4205  },
4206  {
4207   "chips": ["gfx103"],
4208   "map": {"at": 165460, "to": "mm"},
4209   "name": "SPI_PS_INPUT_CNTL_4",
4210   "type_ref": "SPI_PS_INPUT_CNTL_0"
4211  },
4212  {
4213   "chips": ["gfx103"],
4214   "map": {"at": 165464, "to": "mm"},
4215   "name": "SPI_PS_INPUT_CNTL_5",
4216   "type_ref": "SPI_PS_INPUT_CNTL_0"
4217  },
4218  {
4219   "chips": ["gfx103"],
4220   "map": {"at": 165468, "to": "mm"},
4221   "name": "SPI_PS_INPUT_CNTL_6",
4222   "type_ref": "SPI_PS_INPUT_CNTL_0"
4223  },
4224  {
4225   "chips": ["gfx103"],
4226   "map": {"at": 165472, "to": "mm"},
4227   "name": "SPI_PS_INPUT_CNTL_7",
4228   "type_ref": "SPI_PS_INPUT_CNTL_0"
4229  },
4230  {
4231   "chips": ["gfx103"],
4232   "map": {"at": 165476, "to": "mm"},
4233   "name": "SPI_PS_INPUT_CNTL_8",
4234   "type_ref": "SPI_PS_INPUT_CNTL_0"
4235  },
4236  {
4237   "chips": ["gfx103"],
4238   "map": {"at": 165480, "to": "mm"},
4239   "name": "SPI_PS_INPUT_CNTL_9",
4240   "type_ref": "SPI_PS_INPUT_CNTL_0"
4241  },
4242  {
4243   "chips": ["gfx103"],
4244   "map": {"at": 165484, "to": "mm"},
4245   "name": "SPI_PS_INPUT_CNTL_10",
4246   "type_ref": "SPI_PS_INPUT_CNTL_0"
4247  },
4248  {
4249   "chips": ["gfx103"],
4250   "map": {"at": 165488, "to": "mm"},
4251   "name": "SPI_PS_INPUT_CNTL_11",
4252   "type_ref": "SPI_PS_INPUT_CNTL_0"
4253  },
4254  {
4255   "chips": ["gfx103"],
4256   "map": {"at": 165492, "to": "mm"},
4257   "name": "SPI_PS_INPUT_CNTL_12",
4258   "type_ref": "SPI_PS_INPUT_CNTL_0"
4259  },
4260  {
4261   "chips": ["gfx103"],
4262   "map": {"at": 165496, "to": "mm"},
4263   "name": "SPI_PS_INPUT_CNTL_13",
4264   "type_ref": "SPI_PS_INPUT_CNTL_0"
4265  },
4266  {
4267   "chips": ["gfx103"],
4268   "map": {"at": 165500, "to": "mm"},
4269   "name": "SPI_PS_INPUT_CNTL_14",
4270   "type_ref": "SPI_PS_INPUT_CNTL_0"
4271  },
4272  {
4273   "chips": ["gfx103"],
4274   "map": {"at": 165504, "to": "mm"},
4275   "name": "SPI_PS_INPUT_CNTL_15",
4276   "type_ref": "SPI_PS_INPUT_CNTL_0"
4277  },
4278  {
4279   "chips": ["gfx103"],
4280   "map": {"at": 165508, "to": "mm"},
4281   "name": "SPI_PS_INPUT_CNTL_16",
4282   "type_ref": "SPI_PS_INPUT_CNTL_0"
4283  },
4284  {
4285   "chips": ["gfx103"],
4286   "map": {"at": 165512, "to": "mm"},
4287   "name": "SPI_PS_INPUT_CNTL_17",
4288   "type_ref": "SPI_PS_INPUT_CNTL_0"
4289  },
4290  {
4291   "chips": ["gfx103"],
4292   "map": {"at": 165516, "to": "mm"},
4293   "name": "SPI_PS_INPUT_CNTL_18",
4294   "type_ref": "SPI_PS_INPUT_CNTL_0"
4295  },
4296  {
4297   "chips": ["gfx103"],
4298   "map": {"at": 165520, "to": "mm"},
4299   "name": "SPI_PS_INPUT_CNTL_19",
4300   "type_ref": "SPI_PS_INPUT_CNTL_0"
4301  },
4302  {
4303   "chips": ["gfx103"],
4304   "map": {"at": 165524, "to": "mm"},
4305   "name": "SPI_PS_INPUT_CNTL_20",
4306   "type_ref": "SPI_PS_INPUT_CNTL_20"
4307  },
4308  {
4309   "chips": ["gfx103"],
4310   "map": {"at": 165528, "to": "mm"},
4311   "name": "SPI_PS_INPUT_CNTL_21",
4312   "type_ref": "SPI_PS_INPUT_CNTL_20"
4313  },
4314  {
4315   "chips": ["gfx103"],
4316   "map": {"at": 165532, "to": "mm"},
4317   "name": "SPI_PS_INPUT_CNTL_22",
4318   "type_ref": "SPI_PS_INPUT_CNTL_20"
4319  },
4320  {
4321   "chips": ["gfx103"],
4322   "map": {"at": 165536, "to": "mm"},
4323   "name": "SPI_PS_INPUT_CNTL_23",
4324   "type_ref": "SPI_PS_INPUT_CNTL_20"
4325  },
4326  {
4327   "chips": ["gfx103"],
4328   "map": {"at": 165540, "to": "mm"},
4329   "name": "SPI_PS_INPUT_CNTL_24",
4330   "type_ref": "SPI_PS_INPUT_CNTL_20"
4331  },
4332  {
4333   "chips": ["gfx103"],
4334   "map": {"at": 165544, "to": "mm"},
4335   "name": "SPI_PS_INPUT_CNTL_25",
4336   "type_ref": "SPI_PS_INPUT_CNTL_20"
4337  },
4338  {
4339   "chips": ["gfx103"],
4340   "map": {"at": 165548, "to": "mm"},
4341   "name": "SPI_PS_INPUT_CNTL_26",
4342   "type_ref": "SPI_PS_INPUT_CNTL_20"
4343  },
4344  {
4345   "chips": ["gfx103"],
4346   "map": {"at": 165552, "to": "mm"},
4347   "name": "SPI_PS_INPUT_CNTL_27",
4348   "type_ref": "SPI_PS_INPUT_CNTL_20"
4349  },
4350  {
4351   "chips": ["gfx103"],
4352   "map": {"at": 165556, "to": "mm"},
4353   "name": "SPI_PS_INPUT_CNTL_28",
4354   "type_ref": "SPI_PS_INPUT_CNTL_20"
4355  },
4356  {
4357   "chips": ["gfx103"],
4358   "map": {"at": 165560, "to": "mm"},
4359   "name": "SPI_PS_INPUT_CNTL_29",
4360   "type_ref": "SPI_PS_INPUT_CNTL_20"
4361  },
4362  {
4363   "chips": ["gfx103"],
4364   "map": {"at": 165564, "to": "mm"},
4365   "name": "SPI_PS_INPUT_CNTL_30",
4366   "type_ref": "SPI_PS_INPUT_CNTL_20"
4367  },
4368  {
4369   "chips": ["gfx103"],
4370   "map": {"at": 165568, "to": "mm"},
4371   "name": "SPI_PS_INPUT_CNTL_31",
4372   "type_ref": "SPI_PS_INPUT_CNTL_20"
4373  },
4374  {
4375   "chips": ["gfx103"],
4376   "map": {"at": 165572, "to": "mm"},
4377   "name": "SPI_VS_OUT_CONFIG",
4378   "type_ref": "SPI_VS_OUT_CONFIG"
4379  },
4380  {
4381   "chips": ["gfx103"],
4382   "map": {"at": 165580, "to": "mm"},
4383   "name": "SPI_PS_INPUT_ENA",
4384   "type_ref": "SPI_PS_INPUT_ENA"
4385  },
4386  {
4387   "chips": ["gfx103"],
4388   "map": {"at": 165584, "to": "mm"},
4389   "name": "SPI_PS_INPUT_ADDR",
4390   "type_ref": "SPI_PS_INPUT_ENA"
4391  },
4392  {
4393   "chips": ["gfx103"],
4394   "map": {"at": 165588, "to": "mm"},
4395   "name": "SPI_INTERP_CONTROL_0",
4396   "type_ref": "SPI_INTERP_CONTROL_0"
4397  },
4398  {
4399   "chips": ["gfx103"],
4400   "map": {"at": 165592, "to": "mm"},
4401   "name": "SPI_PS_IN_CONTROL",
4402   "type_ref": "SPI_PS_IN_CONTROL"
4403  },
4404  {
4405   "chips": ["gfx103"],
4406   "map": {"at": 165600, "to": "mm"},
4407   "name": "SPI_BARYC_CNTL",
4408   "type_ref": "SPI_BARYC_CNTL"
4409  },
4410  {
4411   "chips": ["gfx103"],
4412   "map": {"at": 165608, "to": "mm"},
4413   "name": "SPI_TMPRING_SIZE",
4414   "type_ref": "COMPUTE_TMPRING_SIZE"
4415  },
4416  {
4417   "chips": ["gfx103"],
4418   "map": {"at": 165640, "to": "mm"},
4419   "name": "SPI_SHADER_IDX_FORMAT",
4420   "type_ref": "SPI_SHADER_IDX_FORMAT"
4421  },
4422  {
4423   "chips": ["gfx103"],
4424   "map": {"at": 165644, "to": "mm"},
4425   "name": "SPI_SHADER_POS_FORMAT",
4426   "type_ref": "SPI_SHADER_POS_FORMAT"
4427  },
4428  {
4429   "chips": ["gfx103"],
4430   "map": {"at": 165648, "to": "mm"},
4431   "name": "SPI_SHADER_Z_FORMAT",
4432   "type_ref": "SPI_SHADER_Z_FORMAT"
4433  },
4434  {
4435   "chips": ["gfx103"],
4436   "map": {"at": 165652, "to": "mm"},
4437   "name": "SPI_SHADER_COL_FORMAT",
4438   "type_ref": "SPI_SHADER_COL_FORMAT"
4439  },
4440  {
4441   "chips": ["gfx103"],
4442   "map": {"at": 165712, "to": "mm"},
4443   "name": "SX_PS_DOWNCONVERT_CONTROL",
4444   "type_ref": "SX_PS_DOWNCONVERT_CONTROL"
4445  },
4446  {
4447   "chips": ["gfx103"],
4448   "map": {"at": 165716, "to": "mm"},
4449   "name": "SX_PS_DOWNCONVERT",
4450   "type_ref": "SX_PS_DOWNCONVERT"
4451  },
4452  {
4453   "chips": ["gfx103"],
4454   "map": {"at": 165720, "to": "mm"},
4455   "name": "SX_BLEND_OPT_EPSILON",
4456   "type_ref": "SX_BLEND_OPT_EPSILON"
4457  },
4458  {
4459   "chips": ["gfx103"],
4460   "map": {"at": 165724, "to": "mm"},
4461   "name": "SX_BLEND_OPT_CONTROL",
4462   "type_ref": "SX_BLEND_OPT_CONTROL"
4463  },
4464  {
4465   "chips": ["gfx103"],
4466   "map": {"at": 165728, "to": "mm"},
4467   "name": "SX_MRT0_BLEND_OPT",
4468   "type_ref": "SX_MRT0_BLEND_OPT"
4469  },
4470  {
4471   "chips": ["gfx103"],
4472   "map": {"at": 165732, "to": "mm"},
4473   "name": "SX_MRT1_BLEND_OPT",
4474   "type_ref": "SX_MRT0_BLEND_OPT"
4475  },
4476  {
4477   "chips": ["gfx103"],
4478   "map": {"at": 165736, "to": "mm"},
4479   "name": "SX_MRT2_BLEND_OPT",
4480   "type_ref": "SX_MRT0_BLEND_OPT"
4481  },
4482  {
4483   "chips": ["gfx103"],
4484   "map": {"at": 165740, "to": "mm"},
4485   "name": "SX_MRT3_BLEND_OPT",
4486   "type_ref": "SX_MRT0_BLEND_OPT"
4487  },
4488  {
4489   "chips": ["gfx103"],
4490   "map": {"at": 165744, "to": "mm"},
4491   "name": "SX_MRT4_BLEND_OPT",
4492   "type_ref": "SX_MRT0_BLEND_OPT"
4493  },
4494  {
4495   "chips": ["gfx103"],
4496   "map": {"at": 165748, "to": "mm"},
4497   "name": "SX_MRT5_BLEND_OPT",
4498   "type_ref": "SX_MRT0_BLEND_OPT"
4499  },
4500  {
4501   "chips": ["gfx103"],
4502   "map": {"at": 165752, "to": "mm"},
4503   "name": "SX_MRT6_BLEND_OPT",
4504   "type_ref": "SX_MRT0_BLEND_OPT"
4505  },
4506  {
4507   "chips": ["gfx103"],
4508   "map": {"at": 165756, "to": "mm"},
4509   "name": "SX_MRT7_BLEND_OPT",
4510   "type_ref": "SX_MRT0_BLEND_OPT"
4511  },
4512  {
4513   "chips": ["gfx103"],
4514   "map": {"at": 165760, "to": "mm"},
4515   "name": "CB_BLEND0_CONTROL",
4516   "type_ref": "CB_BLEND0_CONTROL"
4517  },
4518  {
4519   "chips": ["gfx103"],
4520   "map": {"at": 165764, "to": "mm"},
4521   "name": "CB_BLEND1_CONTROL",
4522   "type_ref": "CB_BLEND0_CONTROL"
4523  },
4524  {
4525   "chips": ["gfx103"],
4526   "map": {"at": 165768, "to": "mm"},
4527   "name": "CB_BLEND2_CONTROL",
4528   "type_ref": "CB_BLEND0_CONTROL"
4529  },
4530  {
4531   "chips": ["gfx103"],
4532   "map": {"at": 165772, "to": "mm"},
4533   "name": "CB_BLEND3_CONTROL",
4534   "type_ref": "CB_BLEND0_CONTROL"
4535  },
4536  {
4537   "chips": ["gfx103"],
4538   "map": {"at": 165776, "to": "mm"},
4539   "name": "CB_BLEND4_CONTROL",
4540   "type_ref": "CB_BLEND0_CONTROL"
4541  },
4542  {
4543   "chips": ["gfx103"],
4544   "map": {"at": 165780, "to": "mm"},
4545   "name": "CB_BLEND5_CONTROL",
4546   "type_ref": "CB_BLEND0_CONTROL"
4547  },
4548  {
4549   "chips": ["gfx103"],
4550   "map": {"at": 165784, "to": "mm"},
4551   "name": "CB_BLEND6_CONTROL",
4552   "type_ref": "CB_BLEND0_CONTROL"
4553  },
4554  {
4555   "chips": ["gfx103"],
4556   "map": {"at": 165788, "to": "mm"},
4557   "name": "CB_BLEND7_CONTROL",
4558   "type_ref": "CB_BLEND0_CONTROL"
4559  },
4560  {
4561   "chips": ["gfx103"],
4562   "map": {"at": 165836, "to": "mm"},
4563   "name": "CS_COPY_STATE",
4564   "type_ref": "CS_COPY_STATE"
4565  },
4566  {
4567   "chips": ["gfx103"],
4568   "map": {"at": 165840, "to": "mm"},
4569   "name": "GFX_COPY_STATE",
4570   "type_ref": "CS_COPY_STATE"
4571  },
4572  {
4573   "chips": ["gfx103"],
4574   "map": {"at": 165844, "to": "mm"},
4575   "name": "PA_CL_POINT_X_RAD"
4576  },
4577  {
4578   "chips": ["gfx103"],
4579   "map": {"at": 165848, "to": "mm"},
4580   "name": "PA_CL_POINT_Y_RAD"
4581  },
4582  {
4583   "chips": ["gfx103"],
4584   "map": {"at": 165852, "to": "mm"},
4585   "name": "PA_CL_POINT_SIZE"
4586  },
4587  {
4588   "chips": ["gfx103"],
4589   "map": {"at": 165856, "to": "mm"},
4590   "name": "PA_CL_POINT_CULL_RAD"
4591  },
4592  {
4593   "chips": ["gfx103"],
4594   "map": {"at": 165860, "to": "mm"},
4595   "name": "VGT_DMA_BASE_HI",
4596   "type_ref": "VGT_DMA_BASE_HI"
4597  },
4598  {
4599   "chips": ["gfx103"],
4600   "map": {"at": 165864, "to": "mm"},
4601   "name": "VGT_DMA_BASE"
4602  },
4603  {
4604   "chips": ["gfx103"],
4605   "map": {"at": 165872, "to": "mm"},
4606   "name": "VGT_DRAW_INITIATOR",
4607   "type_ref": "VGT_DRAW_INITIATOR"
4608  },
4609  {
4610   "chips": ["gfx103"],
4611   "map": {"at": 165876, "to": "mm"},
4612   "name": "VGT_IMMED_DATA"
4613  },
4614  {
4615   "chips": ["gfx103"],
4616   "map": {"at": 165880, "to": "mm"},
4617   "name": "VGT_EVENT_ADDRESS_REG",
4618   "type_ref": "VGT_EVENT_ADDRESS_REG"
4619  },
4620  {
4621   "chips": ["gfx103"],
4622   "map": {"at": 165884, "to": "mm"},
4623   "name": "GE_MAX_OUTPUT_PER_SUBGROUP",
4624   "type_ref": "GE_MAX_OUTPUT_PER_SUBGROUP"
4625  },
4626  {
4627   "chips": ["gfx103"],
4628   "map": {"at": 165888, "to": "mm"},
4629   "name": "DB_DEPTH_CONTROL",
4630   "type_ref": "DB_DEPTH_CONTROL"
4631  },
4632  {
4633   "chips": ["gfx103"],
4634   "map": {"at": 165892, "to": "mm"},
4635   "name": "DB_EQAA",
4636   "type_ref": "DB_EQAA"
4637  },
4638  {
4639   "chips": ["gfx103"],
4640   "map": {"at": 165896, "to": "mm"},
4641   "name": "CB_COLOR_CONTROL",
4642   "type_ref": "CB_COLOR_CONTROL"
4643  },
4644  {
4645   "chips": ["gfx103"],
4646   "map": {"at": 165900, "to": "mm"},
4647   "name": "DB_SHADER_CONTROL",
4648   "type_ref": "DB_SHADER_CONTROL"
4649  },
4650  {
4651   "chips": ["gfx103"],
4652   "map": {"at": 165904, "to": "mm"},
4653   "name": "PA_CL_CLIP_CNTL",
4654   "type_ref": "PA_CL_CLIP_CNTL"
4655  },
4656  {
4657   "chips": ["gfx103"],
4658   "map": {"at": 165908, "to": "mm"},
4659   "name": "PA_SU_SC_MODE_CNTL",
4660   "type_ref": "PA_SU_SC_MODE_CNTL"
4661  },
4662  {
4663   "chips": ["gfx103"],
4664   "map": {"at": 165912, "to": "mm"},
4665   "name": "PA_CL_VTE_CNTL",
4666   "type_ref": "PA_CL_VTE_CNTL"
4667  },
4668  {
4669   "chips": ["gfx103"],
4670   "map": {"at": 165916, "to": "mm"},
4671   "name": "PA_CL_VS_OUT_CNTL",
4672   "type_ref": "PA_CL_VS_OUT_CNTL"
4673  },
4674  {
4675   "chips": ["gfx103"],
4676   "map": {"at": 165920, "to": "mm"},
4677   "name": "PA_CL_NANINF_CNTL",
4678   "type_ref": "PA_CL_NANINF_CNTL"
4679  },
4680  {
4681   "chips": ["gfx103"],
4682   "map": {"at": 165924, "to": "mm"},
4683   "name": "PA_SU_LINE_STIPPLE_CNTL",
4684   "type_ref": "PA_SU_LINE_STIPPLE_CNTL"
4685  },
4686  {
4687   "chips": ["gfx103"],
4688   "map": {"at": 165928, "to": "mm"},
4689   "name": "PA_SU_LINE_STIPPLE_SCALE"
4690  },
4691  {
4692   "chips": ["gfx103"],
4693   "map": {"at": 165932, "to": "mm"},
4694   "name": "PA_SU_PRIM_FILTER_CNTL",
4695   "type_ref": "PA_SU_PRIM_FILTER_CNTL"
4696  },
4697  {
4698   "chips": ["gfx103"],
4699   "map": {"at": 165936, "to": "mm"},
4700   "name": "PA_SU_SMALL_PRIM_FILTER_CNTL",
4701   "type_ref": "PA_SU_SMALL_PRIM_FILTER_CNTL"
4702  },
4703  {
4704   "chips": ["gfx103"],
4705   "map": {"at": 165944, "to": "mm"},
4706   "name": "PA_CL_NGG_CNTL",
4707   "type_ref": "PA_CL_NGG_CNTL"
4708  },
4709  {
4710   "chips": ["gfx103"],
4711   "map": {"at": 165948, "to": "mm"},
4712   "name": "PA_SU_OVER_RASTERIZATION_CNTL",
4713   "type_ref": "PA_SU_OVER_RASTERIZATION_CNTL"
4714  },
4715  {
4716   "chips": ["gfx103"],
4717   "map": {"at": 165952, "to": "mm"},
4718   "name": "PA_STEREO_CNTL",
4719   "type_ref": "PA_STEREO_CNTL"
4720  },
4721  {
4722   "chips": ["gfx103"],
4723   "map": {"at": 165956, "to": "mm"},
4724   "name": "PA_STATE_STEREO_X"
4725  },
4726  {
4727   "chips": ["gfx103"],
4728   "map": {"at": 165960, "to": "mm"},
4729   "name": "PA_CL_VRS_CNTL",
4730   "type_ref": "PA_CL_VRS_CNTL"
4731  },
4732  {
4733   "chips": ["gfx103"],
4734   "map": {"at": 166400, "to": "mm"},
4735   "name": "PA_SU_POINT_SIZE",
4736   "type_ref": "PA_SU_POINT_SIZE"
4737  },
4738  {
4739   "chips": ["gfx103"],
4740   "map": {"at": 166404, "to": "mm"},
4741   "name": "PA_SU_POINT_MINMAX",
4742   "type_ref": "PA_SU_POINT_MINMAX"
4743  },
4744  {
4745   "chips": ["gfx103"],
4746   "map": {"at": 166408, "to": "mm"},
4747   "name": "PA_SU_LINE_CNTL",
4748   "type_ref": "PA_SU_LINE_CNTL"
4749  },
4750  {
4751   "chips": ["gfx103"],
4752   "map": {"at": 166412, "to": "mm"},
4753   "name": "PA_SC_LINE_STIPPLE",
4754   "type_ref": "PA_SC_LINE_STIPPLE"
4755  },
4756  {
4757   "chips": ["gfx103"],
4758   "map": {"at": 166416, "to": "mm"},
4759   "name": "VGT_OUTPUT_PATH_CNTL",
4760   "type_ref": "VGT_OUTPUT_PATH_CNTL"
4761  },
4762  {
4763   "chips": ["gfx103"],
4764   "map": {"at": 166420, "to": "mm"},
4765   "name": "VGT_HOS_CNTL",
4766   "type_ref": "VGT_HOS_CNTL"
4767  },
4768  {
4769   "chips": ["gfx103"],
4770   "map": {"at": 166424, "to": "mm"},
4771   "name": "VGT_HOS_MAX_TESS_LEVEL"
4772  },
4773  {
4774   "chips": ["gfx103"],
4775   "map": {"at": 166428, "to": "mm"},
4776   "name": "VGT_HOS_MIN_TESS_LEVEL"
4777  },
4778  {
4779   "chips": ["gfx103"],
4780   "map": {"at": 166432, "to": "mm"},
4781   "name": "VGT_HOS_REUSE_DEPTH",
4782   "type_ref": "VGT_HOS_REUSE_DEPTH"
4783  },
4784  {
4785   "chips": ["gfx103"],
4786   "map": {"at": 166436, "to": "mm"},
4787   "name": "VGT_GROUP_PRIM_TYPE",
4788   "type_ref": "VGT_GROUP_PRIM_TYPE"
4789  },
4790  {
4791   "chips": ["gfx103"],
4792   "map": {"at": 166440, "to": "mm"},
4793   "name": "VGT_GROUP_FIRST_DECR",
4794   "type_ref": "VGT_GROUP_FIRST_DECR"
4795  },
4796  {
4797   "chips": ["gfx103"],
4798   "map": {"at": 166444, "to": "mm"},
4799   "name": "VGT_GROUP_DECR",
4800   "type_ref": "VGT_GROUP_DECR"
4801  },
4802  {
4803   "chips": ["gfx103"],
4804   "map": {"at": 166448, "to": "mm"},
4805   "name": "VGT_GROUP_VECT_0_CNTL",
4806   "type_ref": "VGT_GROUP_VECT_0_CNTL"
4807  },
4808  {
4809   "chips": ["gfx103"],
4810   "map": {"at": 166452, "to": "mm"},
4811   "name": "VGT_GROUP_VECT_1_CNTL",
4812   "type_ref": "VGT_GROUP_VECT_0_CNTL"
4813  },
4814  {
4815   "chips": ["gfx103"],
4816   "map": {"at": 166456, "to": "mm"},
4817   "name": "VGT_GROUP_VECT_0_FMT_CNTL",
4818   "type_ref": "VGT_GROUP_VECT_0_FMT_CNTL"
4819  },
4820  {
4821   "chips": ["gfx103"],
4822   "map": {"at": 166460, "to": "mm"},
4823   "name": "VGT_GROUP_VECT_1_FMT_CNTL",
4824   "type_ref": "VGT_GROUP_VECT_0_FMT_CNTL"
4825  },
4826  {
4827   "chips": ["gfx103"],
4828   "map": {"at": 166464, "to": "mm"},
4829   "name": "VGT_GS_MODE",
4830   "type_ref": "VGT_GS_MODE"
4831  },
4832  {
4833   "chips": ["gfx103"],
4834   "map": {"at": 166468, "to": "mm"},
4835   "name": "VGT_GS_ONCHIP_CNTL",
4836   "type_ref": "VGT_GS_ONCHIP_CNTL"
4837  },
4838  {
4839   "chips": ["gfx103"],
4840   "map": {"at": 166472, "to": "mm"},
4841   "name": "PA_SC_MODE_CNTL_0",
4842   "type_ref": "PA_SC_MODE_CNTL_0"
4843  },
4844  {
4845   "chips": ["gfx103"],
4846   "map": {"at": 166476, "to": "mm"},
4847   "name": "PA_SC_MODE_CNTL_1",
4848   "type_ref": "PA_SC_MODE_CNTL_1"
4849  },
4850  {
4851   "chips": ["gfx103"],
4852   "map": {"at": 166480, "to": "mm"},
4853   "name": "VGT_ENHANCE"
4854  },
4855  {
4856   "chips": ["gfx103"],
4857   "map": {"at": 166484, "to": "mm"},
4858   "name": "VGT_GS_PER_ES",
4859   "type_ref": "VGT_GS_PER_ES"
4860  },
4861  {
4862   "chips": ["gfx103"],
4863   "map": {"at": 166488, "to": "mm"},
4864   "name": "VGT_ES_PER_GS",
4865   "type_ref": "VGT_ES_PER_GS"
4866  },
4867  {
4868   "chips": ["gfx103"],
4869   "map": {"at": 166492, "to": "mm"},
4870   "name": "VGT_GS_PER_VS",
4871   "type_ref": "VGT_GS_PER_VS"
4872  },
4873  {
4874   "chips": ["gfx103"],
4875   "map": {"at": 166496, "to": "mm"},
4876   "name": "VGT_GSVS_RING_OFFSET_1",
4877   "type_ref": "VGT_GSVS_RING_OFFSET_1"
4878  },
4879  {
4880   "chips": ["gfx103"],
4881   "map": {"at": 166500, "to": "mm"},
4882   "name": "VGT_GSVS_RING_OFFSET_2",
4883   "type_ref": "VGT_GSVS_RING_OFFSET_1"
4884  },
4885  {
4886   "chips": ["gfx103"],
4887   "map": {"at": 166504, "to": "mm"},
4888   "name": "VGT_GSVS_RING_OFFSET_3",
4889   "type_ref": "VGT_GSVS_RING_OFFSET_1"
4890  },
4891  {
4892   "chips": ["gfx103"],
4893   "map": {"at": 166508, "to": "mm"},
4894   "name": "VGT_GS_OUT_PRIM_TYPE",
4895   "type_ref": "VGT_GS_OUT_PRIM_TYPE"
4896  },
4897  {
4898   "chips": ["gfx103"],
4899   "map": {"at": 166512, "to": "mm"},
4900   "name": "IA_ENHANCE"
4901  },
4902  {
4903   "chips": ["gfx103"],
4904   "map": {"at": 166516, "to": "mm"},
4905   "name": "VGT_DMA_SIZE"
4906  },
4907  {
4908   "chips": ["gfx103"],
4909   "map": {"at": 166520, "to": "mm"},
4910   "name": "VGT_DMA_MAX_SIZE"
4911  },
4912  {
4913   "chips": ["gfx103"],
4914   "map": {"at": 166524, "to": "mm"},
4915   "name": "VGT_DMA_INDEX_TYPE",
4916   "type_ref": "VGT_DMA_INDEX_TYPE"
4917  },
4918  {
4919   "chips": ["gfx103"],
4920   "map": {"at": 166528, "to": "mm"},
4921   "name": "WD_ENHANCE"
4922  },
4923  {
4924   "chips": ["gfx103"],
4925   "map": {"at": 166532, "to": "mm"},
4926   "name": "VGT_PRIMITIVEID_EN",
4927   "type_ref": "VGT_PRIMITIVEID_EN"
4928  },
4929  {
4930   "chips": ["gfx103"],
4931   "map": {"at": 166536, "to": "mm"},
4932   "name": "VGT_DMA_NUM_INSTANCES"
4933  },
4934  {
4935   "chips": ["gfx103"],
4936   "map": {"at": 166540, "to": "mm"},
4937   "name": "VGT_PRIMITIVEID_RESET"
4938  },
4939  {
4940   "chips": ["gfx103"],
4941   "map": {"at": 166544, "to": "mm"},
4942   "name": "VGT_EVENT_INITIATOR",
4943   "type_ref": "VGT_EVENT_INITIATOR"
4944  },
4945  {
4946   "chips": ["gfx103"],
4947   "map": {"at": 166548, "to": "mm"},
4948   "name": "VGT_MULTI_PRIM_IB_RESET_EN",
4949   "type_ref": "VGT_MULTI_PRIM_IB_RESET_EN"
4950  },
4951  {
4952   "chips": ["gfx103"],
4953   "map": {"at": 166552, "to": "mm"},
4954   "name": "VGT_DRAW_PAYLOAD_CNTL",
4955   "type_ref": "VGT_DRAW_PAYLOAD_CNTL"
4956  },
4957  {
4958   "chips": ["gfx103"],
4959   "map": {"at": 166560, "to": "mm"},
4960   "name": "VGT_INSTANCE_STEP_RATE_0"
4961  },
4962  {
4963   "chips": ["gfx103"],
4964   "map": {"at": 166564, "to": "mm"},
4965   "name": "VGT_INSTANCE_STEP_RATE_1"
4966  },
4967  {
4968   "chips": ["gfx103"],
4969   "map": {"at": 166568, "to": "mm"},
4970   "name": "IA_MULTI_VGT_PARAM",
4971   "type_ref": "IA_MULTI_VGT_PARAM"
4972  },
4973  {
4974   "chips": ["gfx103"],
4975   "map": {"at": 166572, "to": "mm"},
4976   "name": "VGT_ESGS_RING_ITEMSIZE",
4977   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
4978  },
4979  {
4980   "chips": ["gfx103"],
4981   "map": {"at": 166576, "to": "mm"},
4982   "name": "VGT_GSVS_RING_ITEMSIZE",
4983   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
4984  },
4985  {
4986   "chips": ["gfx103"],
4987   "map": {"at": 166580, "to": "mm"},
4988   "name": "VGT_REUSE_OFF",
4989   "type_ref": "VGT_REUSE_OFF"
4990  },
4991  {
4992   "chips": ["gfx103"],
4993   "map": {"at": 166584, "to": "mm"},
4994   "name": "VGT_VTX_CNT_EN",
4995   "type_ref": "VGT_VTX_CNT_EN"
4996  },
4997  {
4998   "chips": ["gfx103"],
4999   "map": {"at": 166588, "to": "mm"},
5000   "name": "DB_HTILE_SURFACE",
5001   "type_ref": "DB_HTILE_SURFACE"
5002  },
5003  {
5004   "chips": ["gfx103"],
5005   "map": {"at": 166592, "to": "mm"},
5006   "name": "DB_SRESULTS_COMPARE_STATE0",
5007   "type_ref": "DB_SRESULTS_COMPARE_STATE0"
5008  },
5009  {
5010   "chips": ["gfx103"],
5011   "map": {"at": 166596, "to": "mm"},
5012   "name": "DB_SRESULTS_COMPARE_STATE1",
5013   "type_ref": "DB_SRESULTS_COMPARE_STATE1"
5014  },
5015  {
5016   "chips": ["gfx103"],
5017   "map": {"at": 166600, "to": "mm"},
5018   "name": "DB_PRELOAD_CONTROL",
5019   "type_ref": "DB_PRELOAD_CONTROL"
5020  },
5021  {
5022   "chips": ["gfx103"],
5023   "map": {"at": 166608, "to": "mm"},
5024   "name": "VGT_STRMOUT_BUFFER_SIZE_0"
5025  },
5026  {
5027   "chips": ["gfx103"],
5028   "map": {"at": 166612, "to": "mm"},
5029   "name": "VGT_STRMOUT_VTX_STRIDE_0",
5030   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
5031  },
5032  {
5033   "chips": ["gfx103"],
5034   "map": {"at": 166620, "to": "mm"},
5035   "name": "VGT_STRMOUT_BUFFER_OFFSET_0"
5036  },
5037  {
5038   "chips": ["gfx103"],
5039   "map": {"at": 166624, "to": "mm"},
5040   "name": "VGT_STRMOUT_BUFFER_SIZE_1"
5041  },
5042  {
5043   "chips": ["gfx103"],
5044   "map": {"at": 166628, "to": "mm"},
5045   "name": "VGT_STRMOUT_VTX_STRIDE_1",
5046   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
5047  },
5048  {
5049   "chips": ["gfx103"],
5050   "map": {"at": 166636, "to": "mm"},
5051   "name": "VGT_STRMOUT_BUFFER_OFFSET_1"
5052  },
5053  {
5054   "chips": ["gfx103"],
5055   "map": {"at": 166640, "to": "mm"},
5056   "name": "VGT_STRMOUT_BUFFER_SIZE_2"
5057  },
5058  {
5059   "chips": ["gfx103"],
5060   "map": {"at": 166644, "to": "mm"},
5061   "name": "VGT_STRMOUT_VTX_STRIDE_2",
5062   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
5063  },
5064  {
5065   "chips": ["gfx103"],
5066   "map": {"at": 166652, "to": "mm"},
5067   "name": "VGT_STRMOUT_BUFFER_OFFSET_2"
5068  },
5069  {
5070   "chips": ["gfx103"],
5071   "map": {"at": 166656, "to": "mm"},
5072   "name": "VGT_STRMOUT_BUFFER_SIZE_3"
5073  },
5074  {
5075   "chips": ["gfx103"],
5076   "map": {"at": 166660, "to": "mm"},
5077   "name": "VGT_STRMOUT_VTX_STRIDE_3",
5078   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
5079  },
5080  {
5081   "chips": ["gfx103"],
5082   "map": {"at": 166668, "to": "mm"},
5083   "name": "VGT_STRMOUT_BUFFER_OFFSET_3"
5084  },
5085  {
5086   "chips": ["gfx103"],
5087   "map": {"at": 166696, "to": "mm"},
5088   "name": "VGT_STRMOUT_DRAW_OPAQUE_OFFSET"
5089  },
5090  {
5091   "chips": ["gfx103"],
5092   "map": {"at": 166700, "to": "mm"},
5093   "name": "VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE"
5094  },
5095  {
5096   "chips": ["gfx103"],
5097   "map": {"at": 166704, "to": "mm"},
5098   "name": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE",
5099   "type_ref": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE"
5100  },
5101  {
5102   "chips": ["gfx103"],
5103   "map": {"at": 166712, "to": "mm"},
5104   "name": "VGT_GS_MAX_VERT_OUT",
5105   "type_ref": "VGT_GS_MAX_VERT_OUT"
5106  },
5107  {
5108   "chips": ["gfx103"],
5109   "map": {"at": 166732, "to": "mm"},
5110   "name": "GE_NGG_SUBGRP_CNTL",
5111   "type_ref": "GE_NGG_SUBGRP_CNTL"
5112  },
5113  {
5114   "chips": ["gfx103"],
5115   "map": {"at": 166736, "to": "mm"},
5116   "name": "VGT_TESS_DISTRIBUTION",
5117   "type_ref": "VGT_TESS_DISTRIBUTION"
5118  },
5119  {
5120   "chips": ["gfx103"],
5121   "map": {"at": 166740, "to": "mm"},
5122   "name": "VGT_SHADER_STAGES_EN",
5123   "type_ref": "VGT_SHADER_STAGES_EN"
5124  },
5125  {
5126   "chips": ["gfx103"],
5127   "map": {"at": 166744, "to": "mm"},
5128   "name": "VGT_LS_HS_CONFIG",
5129   "type_ref": "VGT_LS_HS_CONFIG"
5130  },
5131  {
5132   "chips": ["gfx103"],
5133   "map": {"at": 166748, "to": "mm"},
5134   "name": "VGT_GS_VERT_ITEMSIZE",
5135   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5136  },
5137  {
5138   "chips": ["gfx103"],
5139   "map": {"at": 166752, "to": "mm"},
5140   "name": "VGT_GS_VERT_ITEMSIZE_1",
5141   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5142  },
5143  {
5144   "chips": ["gfx103"],
5145   "map": {"at": 166756, "to": "mm"},
5146   "name": "VGT_GS_VERT_ITEMSIZE_2",
5147   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5148  },
5149  {
5150   "chips": ["gfx103"],
5151   "map": {"at": 166760, "to": "mm"},
5152   "name": "VGT_GS_VERT_ITEMSIZE_3",
5153   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5154  },
5155  {
5156   "chips": ["gfx103"],
5157   "map": {"at": 166764, "to": "mm"},
5158   "name": "VGT_TF_PARAM",
5159   "type_ref": "VGT_TF_PARAM"
5160  },
5161  {
5162   "chips": ["gfx103"],
5163   "map": {"at": 166768, "to": "mm"},
5164   "name": "DB_ALPHA_TO_MASK",
5165   "type_ref": "DB_ALPHA_TO_MASK"
5166  },
5167  {
5168   "chips": ["gfx103"],
5169   "map": {"at": 166772, "to": "mm"},
5170   "name": "VGT_DISPATCH_DRAW_INDEX"
5171  },
5172  {
5173   "chips": ["gfx103"],
5174   "map": {"at": 166776, "to": "mm"},
5175   "name": "PA_SU_POLY_OFFSET_DB_FMT_CNTL",
5176   "type_ref": "PA_SU_POLY_OFFSET_DB_FMT_CNTL"
5177  },
5178  {
5179   "chips": ["gfx103"],
5180   "map": {"at": 166780, "to": "mm"},
5181   "name": "PA_SU_POLY_OFFSET_CLAMP"
5182  },
5183  {
5184   "chips": ["gfx103"],
5185   "map": {"at": 166784, "to": "mm"},
5186   "name": "PA_SU_POLY_OFFSET_FRONT_SCALE"
5187  },
5188  {
5189   "chips": ["gfx103"],
5190   "map": {"at": 166788, "to": "mm"},
5191   "name": "PA_SU_POLY_OFFSET_FRONT_OFFSET"
5192  },
5193  {
5194   "chips": ["gfx103"],
5195   "map": {"at": 166792, "to": "mm"},
5196   "name": "PA_SU_POLY_OFFSET_BACK_SCALE"
5197  },
5198  {
5199   "chips": ["gfx103"],
5200   "map": {"at": 166796, "to": "mm"},
5201   "name": "PA_SU_POLY_OFFSET_BACK_OFFSET"
5202  },
5203  {
5204   "chips": ["gfx103"],
5205   "map": {"at": 166800, "to": "mm"},
5206   "name": "VGT_GS_INSTANCE_CNT",
5207   "type_ref": "VGT_GS_INSTANCE_CNT"
5208  },
5209  {
5210   "chips": ["gfx103"],
5211   "map": {"at": 166804, "to": "mm"},
5212   "name": "VGT_STRMOUT_CONFIG",
5213   "type_ref": "VGT_STRMOUT_CONFIG"
5214  },
5215  {
5216   "chips": ["gfx103"],
5217   "map": {"at": 166808, "to": "mm"},
5218   "name": "VGT_STRMOUT_BUFFER_CONFIG",
5219   "type_ref": "VGT_STRMOUT_BUFFER_CONFIG"
5220  },
5221  {
5222   "chips": ["gfx103"],
5223   "map": {"at": 166812, "to": "mm"},
5224   "name": "VGT_DMA_EVENT_INITIATOR",
5225   "type_ref": "VGT_EVENT_INITIATOR"
5226  },
5227  {
5228   "chips": ["gfx103"],
5229   "map": {"at": 166868, "to": "mm"},
5230   "name": "PA_SC_CENTROID_PRIORITY_0",
5231   "type_ref": "PA_SC_CENTROID_PRIORITY_0"
5232  },
5233  {
5234   "chips": ["gfx103"],
5235   "map": {"at": 166872, "to": "mm"},
5236   "name": "PA_SC_CENTROID_PRIORITY_1",
5237   "type_ref": "PA_SC_CENTROID_PRIORITY_1"
5238  },
5239  {
5240   "chips": ["gfx103"],
5241   "map": {"at": 166876, "to": "mm"},
5242   "name": "PA_SC_LINE_CNTL",
5243   "type_ref": "PA_SC_LINE_CNTL"
5244  },
5245  {
5246   "chips": ["gfx103"],
5247   "map": {"at": 166880, "to": "mm"},
5248   "name": "PA_SC_AA_CONFIG",
5249   "type_ref": "PA_SC_AA_CONFIG"
5250  },
5251  {
5252   "chips": ["gfx103"],
5253   "map": {"at": 166884, "to": "mm"},
5254   "name": "PA_SU_VTX_CNTL",
5255   "type_ref": "PA_SU_VTX_CNTL"
5256  },
5257  {
5258   "chips": ["gfx103"],
5259   "map": {"at": 166888, "to": "mm"},
5260   "name": "PA_CL_GB_VERT_CLIP_ADJ"
5261  },
5262  {
5263   "chips": ["gfx103"],
5264   "map": {"at": 166892, "to": "mm"},
5265   "name": "PA_CL_GB_VERT_DISC_ADJ"
5266  },
5267  {
5268   "chips": ["gfx103"],
5269   "map": {"at": 166896, "to": "mm"},
5270   "name": "PA_CL_GB_HORZ_CLIP_ADJ"
5271  },
5272  {
5273   "chips": ["gfx103"],
5274   "map": {"at": 166900, "to": "mm"},
5275   "name": "PA_CL_GB_HORZ_DISC_ADJ"
5276  },
5277  {
5278   "chips": ["gfx103"],
5279   "map": {"at": 166904, "to": "mm"},
5280   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0",
5281   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
5282  },
5283  {
5284   "chips": ["gfx103"],
5285   "map": {"at": 166908, "to": "mm"},
5286   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1",
5287   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
5288  },
5289  {
5290   "chips": ["gfx103"],
5291   "map": {"at": 166912, "to": "mm"},
5292   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2",
5293   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
5294  },
5295  {
5296   "chips": ["gfx103"],
5297   "map": {"at": 166916, "to": "mm"},
5298   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3",
5299   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
5300  },
5301  {
5302   "chips": ["gfx103"],
5303   "map": {"at": 166920, "to": "mm"},
5304   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0",
5305   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
5306  },
5307  {
5308   "chips": ["gfx103"],
5309   "map": {"at": 166924, "to": "mm"},
5310   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1",
5311   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
5312  },
5313  {
5314   "chips": ["gfx103"],
5315   "map": {"at": 166928, "to": "mm"},
5316   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2",
5317   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
5318  },
5319  {
5320   "chips": ["gfx103"],
5321   "map": {"at": 166932, "to": "mm"},
5322   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3",
5323   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
5324  },
5325  {
5326   "chips": ["gfx103"],
5327   "map": {"at": 166936, "to": "mm"},
5328   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0",
5329   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
5330  },
5331  {
5332   "chips": ["gfx103"],
5333   "map": {"at": 166940, "to": "mm"},
5334   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1",
5335   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
5336  },
5337  {
5338   "chips": ["gfx103"],
5339   "map": {"at": 166944, "to": "mm"},
5340   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2",
5341   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
5342  },
5343  {
5344   "chips": ["gfx103"],
5345   "map": {"at": 166948, "to": "mm"},
5346   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3",
5347   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
5348  },
5349  {
5350   "chips": ["gfx103"],
5351   "map": {"at": 166952, "to": "mm"},
5352   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0",
5353   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
5354  },
5355  {
5356   "chips": ["gfx103"],
5357   "map": {"at": 166956, "to": "mm"},
5358   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1",
5359   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
5360  },
5361  {
5362   "chips": ["gfx103"],
5363   "map": {"at": 166960, "to": "mm"},
5364   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2",
5365   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
5366  },
5367  {
5368   "chips": ["gfx103"],
5369   "map": {"at": 166964, "to": "mm"},
5370   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3",
5371   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
5372  },
5373  {
5374   "chips": ["gfx103"],
5375   "map": {"at": 166968, "to": "mm"},
5376   "name": "PA_SC_AA_MASK_X0Y0_X1Y0",
5377   "type_ref": "PA_SC_AA_MASK_X0Y0_X1Y0"
5378  },
5379  {
5380   "chips": ["gfx103"],
5381   "map": {"at": 166972, "to": "mm"},
5382   "name": "PA_SC_AA_MASK_X0Y1_X1Y1",
5383   "type_ref": "PA_SC_AA_MASK_X0Y1_X1Y1"
5384  },
5385  {
5386   "chips": ["gfx103"],
5387   "map": {"at": 166976, "to": "mm"},
5388   "name": "PA_SC_SHADER_CONTROL",
5389   "type_ref": "PA_SC_SHADER_CONTROL"
5390  },
5391  {
5392   "chips": ["gfx103"],
5393   "map": {"at": 166980, "to": "mm"},
5394   "name": "PA_SC_BINNER_CNTL_0",
5395   "type_ref": "PA_SC_BINNER_CNTL_0"
5396  },
5397  {
5398   "chips": ["gfx103"],
5399   "map": {"at": 166984, "to": "mm"},
5400   "name": "PA_SC_BINNER_CNTL_1",
5401   "type_ref": "PA_SC_BINNER_CNTL_1"
5402  },
5403  {
5404   "chips": ["gfx103"],
5405   "map": {"at": 166988, "to": "mm"},
5406   "name": "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL",
5407   "type_ref": "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL"
5408  },
5409  {
5410   "chips": ["gfx103"],
5411   "map": {"at": 166992, "to": "mm"},
5412   "name": "PA_SC_NGG_MODE_CNTL",
5413   "type_ref": "PA_SC_NGG_MODE_CNTL"
5414  },
5415  {
5416   "chips": ["gfx103"],
5417   "map": {"at": 167000, "to": "mm"},
5418   "name": "VGT_VERTEX_REUSE_BLOCK_CNTL",
5419   "type_ref": "VGT_VERTEX_REUSE_BLOCK_CNTL"
5420  },
5421  {
5422   "chips": ["gfx103"],
5423   "map": {"at": 167004, "to": "mm"},
5424   "name": "VGT_OUT_DEALLOC_CNTL",
5425   "type_ref": "VGT_OUT_DEALLOC_CNTL"
5426  },
5427  {
5428   "chips": ["gfx103"],
5429   "map": {"at": 167008, "to": "mm"},
5430   "name": "CB_COLOR0_BASE"
5431  },
5432  {
5433   "chips": ["gfx103"],
5434   "map": {"at": 167012, "to": "mm"},
5435   "name": "CB_COLOR0_PITCH",
5436   "type_ref": "CB_COLOR0_PITCH"
5437  },
5438  {
5439   "chips": ["gfx103"],
5440   "map": {"at": 167016, "to": "mm"},
5441   "name": "CB_COLOR0_SLICE",
5442   "type_ref": "CB_COLOR0_SLICE"
5443  },
5444  {
5445   "chips": ["gfx103"],
5446   "map": {"at": 167020, "to": "mm"},
5447   "name": "CB_COLOR0_VIEW",
5448   "type_ref": "CB_COLOR0_VIEW"
5449  },
5450  {
5451   "chips": ["gfx103"],
5452   "map": {"at": 167024, "to": "mm"},
5453   "name": "CB_COLOR0_INFO",
5454   "type_ref": "CB_COLOR0_INFO"
5455  },
5456  {
5457   "chips": ["gfx103"],
5458   "map": {"at": 167028, "to": "mm"},
5459   "name": "CB_COLOR0_ATTRIB",
5460   "type_ref": "CB_COLOR0_ATTRIB"
5461  },
5462  {
5463   "chips": ["gfx103"],
5464   "map": {"at": 167032, "to": "mm"},
5465   "name": "CB_COLOR0_DCC_CONTROL",
5466   "type_ref": "CB_COLOR0_DCC_CONTROL"
5467  },
5468  {
5469   "chips": ["gfx103"],
5470   "map": {"at": 167036, "to": "mm"},
5471   "name": "CB_COLOR0_CMASK"
5472  },
5473  {
5474   "chips": ["gfx103"],
5475   "map": {"at": 167040, "to": "mm"},
5476   "name": "CB_COLOR0_CMASK_SLICE",
5477   "type_ref": "CB_COLOR0_CMASK_SLICE"
5478  },
5479  {
5480   "chips": ["gfx103"],
5481   "map": {"at": 167044, "to": "mm"},
5482   "name": "CB_COLOR0_FMASK"
5483  },
5484  {
5485   "chips": ["gfx103"],
5486   "map": {"at": 167048, "to": "mm"},
5487   "name": "CB_COLOR0_FMASK_SLICE",
5488   "type_ref": "CB_COLOR0_SLICE"
5489  },
5490  {
5491   "chips": ["gfx103"],
5492   "map": {"at": 167052, "to": "mm"},
5493   "name": "CB_COLOR0_CLEAR_WORD0"
5494  },
5495  {
5496   "chips": ["gfx103"],
5497   "map": {"at": 167056, "to": "mm"},
5498   "name": "CB_COLOR0_CLEAR_WORD1"
5499  },
5500  {
5501   "chips": ["gfx103"],
5502   "map": {"at": 167060, "to": "mm"},
5503   "name": "CB_COLOR0_DCC_BASE"
5504  },
5505  {
5506   "chips": ["gfx103"],
5507   "map": {"at": 167068, "to": "mm"},
5508   "name": "CB_COLOR1_BASE"
5509  },
5510  {
5511   "chips": ["gfx103"],
5512   "map": {"at": 167072, "to": "mm"},
5513   "name": "CB_COLOR1_PITCH",
5514   "type_ref": "CB_COLOR0_PITCH"
5515  },
5516  {
5517   "chips": ["gfx103"],
5518   "map": {"at": 167076, "to": "mm"},
5519   "name": "CB_COLOR1_SLICE",
5520   "type_ref": "CB_COLOR0_SLICE"
5521  },
5522  {
5523   "chips": ["gfx103"],
5524   "map": {"at": 167080, "to": "mm"},
5525   "name": "CB_COLOR1_VIEW",
5526   "type_ref": "CB_COLOR0_VIEW"
5527  },
5528  {
5529   "chips": ["gfx103"],
5530   "map": {"at": 167084, "to": "mm"},
5531   "name": "CB_COLOR1_INFO",
5532   "type_ref": "CB_COLOR0_INFO"
5533  },
5534  {
5535   "chips": ["gfx103"],
5536   "map": {"at": 167088, "to": "mm"},
5537   "name": "CB_COLOR1_ATTRIB",
5538   "type_ref": "CB_COLOR0_ATTRIB"
5539  },
5540  {
5541   "chips": ["gfx103"],
5542   "map": {"at": 167092, "to": "mm"},
5543   "name": "CB_COLOR1_DCC_CONTROL",
5544   "type_ref": "CB_COLOR0_DCC_CONTROL"
5545  },
5546  {
5547   "chips": ["gfx103"],
5548   "map": {"at": 167096, "to": "mm"},
5549   "name": "CB_COLOR1_CMASK"
5550  },
5551  {
5552   "chips": ["gfx103"],
5553   "map": {"at": 167100, "to": "mm"},
5554   "name": "CB_COLOR1_CMASK_SLICE",
5555   "type_ref": "CB_COLOR0_CMASK_SLICE"
5556  },
5557  {
5558   "chips": ["gfx103"],
5559   "map": {"at": 167104, "to": "mm"},
5560   "name": "CB_COLOR1_FMASK"
5561  },
5562  {
5563   "chips": ["gfx103"],
5564   "map": {"at": 167108, "to": "mm"},
5565   "name": "CB_COLOR1_FMASK_SLICE",
5566   "type_ref": "CB_COLOR0_SLICE"
5567  },
5568  {
5569   "chips": ["gfx103"],
5570   "map": {"at": 167112, "to": "mm"},
5571   "name": "CB_COLOR1_CLEAR_WORD0"
5572  },
5573  {
5574   "chips": ["gfx103"],
5575   "map": {"at": 167116, "to": "mm"},
5576   "name": "CB_COLOR1_CLEAR_WORD1"
5577  },
5578  {
5579   "chips": ["gfx103"],
5580   "map": {"at": 167120, "to": "mm"},
5581   "name": "CB_COLOR1_DCC_BASE"
5582  },
5583  {
5584   "chips": ["gfx103"],
5585   "map": {"at": 167128, "to": "mm"},
5586   "name": "CB_COLOR2_BASE"
5587  },
5588  {
5589   "chips": ["gfx103"],
5590   "map": {"at": 167132, "to": "mm"},
5591   "name": "CB_COLOR2_PITCH",
5592   "type_ref": "CB_COLOR0_PITCH"
5593  },
5594  {
5595   "chips": ["gfx103"],
5596   "map": {"at": 167136, "to": "mm"},
5597   "name": "CB_COLOR2_SLICE",
5598   "type_ref": "CB_COLOR0_SLICE"
5599  },
5600  {
5601   "chips": ["gfx103"],
5602   "map": {"at": 167140, "to": "mm"},
5603   "name": "CB_COLOR2_VIEW",
5604   "type_ref": "CB_COLOR0_VIEW"
5605  },
5606  {
5607   "chips": ["gfx103"],
5608   "map": {"at": 167144, "to": "mm"},
5609   "name": "CB_COLOR2_INFO",
5610   "type_ref": "CB_COLOR0_INFO"
5611  },
5612  {
5613   "chips": ["gfx103"],
5614   "map": {"at": 167148, "to": "mm"},
5615   "name": "CB_COLOR2_ATTRIB",
5616   "type_ref": "CB_COLOR0_ATTRIB"
5617  },
5618  {
5619   "chips": ["gfx103"],
5620   "map": {"at": 167152, "to": "mm"},
5621   "name": "CB_COLOR2_DCC_CONTROL",
5622   "type_ref": "CB_COLOR0_DCC_CONTROL"
5623  },
5624  {
5625   "chips": ["gfx103"],
5626   "map": {"at": 167156, "to": "mm"},
5627   "name": "CB_COLOR2_CMASK"
5628  },
5629  {
5630   "chips": ["gfx103"],
5631   "map": {"at": 167160, "to": "mm"},
5632   "name": "CB_COLOR2_CMASK_SLICE",
5633   "type_ref": "CB_COLOR0_CMASK_SLICE"
5634  },
5635  {
5636   "chips": ["gfx103"],
5637   "map": {"at": 167164, "to": "mm"},
5638   "name": "CB_COLOR2_FMASK"
5639  },
5640  {
5641   "chips": ["gfx103"],
5642   "map": {"at": 167168, "to": "mm"},
5643   "name": "CB_COLOR2_FMASK_SLICE",
5644   "type_ref": "CB_COLOR0_SLICE"
5645  },
5646  {
5647   "chips": ["gfx103"],
5648   "map": {"at": 167172, "to": "mm"},
5649   "name": "CB_COLOR2_CLEAR_WORD0"
5650  },
5651  {
5652   "chips": ["gfx103"],
5653   "map": {"at": 167176, "to": "mm"},
5654   "name": "CB_COLOR2_CLEAR_WORD1"
5655  },
5656  {
5657   "chips": ["gfx103"],
5658   "map": {"at": 167180, "to": "mm"},
5659   "name": "CB_COLOR2_DCC_BASE"
5660  },
5661  {
5662   "chips": ["gfx103"],
5663   "map": {"at": 167188, "to": "mm"},
5664   "name": "CB_COLOR3_BASE"
5665  },
5666  {
5667   "chips": ["gfx103"],
5668   "map": {"at": 167192, "to": "mm"},
5669   "name": "CB_COLOR3_PITCH",
5670   "type_ref": "CB_COLOR0_PITCH"
5671  },
5672  {
5673   "chips": ["gfx103"],
5674   "map": {"at": 167196, "to": "mm"},
5675   "name": "CB_COLOR3_SLICE",
5676   "type_ref": "CB_COLOR0_SLICE"
5677  },
5678  {
5679   "chips": ["gfx103"],
5680   "map": {"at": 167200, "to": "mm"},
5681   "name": "CB_COLOR3_VIEW",
5682   "type_ref": "CB_COLOR0_VIEW"
5683  },
5684  {
5685   "chips": ["gfx103"],
5686   "map": {"at": 167204, "to": "mm"},
5687   "name": "CB_COLOR3_INFO",
5688   "type_ref": "CB_COLOR0_INFO"
5689  },
5690  {
5691   "chips": ["gfx103"],
5692   "map": {"at": 167208, "to": "mm"},
5693   "name": "CB_COLOR3_ATTRIB",
5694   "type_ref": "CB_COLOR0_ATTRIB"
5695  },
5696  {
5697   "chips": ["gfx103"],
5698   "map": {"at": 167212, "to": "mm"},
5699   "name": "CB_COLOR3_DCC_CONTROL",
5700   "type_ref": "CB_COLOR0_DCC_CONTROL"
5701  },
5702  {
5703   "chips": ["gfx103"],
5704   "map": {"at": 167216, "to": "mm"},
5705   "name": "CB_COLOR3_CMASK"
5706  },
5707  {
5708   "chips": ["gfx103"],
5709   "map": {"at": 167220, "to": "mm"},
5710   "name": "CB_COLOR3_CMASK_SLICE",
5711   "type_ref": "CB_COLOR0_CMASK_SLICE"
5712  },
5713  {
5714   "chips": ["gfx103"],
5715   "map": {"at": 167224, "to": "mm"},
5716   "name": "CB_COLOR3_FMASK"
5717  },
5718  {
5719   "chips": ["gfx103"],
5720   "map": {"at": 167228, "to": "mm"},
5721   "name": "CB_COLOR3_FMASK_SLICE",
5722   "type_ref": "CB_COLOR0_SLICE"
5723  },
5724  {
5725   "chips": ["gfx103"],
5726   "map": {"at": 167232, "to": "mm"},
5727   "name": "CB_COLOR3_CLEAR_WORD0"
5728  },
5729  {
5730   "chips": ["gfx103"],
5731   "map": {"at": 167236, "to": "mm"},
5732   "name": "CB_COLOR3_CLEAR_WORD1"
5733  },
5734  {
5735   "chips": ["gfx103"],
5736   "map": {"at": 167240, "to": "mm"},
5737   "name": "CB_COLOR3_DCC_BASE"
5738  },
5739  {
5740   "chips": ["gfx103"],
5741   "map": {"at": 167248, "to": "mm"},
5742   "name": "CB_COLOR4_BASE"
5743  },
5744  {
5745   "chips": ["gfx103"],
5746   "map": {"at": 167252, "to": "mm"},
5747   "name": "CB_COLOR4_PITCH",
5748   "type_ref": "CB_COLOR0_PITCH"
5749  },
5750  {
5751   "chips": ["gfx103"],
5752   "map": {"at": 167256, "to": "mm"},
5753   "name": "CB_COLOR4_SLICE",
5754   "type_ref": "CB_COLOR0_SLICE"
5755  },
5756  {
5757   "chips": ["gfx103"],
5758   "map": {"at": 167260, "to": "mm"},
5759   "name": "CB_COLOR4_VIEW",
5760   "type_ref": "CB_COLOR0_VIEW"
5761  },
5762  {
5763   "chips": ["gfx103"],
5764   "map": {"at": 167264, "to": "mm"},
5765   "name": "CB_COLOR4_INFO",
5766   "type_ref": "CB_COLOR0_INFO"
5767  },
5768  {
5769   "chips": ["gfx103"],
5770   "map": {"at": 167268, "to": "mm"},
5771   "name": "CB_COLOR4_ATTRIB",
5772   "type_ref": "CB_COLOR0_ATTRIB"
5773  },
5774  {
5775   "chips": ["gfx103"],
5776   "map": {"at": 167272, "to": "mm"},
5777   "name": "CB_COLOR4_DCC_CONTROL",
5778   "type_ref": "CB_COLOR0_DCC_CONTROL"
5779  },
5780  {
5781   "chips": ["gfx103"],
5782   "map": {"at": 167276, "to": "mm"},
5783   "name": "CB_COLOR4_CMASK"
5784  },
5785  {
5786   "chips": ["gfx103"],
5787   "map": {"at": 167280, "to": "mm"},
5788   "name": "CB_COLOR4_CMASK_SLICE",
5789   "type_ref": "CB_COLOR0_CMASK_SLICE"
5790  },
5791  {
5792   "chips": ["gfx103"],
5793   "map": {"at": 167284, "to": "mm"},
5794   "name": "CB_COLOR4_FMASK"
5795  },
5796  {
5797   "chips": ["gfx103"],
5798   "map": {"at": 167288, "to": "mm"},
5799   "name": "CB_COLOR4_FMASK_SLICE",
5800   "type_ref": "CB_COLOR0_SLICE"
5801  },
5802  {
5803   "chips": ["gfx103"],
5804   "map": {"at": 167292, "to": "mm"},
5805   "name": "CB_COLOR4_CLEAR_WORD0"
5806  },
5807  {
5808   "chips": ["gfx103"],
5809   "map": {"at": 167296, "to": "mm"},
5810   "name": "CB_COLOR4_CLEAR_WORD1"
5811  },
5812  {
5813   "chips": ["gfx103"],
5814   "map": {"at": 167300, "to": "mm"},
5815   "name": "CB_COLOR4_DCC_BASE"
5816  },
5817  {
5818   "chips": ["gfx103"],
5819   "map": {"at": 167308, "to": "mm"},
5820   "name": "CB_COLOR5_BASE"
5821  },
5822  {
5823   "chips": ["gfx103"],
5824   "map": {"at": 167312, "to": "mm"},
5825   "name": "CB_COLOR5_PITCH",
5826   "type_ref": "CB_COLOR0_PITCH"
5827  },
5828  {
5829   "chips": ["gfx103"],
5830   "map": {"at": 167316, "to": "mm"},
5831   "name": "CB_COLOR5_SLICE",
5832   "type_ref": "CB_COLOR0_SLICE"
5833  },
5834  {
5835   "chips": ["gfx103"],
5836   "map": {"at": 167320, "to": "mm"},
5837   "name": "CB_COLOR5_VIEW",
5838   "type_ref": "CB_COLOR0_VIEW"
5839  },
5840  {
5841   "chips": ["gfx103"],
5842   "map": {"at": 167324, "to": "mm"},
5843   "name": "CB_COLOR5_INFO",
5844   "type_ref": "CB_COLOR0_INFO"
5845  },
5846  {
5847   "chips": ["gfx103"],
5848   "map": {"at": 167328, "to": "mm"},
5849   "name": "CB_COLOR5_ATTRIB",
5850   "type_ref": "CB_COLOR0_ATTRIB"
5851  },
5852  {
5853   "chips": ["gfx103"],
5854   "map": {"at": 167332, "to": "mm"},
5855   "name": "CB_COLOR5_DCC_CONTROL",
5856   "type_ref": "CB_COLOR0_DCC_CONTROL"
5857  },
5858  {
5859   "chips": ["gfx103"],
5860   "map": {"at": 167336, "to": "mm"},
5861   "name": "CB_COLOR5_CMASK"
5862  },
5863  {
5864   "chips": ["gfx103"],
5865   "map": {"at": 167340, "to": "mm"},
5866   "name": "CB_COLOR5_CMASK_SLICE",
5867   "type_ref": "CB_COLOR0_CMASK_SLICE"
5868  },
5869  {
5870   "chips": ["gfx103"],
5871   "map": {"at": 167344, "to": "mm"},
5872   "name": "CB_COLOR5_FMASK"
5873  },
5874  {
5875   "chips": ["gfx103"],
5876   "map": {"at": 167348, "to": "mm"},
5877   "name": "CB_COLOR5_FMASK_SLICE",
5878   "type_ref": "CB_COLOR0_SLICE"
5879  },
5880  {
5881   "chips": ["gfx103"],
5882   "map": {"at": 167352, "to": "mm"},
5883   "name": "CB_COLOR5_CLEAR_WORD0"
5884  },
5885  {
5886   "chips": ["gfx103"],
5887   "map": {"at": 167356, "to": "mm"},
5888   "name": "CB_COLOR5_CLEAR_WORD1"
5889  },
5890  {
5891   "chips": ["gfx103"],
5892   "map": {"at": 167360, "to": "mm"},
5893   "name": "CB_COLOR5_DCC_BASE"
5894  },
5895  {
5896   "chips": ["gfx103"],
5897   "map": {"at": 167368, "to": "mm"},
5898   "name": "CB_COLOR6_BASE"
5899  },
5900  {
5901   "chips": ["gfx103"],
5902   "map": {"at": 167372, "to": "mm"},
5903   "name": "CB_COLOR6_PITCH",
5904   "type_ref": "CB_COLOR0_PITCH"
5905  },
5906  {
5907   "chips": ["gfx103"],
5908   "map": {"at": 167376, "to": "mm"},
5909   "name": "CB_COLOR6_SLICE",
5910   "type_ref": "CB_COLOR0_SLICE"
5911  },
5912  {
5913   "chips": ["gfx103"],
5914   "map": {"at": 167380, "to": "mm"},
5915   "name": "CB_COLOR6_VIEW",
5916   "type_ref": "CB_COLOR0_VIEW"
5917  },
5918  {
5919   "chips": ["gfx103"],
5920   "map": {"at": 167384, "to": "mm"},
5921   "name": "CB_COLOR6_INFO",
5922   "type_ref": "CB_COLOR0_INFO"
5923  },
5924  {
5925   "chips": ["gfx103"],
5926   "map": {"at": 167388, "to": "mm"},
5927   "name": "CB_COLOR6_ATTRIB",
5928   "type_ref": "CB_COLOR0_ATTRIB"
5929  },
5930  {
5931   "chips": ["gfx103"],
5932   "map": {"at": 167392, "to": "mm"},
5933   "name": "CB_COLOR6_DCC_CONTROL",
5934   "type_ref": "CB_COLOR0_DCC_CONTROL"
5935  },
5936  {
5937   "chips": ["gfx103"],
5938   "map": {"at": 167396, "to": "mm"},
5939   "name": "CB_COLOR6_CMASK"
5940  },
5941  {
5942   "chips": ["gfx103"],
5943   "map": {"at": 167400, "to": "mm"},
5944   "name": "CB_COLOR6_CMASK_SLICE",
5945   "type_ref": "CB_COLOR0_CMASK_SLICE"
5946  },
5947  {
5948   "chips": ["gfx103"],
5949   "map": {"at": 167404, "to": "mm"},
5950   "name": "CB_COLOR6_FMASK"
5951  },
5952  {
5953   "chips": ["gfx103"],
5954   "map": {"at": 167408, "to": "mm"},
5955   "name": "CB_COLOR6_FMASK_SLICE",
5956   "type_ref": "CB_COLOR0_SLICE"
5957  },
5958  {
5959   "chips": ["gfx103"],
5960   "map": {"at": 167412, "to": "mm"},
5961   "name": "CB_COLOR6_CLEAR_WORD0"
5962  },
5963  {
5964   "chips": ["gfx103"],
5965   "map": {"at": 167416, "to": "mm"},
5966   "name": "CB_COLOR6_CLEAR_WORD1"
5967  },
5968  {
5969   "chips": ["gfx103"],
5970   "map": {"at": 167420, "to": "mm"},
5971   "name": "CB_COLOR6_DCC_BASE"
5972  },
5973  {
5974   "chips": ["gfx103"],
5975   "map": {"at": 167428, "to": "mm"},
5976   "name": "CB_COLOR7_BASE"
5977  },
5978  {
5979   "chips": ["gfx103"],
5980   "map": {"at": 167432, "to": "mm"},
5981   "name": "CB_COLOR7_PITCH",
5982   "type_ref": "CB_COLOR0_PITCH"
5983  },
5984  {
5985   "chips": ["gfx103"],
5986   "map": {"at": 167436, "to": "mm"},
5987   "name": "CB_COLOR7_SLICE",
5988   "type_ref": "CB_COLOR0_SLICE"
5989  },
5990  {
5991   "chips": ["gfx103"],
5992   "map": {"at": 167440, "to": "mm"},
5993   "name": "CB_COLOR7_VIEW",
5994   "type_ref": "CB_COLOR0_VIEW"
5995  },
5996  {
5997   "chips": ["gfx103"],
5998   "map": {"at": 167444, "to": "mm"},
5999   "name": "CB_COLOR7_INFO",
6000   "type_ref": "CB_COLOR0_INFO"
6001  },
6002  {
6003   "chips": ["gfx103"],
6004   "map": {"at": 167448, "to": "mm"},
6005   "name": "CB_COLOR7_ATTRIB",
6006   "type_ref": "CB_COLOR0_ATTRIB"
6007  },
6008  {
6009   "chips": ["gfx103"],
6010   "map": {"at": 167452, "to": "mm"},
6011   "name": "CB_COLOR7_DCC_CONTROL",
6012   "type_ref": "CB_COLOR0_DCC_CONTROL"
6013  },
6014  {
6015   "chips": ["gfx103"],
6016   "map": {"at": 167456, "to": "mm"},
6017   "name": "CB_COLOR7_CMASK"
6018  },
6019  {
6020   "chips": ["gfx103"],
6021   "map": {"at": 167460, "to": "mm"},
6022   "name": "CB_COLOR7_CMASK_SLICE",
6023   "type_ref": "CB_COLOR0_CMASK_SLICE"
6024  },
6025  {
6026   "chips": ["gfx103"],
6027   "map": {"at": 167464, "to": "mm"},
6028   "name": "CB_COLOR7_FMASK"
6029  },
6030  {
6031   "chips": ["gfx103"],
6032   "map": {"at": 167468, "to": "mm"},
6033   "name": "CB_COLOR7_FMASK_SLICE",
6034   "type_ref": "CB_COLOR0_SLICE"
6035  },
6036  {
6037   "chips": ["gfx103"],
6038   "map": {"at": 167472, "to": "mm"},
6039   "name": "CB_COLOR7_CLEAR_WORD0"
6040  },
6041  {
6042   "chips": ["gfx103"],
6043   "map": {"at": 167476, "to": "mm"},
6044   "name": "CB_COLOR7_CLEAR_WORD1"
6045  },
6046  {
6047   "chips": ["gfx103"],
6048   "map": {"at": 167480, "to": "mm"},
6049   "name": "CB_COLOR7_DCC_BASE"
6050  },
6051  {
6052   "chips": ["gfx103"],
6053   "map": {"at": 167488, "to": "mm"},
6054   "name": "CB_COLOR0_BASE_EXT",
6055   "type_ref": "CB_COLOR0_BASE_EXT"
6056  },
6057  {
6058   "chips": ["gfx103"],
6059   "map": {"at": 167492, "to": "mm"},
6060   "name": "CB_COLOR1_BASE_EXT",
6061   "type_ref": "CB_COLOR0_BASE_EXT"
6062  },
6063  {
6064   "chips": ["gfx103"],
6065   "map": {"at": 167496, "to": "mm"},
6066   "name": "CB_COLOR2_BASE_EXT",
6067   "type_ref": "CB_COLOR0_BASE_EXT"
6068  },
6069  {
6070   "chips": ["gfx103"],
6071   "map": {"at": 167500, "to": "mm"},
6072   "name": "CB_COLOR3_BASE_EXT",
6073   "type_ref": "CB_COLOR0_BASE_EXT"
6074  },
6075  {
6076   "chips": ["gfx103"],
6077   "map": {"at": 167504, "to": "mm"},
6078   "name": "CB_COLOR4_BASE_EXT",
6079   "type_ref": "CB_COLOR0_BASE_EXT"
6080  },
6081  {
6082   "chips": ["gfx103"],
6083   "map": {"at": 167508, "to": "mm"},
6084   "name": "CB_COLOR5_BASE_EXT",
6085   "type_ref": "CB_COLOR0_BASE_EXT"
6086  },
6087  {
6088   "chips": ["gfx103"],
6089   "map": {"at": 167512, "to": "mm"},
6090   "name": "CB_COLOR6_BASE_EXT",
6091   "type_ref": "CB_COLOR0_BASE_EXT"
6092  },
6093  {
6094   "chips": ["gfx103"],
6095   "map": {"at": 167516, "to": "mm"},
6096   "name": "CB_COLOR7_BASE_EXT",
6097   "type_ref": "CB_COLOR0_BASE_EXT"
6098  },
6099  {
6100   "chips": ["gfx103"],
6101   "map": {"at": 167520, "to": "mm"},
6102   "name": "CB_COLOR0_CMASK_BASE_EXT",
6103   "type_ref": "CB_COLOR0_BASE_EXT"
6104  },
6105  {
6106   "chips": ["gfx103"],
6107   "map": {"at": 167524, "to": "mm"},
6108   "name": "CB_COLOR1_CMASK_BASE_EXT",
6109   "type_ref": "CB_COLOR0_BASE_EXT"
6110  },
6111  {
6112   "chips": ["gfx103"],
6113   "map": {"at": 167528, "to": "mm"},
6114   "name": "CB_COLOR2_CMASK_BASE_EXT",
6115   "type_ref": "CB_COLOR0_BASE_EXT"
6116  },
6117  {
6118   "chips": ["gfx103"],
6119   "map": {"at": 167532, "to": "mm"},
6120   "name": "CB_COLOR3_CMASK_BASE_EXT",
6121   "type_ref": "CB_COLOR0_BASE_EXT"
6122  },
6123  {
6124   "chips": ["gfx103"],
6125   "map": {"at": 167536, "to": "mm"},
6126   "name": "CB_COLOR4_CMASK_BASE_EXT",
6127   "type_ref": "CB_COLOR0_BASE_EXT"
6128  },
6129  {
6130   "chips": ["gfx103"],
6131   "map": {"at": 167540, "to": "mm"},
6132   "name": "CB_COLOR5_CMASK_BASE_EXT",
6133   "type_ref": "CB_COLOR0_BASE_EXT"
6134  },
6135  {
6136   "chips": ["gfx103"],
6137   "map": {"at": 167544, "to": "mm"},
6138   "name": "CB_COLOR6_CMASK_BASE_EXT",
6139   "type_ref": "CB_COLOR0_BASE_EXT"
6140  },
6141  {
6142   "chips": ["gfx103"],
6143   "map": {"at": 167548, "to": "mm"},
6144   "name": "CB_COLOR7_CMASK_BASE_EXT",
6145   "type_ref": "CB_COLOR0_BASE_EXT"
6146  },
6147  {
6148   "chips": ["gfx103"],
6149   "map": {"at": 167552, "to": "mm"},
6150   "name": "CB_COLOR0_FMASK_BASE_EXT",
6151   "type_ref": "CB_COLOR0_BASE_EXT"
6152  },
6153  {
6154   "chips": ["gfx103"],
6155   "map": {"at": 167556, "to": "mm"},
6156   "name": "CB_COLOR1_FMASK_BASE_EXT",
6157   "type_ref": "CB_COLOR0_BASE_EXT"
6158  },
6159  {
6160   "chips": ["gfx103"],
6161   "map": {"at": 167560, "to": "mm"},
6162   "name": "CB_COLOR2_FMASK_BASE_EXT",
6163   "type_ref": "CB_COLOR0_BASE_EXT"
6164  },
6165  {
6166   "chips": ["gfx103"],
6167   "map": {"at": 167564, "to": "mm"},
6168   "name": "CB_COLOR3_FMASK_BASE_EXT",
6169   "type_ref": "CB_COLOR0_BASE_EXT"
6170  },
6171  {
6172   "chips": ["gfx103"],
6173   "map": {"at": 167568, "to": "mm"},
6174   "name": "CB_COLOR4_FMASK_BASE_EXT",
6175   "type_ref": "CB_COLOR0_BASE_EXT"
6176  },
6177  {
6178   "chips": ["gfx103"],
6179   "map": {"at": 167572, "to": "mm"},
6180   "name": "CB_COLOR5_FMASK_BASE_EXT",
6181   "type_ref": "CB_COLOR0_BASE_EXT"
6182  },
6183  {
6184   "chips": ["gfx103"],
6185   "map": {"at": 167576, "to": "mm"},
6186   "name": "CB_COLOR6_FMASK_BASE_EXT",
6187   "type_ref": "CB_COLOR0_BASE_EXT"
6188  },
6189  {
6190   "chips": ["gfx103"],
6191   "map": {"at": 167580, "to": "mm"},
6192   "name": "CB_COLOR7_FMASK_BASE_EXT",
6193   "type_ref": "CB_COLOR0_BASE_EXT"
6194  },
6195  {
6196   "chips": ["gfx103"],
6197   "map": {"at": 167584, "to": "mm"},
6198   "name": "CB_COLOR0_DCC_BASE_EXT",
6199   "type_ref": "CB_COLOR0_BASE_EXT"
6200  },
6201  {
6202   "chips": ["gfx103"],
6203   "map": {"at": 167588, "to": "mm"},
6204   "name": "CB_COLOR1_DCC_BASE_EXT",
6205   "type_ref": "CB_COLOR0_BASE_EXT"
6206  },
6207  {
6208   "chips": ["gfx103"],
6209   "map": {"at": 167592, "to": "mm"},
6210   "name": "CB_COLOR2_DCC_BASE_EXT",
6211   "type_ref": "CB_COLOR0_BASE_EXT"
6212  },
6213  {
6214   "chips": ["gfx103"],
6215   "map": {"at": 167596, "to": "mm"},
6216   "name": "CB_COLOR3_DCC_BASE_EXT",
6217   "type_ref": "CB_COLOR0_BASE_EXT"
6218  },
6219  {
6220   "chips": ["gfx103"],
6221   "map": {"at": 167600, "to": "mm"},
6222   "name": "CB_COLOR4_DCC_BASE_EXT",
6223   "type_ref": "CB_COLOR0_BASE_EXT"
6224  },
6225  {
6226   "chips": ["gfx103"],
6227   "map": {"at": 167604, "to": "mm"},
6228   "name": "CB_COLOR5_DCC_BASE_EXT",
6229   "type_ref": "CB_COLOR0_BASE_EXT"
6230  },
6231  {
6232   "chips": ["gfx103"],
6233   "map": {"at": 167608, "to": "mm"},
6234   "name": "CB_COLOR6_DCC_BASE_EXT",
6235   "type_ref": "CB_COLOR0_BASE_EXT"
6236  },
6237  {
6238   "chips": ["gfx103"],
6239   "map": {"at": 167612, "to": "mm"},
6240   "name": "CB_COLOR7_DCC_BASE_EXT",
6241   "type_ref": "CB_COLOR0_BASE_EXT"
6242  },
6243  {
6244   "chips": ["gfx103"],
6245   "map": {"at": 167616, "to": "mm"},
6246   "name": "CB_COLOR0_ATTRIB2",
6247   "type_ref": "CB_COLOR0_ATTRIB2"
6248  },
6249  {
6250   "chips": ["gfx103"],
6251   "map": {"at": 167620, "to": "mm"},
6252   "name": "CB_COLOR1_ATTRIB2",
6253   "type_ref": "CB_COLOR0_ATTRIB2"
6254  },
6255  {
6256   "chips": ["gfx103"],
6257   "map": {"at": 167624, "to": "mm"},
6258   "name": "CB_COLOR2_ATTRIB2",
6259   "type_ref": "CB_COLOR0_ATTRIB2"
6260  },
6261  {
6262   "chips": ["gfx103"],
6263   "map": {"at": 167628, "to": "mm"},
6264   "name": "CB_COLOR3_ATTRIB2",
6265   "type_ref": "CB_COLOR0_ATTRIB2"
6266  },
6267  {
6268   "chips": ["gfx103"],
6269   "map": {"at": 167632, "to": "mm"},
6270   "name": "CB_COLOR4_ATTRIB2",
6271   "type_ref": "CB_COLOR0_ATTRIB2"
6272  },
6273  {
6274   "chips": ["gfx103"],
6275   "map": {"at": 167636, "to": "mm"},
6276   "name": "CB_COLOR5_ATTRIB2",
6277   "type_ref": "CB_COLOR0_ATTRIB2"
6278  },
6279  {
6280   "chips": ["gfx103"],
6281   "map": {"at": 167640, "to": "mm"},
6282   "name": "CB_COLOR6_ATTRIB2",
6283   "type_ref": "CB_COLOR0_ATTRIB2"
6284  },
6285  {
6286   "chips": ["gfx103"],
6287   "map": {"at": 167644, "to": "mm"},
6288   "name": "CB_COLOR7_ATTRIB2",
6289   "type_ref": "CB_COLOR0_ATTRIB2"
6290  },
6291  {
6292   "chips": ["gfx103"],
6293   "map": {"at": 167648, "to": "mm"},
6294   "name": "CB_COLOR0_ATTRIB3",
6295   "type_ref": "CB_COLOR0_ATTRIB3"
6296  },
6297  {
6298   "chips": ["gfx103"],
6299   "map": {"at": 167652, "to": "mm"},
6300   "name": "CB_COLOR1_ATTRIB3",
6301   "type_ref": "CB_COLOR0_ATTRIB3"
6302  },
6303  {
6304   "chips": ["gfx103"],
6305   "map": {"at": 167656, "to": "mm"},
6306   "name": "CB_COLOR2_ATTRIB3",
6307   "type_ref": "CB_COLOR0_ATTRIB3"
6308  },
6309  {
6310   "chips": ["gfx103"],
6311   "map": {"at": 167660, "to": "mm"},
6312   "name": "CB_COLOR3_ATTRIB3",
6313   "type_ref": "CB_COLOR0_ATTRIB3"
6314  },
6315  {
6316   "chips": ["gfx103"],
6317   "map": {"at": 167664, "to": "mm"},
6318   "name": "CB_COLOR4_ATTRIB3",
6319   "type_ref": "CB_COLOR0_ATTRIB3"
6320  },
6321  {
6322   "chips": ["gfx103"],
6323   "map": {"at": 167668, "to": "mm"},
6324   "name": "CB_COLOR5_ATTRIB3",
6325   "type_ref": "CB_COLOR0_ATTRIB3"
6326  },
6327  {
6328   "chips": ["gfx103"],
6329   "map": {"at": 167672, "to": "mm"},
6330   "name": "CB_COLOR6_ATTRIB3",
6331   "type_ref": "CB_COLOR0_ATTRIB3"
6332  },
6333  {
6334   "chips": ["gfx103"],
6335   "map": {"at": 167676, "to": "mm"},
6336   "name": "CB_COLOR7_ATTRIB3",
6337   "type_ref": "CB_COLOR0_ATTRIB3"
6338  },
6339  {
6340   "chips": ["gfx103"],
6341   "map": {"at": 196608, "to": "mm"},
6342   "name": "CP_EOP_DONE_ADDR_LO",
6343   "type_ref": "CP_EOP_DONE_ADDR_LO"
6344  },
6345  {
6346   "chips": ["gfx103"],
6347   "map": {"at": 196612, "to": "mm"},
6348   "name": "CP_EOP_DONE_ADDR_HI",
6349   "type_ref": "CP_EOP_DONE_ADDR_HI"
6350  },
6351  {
6352   "chips": ["gfx103"],
6353   "map": {"at": 196616, "to": "mm"},
6354   "name": "CP_EOP_DONE_DATA_LO"
6355  },
6356  {
6357   "chips": ["gfx103"],
6358   "map": {"at": 196620, "to": "mm"},
6359   "name": "CP_EOP_DONE_DATA_HI"
6360  },
6361  {
6362   "chips": ["gfx103"],
6363   "map": {"at": 196624, "to": "mm"},
6364   "name": "CP_EOP_LAST_FENCE_LO"
6365  },
6366  {
6367   "chips": ["gfx103"],
6368   "map": {"at": 196628, "to": "mm"},
6369   "name": "CP_EOP_LAST_FENCE_HI"
6370  },
6371  {
6372   "chips": ["gfx103"],
6373   "map": {"at": 196632, "to": "mm"},
6374   "name": "CP_STREAM_OUT_ADDR_LO",
6375   "type_ref": "CP_STREAM_OUT_ADDR_LO"
6376  },
6377  {
6378   "chips": ["gfx103"],
6379   "map": {"at": 196636, "to": "mm"},
6380   "name": "CP_STREAM_OUT_ADDR_HI",
6381   "type_ref": "CP_STREAM_OUT_ADDR_HI"
6382  },
6383  {
6384   "chips": ["gfx103"],
6385   "map": {"at": 196640, "to": "mm"},
6386   "name": "CP_NUM_PRIM_WRITTEN_COUNT0_LO"
6387  },
6388  {
6389   "chips": ["gfx103"],
6390   "map": {"at": 196644, "to": "mm"},
6391   "name": "CP_NUM_PRIM_WRITTEN_COUNT0_HI"
6392  },
6393  {
6394   "chips": ["gfx103"],
6395   "map": {"at": 196648, "to": "mm"},
6396   "name": "CP_NUM_PRIM_NEEDED_COUNT0_LO"
6397  },
6398  {
6399   "chips": ["gfx103"],
6400   "map": {"at": 196652, "to": "mm"},
6401   "name": "CP_NUM_PRIM_NEEDED_COUNT0_HI"
6402  },
6403  {
6404   "chips": ["gfx103"],
6405   "map": {"at": 196656, "to": "mm"},
6406   "name": "CP_NUM_PRIM_WRITTEN_COUNT1_LO"
6407  },
6408  {
6409   "chips": ["gfx103"],
6410   "map": {"at": 196660, "to": "mm"},
6411   "name": "CP_NUM_PRIM_WRITTEN_COUNT1_HI"
6412  },
6413  {
6414   "chips": ["gfx103"],
6415   "map": {"at": 196664, "to": "mm"},
6416   "name": "CP_NUM_PRIM_NEEDED_COUNT1_LO"
6417  },
6418  {
6419   "chips": ["gfx103"],
6420   "map": {"at": 196668, "to": "mm"},
6421   "name": "CP_NUM_PRIM_NEEDED_COUNT1_HI"
6422  },
6423  {
6424   "chips": ["gfx103"],
6425   "map": {"at": 196672, "to": "mm"},
6426   "name": "CP_NUM_PRIM_WRITTEN_COUNT2_LO"
6427  },
6428  {
6429   "chips": ["gfx103"],
6430   "map": {"at": 196676, "to": "mm"},
6431   "name": "CP_NUM_PRIM_WRITTEN_COUNT2_HI"
6432  },
6433  {
6434   "chips": ["gfx103"],
6435   "map": {"at": 196680, "to": "mm"},
6436   "name": "CP_NUM_PRIM_NEEDED_COUNT2_LO"
6437  },
6438  {
6439   "chips": ["gfx103"],
6440   "map": {"at": 196684, "to": "mm"},
6441   "name": "CP_NUM_PRIM_NEEDED_COUNT2_HI"
6442  },
6443  {
6444   "chips": ["gfx103"],
6445   "map": {"at": 196688, "to": "mm"},
6446   "name": "CP_NUM_PRIM_WRITTEN_COUNT3_LO"
6447  },
6448  {
6449   "chips": ["gfx103"],
6450   "map": {"at": 196692, "to": "mm"},
6451   "name": "CP_NUM_PRIM_WRITTEN_COUNT3_HI"
6452  },
6453  {
6454   "chips": ["gfx103"],
6455   "map": {"at": 196696, "to": "mm"},
6456   "name": "CP_NUM_PRIM_NEEDED_COUNT3_LO"
6457  },
6458  {
6459   "chips": ["gfx103"],
6460   "map": {"at": 196700, "to": "mm"},
6461   "name": "CP_NUM_PRIM_NEEDED_COUNT3_HI"
6462  },
6463  {
6464   "chips": ["gfx103"],
6465   "map": {"at": 196704, "to": "mm"},
6466   "name": "CP_PIPE_STATS_ADDR_LO",
6467   "type_ref": "CP_PIPE_STATS_ADDR_LO"
6468  },
6469  {
6470   "chips": ["gfx103"],
6471   "map": {"at": 196708, "to": "mm"},
6472   "name": "CP_PIPE_STATS_ADDR_HI",
6473   "type_ref": "CP_PIPE_STATS_ADDR_HI"
6474  },
6475  {
6476   "chips": ["gfx103"],
6477   "map": {"at": 196712, "to": "mm"},
6478   "name": "CP_VGT_IAVERT_COUNT_LO"
6479  },
6480  {
6481   "chips": ["gfx103"],
6482   "map": {"at": 196716, "to": "mm"},
6483   "name": "CP_VGT_IAVERT_COUNT_HI"
6484  },
6485  {
6486   "chips": ["gfx103"],
6487   "map": {"at": 196720, "to": "mm"},
6488   "name": "CP_VGT_IAPRIM_COUNT_LO"
6489  },
6490  {
6491   "chips": ["gfx103"],
6492   "map": {"at": 196724, "to": "mm"},
6493   "name": "CP_VGT_IAPRIM_COUNT_HI"
6494  },
6495  {
6496   "chips": ["gfx103"],
6497   "map": {"at": 196728, "to": "mm"},
6498   "name": "CP_VGT_GSPRIM_COUNT_LO"
6499  },
6500  {
6501   "chips": ["gfx103"],
6502   "map": {"at": 196732, "to": "mm"},
6503   "name": "CP_VGT_GSPRIM_COUNT_HI"
6504  },
6505  {
6506   "chips": ["gfx103"],
6507   "map": {"at": 196736, "to": "mm"},
6508   "name": "CP_VGT_VSINVOC_COUNT_LO"
6509  },
6510  {
6511   "chips": ["gfx103"],
6512   "map": {"at": 196740, "to": "mm"},
6513   "name": "CP_VGT_VSINVOC_COUNT_HI"
6514  },
6515  {
6516   "chips": ["gfx103"],
6517   "map": {"at": 196744, "to": "mm"},
6518   "name": "CP_VGT_GSINVOC_COUNT_LO"
6519  },
6520  {
6521   "chips": ["gfx103"],
6522   "map": {"at": 196748, "to": "mm"},
6523   "name": "CP_VGT_GSINVOC_COUNT_HI"
6524  },
6525  {
6526   "chips": ["gfx103"],
6527   "map": {"at": 196752, "to": "mm"},
6528   "name": "CP_VGT_HSINVOC_COUNT_LO"
6529  },
6530  {
6531   "chips": ["gfx103"],
6532   "map": {"at": 196756, "to": "mm"},
6533   "name": "CP_VGT_HSINVOC_COUNT_HI"
6534  },
6535  {
6536   "chips": ["gfx103"],
6537   "map": {"at": 196760, "to": "mm"},
6538   "name": "CP_VGT_DSINVOC_COUNT_LO"
6539  },
6540  {
6541   "chips": ["gfx103"],
6542   "map": {"at": 196764, "to": "mm"},
6543   "name": "CP_VGT_DSINVOC_COUNT_HI"
6544  },
6545  {
6546   "chips": ["gfx103"],
6547   "map": {"at": 196768, "to": "mm"},
6548   "name": "CP_PA_CINVOC_COUNT_LO"
6549  },
6550  {
6551   "chips": ["gfx103"],
6552   "map": {"at": 196772, "to": "mm"},
6553   "name": "CP_PA_CINVOC_COUNT_HI"
6554  },
6555  {
6556   "chips": ["gfx103"],
6557   "map": {"at": 196776, "to": "mm"},
6558   "name": "CP_PA_CPRIM_COUNT_LO"
6559  },
6560  {
6561   "chips": ["gfx103"],
6562   "map": {"at": 196780, "to": "mm"},
6563   "name": "CP_PA_CPRIM_COUNT_HI"
6564  },
6565  {
6566   "chips": ["gfx103"],
6567   "map": {"at": 196784, "to": "mm"},
6568   "name": "CP_SC_PSINVOC_COUNT0_LO"
6569  },
6570  {
6571   "chips": ["gfx103"],
6572   "map": {"at": 196788, "to": "mm"},
6573   "name": "CP_SC_PSINVOC_COUNT0_HI"
6574  },
6575  {
6576   "chips": ["gfx103"],
6577   "map": {"at": 196792, "to": "mm"},
6578   "name": "CP_SC_PSINVOC_COUNT1_LO"
6579  },
6580  {
6581   "chips": ["gfx103"],
6582   "map": {"at": 196796, "to": "mm"},
6583   "name": "CP_SC_PSINVOC_COUNT1_HI"
6584  },
6585  {
6586   "chips": ["gfx103"],
6587   "map": {"at": 196800, "to": "mm"},
6588   "name": "CP_VGT_CSINVOC_COUNT_LO"
6589  },
6590  {
6591   "chips": ["gfx103"],
6592   "map": {"at": 196804, "to": "mm"},
6593   "name": "CP_VGT_CSINVOC_COUNT_HI"
6594  },
6595  {
6596   "chips": ["gfx103"],
6597   "map": {"at": 196852, "to": "mm"},
6598   "name": "CP_PIPE_STATS_CONTROL",
6599   "type_ref": "CP_PIPE_STATS_CONTROL"
6600  },
6601  {
6602   "chips": ["gfx103"],
6603   "map": {"at": 196856, "to": "mm"},
6604   "name": "CP_STREAM_OUT_CONTROL",
6605   "type_ref": "CP_PIPE_STATS_CONTROL"
6606  },
6607  {
6608   "chips": ["gfx103"],
6609   "map": {"at": 196860, "to": "mm"},
6610   "name": "CP_STRMOUT_CNTL",
6611   "type_ref": "CP_STRMOUT_CNTL"
6612  },
6613  {
6614   "chips": ["gfx103"],
6615   "map": {"at": 196864, "to": "mm"},
6616   "name": "SCRATCH_REG0"
6617  },
6618  {
6619   "chips": ["gfx103"],
6620   "map": {"at": 196868, "to": "mm"},
6621   "name": "SCRATCH_REG1"
6622  },
6623  {
6624   "chips": ["gfx103"],
6625   "map": {"at": 196872, "to": "mm"},
6626   "name": "SCRATCH_REG2"
6627  },
6628  {
6629   "chips": ["gfx103"],
6630   "map": {"at": 196876, "to": "mm"},
6631   "name": "SCRATCH_REG3"
6632  },
6633  {
6634   "chips": ["gfx103"],
6635   "map": {"at": 196880, "to": "mm"},
6636   "name": "SCRATCH_REG4"
6637  },
6638  {
6639   "chips": ["gfx103"],
6640   "map": {"at": 196884, "to": "mm"},
6641   "name": "SCRATCH_REG5"
6642  },
6643  {
6644   "chips": ["gfx103"],
6645   "map": {"at": 196888, "to": "mm"},
6646   "name": "SCRATCH_REG6"
6647  },
6648  {
6649   "chips": ["gfx103"],
6650   "map": {"at": 196892, "to": "mm"},
6651   "name": "SCRATCH_REG7"
6652  },
6653  {
6654   "chips": ["gfx103"],
6655   "map": {"at": 196896, "to": "mm"},
6656   "name": "SCRATCH_REG_ATOMIC",
6657   "type_ref": "SCRATCH_REG_ATOMIC"
6658  },
6659  {
6660   "chips": ["gfx103"],
6661   "map": {"at": 196908, "to": "mm"},
6662   "name": "CP_APPEND_DDID_CNT",
6663   "type_ref": "COMPUTE_PGM_HI"
6664  },
6665  {
6666   "chips": ["gfx103"],
6667   "map": {"at": 196912, "to": "mm"},
6668   "name": "CP_APPEND_DATA_HI"
6669  },
6670  {
6671   "chips": ["gfx103"],
6672   "map": {"at": 196916, "to": "mm"},
6673   "name": "CP_APPEND_LAST_CS_FENCE_HI"
6674  },
6675  {
6676   "chips": ["gfx103"],
6677   "map": {"at": 196920, "to": "mm"},
6678   "name": "CP_APPEND_LAST_PS_FENCE_HI"
6679  },
6680  {
6681   "chips": ["gfx103"],
6682   "map": {"at": 196928, "to": "mm"},
6683   "name": "SCRATCH_UMSK",
6684   "type_ref": "SCRATCH_UMSK"
6685  },
6686  {
6687   "chips": ["gfx103"],
6688   "map": {"at": 196932, "to": "mm"},
6689   "name": "SCRATCH_ADDR"
6690  },
6691  {
6692   "chips": ["gfx103"],
6693   "map": {"at": 196936, "to": "mm"},
6694   "name": "CP_PFP_ATOMIC_PREOP_LO"
6695  },
6696  {
6697   "chips": ["gfx103"],
6698   "map": {"at": 196940, "to": "mm"},
6699   "name": "CP_PFP_ATOMIC_PREOP_HI"
6700  },
6701  {
6702   "chips": ["gfx103"],
6703   "map": {"at": 196944, "to": "mm"},
6704   "name": "CP_PFP_GDS_ATOMIC0_PREOP_LO"
6705  },
6706  {
6707   "chips": ["gfx103"],
6708   "map": {"at": 196948, "to": "mm"},
6709   "name": "CP_PFP_GDS_ATOMIC0_PREOP_HI"
6710  },
6711  {
6712   "chips": ["gfx103"],
6713   "map": {"at": 196952, "to": "mm"},
6714   "name": "CP_PFP_GDS_ATOMIC1_PREOP_LO"
6715  },
6716  {
6717   "chips": ["gfx103"],
6718   "map": {"at": 196956, "to": "mm"},
6719   "name": "CP_PFP_GDS_ATOMIC1_PREOP_HI"
6720  },
6721  {
6722   "chips": ["gfx103"],
6723   "map": {"at": 196960, "to": "mm"},
6724   "name": "CP_APPEND_ADDR_LO",
6725   "type_ref": "CP_APPEND_ADDR_LO"
6726  },
6727  {
6728   "chips": ["gfx103"],
6729   "map": {"at": 196964, "to": "mm"},
6730   "name": "CP_APPEND_ADDR_HI",
6731   "type_ref": "CP_APPEND_ADDR_HI"
6732  },
6733  {
6734   "chips": ["gfx103"],
6735   "map": {"at": 196968, "to": "mm"},
6736   "name": "CP_APPEND_DATA"
6737  },
6738  {
6739   "chips": ["gfx103"],
6740   "map": {"at": 196972, "to": "mm"},
6741   "name": "CP_APPEND_LAST_CS_FENCE"
6742  },
6743  {
6744   "chips": ["gfx103"],
6745   "map": {"at": 196976, "to": "mm"},
6746   "name": "CP_APPEND_LAST_PS_FENCE"
6747  },
6748  {
6749   "chips": ["gfx103"],
6750   "map": {"at": 196980, "to": "mm"},
6751   "name": "CP_ATOMIC_PREOP_LO"
6752  },
6753  {
6754   "chips": ["gfx103"],
6755   "map": {"at": 196984, "to": "mm"},
6756   "name": "CP_ATOMIC_PREOP_HI"
6757  },
6758  {
6759   "chips": ["gfx103"],
6760   "map": {"at": 196988, "to": "mm"},
6761   "name": "CP_GDS_ATOMIC0_PREOP_LO"
6762  },
6763  {
6764   "chips": ["gfx103"],
6765   "map": {"at": 196992, "to": "mm"},
6766   "name": "CP_GDS_ATOMIC0_PREOP_HI"
6767  },
6768  {
6769   "chips": ["gfx103"],
6770   "map": {"at": 196996, "to": "mm"},
6771   "name": "CP_GDS_ATOMIC1_PREOP_LO"
6772  },
6773  {
6774   "chips": ["gfx103"],
6775   "map": {"at": 197000, "to": "mm"},
6776   "name": "CP_GDS_ATOMIC1_PREOP_HI"
6777  },
6778  {
6779   "chips": ["gfx103"],
6780   "map": {"at": 197028, "to": "mm"},
6781   "name": "CP_ME_MC_WADDR_LO",
6782   "type_ref": "CP_ME_MC_WADDR_LO"
6783  },
6784  {
6785   "chips": ["gfx103"],
6786   "map": {"at": 197032, "to": "mm"},
6787   "name": "CP_ME_MC_WADDR_HI",
6788   "type_ref": "CP_ME_MC_WADDR_HI"
6789  },
6790  {
6791   "chips": ["gfx103"],
6792   "map": {"at": 197036, "to": "mm"},
6793   "name": "CP_ME_MC_WDATA_LO"
6794  },
6795  {
6796   "chips": ["gfx103"],
6797   "map": {"at": 197040, "to": "mm"},
6798   "name": "CP_ME_MC_WDATA_HI"
6799  },
6800  {
6801   "chips": ["gfx103"],
6802   "map": {"at": 197044, "to": "mm"},
6803   "name": "CP_ME_MC_RADDR_LO",
6804   "type_ref": "CP_ME_MC_RADDR_LO"
6805  },
6806  {
6807   "chips": ["gfx103"],
6808   "map": {"at": 197048, "to": "mm"},
6809   "name": "CP_ME_MC_RADDR_HI",
6810   "type_ref": "CP_ME_MC_RADDR_HI"
6811  },
6812  {
6813   "chips": ["gfx103"],
6814   "map": {"at": 197052, "to": "mm"},
6815   "name": "CP_SEM_WAIT_TIMER"
6816  },
6817  {
6818   "chips": ["gfx103"],
6819   "map": {"at": 197056, "to": "mm"},
6820   "name": "CP_SIG_SEM_ADDR_LO",
6821   "type_ref": "CP_SIG_SEM_ADDR_LO"
6822  },
6823  {
6824   "chips": ["gfx103"],
6825   "map": {"at": 197060, "to": "mm"},
6826   "name": "CP_SIG_SEM_ADDR_HI",
6827   "type_ref": "CP_SIG_SEM_ADDR_HI"
6828  },
6829  {
6830   "chips": ["gfx103"],
6831   "map": {"at": 197072, "to": "mm"},
6832   "name": "CP_WAIT_REG_MEM_TIMEOUT"
6833  },
6834  {
6835   "chips": ["gfx103"],
6836   "map": {"at": 197076, "to": "mm"},
6837   "name": "CP_WAIT_SEM_ADDR_LO",
6838   "type_ref": "CP_SIG_SEM_ADDR_LO"
6839  },
6840  {
6841   "chips": ["gfx103"],
6842   "map": {"at": 197080, "to": "mm"},
6843   "name": "CP_WAIT_SEM_ADDR_HI",
6844   "type_ref": "CP_SIG_SEM_ADDR_HI"
6845  },
6846  {
6847   "chips": ["gfx103"],
6848   "map": {"at": 197084, "to": "mm"},
6849   "name": "CP_DMA_PFP_CONTROL",
6850   "type_ref": "CP_DMA_PFP_CONTROL"
6851  },
6852  {
6853   "chips": ["gfx103"],
6854   "map": {"at": 197088, "to": "mm"},
6855   "name": "CP_DMA_ME_CONTROL",
6856   "type_ref": "CP_DMA_PFP_CONTROL"
6857  },
6858  {
6859   "chips": ["gfx103"],
6860   "map": {"at": 197092, "to": "mm"},
6861   "name": "CP_COHER_BASE_HI",
6862   "type_ref": "CP_COHER_BASE_HI"
6863  },
6864  {
6865   "chips": ["gfx103"],
6866   "map": {"at": 197100, "to": "mm"},
6867   "name": "CP_COHER_START_DELAY",
6868   "type_ref": "CP_COHER_START_DELAY"
6869  },
6870  {
6871   "chips": ["gfx103"],
6872   "map": {"at": 197104, "to": "mm"},
6873   "name": "CP_COHER_CNTL",
6874   "type_ref": "CP_COHER_CNTL"
6875  },
6876  {
6877   "chips": ["gfx103"],
6878   "map": {"at": 197108, "to": "mm"},
6879   "name": "CP_COHER_SIZE"
6880  },
6881  {
6882   "chips": ["gfx103"],
6883   "map": {"at": 197112, "to": "mm"},
6884   "name": "CP_COHER_BASE"
6885  },
6886  {
6887   "chips": ["gfx103"],
6888   "map": {"at": 197116, "to": "mm"},
6889   "name": "CP_COHER_STATUS",
6890   "type_ref": "CP_COHER_STATUS"
6891  },
6892  {
6893   "chips": ["gfx103"],
6894   "map": {"at": 197120, "to": "mm"},
6895   "name": "CP_DMA_ME_SRC_ADDR"
6896  },
6897  {
6898   "chips": ["gfx103"],
6899   "map": {"at": 197124, "to": "mm"},
6900   "name": "CP_DMA_ME_SRC_ADDR_HI",
6901   "type_ref": "CP_DMA_ME_SRC_ADDR_HI"
6902  },
6903  {
6904   "chips": ["gfx103"],
6905   "map": {"at": 197128, "to": "mm"},
6906   "name": "CP_DMA_ME_DST_ADDR"
6907  },
6908  {
6909   "chips": ["gfx103"],
6910   "map": {"at": 197132, "to": "mm"},
6911   "name": "CP_DMA_ME_DST_ADDR_HI",
6912   "type_ref": "CP_DMA_ME_DST_ADDR_HI"
6913  },
6914  {
6915   "chips": ["gfx103"],
6916   "map": {"at": 197136, "to": "mm"},
6917   "name": "CP_DMA_ME_COMMAND",
6918   "type_ref": "CP_DMA_ME_COMMAND"
6919  },
6920  {
6921   "chips": ["gfx103"],
6922   "map": {"at": 197140, "to": "mm"},
6923   "name": "CP_DMA_PFP_SRC_ADDR"
6924  },
6925  {
6926   "chips": ["gfx103"],
6927   "map": {"at": 197144, "to": "mm"},
6928   "name": "CP_DMA_PFP_SRC_ADDR_HI",
6929   "type_ref": "CP_DMA_ME_SRC_ADDR_HI"
6930  },
6931  {
6932   "chips": ["gfx103"],
6933   "map": {"at": 197148, "to": "mm"},
6934   "name": "CP_DMA_PFP_DST_ADDR"
6935  },
6936  {
6937   "chips": ["gfx103"],
6938   "map": {"at": 197152, "to": "mm"},
6939   "name": "CP_DMA_PFP_DST_ADDR_HI",
6940   "type_ref": "CP_DMA_ME_DST_ADDR_HI"
6941  },
6942  {
6943   "chips": ["gfx103"],
6944   "map": {"at": 197156, "to": "mm"},
6945   "name": "CP_DMA_PFP_COMMAND",
6946   "type_ref": "CP_DMA_ME_COMMAND"
6947  },
6948  {
6949   "chips": ["gfx103"],
6950   "map": {"at": 197160, "to": "mm"},
6951   "name": "CP_DMA_CNTL",
6952   "type_ref": "CP_DMA_CNTL"
6953  },
6954  {
6955   "chips": ["gfx103"],
6956   "map": {"at": 197164, "to": "mm"},
6957   "name": "CP_DMA_READ_TAGS",
6958   "type_ref": "CP_DMA_READ_TAGS"
6959  },
6960  {
6961   "chips": ["gfx103"],
6962   "map": {"at": 197168, "to": "mm"},
6963   "name": "CP_COHER_SIZE_HI",
6964   "type_ref": "CP_COHER_SIZE_HI"
6965  },
6966  {
6967   "chips": ["gfx103"],
6968   "map": {"at": 197172, "to": "mm"},
6969   "name": "CP_PFP_IB_CONTROL",
6970   "type_ref": "CP_PFP_IB_CONTROL"
6971  },
6972  {
6973   "chips": ["gfx103"],
6974   "map": {"at": 197176, "to": "mm"},
6975   "name": "CP_PFP_LOAD_CONTROL",
6976   "type_ref": "CP_PFP_LOAD_CONTROL"
6977  },
6978  {
6979   "chips": ["gfx103"],
6980   "map": {"at": 197180, "to": "mm"},
6981   "name": "CP_SCRATCH_INDEX",
6982   "type_ref": "CP_CPC_SCRATCH_INDEX"
6983  },
6984  {
6985   "chips": ["gfx103"],
6986   "map": {"at": 197184, "to": "mm"},
6987   "name": "CP_SCRATCH_DATA"
6988  },
6989  {
6990   "chips": ["gfx103"],
6991   "map": {"at": 197188, "to": "mm"},
6992   "name": "CP_RB_OFFSET",
6993   "type_ref": "CP_RB_OFFSET"
6994  },
6995  {
6996   "chips": ["gfx103"],
6997   "map": {"at": 197196, "to": "mm"},
6998   "name": "CP_IB2_OFFSET",
6999   "type_ref": "CP_IB2_OFFSET"
7000  },
7001  {
7002   "chips": ["gfx103"],
7003   "map": {"at": 197208, "to": "mm"},
7004   "name": "CP_IB2_PREAMBLE_BEGIN",
7005   "type_ref": "CP_IB2_PREAMBLE_BEGIN"
7006  },
7007  {
7008   "chips": ["gfx103"],
7009   "map": {"at": 197212, "to": "mm"},
7010   "name": "CP_IB2_PREAMBLE_END",
7011   "type_ref": "CP_IB2_PREAMBLE_END"
7012  },
7013  {
7014   "chips": ["gfx103"],
7015   "map": {"at": 197216, "to": "mm"},
7016   "name": "CP_CE_IB1_OFFSET",
7017   "type_ref": "CP_CE_IB1_OFFSET"
7018  },
7019  {
7020   "chips": ["gfx103"],
7021   "map": {"at": 197220, "to": "mm"},
7022   "name": "CP_CE_IB2_OFFSET",
7023   "type_ref": "CP_IB2_OFFSET"
7024  },
7025  {
7026   "chips": ["gfx103"],
7027   "map": {"at": 197224, "to": "mm"},
7028   "name": "CP_CE_COUNTER"
7029  },
7030  {
7031   "chips": ["gfx103"],
7032   "map": {"at": 197232, "to": "mm"},
7033   "name": "CP_DMA_ME_CMD_ADDR_LO",
7034   "type_ref": "CP_DMA_ME_CMD_ADDR_LO"
7035  },
7036  {
7037   "chips": ["gfx103"],
7038   "map": {"at": 197236, "to": "mm"},
7039   "name": "CP_DMA_ME_CMD_ADDR_HI",
7040   "type_ref": "CP_DMA_ME_CMD_ADDR_HI"
7041  },
7042  {
7043   "chips": ["gfx103"],
7044   "map": {"at": 197240, "to": "mm"},
7045   "name": "CP_DMA_PFP_CMD_ADDR_LO",
7046   "type_ref": "CP_DMA_ME_CMD_ADDR_LO"
7047  },
7048  {
7049   "chips": ["gfx103"],
7050   "map": {"at": 197244, "to": "mm"},
7051   "name": "CP_DMA_PFP_CMD_ADDR_HI",
7052   "type_ref": "CP_DMA_ME_CMD_ADDR_HI"
7053  },
7054  {
7055   "chips": ["gfx103"],
7056   "map": {"at": 197248, "to": "mm"},
7057   "name": "CP_APPEND_CMD_ADDR_LO",
7058   "type_ref": "CP_DMA_ME_CMD_ADDR_LO"
7059  },
7060  {
7061   "chips": ["gfx103"],
7062   "map": {"at": 197252, "to": "mm"},
7063   "name": "CP_APPEND_CMD_ADDR_HI",
7064   "type_ref": "CP_DMA_ME_CMD_ADDR_HI"
7065  },
7066  {
7067   "chips": ["gfx103"],
7068   "map": {"at": 197256, "to": "mm"},
7069   "name": "UCONFIG_RESERVED_REG0"
7070  },
7071  {
7072   "chips": ["gfx103"],
7073   "map": {"at": 197260, "to": "mm"},
7074   "name": "UCONFIG_RESERVED_REG1"
7075  },
7076  {
7077   "chips": ["gfx103"],
7078   "map": {"at": 197280, "to": "mm"},
7079   "name": "CP_CE_ATOMIC_PREOP_LO"
7080  },
7081  {
7082   "chips": ["gfx103"],
7083   "map": {"at": 197284, "to": "mm"},
7084   "name": "CP_CE_ATOMIC_PREOP_HI"
7085  },
7086  {
7087   "chips": ["gfx103"],
7088   "map": {"at": 197288, "to": "mm"},
7089   "name": "CP_CE_GDS_ATOMIC0_PREOP_LO"
7090  },
7091  {
7092   "chips": ["gfx103"],
7093   "map": {"at": 197292, "to": "mm"},
7094   "name": "CP_CE_GDS_ATOMIC0_PREOP_HI"
7095  },
7096  {
7097   "chips": ["gfx103"],
7098   "map": {"at": 197296, "to": "mm"},
7099   "name": "CP_CE_GDS_ATOMIC1_PREOP_LO"
7100  },
7101  {
7102   "chips": ["gfx103"],
7103   "map": {"at": 197300, "to": "mm"},
7104   "name": "CP_CE_GDS_ATOMIC1_PREOP_HI"
7105  },
7106  {
7107   "chips": ["gfx103"],
7108   "map": {"at": 197364, "to": "mm"},
7109   "name": "CP_CE_INIT_CMD_BUFSZ",
7110   "type_ref": "CP_CE_INIT_CMD_BUFSZ"
7111  },
7112  {
7113   "chips": ["gfx103"],
7114   "map": {"at": 197368, "to": "mm"},
7115   "name": "CP_CE_IB1_CMD_BUFSZ",
7116   "type_ref": "CP_CE_IB1_CMD_BUFSZ"
7117  },
7118  {
7119   "chips": ["gfx103"],
7120   "map": {"at": 197372, "to": "mm"},
7121   "name": "CP_CE_IB2_CMD_BUFSZ",
7122   "type_ref": "CP_CE_IB2_CMD_BUFSZ"
7123  },
7124  {
7125   "chips": ["gfx103"],
7126   "map": {"at": 197380, "to": "mm"},
7127   "name": "CP_IB2_CMD_BUFSZ",
7128   "type_ref": "CP_CE_IB2_CMD_BUFSZ"
7129  },
7130  {
7131   "chips": ["gfx103"],
7132   "map": {"at": 197384, "to": "mm"},
7133   "name": "CP_ST_CMD_BUFSZ",
7134   "type_ref": "CP_ST_CMD_BUFSZ"
7135  },
7136  {
7137   "chips": ["gfx103"],
7138   "map": {"at": 197388, "to": "mm"},
7139   "name": "CP_CE_INIT_BASE_LO",
7140   "type_ref": "CP_CE_INIT_BASE_LO"
7141  },
7142  {
7143   "chips": ["gfx103"],
7144   "map": {"at": 197392, "to": "mm"},
7145   "name": "CP_CE_INIT_BASE_HI",
7146   "type_ref": "CP_CE_INIT_BASE_HI"
7147  },
7148  {
7149   "chips": ["gfx103"],
7150   "map": {"at": 197396, "to": "mm"},
7151   "name": "CP_CE_INIT_BUFSZ",
7152   "type_ref": "CP_CE_INIT_BUFSZ"
7153  },
7154  {
7155   "chips": ["gfx103"],
7156   "map": {"at": 197400, "to": "mm"},
7157   "name": "CP_CE_IB1_BASE_LO",
7158   "type_ref": "CP_CE_IB1_BASE_LO"
7159  },
7160  {
7161   "chips": ["gfx103"],
7162   "map": {"at": 197404, "to": "mm"},
7163   "name": "CP_CE_IB1_BASE_HI",
7164   "type_ref": "CP_CE_IB1_BASE_HI"
7165  },
7166  {
7167   "chips": ["gfx103"],
7168   "map": {"at": 197408, "to": "mm"},
7169   "name": "CP_CE_IB1_BUFSZ",
7170   "type_ref": "CP_CE_IB1_BUFSZ"
7171  },
7172  {
7173   "chips": ["gfx103"],
7174   "map": {"at": 197412, "to": "mm"},
7175   "name": "CP_CE_IB2_BASE_LO",
7176   "type_ref": "CP_CE_IB2_BASE_LO"
7177  },
7178  {
7179   "chips": ["gfx103"],
7180   "map": {"at": 197416, "to": "mm"},
7181   "name": "CP_CE_IB2_BASE_HI",
7182   "type_ref": "CP_CE_IB2_BASE_HI"
7183  },
7184  {
7185   "chips": ["gfx103"],
7186   "map": {"at": 197420, "to": "mm"},
7187   "name": "CP_CE_IB2_BUFSZ",
7188   "type_ref": "CP_CE_IB2_BUFSZ"
7189  },
7190  {
7191   "chips": ["gfx103"],
7192   "map": {"at": 197424, "to": "mm"},
7193   "name": "CP_IB1_BASE_LO",
7194   "type_ref": "CP_CE_IB1_BASE_LO"
7195  },
7196  {
7197   "chips": ["gfx103"],
7198   "map": {"at": 197428, "to": "mm"},
7199   "name": "CP_IB1_BASE_HI",
7200   "type_ref": "CP_CE_IB1_BASE_HI"
7201  },
7202  {
7203   "chips": ["gfx103"],
7204   "map": {"at": 197432, "to": "mm"},
7205   "name": "CP_IB1_BUFSZ",
7206   "type_ref": "CP_CE_IB1_BUFSZ"
7207  },
7208  {
7209   "chips": ["gfx103"],
7210   "map": {"at": 197436, "to": "mm"},
7211   "name": "CP_IB2_BASE_LO",
7212   "type_ref": "CP_CE_IB2_BASE_LO"
7213  },
7214  {
7215   "chips": ["gfx103"],
7216   "map": {"at": 197440, "to": "mm"},
7217   "name": "CP_IB2_BASE_HI",
7218   "type_ref": "CP_CE_IB2_BASE_HI"
7219  },
7220  {
7221   "chips": ["gfx103"],
7222   "map": {"at": 197444, "to": "mm"},
7223   "name": "CP_IB2_BUFSZ",
7224   "type_ref": "CP_CE_IB2_BUFSZ"
7225  },
7226  {
7227   "chips": ["gfx103"],
7228   "map": {"at": 197448, "to": "mm"},
7229   "name": "CP_ST_BASE_LO",
7230   "type_ref": "CP_ST_BASE_LO"
7231  },
7232  {
7233   "chips": ["gfx103"],
7234   "map": {"at": 197452, "to": "mm"},
7235   "name": "CP_ST_BASE_HI",
7236   "type_ref": "CP_ST_BASE_HI"
7237  },
7238  {
7239   "chips": ["gfx103"],
7240   "map": {"at": 197456, "to": "mm"},
7241   "name": "CP_ST_BUFSZ",
7242   "type_ref": "CP_ST_BUFSZ"
7243  },
7244  {
7245   "chips": ["gfx103"],
7246   "map": {"at": 197460, "to": "mm"},
7247   "name": "CP_EOP_DONE_EVENT_CNTL",
7248   "type_ref": "CP_EOP_DONE_EVENT_CNTL"
7249  },
7250  {
7251   "chips": ["gfx103"],
7252   "map": {"at": 197464, "to": "mm"},
7253   "name": "CP_EOP_DONE_DATA_CNTL",
7254   "type_ref": "CP_EOP_DONE_DATA_CNTL"
7255  },
7256  {
7257   "chips": ["gfx103"],
7258   "map": {"at": 197468, "to": "mm"},
7259   "name": "CP_EOP_DONE_CNTX_ID"
7260  },
7261  {
7262   "chips": ["gfx103"],
7263   "map": {"at": 197472, "to": "mm"},
7264   "name": "CP_DB_BASE_LO",
7265   "type_ref": "CP_DB_BASE_LO"
7266  },
7267  {
7268   "chips": ["gfx103"],
7269   "map": {"at": 197476, "to": "mm"},
7270   "name": "CP_DB_BASE_HI",
7271   "type_ref": "CP_DB_BASE_HI"
7272  },
7273  {
7274   "chips": ["gfx103"],
7275   "map": {"at": 197480, "to": "mm"},
7276   "name": "CP_DB_BUFSZ",
7277   "type_ref": "CP_DB_BUFSZ"
7278  },
7279  {
7280   "chips": ["gfx103"],
7281   "map": {"at": 197484, "to": "mm"},
7282   "name": "CP_DB_CMD_BUFSZ",
7283   "type_ref": "CP_DB_CMD_BUFSZ"
7284  },
7285  {
7286   "chips": ["gfx103"],
7287   "map": {"at": 197488, "to": "mm"},
7288   "name": "CP_CE_DB_BASE_LO",
7289   "type_ref": "CP_DB_BASE_LO"
7290  },
7291  {
7292   "chips": ["gfx103"],
7293   "map": {"at": 197492, "to": "mm"},
7294   "name": "CP_CE_DB_BASE_HI",
7295   "type_ref": "CP_DB_BASE_HI"
7296  },
7297  {
7298   "chips": ["gfx103"],
7299   "map": {"at": 197496, "to": "mm"},
7300   "name": "CP_CE_DB_BUFSZ",
7301   "type_ref": "CP_DB_BUFSZ"
7302  },
7303  {
7304   "chips": ["gfx103"],
7305   "map": {"at": 197500, "to": "mm"},
7306   "name": "CP_CE_DB_CMD_BUFSZ",
7307   "type_ref": "CP_DB_CMD_BUFSZ"
7308  },
7309  {
7310   "chips": ["gfx103"],
7311   "map": {"at": 197552, "to": "mm"},
7312   "name": "CP_PFP_COMPLETION_STATUS",
7313   "type_ref": "CP_PFP_COMPLETION_STATUS"
7314  },
7315  {
7316   "chips": ["gfx103"],
7317   "map": {"at": 197556, "to": "mm"},
7318   "name": "CP_CE_COMPLETION_STATUS",
7319   "type_ref": "CP_PFP_COMPLETION_STATUS"
7320  },
7321  {
7322   "chips": ["gfx103"],
7323   "map": {"at": 197560, "to": "mm"},
7324   "name": "CP_PRED_NOT_VISIBLE",
7325   "type_ref": "CP_PRED_NOT_VISIBLE"
7326  },
7327  {
7328   "chips": ["gfx103"],
7329   "map": {"at": 197568, "to": "mm"},
7330   "name": "CP_PFP_METADATA_BASE_ADDR"
7331  },
7332  {
7333   "chips": ["gfx103"],
7334   "map": {"at": 197572, "to": "mm"},
7335   "name": "CP_PFP_METADATA_BASE_ADDR_HI",
7336   "type_ref": "CP_EOP_DONE_ADDR_HI"
7337  },
7338  {
7339   "chips": ["gfx103"],
7340   "map": {"at": 197576, "to": "mm"},
7341   "name": "CP_CE_METADATA_BASE_ADDR"
7342  },
7343  {
7344   "chips": ["gfx103"],
7345   "map": {"at": 197580, "to": "mm"},
7346   "name": "CP_CE_METADATA_BASE_ADDR_HI",
7347   "type_ref": "CP_EOP_DONE_ADDR_HI"
7348  },
7349  {
7350   "chips": ["gfx103"],
7351   "map": {"at": 197584, "to": "mm"},
7352   "name": "CP_DRAW_INDX_INDR_ADDR"
7353  },
7354  {
7355   "chips": ["gfx103"],
7356   "map": {"at": 197588, "to": "mm"},
7357   "name": "CP_DRAW_INDX_INDR_ADDR_HI",
7358   "type_ref": "CP_EOP_DONE_ADDR_HI"
7359  },
7360  {
7361   "chips": ["gfx103"],
7362   "map": {"at": 197592, "to": "mm"},
7363   "name": "CP_DISPATCH_INDR_ADDR"
7364  },
7365  {
7366   "chips": ["gfx103"],
7367   "map": {"at": 197596, "to": "mm"},
7368   "name": "CP_DISPATCH_INDR_ADDR_HI",
7369   "type_ref": "CP_EOP_DONE_ADDR_HI"
7370  },
7371  {
7372   "chips": ["gfx103"],
7373   "map": {"at": 197600, "to": "mm"},
7374   "name": "CP_INDEX_BASE_ADDR"
7375  },
7376  {
7377   "chips": ["gfx103"],
7378   "map": {"at": 197604, "to": "mm"},
7379   "name": "CP_INDEX_BASE_ADDR_HI",
7380   "type_ref": "CP_EOP_DONE_ADDR_HI"
7381  },
7382  {
7383   "chips": ["gfx103"],
7384   "map": {"at": 197608, "to": "mm"},
7385   "name": "CP_INDEX_TYPE",
7386   "type_ref": "CP_INDEX_TYPE"
7387  },
7388  {
7389   "chips": ["gfx103"],
7390   "map": {"at": 197612, "to": "mm"},
7391   "name": "CP_GDS_BKUP_ADDR"
7392  },
7393  {
7394   "chips": ["gfx103"],
7395   "map": {"at": 197616, "to": "mm"},
7396   "name": "CP_GDS_BKUP_ADDR_HI",
7397   "type_ref": "CP_EOP_DONE_ADDR_HI"
7398  },
7399  {
7400   "chips": ["gfx103"],
7401   "map": {"at": 197620, "to": "mm"},
7402   "name": "CP_SAMPLE_STATUS",
7403   "type_ref": "CP_SAMPLE_STATUS"
7404  },
7405  {
7406   "chips": ["gfx103"],
7407   "map": {"at": 197624, "to": "mm"},
7408   "name": "CP_ME_COHER_CNTL",
7409   "type_ref": "CP_ME_COHER_CNTL"
7410  },
7411  {
7412   "chips": ["gfx103"],
7413   "map": {"at": 197628, "to": "mm"},
7414   "name": "CP_ME_COHER_SIZE"
7415  },
7416  {
7417   "chips": ["gfx103"],
7418   "map": {"at": 197632, "to": "mm"},
7419   "name": "CP_ME_COHER_SIZE_HI",
7420   "type_ref": "CP_COHER_SIZE_HI"
7421  },
7422  {
7423   "chips": ["gfx103"],
7424   "map": {"at": 197636, "to": "mm"},
7425   "name": "CP_ME_COHER_BASE"
7426  },
7427  {
7428   "chips": ["gfx103"],
7429   "map": {"at": 197640, "to": "mm"},
7430   "name": "CP_ME_COHER_BASE_HI",
7431   "type_ref": "CP_COHER_BASE_HI"
7432  },
7433  {
7434   "chips": ["gfx103"],
7435   "map": {"at": 197644, "to": "mm"},
7436   "name": "CP_ME_COHER_STATUS",
7437   "type_ref": "CP_ME_COHER_STATUS"
7438  },
7439  {
7440   "chips": ["gfx103"],
7441   "map": {"at": 197888, "to": "mm"},
7442   "name": "RLC_GPM_PERF_COUNT_0",
7443   "type_ref": "RLC_GPM_PERF_COUNT_0"
7444  },
7445  {
7446   "chips": ["gfx103"],
7447   "map": {"at": 197892, "to": "mm"},
7448   "name": "RLC_GPM_PERF_COUNT_1",
7449   "type_ref": "RLC_GPM_PERF_COUNT_0"
7450  },
7451  {
7452   "chips": ["gfx103"],
7453   "map": {"at": 198656, "to": "mm"},
7454   "name": "GRBM_GFX_INDEX",
7455   "type_ref": "GRBM_GFX_INDEX"
7456  },
7457  {
7458   "chips": ["gfx103"],
7459   "map": {"at": 198912, "to": "mm"},
7460   "name": "VGT_ESGS_RING_SIZE"
7461  },
7462  {
7463   "chips": ["gfx103"],
7464   "map": {"at": 198916, "to": "mm"},
7465   "name": "VGT_GSVS_RING_SIZE"
7466  },
7467  {
7468   "chips": ["gfx103"],
7469   "map": {"at": 198920, "to": "mm"},
7470   "name": "VGT_PRIMITIVE_TYPE",
7471   "type_ref": "VGT_PRIMITIVE_TYPE"
7472  },
7473  {
7474   "chips": ["gfx103"],
7475   "map": {"at": 198924, "to": "mm"},
7476   "name": "VGT_INDEX_TYPE",
7477   "type_ref": "VGT_INDEX_TYPE"
7478  },
7479  {
7480   "chips": ["gfx103"],
7481   "map": {"at": 198928, "to": "mm"},
7482   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_0"
7483  },
7484  {
7485   "chips": ["gfx103"],
7486   "map": {"at": 198932, "to": "mm"},
7487   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_1"
7488  },
7489  {
7490   "chips": ["gfx103"],
7491   "map": {"at": 198936, "to": "mm"},
7492   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_2"
7493  },
7494  {
7495   "chips": ["gfx103"],
7496   "map": {"at": 198940, "to": "mm"},
7497   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_3"
7498  },
7499  {
7500   "chips": ["gfx103"],
7501   "map": {"at": 198948, "to": "mm"},
7502   "name": "GE_MIN_VTX_INDX"
7503  },
7504  {
7505   "chips": ["gfx103"],
7506   "map": {"at": 198952, "to": "mm"},
7507   "name": "GE_INDX_OFFSET"
7508  },
7509  {
7510   "chips": ["gfx103"],
7511   "map": {"at": 198956, "to": "mm"},
7512   "name": "GE_MULTI_PRIM_IB_RESET_EN",
7513   "type_ref": "VGT_MULTI_PRIM_IB_RESET_EN"
7514  },
7515  {
7516   "chips": ["gfx103"],
7517   "map": {"at": 198960, "to": "mm"},
7518   "name": "VGT_NUM_INDICES"
7519  },
7520  {
7521   "chips": ["gfx103"],
7522   "map": {"at": 198964, "to": "mm"},
7523   "name": "VGT_NUM_INSTANCES"
7524  },
7525  {
7526   "chips": ["gfx103"],
7527   "map": {"at": 198968, "to": "mm"},
7528   "name": "VGT_TF_RING_SIZE",
7529   "type_ref": "VGT_TF_RING_SIZE"
7530  },
7531  {
7532   "chips": ["gfx103"],
7533   "map": {"at": 198972, "to": "mm"},
7534   "name": "VGT_HS_OFFCHIP_PARAM",
7535   "type_ref": "VGT_HS_OFFCHIP_PARAM"
7536  },
7537  {
7538   "chips": ["gfx103"],
7539   "map": {"at": 198976, "to": "mm"},
7540   "name": "VGT_TF_MEMORY_BASE"
7541  },
7542  {
7543   "chips": ["gfx103"],
7544   "map": {"at": 198980, "to": "mm"},
7545   "name": "GE_DMA_FIRST_INDEX"
7546  },
7547  {
7548   "chips": ["gfx103"],
7549   "map": {"at": 198984, "to": "mm"},
7550   "name": "WD_POS_BUF_BASE"
7551  },
7552  {
7553   "chips": ["gfx103"],
7554   "map": {"at": 198988, "to": "mm"},
7555   "name": "WD_POS_BUF_BASE_HI",
7556   "type_ref": "DB_Z_READ_BASE_HI"
7557  },
7558  {
7559   "chips": ["gfx103"],
7560   "map": {"at": 198992, "to": "mm"},
7561   "name": "WD_CNTL_SB_BUF_BASE"
7562  },
7563  {
7564   "chips": ["gfx103"],
7565   "map": {"at": 198996, "to": "mm"},
7566   "name": "WD_CNTL_SB_BUF_BASE_HI",
7567   "type_ref": "DB_Z_READ_BASE_HI"
7568  },
7569  {
7570   "chips": ["gfx103"],
7571   "map": {"at": 199000, "to": "mm"},
7572   "name": "WD_INDEX_BUF_BASE"
7573  },
7574  {
7575   "chips": ["gfx103"],
7576   "map": {"at": 199004, "to": "mm"},
7577   "name": "WD_INDEX_BUF_BASE_HI",
7578   "type_ref": "DB_Z_READ_BASE_HI"
7579  },
7580  {
7581   "chips": ["gfx103"],
7582   "map": {"at": 199008, "to": "mm"},
7583   "name": "IA_MULTI_VGT_PARAM_PIPED",
7584   "type_ref": "IA_MULTI_VGT_PARAM_PIPED"
7585  },
7586  {
7587   "chips": ["gfx103"],
7588   "map": {"at": 199012, "to": "mm"},
7589   "name": "GE_MAX_VTX_INDX"
7590  },
7591  {
7592   "chips": ["gfx103"],
7593   "map": {"at": 199016, "to": "mm"},
7594   "name": "VGT_INSTANCE_BASE_ID"
7595  },
7596  {
7597   "chips": ["gfx103"],
7598   "map": {"at": 199020, "to": "mm"},
7599   "name": "GE_CNTL",
7600   "type_ref": "GE_CNTL"
7601  },
7602  {
7603   "chips": ["gfx103"],
7604   "map": {"at": 199024, "to": "mm"},
7605   "name": "GE_USER_VGPR1"
7606  },
7607  {
7608   "chips": ["gfx103"],
7609   "map": {"at": 199028, "to": "mm"},
7610   "name": "GE_USER_VGPR2"
7611  },
7612  {
7613   "chips": ["gfx103"],
7614   "map": {"at": 199032, "to": "mm"},
7615   "name": "GE_USER_VGPR3"
7616  },
7617  {
7618   "chips": ["gfx103"],
7619   "map": {"at": 199036, "to": "mm"},
7620   "name": "GE_STEREO_CNTL",
7621   "type_ref": "GE_STEREO_CNTL"
7622  },
7623  {
7624   "chips": ["gfx103"],
7625   "map": {"at": 199040, "to": "mm"},
7626   "name": "GE_PC_ALLOC",
7627   "type_ref": "GE_PC_ALLOC"
7628  },
7629  {
7630   "chips": ["gfx103"],
7631   "map": {"at": 199044, "to": "mm"},
7632   "name": "VGT_TF_MEMORY_BASE_HI",
7633   "type_ref": "DB_Z_READ_BASE_HI"
7634  },
7635  {
7636   "chips": ["gfx103"],
7637   "map": {"at": 199048, "to": "mm"},
7638   "name": "GE_USER_VGPR_EN",
7639   "type_ref": "GE_USER_VGPR_EN"
7640  },
7641  {
7642   "chips": ["gfx103"],
7643   "map": {"at": 199168, "to": "mm"},
7644   "name": "PA_SU_LINE_STIPPLE_VALUE",
7645   "type_ref": "PA_SU_LINE_STIPPLE_VALUE"
7646  },
7647  {
7648   "chips": ["gfx103"],
7649   "map": {"at": 199172, "to": "mm"},
7650   "name": "PA_SC_LINE_STIPPLE_STATE",
7651   "type_ref": "PA_SC_LINE_STIPPLE_STATE"
7652  },
7653  {
7654   "chips": ["gfx103"],
7655   "map": {"at": 199184, "to": "mm"},
7656   "name": "PA_SC_SCREEN_EXTENT_MIN_0",
7657   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
7658  },
7659  {
7660   "chips": ["gfx103"],
7661   "map": {"at": 199188, "to": "mm"},
7662   "name": "PA_SC_SCREEN_EXTENT_MAX_0",
7663   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
7664  },
7665  {
7666   "chips": ["gfx103"],
7667   "map": {"at": 199192, "to": "mm"},
7668   "name": "PA_SC_SCREEN_EXTENT_MIN_1",
7669   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
7670  },
7671  {
7672   "chips": ["gfx103"],
7673   "map": {"at": 199212, "to": "mm"},
7674   "name": "PA_SC_SCREEN_EXTENT_MAX_1",
7675   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
7676  },
7677  {
7678   "chips": ["gfx103"],
7679   "map": {"at": 199296, "to": "mm"},
7680   "name": "PA_SC_P3D_TRAP_SCREEN_HV_EN",
7681   "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN"
7682  },
7683  {
7684   "chips": ["gfx103"],
7685   "map": {"at": 199300, "to": "mm"},
7686   "name": "PA_SC_P3D_TRAP_SCREEN_H",
7687   "type_ref": "PA_SC_P3D_TRAP_SCREEN_H"
7688  },
7689  {
7690   "chips": ["gfx103"],
7691   "map": {"at": 199304, "to": "mm"},
7692   "name": "PA_SC_P3D_TRAP_SCREEN_V",
7693   "type_ref": "PA_SC_P3D_TRAP_SCREEN_V"
7694  },
7695  {
7696   "chips": ["gfx103"],
7697   "map": {"at": 199308, "to": "mm"},
7698   "name": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE",
7699   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
7700  },
7701  {
7702   "chips": ["gfx103"],
7703   "map": {"at": 199312, "to": "mm"},
7704   "name": "PA_SC_P3D_TRAP_SCREEN_COUNT",
7705   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
7706  },
7707  {
7708   "chips": ["gfx103"],
7709   "map": {"at": 199328, "to": "mm"},
7710   "name": "PA_SC_HP3D_TRAP_SCREEN_HV_EN",
7711   "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN"
7712  },
7713  {
7714   "chips": ["gfx103"],
7715   "map": {"at": 199332, "to": "mm"},
7716   "name": "PA_SC_HP3D_TRAP_SCREEN_H",
7717   "type_ref": "PA_SC_P3D_TRAP_SCREEN_H"
7718  },
7719  {
7720   "chips": ["gfx103"],
7721   "map": {"at": 199336, "to": "mm"},
7722   "name": "PA_SC_HP3D_TRAP_SCREEN_V",
7723   "type_ref": "PA_SC_P3D_TRAP_SCREEN_V"
7724  },
7725  {
7726   "chips": ["gfx103"],
7727   "map": {"at": 199340, "to": "mm"},
7728   "name": "PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE",
7729   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
7730  },
7731  {
7732   "chips": ["gfx103"],
7733   "map": {"at": 199344, "to": "mm"},
7734   "name": "PA_SC_HP3D_TRAP_SCREEN_COUNT",
7735   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
7736  },
7737  {
7738   "chips": ["gfx103"],
7739   "map": {"at": 199360, "to": "mm"},
7740   "name": "PA_SC_TRAP_SCREEN_HV_EN",
7741   "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN"
7742  },
7743  {
7744   "chips": ["gfx103"],
7745   "map": {"at": 199364, "to": "mm"},
7746   "name": "PA_SC_TRAP_SCREEN_H",
7747   "type_ref": "PA_SC_P3D_TRAP_SCREEN_H"
7748  },
7749  {
7750   "chips": ["gfx103"],
7751   "map": {"at": 199368, "to": "mm"},
7752   "name": "PA_SC_TRAP_SCREEN_V",
7753   "type_ref": "PA_SC_P3D_TRAP_SCREEN_V"
7754  },
7755  {
7756   "chips": ["gfx103"],
7757   "map": {"at": 199372, "to": "mm"},
7758   "name": "PA_SC_TRAP_SCREEN_OCCURRENCE",
7759   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
7760  },
7761  {
7762   "chips": ["gfx103"],
7763   "map": {"at": 199376, "to": "mm"},
7764   "name": "PA_SC_TRAP_SCREEN_COUNT",
7765   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
7766  },
7767  {
7768   "chips": ["gfx103"],
7769   "map": {"at": 199936, "to": "mm"},
7770   "name": "SQ_THREAD_TRACE_USERDATA_0"
7771  },
7772  {
7773   "chips": ["gfx103"],
7774   "map": {"at": 199940, "to": "mm"},
7775   "name": "SQ_THREAD_TRACE_USERDATA_1"
7776  },
7777  {
7778   "chips": ["gfx103"],
7779   "map": {"at": 199944, "to": "mm"},
7780   "name": "SQ_THREAD_TRACE_USERDATA_2"
7781  },
7782  {
7783   "chips": ["gfx103"],
7784   "map": {"at": 199948, "to": "mm"},
7785   "name": "SQ_THREAD_TRACE_USERDATA_3"
7786  },
7787  {
7788   "chips": ["gfx103"],
7789   "map": {"at": 199952, "to": "mm"},
7790   "name": "SQ_THREAD_TRACE_USERDATA_4"
7791  },
7792  {
7793   "chips": ["gfx103"],
7794   "map": {"at": 199956, "to": "mm"},
7795   "name": "SQ_THREAD_TRACE_USERDATA_5"
7796  },
7797  {
7798   "chips": ["gfx103"],
7799   "map": {"at": 199960, "to": "mm"},
7800   "name": "SQ_THREAD_TRACE_USERDATA_6"
7801  },
7802  {
7803   "chips": ["gfx103"],
7804   "map": {"at": 199964, "to": "mm"},
7805   "name": "SQ_THREAD_TRACE_USERDATA_7"
7806  },
7807  {
7808   "chips": ["gfx103"],
7809   "map": {"at": 199968, "to": "mm"},
7810   "name": "SQC_CACHES",
7811   "type_ref": "SQC_CACHES"
7812  },
7813  {
7814   "chips": ["gfx103"],
7815   "map": {"at": 200192, "to": "mm"},
7816   "name": "TA_CS_BC_BASE_ADDR"
7817  },
7818  {
7819   "chips": ["gfx103"],
7820   "map": {"at": 200196, "to": "mm"},
7821   "name": "TA_CS_BC_BASE_ADDR_HI",
7822   "type_ref": "TA_BC_BASE_ADDR_HI"
7823  },
7824  {
7825   "chips": ["gfx103"],
7826   "map": {"at": 200448, "to": "mm"},
7827   "name": "DB_OCCLUSION_COUNT0_LOW"
7828  },
7829  {
7830   "chips": ["gfx103"],
7831   "map": {"at": 200452, "to": "mm"},
7832   "name": "DB_OCCLUSION_COUNT0_HI",
7833   "type_ref": "DB_OCCLUSION_COUNT0_HI"
7834  },
7835  {
7836   "chips": ["gfx103"],
7837   "map": {"at": 200456, "to": "mm"},
7838   "name": "DB_OCCLUSION_COUNT1_LOW"
7839  },
7840  {
7841   "chips": ["gfx103"],
7842   "map": {"at": 200460, "to": "mm"},
7843   "name": "DB_OCCLUSION_COUNT1_HI",
7844   "type_ref": "DB_OCCLUSION_COUNT0_HI"
7845  },
7846  {
7847   "chips": ["gfx103"],
7848   "map": {"at": 200464, "to": "mm"},
7849   "name": "DB_OCCLUSION_COUNT2_LOW"
7850  },
7851  {
7852   "chips": ["gfx103"],
7853   "map": {"at": 200468, "to": "mm"},
7854   "name": "DB_OCCLUSION_COUNT2_HI",
7855   "type_ref": "DB_OCCLUSION_COUNT0_HI"
7856  },
7857  {
7858   "chips": ["gfx103"],
7859   "map": {"at": 200472, "to": "mm"},
7860   "name": "DB_OCCLUSION_COUNT3_LOW"
7861  },
7862  {
7863   "chips": ["gfx103"],
7864   "map": {"at": 200476, "to": "mm"},
7865   "name": "DB_OCCLUSION_COUNT3_HI",
7866   "type_ref": "DB_OCCLUSION_COUNT0_HI"
7867  },
7868  {
7869   "chips": ["gfx103"],
7870   "map": {"at": 200696, "to": "mm"},
7871   "name": "DB_ZPASS_COUNT_LOW"
7872  },
7873  {
7874   "chips": ["gfx103"],
7875   "map": {"at": 200700, "to": "mm"},
7876   "name": "DB_ZPASS_COUNT_HI",
7877   "type_ref": "DB_OCCLUSION_COUNT0_HI"
7878  },
7879  {
7880   "chips": ["gfx103"],
7881   "map": {"at": 200704, "to": "mm"},
7882   "name": "GDS_RD_ADDR"
7883  },
7884  {
7885   "chips": ["gfx103"],
7886   "map": {"at": 200708, "to": "mm"},
7887   "name": "GDS_RD_DATA"
7888  },
7889  {
7890   "chips": ["gfx103"],
7891   "map": {"at": 200712, "to": "mm"},
7892   "name": "GDS_RD_BURST_ADDR"
7893  },
7894  {
7895   "chips": ["gfx103"],
7896   "map": {"at": 200716, "to": "mm"},
7897   "name": "GDS_RD_BURST_COUNT"
7898  },
7899  {
7900   "chips": ["gfx103"],
7901   "map": {"at": 200720, "to": "mm"},
7902   "name": "GDS_RD_BURST_DATA"
7903  },
7904  {
7905   "chips": ["gfx103"],
7906   "map": {"at": 200724, "to": "mm"},
7907   "name": "GDS_WR_ADDR"
7908  },
7909  {
7910   "chips": ["gfx103"],
7911   "map": {"at": 200728, "to": "mm"},
7912   "name": "GDS_WR_DATA"
7913  },
7914  {
7915   "chips": ["gfx103"],
7916   "map": {"at": 200732, "to": "mm"},
7917   "name": "GDS_WR_BURST_ADDR"
7918  },
7919  {
7920   "chips": ["gfx103"],
7921   "map": {"at": 200736, "to": "mm"},
7922   "name": "GDS_WR_BURST_DATA"
7923  },
7924  {
7925   "chips": ["gfx103"],
7926   "map": {"at": 200740, "to": "mm"},
7927   "name": "GDS_WRITE_COMPLETE"
7928  },
7929  {
7930   "chips": ["gfx103"],
7931   "map": {"at": 200744, "to": "mm"},
7932   "name": "GDS_ATOM_CNTL",
7933   "type_ref": "GDS_ATOM_CNTL"
7934  },
7935  {
7936   "chips": ["gfx103"],
7937   "map": {"at": 200748, "to": "mm"},
7938   "name": "GDS_ATOM_COMPLETE",
7939   "type_ref": "GDS_ATOM_COMPLETE"
7940  },
7941  {
7942   "chips": ["gfx103"],
7943   "map": {"at": 200752, "to": "mm"},
7944   "name": "GDS_ATOM_BASE",
7945   "type_ref": "GDS_ATOM_BASE"
7946  },
7947  {
7948   "chips": ["gfx103"],
7949   "map": {"at": 200756, "to": "mm"},
7950   "name": "GDS_ATOM_SIZE",
7951   "type_ref": "GDS_ATOM_SIZE"
7952  },
7953  {
7954   "chips": ["gfx103"],
7955   "map": {"at": 200760, "to": "mm"},
7956   "name": "GDS_ATOM_OFFSET0",
7957   "type_ref": "GDS_ATOM_OFFSET0"
7958  },
7959  {
7960   "chips": ["gfx103"],
7961   "map": {"at": 200764, "to": "mm"},
7962   "name": "GDS_ATOM_OFFSET1",
7963   "type_ref": "GDS_ATOM_OFFSET1"
7964  },
7965  {
7966   "chips": ["gfx103"],
7967   "map": {"at": 200768, "to": "mm"},
7968   "name": "GDS_ATOM_DST"
7969  },
7970  {
7971   "chips": ["gfx103"],
7972   "map": {"at": 200772, "to": "mm"},
7973   "name": "GDS_ATOM_OP",
7974   "type_ref": "GDS_ATOM_OP"
7975  },
7976  {
7977   "chips": ["gfx103"],
7978   "map": {"at": 200776, "to": "mm"},
7979   "name": "GDS_ATOM_SRC0"
7980  },
7981  {
7982   "chips": ["gfx103"],
7983   "map": {"at": 200780, "to": "mm"},
7984   "name": "GDS_ATOM_SRC0_U"
7985  },
7986  {
7987   "chips": ["gfx103"],
7988   "map": {"at": 200784, "to": "mm"},
7989   "name": "GDS_ATOM_SRC1"
7990  },
7991  {
7992   "chips": ["gfx103"],
7993   "map": {"at": 200788, "to": "mm"},
7994   "name": "GDS_ATOM_SRC1_U"
7995  },
7996  {
7997   "chips": ["gfx103"],
7998   "map": {"at": 200792, "to": "mm"},
7999   "name": "GDS_ATOM_READ0"
8000  },
8001  {
8002   "chips": ["gfx103"],
8003   "map": {"at": 200796, "to": "mm"},
8004   "name": "GDS_ATOM_READ0_U"
8005  },
8006  {
8007   "chips": ["gfx103"],
8008   "map": {"at": 200800, "to": "mm"},
8009   "name": "GDS_ATOM_READ1"
8010  },
8011  {
8012   "chips": ["gfx103"],
8013   "map": {"at": 200804, "to": "mm"},
8014   "name": "GDS_ATOM_READ1_U"
8015  },
8016  {
8017   "chips": ["gfx103"],
8018   "map": {"at": 200808, "to": "mm"},
8019   "name": "GDS_GWS_RESOURCE_CNTL",
8020   "type_ref": "GDS_GWS_RESOURCE_CNTL"
8021  },
8022  {
8023   "chips": ["gfx103"],
8024   "map": {"at": 200812, "to": "mm"},
8025   "name": "GDS_GWS_RESOURCE",
8026   "type_ref": "GDS_GWS_RESOURCE"
8027  },
8028  {
8029   "chips": ["gfx103"],
8030   "map": {"at": 200816, "to": "mm"},
8031   "name": "GDS_GWS_RESOURCE_CNT",
8032   "type_ref": "GDS_GWS_RESOURCE_CNT"
8033  },
8034  {
8035   "chips": ["gfx103"],
8036   "map": {"at": 200820, "to": "mm"},
8037   "name": "GDS_OA_CNTL",
8038   "type_ref": "GDS_OA_CNTL"
8039  },
8040  {
8041   "chips": ["gfx103"],
8042   "map": {"at": 200824, "to": "mm"},
8043   "name": "GDS_OA_COUNTER"
8044  },
8045  {
8046   "chips": ["gfx103"],
8047   "map": {"at": 200828, "to": "mm"},
8048   "name": "GDS_OA_ADDRESS",
8049   "type_ref": "GDS_OA_ADDRESS"
8050  },
8051  {
8052   "chips": ["gfx103"],
8053   "map": {"at": 200832, "to": "mm"},
8054   "name": "GDS_OA_INCDEC",
8055   "type_ref": "GDS_OA_INCDEC"
8056  },
8057  {
8058   "chips": ["gfx103"],
8059   "map": {"at": 200836, "to": "mm"},
8060   "name": "GDS_OA_RING_SIZE"
8061  },
8062  {
8063   "chips": ["gfx103"],
8064   "map": {"at": 200960, "to": "mm"},
8065   "name": "SPI_CONFIG_CNTL_REMAP"
8066  },
8067  {
8068   "chips": ["gfx103"],
8069   "map": {"at": 200964, "to": "mm"},
8070   "name": "SPI_CONFIG_CNTL_1_REMAP"
8071  },
8072  {
8073   "chips": ["gfx103"],
8074   "map": {"at": 200968, "to": "mm"},
8075   "name": "SPI_CONFIG_CNTL_2_REMAP"
8076  },
8077  {
8078   "chips": ["gfx103"],
8079   "map": {"at": 200972, "to": "mm"},
8080   "name": "SPI_WAVE_LIMIT_CNTL_REMAP"
8081  },
8082  {
8083   "chips": ["gfx103"],
8084   "map": {"at": 212992, "to": "mm"},
8085   "name": "CPG_PERFCOUNTER1_LO"
8086  },
8087  {
8088   "chips": ["gfx103"],
8089   "map": {"at": 212996, "to": "mm"},
8090   "name": "CPG_PERFCOUNTER1_HI"
8091  },
8092  {
8093   "chips": ["gfx103"],
8094   "map": {"at": 213000, "to": "mm"},
8095   "name": "CPG_PERFCOUNTER0_LO"
8096  },
8097  {
8098   "chips": ["gfx103"],
8099   "map": {"at": 213004, "to": "mm"},
8100   "name": "CPG_PERFCOUNTER0_HI"
8101  },
8102  {
8103   "chips": ["gfx103"],
8104   "map": {"at": 213008, "to": "mm"},
8105   "name": "CPC_PERFCOUNTER1_LO"
8106  },
8107  {
8108   "chips": ["gfx103"],
8109   "map": {"at": 213012, "to": "mm"},
8110   "name": "CPC_PERFCOUNTER1_HI"
8111  },
8112  {
8113   "chips": ["gfx103"],
8114   "map": {"at": 213016, "to": "mm"},
8115   "name": "CPC_PERFCOUNTER0_LO"
8116  },
8117  {
8118   "chips": ["gfx103"],
8119   "map": {"at": 213020, "to": "mm"},
8120   "name": "CPC_PERFCOUNTER0_HI"
8121  },
8122  {
8123   "chips": ["gfx103"],
8124   "map": {"at": 213024, "to": "mm"},
8125   "name": "CPF_PERFCOUNTER1_LO"
8126  },
8127  {
8128   "chips": ["gfx103"],
8129   "map": {"at": 213028, "to": "mm"},
8130   "name": "CPF_PERFCOUNTER1_HI"
8131  },
8132  {
8133   "chips": ["gfx103"],
8134   "map": {"at": 213032, "to": "mm"},
8135   "name": "CPF_PERFCOUNTER0_LO"
8136  },
8137  {
8138   "chips": ["gfx103"],
8139   "map": {"at": 213036, "to": "mm"},
8140   "name": "CPF_PERFCOUNTER0_HI"
8141  },
8142  {
8143   "chips": ["gfx103"],
8144   "map": {"at": 213040, "to": "mm"},
8145   "name": "CPF_LATENCY_STATS_DATA"
8146  },
8147  {
8148   "chips": ["gfx103"],
8149   "map": {"at": 213044, "to": "mm"},
8150   "name": "CPG_LATENCY_STATS_DATA"
8151  },
8152  {
8153   "chips": ["gfx103"],
8154   "map": {"at": 213048, "to": "mm"},
8155   "name": "CPC_LATENCY_STATS_DATA"
8156  },
8157  {
8158   "chips": ["gfx103"],
8159   "map": {"at": 213248, "to": "mm"},
8160   "name": "GRBM_PERFCOUNTER0_LO"
8161  },
8162  {
8163   "chips": ["gfx103"],
8164   "map": {"at": 213252, "to": "mm"},
8165   "name": "GRBM_PERFCOUNTER0_HI"
8166  },
8167  {
8168   "chips": ["gfx103"],
8169   "map": {"at": 213260, "to": "mm"},
8170   "name": "GRBM_PERFCOUNTER1_LO"
8171  },
8172  {
8173   "chips": ["gfx103"],
8174   "map": {"at": 213264, "to": "mm"},
8175   "name": "GRBM_PERFCOUNTER1_HI"
8176  },
8177  {
8178   "chips": ["gfx103"],
8179   "map": {"at": 213268, "to": "mm"},
8180   "name": "GRBM_SE0_PERFCOUNTER_LO"
8181  },
8182  {
8183   "chips": ["gfx103"],
8184   "map": {"at": 213272, "to": "mm"},
8185   "name": "GRBM_SE0_PERFCOUNTER_HI"
8186  },
8187  {
8188   "chips": ["gfx103"],
8189   "map": {"at": 213276, "to": "mm"},
8190   "name": "GRBM_SE1_PERFCOUNTER_LO"
8191  },
8192  {
8193   "chips": ["gfx103"],
8194   "map": {"at": 213280, "to": "mm"},
8195   "name": "GRBM_SE1_PERFCOUNTER_HI"
8196  },
8197  {
8198   "chips": ["gfx103"],
8199   "map": {"at": 213284, "to": "mm"},
8200   "name": "GRBM_SE2_PERFCOUNTER_LO"
8201  },
8202  {
8203   "chips": ["gfx103"],
8204   "map": {"at": 213288, "to": "mm"},
8205   "name": "GRBM_SE2_PERFCOUNTER_HI"
8206  },
8207  {
8208   "chips": ["gfx103"],
8209   "map": {"at": 213292, "to": "mm"},
8210   "name": "GRBM_SE3_PERFCOUNTER_LO"
8211  },
8212  {
8213   "chips": ["gfx103"],
8214   "map": {"at": 213296, "to": "mm"},
8215   "name": "GRBM_SE3_PERFCOUNTER_HI"
8216  },
8217  {
8218   "chips": ["gfx103"],
8219   "map": {"at": 213648, "to": "mm"},
8220   "name": "GE1_PERFCOUNTER0_LO"
8221  },
8222  {
8223   "chips": ["gfx103"],
8224   "map": {"at": 213652, "to": "mm"},
8225   "name": "GE1_PERFCOUNTER0_HI"
8226  },
8227  {
8228   "chips": ["gfx103"],
8229   "map": {"at": 213656, "to": "mm"},
8230   "name": "GE1_PERFCOUNTER1_LO"
8231  },
8232  {
8233   "chips": ["gfx103"],
8234   "map": {"at": 213660, "to": "mm"},
8235   "name": "GE1_PERFCOUNTER1_HI"
8236  },
8237  {
8238   "chips": ["gfx103"],
8239   "map": {"at": 213664, "to": "mm"},
8240   "name": "GE1_PERFCOUNTER2_LO"
8241  },
8242  {
8243   "chips": ["gfx103"],
8244   "map": {"at": 213668, "to": "mm"},
8245   "name": "GE1_PERFCOUNTER2_HI"
8246  },
8247  {
8248   "chips": ["gfx103"],
8249   "map": {"at": 213672, "to": "mm"},
8250   "name": "GE1_PERFCOUNTER3_LO"
8251  },
8252  {
8253   "chips": ["gfx103"],
8254   "map": {"at": 213676, "to": "mm"},
8255   "name": "GE1_PERFCOUNTER3_HI"
8256  },
8257  {
8258   "chips": ["gfx103"],
8259   "map": {"at": 213680, "to": "mm"},
8260   "name": "GE2_DIST_PERFCOUNTER0_LO"
8261  },
8262  {
8263   "chips": ["gfx103"],
8264   "map": {"at": 213684, "to": "mm"},
8265   "name": "GE2_DIST_PERFCOUNTER0_HI"
8266  },
8267  {
8268   "chips": ["gfx103"],
8269   "map": {"at": 213688, "to": "mm"},
8270   "name": "GE2_DIST_PERFCOUNTER1_LO"
8271  },
8272  {
8273   "chips": ["gfx103"],
8274   "map": {"at": 213692, "to": "mm"},
8275   "name": "GE2_DIST_PERFCOUNTER1_HI"
8276  },
8277  {
8278   "chips": ["gfx103"],
8279   "map": {"at": 213696, "to": "mm"},
8280   "name": "GE2_DIST_PERFCOUNTER2_LO"
8281  },
8282  {
8283   "chips": ["gfx103"],
8284   "map": {"at": 213700, "to": "mm"},
8285   "name": "GE2_DIST_PERFCOUNTER2_HI"
8286  },
8287  {
8288   "chips": ["gfx103"],
8289   "map": {"at": 213704, "to": "mm"},
8290   "name": "GE2_DIST_PERFCOUNTER3_LO"
8291  },
8292  {
8293   "chips": ["gfx103"],
8294   "map": {"at": 213708, "to": "mm"},
8295   "name": "GE2_DIST_PERFCOUNTER3_HI"
8296  },
8297  {
8298   "chips": ["gfx103"],
8299   "map": {"at": 213712, "to": "mm"},
8300   "name": "GE2_SE_PERFCOUNTER0_LO"
8301  },
8302  {
8303   "chips": ["gfx103"],
8304   "map": {"at": 213716, "to": "mm"},
8305   "name": "GE2_SE_PERFCOUNTER0_HI"
8306  },
8307  {
8308   "chips": ["gfx103"],
8309   "map": {"at": 213720, "to": "mm"},
8310   "name": "GE2_SE_PERFCOUNTER1_LO"
8311  },
8312  {
8313   "chips": ["gfx103"],
8314   "map": {"at": 213724, "to": "mm"},
8315   "name": "GE2_SE_PERFCOUNTER1_HI"
8316  },
8317  {
8318   "chips": ["gfx103"],
8319   "map": {"at": 213728, "to": "mm"},
8320   "name": "GE2_SE_PERFCOUNTER2_LO"
8321  },
8322  {
8323   "chips": ["gfx103"],
8324   "map": {"at": 213732, "to": "mm"},
8325   "name": "GE2_SE_PERFCOUNTER2_HI"
8326  },
8327  {
8328   "chips": ["gfx103"],
8329   "map": {"at": 213736, "to": "mm"},
8330   "name": "GE2_SE_PERFCOUNTER3_LO"
8331  },
8332  {
8333   "chips": ["gfx103"],
8334   "map": {"at": 213740, "to": "mm"},
8335   "name": "GE2_SE_PERFCOUNTER3_HI"
8336  },
8337  {
8338   "chips": ["gfx103"],
8339   "map": {"at": 214016, "to": "mm"},
8340   "name": "PA_SU_PERFCOUNTER0_LO"
8341  },
8342  {
8343   "chips": ["gfx103"],
8344   "map": {"at": 214020, "to": "mm"},
8345   "name": "PA_SU_PERFCOUNTER0_HI"
8346  },
8347  {
8348   "chips": ["gfx103"],
8349   "map": {"at": 214024, "to": "mm"},
8350   "name": "PA_SU_PERFCOUNTER1_LO"
8351  },
8352  {
8353   "chips": ["gfx103"],
8354   "map": {"at": 214028, "to": "mm"},
8355   "name": "PA_SU_PERFCOUNTER1_HI"
8356  },
8357  {
8358   "chips": ["gfx103"],
8359   "map": {"at": 214032, "to": "mm"},
8360   "name": "PA_SU_PERFCOUNTER2_LO"
8361  },
8362  {
8363   "chips": ["gfx103"],
8364   "map": {"at": 214036, "to": "mm"},
8365   "name": "PA_SU_PERFCOUNTER2_HI"
8366  },
8367  {
8368   "chips": ["gfx103"],
8369   "map": {"at": 214040, "to": "mm"},
8370   "name": "PA_SU_PERFCOUNTER3_LO"
8371  },
8372  {
8373   "chips": ["gfx103"],
8374   "map": {"at": 214044, "to": "mm"},
8375   "name": "PA_SU_PERFCOUNTER3_HI"
8376  },
8377  {
8378   "chips": ["gfx103"],
8379   "map": {"at": 214272, "to": "mm"},
8380   "name": "PA_SC_PERFCOUNTER0_LO"
8381  },
8382  {
8383   "chips": ["gfx103"],
8384   "map": {"at": 214276, "to": "mm"},
8385   "name": "PA_SC_PERFCOUNTER0_HI"
8386  },
8387  {
8388   "chips": ["gfx103"],
8389   "map": {"at": 214280, "to": "mm"},
8390   "name": "PA_SC_PERFCOUNTER1_LO"
8391  },
8392  {
8393   "chips": ["gfx103"],
8394   "map": {"at": 214284, "to": "mm"},
8395   "name": "PA_SC_PERFCOUNTER1_HI"
8396  },
8397  {
8398   "chips": ["gfx103"],
8399   "map": {"at": 214288, "to": "mm"},
8400   "name": "PA_SC_PERFCOUNTER2_LO"
8401  },
8402  {
8403   "chips": ["gfx103"],
8404   "map": {"at": 214292, "to": "mm"},
8405   "name": "PA_SC_PERFCOUNTER2_HI"
8406  },
8407  {
8408   "chips": ["gfx103"],
8409   "map": {"at": 214296, "to": "mm"},
8410   "name": "PA_SC_PERFCOUNTER3_LO"
8411  },
8412  {
8413   "chips": ["gfx103"],
8414   "map": {"at": 214300, "to": "mm"},
8415   "name": "PA_SC_PERFCOUNTER3_HI"
8416  },
8417  {
8418   "chips": ["gfx103"],
8419   "map": {"at": 214304, "to": "mm"},
8420   "name": "PA_SC_PERFCOUNTER4_LO"
8421  },
8422  {
8423   "chips": ["gfx103"],
8424   "map": {"at": 214308, "to": "mm"},
8425   "name": "PA_SC_PERFCOUNTER4_HI"
8426  },
8427  {
8428   "chips": ["gfx103"],
8429   "map": {"at": 214312, "to": "mm"},
8430   "name": "PA_SC_PERFCOUNTER5_LO"
8431  },
8432  {
8433   "chips": ["gfx103"],
8434   "map": {"at": 214316, "to": "mm"},
8435   "name": "PA_SC_PERFCOUNTER5_HI"
8436  },
8437  {
8438   "chips": ["gfx103"],
8439   "map": {"at": 214320, "to": "mm"},
8440   "name": "PA_SC_PERFCOUNTER6_LO"
8441  },
8442  {
8443   "chips": ["gfx103"],
8444   "map": {"at": 214324, "to": "mm"},
8445   "name": "PA_SC_PERFCOUNTER6_HI"
8446  },
8447  {
8448   "chips": ["gfx103"],
8449   "map": {"at": 214328, "to": "mm"},
8450   "name": "PA_SC_PERFCOUNTER7_LO"
8451  },
8452  {
8453   "chips": ["gfx103"],
8454   "map": {"at": 214332, "to": "mm"},
8455   "name": "PA_SC_PERFCOUNTER7_HI"
8456  },
8457  {
8458   "chips": ["gfx103"],
8459   "map": {"at": 214528, "to": "mm"},
8460   "name": "SPI_PERFCOUNTER0_HI"
8461  },
8462  {
8463   "chips": ["gfx103"],
8464   "map": {"at": 214532, "to": "mm"},
8465   "name": "SPI_PERFCOUNTER0_LO"
8466  },
8467  {
8468   "chips": ["gfx103"],
8469   "map": {"at": 214536, "to": "mm"},
8470   "name": "SPI_PERFCOUNTER1_HI"
8471  },
8472  {
8473   "chips": ["gfx103"],
8474   "map": {"at": 214540, "to": "mm"},
8475   "name": "SPI_PERFCOUNTER1_LO"
8476  },
8477  {
8478   "chips": ["gfx103"],
8479   "map": {"at": 214544, "to": "mm"},
8480   "name": "SPI_PERFCOUNTER2_HI"
8481  },
8482  {
8483   "chips": ["gfx103"],
8484   "map": {"at": 214548, "to": "mm"},
8485   "name": "SPI_PERFCOUNTER2_LO"
8486  },
8487  {
8488   "chips": ["gfx103"],
8489   "map": {"at": 214552, "to": "mm"},
8490   "name": "SPI_PERFCOUNTER3_HI"
8491  },
8492  {
8493   "chips": ["gfx103"],
8494   "map": {"at": 214556, "to": "mm"},
8495   "name": "SPI_PERFCOUNTER3_LO"
8496  },
8497  {
8498   "chips": ["gfx103"],
8499   "map": {"at": 214560, "to": "mm"},
8500   "name": "SPI_PERFCOUNTER4_HI"
8501  },
8502  {
8503   "chips": ["gfx103"],
8504   "map": {"at": 214564, "to": "mm"},
8505   "name": "SPI_PERFCOUNTER4_LO"
8506  },
8507  {
8508   "chips": ["gfx103"],
8509   "map": {"at": 214568, "to": "mm"},
8510   "name": "SPI_PERFCOUNTER5_HI"
8511  },
8512  {
8513   "chips": ["gfx103"],
8514   "map": {"at": 214572, "to": "mm"},
8515   "name": "SPI_PERFCOUNTER5_LO"
8516  },
8517  {
8518   "chips": ["gfx103"],
8519   "map": {"at": 214784, "to": "mm"},
8520   "name": "SQ_PERFCOUNTER0_LO"
8521  },
8522  {
8523   "chips": ["gfx103"],
8524   "map": {"at": 214788, "to": "mm"},
8525   "name": "SQ_PERFCOUNTER0_HI"
8526  },
8527  {
8528   "chips": ["gfx103"],
8529   "map": {"at": 214792, "to": "mm"},
8530   "name": "SQ_PERFCOUNTER1_LO"
8531  },
8532  {
8533   "chips": ["gfx103"],
8534   "map": {"at": 214796, "to": "mm"},
8535   "name": "SQ_PERFCOUNTER1_HI"
8536  },
8537  {
8538   "chips": ["gfx103"],
8539   "map": {"at": 214800, "to": "mm"},
8540   "name": "SQ_PERFCOUNTER2_LO"
8541  },
8542  {
8543   "chips": ["gfx103"],
8544   "map": {"at": 214804, "to": "mm"},
8545   "name": "SQ_PERFCOUNTER2_HI"
8546  },
8547  {
8548   "chips": ["gfx103"],
8549   "map": {"at": 214808, "to": "mm"},
8550   "name": "SQ_PERFCOUNTER3_LO"
8551  },
8552  {
8553   "chips": ["gfx103"],
8554   "map": {"at": 214812, "to": "mm"},
8555   "name": "SQ_PERFCOUNTER3_HI"
8556  },
8557  {
8558   "chips": ["gfx103"],
8559   "map": {"at": 214816, "to": "mm"},
8560   "name": "SQ_PERFCOUNTER4_LO"
8561  },
8562  {
8563   "chips": ["gfx103"],
8564   "map": {"at": 214820, "to": "mm"},
8565   "name": "SQ_PERFCOUNTER4_HI"
8566  },
8567  {
8568   "chips": ["gfx103"],
8569   "map": {"at": 214824, "to": "mm"},
8570   "name": "SQ_PERFCOUNTER5_LO"
8571  },
8572  {
8573   "chips": ["gfx103"],
8574   "map": {"at": 214828, "to": "mm"},
8575   "name": "SQ_PERFCOUNTER5_HI"
8576  },
8577  {
8578   "chips": ["gfx103"],
8579   "map": {"at": 214832, "to": "mm"},
8580   "name": "SQ_PERFCOUNTER6_LO"
8581  },
8582  {
8583   "chips": ["gfx103"],
8584   "map": {"at": 214836, "to": "mm"},
8585   "name": "SQ_PERFCOUNTER6_HI"
8586  },
8587  {
8588   "chips": ["gfx103"],
8589   "map": {"at": 214840, "to": "mm"},
8590   "name": "SQ_PERFCOUNTER7_LO"
8591  },
8592  {
8593   "chips": ["gfx103"],
8594   "map": {"at": 214844, "to": "mm"},
8595   "name": "SQ_PERFCOUNTER7_HI"
8596  },
8597  {
8598   "chips": ["gfx103"],
8599   "map": {"at": 214848, "to": "mm"},
8600   "name": "SQ_PERFCOUNTER8_LO"
8601  },
8602  {
8603   "chips": ["gfx103"],
8604   "map": {"at": 214852, "to": "mm"},
8605   "name": "SQ_PERFCOUNTER8_HI"
8606  },
8607  {
8608   "chips": ["gfx103"],
8609   "map": {"at": 214856, "to": "mm"},
8610   "name": "SQ_PERFCOUNTER9_LO"
8611  },
8612  {
8613   "chips": ["gfx103"],
8614   "map": {"at": 214860, "to": "mm"},
8615   "name": "SQ_PERFCOUNTER9_HI"
8616  },
8617  {
8618   "chips": ["gfx103"],
8619   "map": {"at": 214864, "to": "mm"},
8620   "name": "SQ_PERFCOUNTER10_LO"
8621  },
8622  {
8623   "chips": ["gfx103"],
8624   "map": {"at": 214868, "to": "mm"},
8625   "name": "SQ_PERFCOUNTER10_HI"
8626  },
8627  {
8628   "chips": ["gfx103"],
8629   "map": {"at": 214872, "to": "mm"},
8630   "name": "SQ_PERFCOUNTER11_LO"
8631  },
8632  {
8633   "chips": ["gfx103"],
8634   "map": {"at": 214876, "to": "mm"},
8635   "name": "SQ_PERFCOUNTER11_HI"
8636  },
8637  {
8638   "chips": ["gfx103"],
8639   "map": {"at": 214880, "to": "mm"},
8640   "name": "SQ_PERFCOUNTER12_LO"
8641  },
8642  {
8643   "chips": ["gfx103"],
8644   "map": {"at": 214884, "to": "mm"},
8645   "name": "SQ_PERFCOUNTER12_HI"
8646  },
8647  {
8648   "chips": ["gfx103"],
8649   "map": {"at": 214888, "to": "mm"},
8650   "name": "SQ_PERFCOUNTER13_LO"
8651  },
8652  {
8653   "chips": ["gfx103"],
8654   "map": {"at": 214892, "to": "mm"},
8655   "name": "SQ_PERFCOUNTER13_HI"
8656  },
8657  {
8658   "chips": ["gfx103"],
8659   "map": {"at": 214896, "to": "mm"},
8660   "name": "SQ_PERFCOUNTER14_LO"
8661  },
8662  {
8663   "chips": ["gfx103"],
8664   "map": {"at": 214900, "to": "mm"},
8665   "name": "SQ_PERFCOUNTER14_HI"
8666  },
8667  {
8668   "chips": ["gfx103"],
8669   "map": {"at": 214904, "to": "mm"},
8670   "name": "SQ_PERFCOUNTER15_LO"
8671  },
8672  {
8673   "chips": ["gfx103"],
8674   "map": {"at": 214908, "to": "mm"},
8675   "name": "SQ_PERFCOUNTER15_HI"
8676  },
8677  {
8678   "chips": ["gfx103"],
8679   "map": {"at": 215296, "to": "mm"},
8680   "name": "SX_PERFCOUNTER0_LO"
8681  },
8682  {
8683   "chips": ["gfx103"],
8684   "map": {"at": 215300, "to": "mm"},
8685   "name": "SX_PERFCOUNTER0_HI"
8686  },
8687  {
8688   "chips": ["gfx103"],
8689   "map": {"at": 215304, "to": "mm"},
8690   "name": "SX_PERFCOUNTER1_LO"
8691  },
8692  {
8693   "chips": ["gfx103"],
8694   "map": {"at": 215308, "to": "mm"},
8695   "name": "SX_PERFCOUNTER1_HI"
8696  },
8697  {
8698   "chips": ["gfx103"],
8699   "map": {"at": 215312, "to": "mm"},
8700   "name": "SX_PERFCOUNTER2_LO"
8701  },
8702  {
8703   "chips": ["gfx103"],
8704   "map": {"at": 215316, "to": "mm"},
8705   "name": "SX_PERFCOUNTER2_HI"
8706  },
8707  {
8708   "chips": ["gfx103"],
8709   "map": {"at": 215320, "to": "mm"},
8710   "name": "SX_PERFCOUNTER3_LO"
8711  },
8712  {
8713   "chips": ["gfx103"],
8714   "map": {"at": 215324, "to": "mm"},
8715   "name": "SX_PERFCOUNTER3_HI"
8716  },
8717  {
8718   "chips": ["gfx103"],
8719   "map": {"at": 215424, "to": "mm"},
8720   "name": "GCEA_PERFCOUNTER2_LO"
8721  },
8722  {
8723   "chips": ["gfx103"],
8724   "map": {"at": 215428, "to": "mm"},
8725   "name": "GCEA_PERFCOUNTER2_HI"
8726  },
8727  {
8728   "chips": ["gfx103"],
8729   "map": {"at": 215432, "to": "mm"},
8730   "name": "GCEA_PERFCOUNTER_LO"
8731  },
8732  {
8733   "chips": ["gfx103"],
8734   "map": {"at": 215436, "to": "mm"},
8735   "name": "GCEA_PERFCOUNTER_HI",
8736   "type_ref": "GCEA_PERFCOUNTER_HI"
8737  },
8738  {
8739   "chips": ["gfx103"],
8740   "map": {"at": 215552, "to": "mm"},
8741   "name": "GDS_PERFCOUNTER0_LO"
8742  },
8743  {
8744   "chips": ["gfx103"],
8745   "map": {"at": 215556, "to": "mm"},
8746   "name": "GDS_PERFCOUNTER0_HI"
8747  },
8748  {
8749   "chips": ["gfx103"],
8750   "map": {"at": 215560, "to": "mm"},
8751   "name": "GDS_PERFCOUNTER1_LO"
8752  },
8753  {
8754   "chips": ["gfx103"],
8755   "map": {"at": 215564, "to": "mm"},
8756   "name": "GDS_PERFCOUNTER1_HI"
8757  },
8758  {
8759   "chips": ["gfx103"],
8760   "map": {"at": 215568, "to": "mm"},
8761   "name": "GDS_PERFCOUNTER2_LO"
8762  },
8763  {
8764   "chips": ["gfx103"],
8765   "map": {"at": 215572, "to": "mm"},
8766   "name": "GDS_PERFCOUNTER2_HI"
8767  },
8768  {
8769   "chips": ["gfx103"],
8770   "map": {"at": 215576, "to": "mm"},
8771   "name": "GDS_PERFCOUNTER3_LO"
8772  },
8773  {
8774   "chips": ["gfx103"],
8775   "map": {"at": 215580, "to": "mm"},
8776   "name": "GDS_PERFCOUNTER3_HI"
8777  },
8778  {
8779   "chips": ["gfx103"],
8780   "map": {"at": 215808, "to": "mm"},
8781   "name": "TA_PERFCOUNTER0_LO"
8782  },
8783  {
8784   "chips": ["gfx103"],
8785   "map": {"at": 215812, "to": "mm"},
8786   "name": "TA_PERFCOUNTER0_HI"
8787  },
8788  {
8789   "chips": ["gfx103"],
8790   "map": {"at": 215816, "to": "mm"},
8791   "name": "TA_PERFCOUNTER1_LO"
8792  },
8793  {
8794   "chips": ["gfx103"],
8795   "map": {"at": 215820, "to": "mm"},
8796   "name": "TA_PERFCOUNTER1_HI"
8797  },
8798  {
8799   "chips": ["gfx103"],
8800   "map": {"at": 216064, "to": "mm"},
8801   "name": "TD_PERFCOUNTER0_LO"
8802  },
8803  {
8804   "chips": ["gfx103"],
8805   "map": {"at": 216068, "to": "mm"},
8806   "name": "TD_PERFCOUNTER0_HI"
8807  },
8808  {
8809   "chips": ["gfx103"],
8810   "map": {"at": 216072, "to": "mm"},
8811   "name": "TD_PERFCOUNTER1_LO"
8812  },
8813  {
8814   "chips": ["gfx103"],
8815   "map": {"at": 216076, "to": "mm"},
8816   "name": "TD_PERFCOUNTER1_HI"
8817  },
8818  {
8819   "chips": ["gfx103"],
8820   "map": {"at": 216320, "to": "mm"},
8821   "name": "TCP_PERFCOUNTER0_LO"
8822  },
8823  {
8824   "chips": ["gfx103"],
8825   "map": {"at": 216324, "to": "mm"},
8826   "name": "TCP_PERFCOUNTER0_HI"
8827  },
8828  {
8829   "chips": ["gfx103"],
8830   "map": {"at": 216328, "to": "mm"},
8831   "name": "TCP_PERFCOUNTER1_LO"
8832  },
8833  {
8834   "chips": ["gfx103"],
8835   "map": {"at": 216332, "to": "mm"},
8836   "name": "TCP_PERFCOUNTER1_HI"
8837  },
8838  {
8839   "chips": ["gfx103"],
8840   "map": {"at": 216336, "to": "mm"},
8841   "name": "TCP_PERFCOUNTER2_LO"
8842  },
8843  {
8844   "chips": ["gfx103"],
8845   "map": {"at": 216340, "to": "mm"},
8846   "name": "TCP_PERFCOUNTER2_HI"
8847  },
8848  {
8849   "chips": ["gfx103"],
8850   "map": {"at": 216344, "to": "mm"},
8851   "name": "TCP_PERFCOUNTER3_LO"
8852  },
8853  {
8854   "chips": ["gfx103"],
8855   "map": {"at": 216348, "to": "mm"},
8856   "name": "TCP_PERFCOUNTER3_HI"
8857  },
8858  {
8859   "chips": ["gfx103"],
8860   "map": {"at": 216576, "to": "mm"},
8861   "name": "GL2C_PERFCOUNTER0_LO"
8862  },
8863  {
8864   "chips": ["gfx103"],
8865   "map": {"at": 216580, "to": "mm"},
8866   "name": "GL2C_PERFCOUNTER0_HI"
8867  },
8868  {
8869   "chips": ["gfx103"],
8870   "map": {"at": 216584, "to": "mm"},
8871   "name": "GL2C_PERFCOUNTER1_LO"
8872  },
8873  {
8874   "chips": ["gfx103"],
8875   "map": {"at": 216588, "to": "mm"},
8876   "name": "GL2C_PERFCOUNTER1_HI"
8877  },
8878  {
8879   "chips": ["gfx103"],
8880   "map": {"at": 216592, "to": "mm"},
8881   "name": "GL2C_PERFCOUNTER2_LO"
8882  },
8883  {
8884   "chips": ["gfx103"],
8885   "map": {"at": 216596, "to": "mm"},
8886   "name": "GL2C_PERFCOUNTER2_HI"
8887  },
8888  {
8889   "chips": ["gfx103"],
8890   "map": {"at": 216600, "to": "mm"},
8891   "name": "GL2C_PERFCOUNTER3_LO"
8892  },
8893  {
8894   "chips": ["gfx103"],
8895   "map": {"at": 216604, "to": "mm"},
8896   "name": "GL2C_PERFCOUNTER3_HI"
8897  },
8898  {
8899   "chips": ["gfx103"],
8900   "map": {"at": 216640, "to": "mm"},
8901   "name": "GL2A_PERFCOUNTER0_LO"
8902  },
8903  {
8904   "chips": ["gfx103"],
8905   "map": {"at": 216644, "to": "mm"},
8906   "name": "GL2A_PERFCOUNTER0_HI"
8907  },
8908  {
8909   "chips": ["gfx103"],
8910   "map": {"at": 216648, "to": "mm"},
8911   "name": "GL2A_PERFCOUNTER1_LO"
8912  },
8913  {
8914   "chips": ["gfx103"],
8915   "map": {"at": 216652, "to": "mm"},
8916   "name": "GL2A_PERFCOUNTER1_HI"
8917  },
8918  {
8919   "chips": ["gfx103"],
8920   "map": {"at": 216656, "to": "mm"},
8921   "name": "GL2A_PERFCOUNTER2_LO"
8922  },
8923  {
8924   "chips": ["gfx103"],
8925   "map": {"at": 216660, "to": "mm"},
8926   "name": "GL2A_PERFCOUNTER2_HI"
8927  },
8928  {
8929   "chips": ["gfx103"],
8930   "map": {"at": 216664, "to": "mm"},
8931   "name": "GL2A_PERFCOUNTER3_LO"
8932  },
8933  {
8934   "chips": ["gfx103"],
8935   "map": {"at": 216668, "to": "mm"},
8936   "name": "GL2A_PERFCOUNTER3_HI"
8937  },
8938  {
8939   "chips": ["gfx103"],
8940   "map": {"at": 216704, "to": "mm"},
8941   "name": "GL1C_PERFCOUNTER0_LO"
8942  },
8943  {
8944   "chips": ["gfx103"],
8945   "map": {"at": 216708, "to": "mm"},
8946   "name": "GL1C_PERFCOUNTER0_HI"
8947  },
8948  {
8949   "chips": ["gfx103"],
8950   "map": {"at": 216712, "to": "mm"},
8951   "name": "GL1C_PERFCOUNTER1_LO"
8952  },
8953  {
8954   "chips": ["gfx103"],
8955   "map": {"at": 216716, "to": "mm"},
8956   "name": "GL1C_PERFCOUNTER1_HI"
8957  },
8958  {
8959   "chips": ["gfx103"],
8960   "map": {"at": 216720, "to": "mm"},
8961   "name": "GL1C_PERFCOUNTER2_LO"
8962  },
8963  {
8964   "chips": ["gfx103"],
8965   "map": {"at": 216724, "to": "mm"},
8966   "name": "GL1C_PERFCOUNTER2_HI"
8967  },
8968  {
8969   "chips": ["gfx103"],
8970   "map": {"at": 216728, "to": "mm"},
8971   "name": "GL1C_PERFCOUNTER3_LO"
8972  },
8973  {
8974   "chips": ["gfx103"],
8975   "map": {"at": 216732, "to": "mm"},
8976   "name": "GL1C_PERFCOUNTER3_HI"
8977  },
8978  {
8979   "chips": ["gfx103"],
8980   "map": {"at": 216832, "to": "mm"},
8981   "name": "CHC_PERFCOUNTER0_LO"
8982  },
8983  {
8984   "chips": ["gfx103"],
8985   "map": {"at": 216836, "to": "mm"},
8986   "name": "CHC_PERFCOUNTER0_HI"
8987  },
8988  {
8989   "chips": ["gfx103"],
8990   "map": {"at": 216840, "to": "mm"},
8991   "name": "CHC_PERFCOUNTER1_LO"
8992  },
8993  {
8994   "chips": ["gfx103"],
8995   "map": {"at": 216844, "to": "mm"},
8996   "name": "CHC_PERFCOUNTER1_HI"
8997  },
8998  {
8999   "chips": ["gfx103"],
9000   "map": {"at": 216848, "to": "mm"},
9001   "name": "CHC_PERFCOUNTER2_LO"
9002  },
9003  {
9004   "chips": ["gfx103"],
9005   "map": {"at": 216852, "to": "mm"},
9006   "name": "CHC_PERFCOUNTER2_HI"
9007  },
9008  {
9009   "chips": ["gfx103"],
9010   "map": {"at": 216856, "to": "mm"},
9011   "name": "CHC_PERFCOUNTER3_LO"
9012  },
9013  {
9014   "chips": ["gfx103"],
9015   "map": {"at": 216860, "to": "mm"},
9016   "name": "CHC_PERFCOUNTER3_HI"
9017  },
9018  {
9019   "chips": ["gfx103"],
9020   "map": {"at": 216864, "to": "mm"},
9021   "name": "CHCG_PERFCOUNTER0_LO"
9022  },
9023  {
9024   "chips": ["gfx103"],
9025   "map": {"at": 216868, "to": "mm"},
9026   "name": "CHCG_PERFCOUNTER0_HI"
9027  },
9028  {
9029   "chips": ["gfx103"],
9030   "map": {"at": 216872, "to": "mm"},
9031   "name": "CHCG_PERFCOUNTER1_LO"
9032  },
9033  {
9034   "chips": ["gfx103"],
9035   "map": {"at": 216876, "to": "mm"},
9036   "name": "CHCG_PERFCOUNTER1_HI"
9037  },
9038  {
9039   "chips": ["gfx103"],
9040   "map": {"at": 216880, "to": "mm"},
9041   "name": "CHCG_PERFCOUNTER2_LO"
9042  },
9043  {
9044   "chips": ["gfx103"],
9045   "map": {"at": 216884, "to": "mm"},
9046   "name": "CHCG_PERFCOUNTER2_HI"
9047  },
9048  {
9049   "chips": ["gfx103"],
9050   "map": {"at": 216888, "to": "mm"},
9051   "name": "CHCG_PERFCOUNTER3_LO"
9052  },
9053  {
9054   "chips": ["gfx103"],
9055   "map": {"at": 216892, "to": "mm"},
9056   "name": "CHCG_PERFCOUNTER3_HI"
9057  },
9058  {
9059   "chips": ["gfx103"],
9060   "map": {"at": 217112, "to": "mm"},
9061   "name": "CB_PERFCOUNTER0_LO"
9062  },
9063  {
9064   "chips": ["gfx103"],
9065   "map": {"at": 217116, "to": "mm"},
9066   "name": "CB_PERFCOUNTER0_HI"
9067  },
9068  {
9069   "chips": ["gfx103"],
9070   "map": {"at": 217120, "to": "mm"},
9071   "name": "CB_PERFCOUNTER1_LO"
9072  },
9073  {
9074   "chips": ["gfx103"],
9075   "map": {"at": 217124, "to": "mm"},
9076   "name": "CB_PERFCOUNTER1_HI"
9077  },
9078  {
9079   "chips": ["gfx103"],
9080   "map": {"at": 217128, "to": "mm"},
9081   "name": "CB_PERFCOUNTER2_LO"
9082  },
9083  {
9084   "chips": ["gfx103"],
9085   "map": {"at": 217132, "to": "mm"},
9086   "name": "CB_PERFCOUNTER2_HI"
9087  },
9088  {
9089   "chips": ["gfx103"],
9090   "map": {"at": 217136, "to": "mm"},
9091   "name": "CB_PERFCOUNTER3_LO"
9092  },
9093  {
9094   "chips": ["gfx103"],
9095   "map": {"at": 217140, "to": "mm"},
9096   "name": "CB_PERFCOUNTER3_HI"
9097  },
9098  {
9099   "chips": ["gfx103"],
9100   "map": {"at": 217344, "to": "mm"},
9101   "name": "DB_PERFCOUNTER0_LO"
9102  },
9103  {
9104   "chips": ["gfx103"],
9105   "map": {"at": 217348, "to": "mm"},
9106   "name": "DB_PERFCOUNTER0_HI"
9107  },
9108  {
9109   "chips": ["gfx103"],
9110   "map": {"at": 217352, "to": "mm"},
9111   "name": "DB_PERFCOUNTER1_LO"
9112  },
9113  {
9114   "chips": ["gfx103"],
9115   "map": {"at": 217356, "to": "mm"},
9116   "name": "DB_PERFCOUNTER1_HI"
9117  },
9118  {
9119   "chips": ["gfx103"],
9120   "map": {"at": 217360, "to": "mm"},
9121   "name": "DB_PERFCOUNTER2_LO"
9122  },
9123  {
9124   "chips": ["gfx103"],
9125   "map": {"at": 217364, "to": "mm"},
9126   "name": "DB_PERFCOUNTER2_HI"
9127  },
9128  {
9129   "chips": ["gfx103"],
9130   "map": {"at": 217368, "to": "mm"},
9131   "name": "DB_PERFCOUNTER3_LO"
9132  },
9133  {
9134   "chips": ["gfx103"],
9135   "map": {"at": 217372, "to": "mm"},
9136   "name": "DB_PERFCOUNTER3_HI"
9137  },
9138  {
9139   "chips": ["gfx103"],
9140   "map": {"at": 217600, "to": "mm"},
9141   "name": "RLC_PERFCOUNTER0_LO"
9142  },
9143  {
9144   "chips": ["gfx103"],
9145   "map": {"at": 217604, "to": "mm"},
9146   "name": "RLC_PERFCOUNTER0_HI"
9147  },
9148  {
9149   "chips": ["gfx103"],
9150   "map": {"at": 217608, "to": "mm"},
9151   "name": "RLC_PERFCOUNTER1_LO"
9152  },
9153  {
9154   "chips": ["gfx103"],
9155   "map": {"at": 217612, "to": "mm"},
9156   "name": "RLC_PERFCOUNTER1_HI"
9157  },
9158  {
9159   "chips": ["gfx103"],
9160   "map": {"at": 217856, "to": "mm"},
9161   "name": "RMI_PERFCOUNTER0_LO"
9162  },
9163  {
9164   "chips": ["gfx103"],
9165   "map": {"at": 217860, "to": "mm"},
9166   "name": "RMI_PERFCOUNTER0_HI"
9167  },
9168  {
9169   "chips": ["gfx103"],
9170   "map": {"at": 217864, "to": "mm"},
9171   "name": "RMI_PERFCOUNTER1_LO"
9172  },
9173  {
9174   "chips": ["gfx103"],
9175   "map": {"at": 217868, "to": "mm"},
9176   "name": "RMI_PERFCOUNTER1_HI"
9177  },
9178  {
9179   "chips": ["gfx103"],
9180   "map": {"at": 217872, "to": "mm"},
9181   "name": "RMI_PERFCOUNTER2_LO"
9182  },
9183  {
9184   "chips": ["gfx103"],
9185   "map": {"at": 217876, "to": "mm"},
9186   "name": "RMI_PERFCOUNTER2_HI"
9187  },
9188  {
9189   "chips": ["gfx103"],
9190   "map": {"at": 217880, "to": "mm"},
9191   "name": "RMI_PERFCOUNTER3_LO"
9192  },
9193  {
9194   "chips": ["gfx103"],
9195   "map": {"at": 217884, "to": "mm"},
9196   "name": "RMI_PERFCOUNTER3_HI"
9197  },
9198  {
9199   "chips": ["gfx103"],
9200   "map": {"at": 218016, "to": "mm"},
9201   "name": "GCMC_VM_L2_PERFCOUNTER_LO"
9202  },
9203  {
9204   "chips": ["gfx103"],
9205   "map": {"at": 218020, "to": "mm"},
9206   "name": "GCMC_VM_L2_PERFCOUNTER_HI",
9207   "type_ref": "GCEA_PERFCOUNTER_HI"
9208  },
9209  {
9210   "chips": ["gfx103"],
9211   "map": {"at": 218024, "to": "mm"},
9212   "name": "GCUTCL2_PERFCOUNTER_LO"
9213  },
9214  {
9215   "chips": ["gfx103"],
9216   "map": {"at": 218028, "to": "mm"},
9217   "name": "GCUTCL2_PERFCOUNTER_HI",
9218   "type_ref": "GCEA_PERFCOUNTER_HI"
9219  },
9220  {
9221   "chips": ["gfx103"],
9222   "map": {"at": 218080, "to": "mm"},
9223   "name": "GCVML2_PERFCOUNTER2_0_LO"
9224  },
9225  {
9226   "chips": ["gfx103"],
9227   "map": {"at": 218084, "to": "mm"},
9228   "name": "GCVML2_PERFCOUNTER2_1_LO"
9229  },
9230  {
9231   "chips": ["gfx103"],
9232   "map": {"at": 218088, "to": "mm"},
9233   "name": "GCVML2_PERFCOUNTER2_0_HI"
9234  },
9235  {
9236   "chips": ["gfx103"],
9237   "map": {"at": 218092, "to": "mm"},
9238   "name": "GCVML2_PERFCOUNTER2_1_HI"
9239  },
9240  {
9241   "chips": ["gfx103"],
9242   "map": {"at": 218224, "to": "mm"},
9243   "name": "UTCL1_PERFCOUNTER0_LO"
9244  },
9245  {
9246   "chips": ["gfx103"],
9247   "map": {"at": 218228, "to": "mm"},
9248   "name": "UTCL1_PERFCOUNTER0_HI"
9249  },
9250  {
9251   "chips": ["gfx103"],
9252   "map": {"at": 218232, "to": "mm"},
9253   "name": "UTCL1_PERFCOUNTER1_LO"
9254  },
9255  {
9256   "chips": ["gfx103"],
9257   "map": {"at": 218236, "to": "mm"},
9258   "name": "UTCL1_PERFCOUNTER1_HI"
9259  },
9260  {
9261   "chips": ["gfx103"],
9262   "map": {"at": 218240, "to": "mm"},
9263   "name": "GCR_PERFCOUNTER0_LO"
9264  },
9265  {
9266   "chips": ["gfx103"],
9267   "map": {"at": 218244, "to": "mm"},
9268   "name": "GCR_PERFCOUNTER0_HI"
9269  },
9270  {
9271   "chips": ["gfx103"],
9272   "map": {"at": 218248, "to": "mm"},
9273   "name": "GCR_PERFCOUNTER1_LO"
9274  },
9275  {
9276   "chips": ["gfx103"],
9277   "map": {"at": 218252, "to": "mm"},
9278   "name": "GCR_PERFCOUNTER1_HI"
9279  },
9280  {
9281   "chips": ["gfx103"],
9282   "map": {"at": 218624, "to": "mm"},
9283   "name": "PA_PH_PERFCOUNTER0_LO"
9284  },
9285  {
9286   "chips": ["gfx103"],
9287   "map": {"at": 218628, "to": "mm"},
9288   "name": "PA_PH_PERFCOUNTER0_HI"
9289  },
9290  {
9291   "chips": ["gfx103"],
9292   "map": {"at": 218632, "to": "mm"},
9293   "name": "PA_PH_PERFCOUNTER1_LO"
9294  },
9295  {
9296   "chips": ["gfx103"],
9297   "map": {"at": 218636, "to": "mm"},
9298   "name": "PA_PH_PERFCOUNTER1_HI"
9299  },
9300  {
9301   "chips": ["gfx103"],
9302   "map": {"at": 218640, "to": "mm"},
9303   "name": "PA_PH_PERFCOUNTER2_LO"
9304  },
9305  {
9306   "chips": ["gfx103"],
9307   "map": {"at": 218644, "to": "mm"},
9308   "name": "PA_PH_PERFCOUNTER2_HI"
9309  },
9310  {
9311   "chips": ["gfx103"],
9312   "map": {"at": 218648, "to": "mm"},
9313   "name": "PA_PH_PERFCOUNTER3_LO"
9314  },
9315  {
9316   "chips": ["gfx103"],
9317   "map": {"at": 218652, "to": "mm"},
9318   "name": "PA_PH_PERFCOUNTER3_HI"
9319  },
9320  {
9321   "chips": ["gfx103"],
9322   "map": {"at": 218656, "to": "mm"},
9323   "name": "PA_PH_PERFCOUNTER4_LO"
9324  },
9325  {
9326   "chips": ["gfx103"],
9327   "map": {"at": 218660, "to": "mm"},
9328   "name": "PA_PH_PERFCOUNTER4_HI"
9329  },
9330  {
9331   "chips": ["gfx103"],
9332   "map": {"at": 218664, "to": "mm"},
9333   "name": "PA_PH_PERFCOUNTER5_LO"
9334  },
9335  {
9336   "chips": ["gfx103"],
9337   "map": {"at": 218668, "to": "mm"},
9338   "name": "PA_PH_PERFCOUNTER5_HI"
9339  },
9340  {
9341   "chips": ["gfx103"],
9342   "map": {"at": 218672, "to": "mm"},
9343   "name": "PA_PH_PERFCOUNTER6_LO"
9344  },
9345  {
9346   "chips": ["gfx103"],
9347   "map": {"at": 218676, "to": "mm"},
9348   "name": "PA_PH_PERFCOUNTER6_HI"
9349  },
9350  {
9351   "chips": ["gfx103"],
9352   "map": {"at": 218680, "to": "mm"},
9353   "name": "PA_PH_PERFCOUNTER7_LO"
9354  },
9355  {
9356   "chips": ["gfx103"],
9357   "map": {"at": 218684, "to": "mm"},
9358   "name": "PA_PH_PERFCOUNTER7_HI"
9359  },
9360  {
9361   "chips": ["gfx103"],
9362   "map": {"at": 218880, "to": "mm"},
9363   "name": "GL1A_PERFCOUNTER0_LO"
9364  },
9365  {
9366   "chips": ["gfx103"],
9367   "map": {"at": 218884, "to": "mm"},
9368   "name": "GL1A_PERFCOUNTER0_HI"
9369  },
9370  {
9371   "chips": ["gfx103"],
9372   "map": {"at": 218888, "to": "mm"},
9373   "name": "GL1A_PERFCOUNTER1_LO"
9374  },
9375  {
9376   "chips": ["gfx103"],
9377   "map": {"at": 218892, "to": "mm"},
9378   "name": "GL1A_PERFCOUNTER1_HI"
9379  },
9380  {
9381   "chips": ["gfx103"],
9382   "map": {"at": 218896, "to": "mm"},
9383   "name": "GL1A_PERFCOUNTER2_LO"
9384  },
9385  {
9386   "chips": ["gfx103"],
9387   "map": {"at": 218900, "to": "mm"},
9388   "name": "GL1A_PERFCOUNTER2_HI"
9389  },
9390  {
9391   "chips": ["gfx103"],
9392   "map": {"at": 218904, "to": "mm"},
9393   "name": "GL1A_PERFCOUNTER3_LO"
9394  },
9395  {
9396   "chips": ["gfx103"],
9397   "map": {"at": 218908, "to": "mm"},
9398   "name": "GL1A_PERFCOUNTER3_HI"
9399  },
9400  {
9401   "chips": ["gfx103"],
9402   "map": {"at": 219136, "to": "mm"},
9403   "name": "CHA_PERFCOUNTER0_LO"
9404  },
9405  {
9406   "chips": ["gfx103"],
9407   "map": {"at": 219140, "to": "mm"},
9408   "name": "CHA_PERFCOUNTER0_HI"
9409  },
9410  {
9411   "chips": ["gfx103"],
9412   "map": {"at": 219144, "to": "mm"},
9413   "name": "CHA_PERFCOUNTER1_LO"
9414  },
9415  {
9416   "chips": ["gfx103"],
9417   "map": {"at": 219148, "to": "mm"},
9418   "name": "CHA_PERFCOUNTER1_HI"
9419  },
9420  {
9421   "chips": ["gfx103"],
9422   "map": {"at": 219152, "to": "mm"},
9423   "name": "CHA_PERFCOUNTER2_LO"
9424  },
9425  {
9426   "chips": ["gfx103"],
9427   "map": {"at": 219156, "to": "mm"},
9428   "name": "CHA_PERFCOUNTER2_HI"
9429  },
9430  {
9431   "chips": ["gfx103"],
9432   "map": {"at": 219160, "to": "mm"},
9433   "name": "CHA_PERFCOUNTER3_LO"
9434  },
9435  {
9436   "chips": ["gfx103"],
9437   "map": {"at": 219164, "to": "mm"},
9438   "name": "CHA_PERFCOUNTER3_HI"
9439  },
9440  {
9441   "chips": ["gfx103"],
9442   "map": {"at": 219392, "to": "mm"},
9443   "name": "GUS_PERFCOUNTER2_LO"
9444  },
9445  {
9446   "chips": ["gfx103"],
9447   "map": {"at": 219396, "to": "mm"},
9448   "name": "GUS_PERFCOUNTER2_HI"
9449  },
9450  {
9451   "chips": ["gfx103"],
9452   "map": {"at": 219400, "to": "mm"},
9453   "name": "GUS_PERFCOUNTER_LO"
9454  },
9455  {
9456   "chips": ["gfx103"],
9457   "map": {"at": 219404, "to": "mm"},
9458   "name": "GUS_PERFCOUNTER_HI",
9459   "type_ref": "GCEA_PERFCOUNTER_HI"
9460  },
9461  {
9462   "chips": ["gfx103"],
9463   "map": {"at": 219520, "to": "mm"},
9464   "name": "SDMA0_PERFCNT_PERFCOUNTER_LO"
9465  },
9466  {
9467   "chips": ["gfx103"],
9468   "map": {"at": 219524, "to": "mm"},
9469   "name": "SDMA0_PERFCNT_PERFCOUNTER_HI",
9470   "type_ref": "GCEA_PERFCOUNTER_HI"
9471  },
9472  {
9473   "chips": ["gfx103"],
9474   "map": {"at": 219528, "to": "mm"},
9475   "name": "SDMA0_PERFCOUNTER0_LO"
9476  },
9477  {
9478   "chips": ["gfx103"],
9479   "map": {"at": 219532, "to": "mm"},
9480   "name": "SDMA0_PERFCOUNTER0_HI"
9481  },
9482  {
9483   "chips": ["gfx103"],
9484   "map": {"at": 219536, "to": "mm"},
9485   "name": "SDMA0_PERFCOUNTER1_LO"
9486  },
9487  {
9488   "chips": ["gfx103"],
9489   "map": {"at": 219540, "to": "mm"},
9490   "name": "SDMA0_PERFCOUNTER1_HI"
9491  },
9492  {
9493   "chips": ["gfx103"],
9494   "map": {"at": 219568, "to": "mm"},
9495   "name": "SDMA1_PERFCNT_PERFCOUNTER_LO"
9496  },
9497  {
9498   "chips": ["gfx103"],
9499   "map": {"at": 219572, "to": "mm"},
9500   "name": "SDMA1_PERFCNT_PERFCOUNTER_HI",
9501   "type_ref": "GCEA_PERFCOUNTER_HI"
9502  },
9503  {
9504   "chips": ["gfx103"],
9505   "map": {"at": 219576, "to": "mm"},
9506   "name": "SDMA1_PERFCOUNTER0_LO"
9507  },
9508  {
9509   "chips": ["gfx103"],
9510   "map": {"at": 219580, "to": "mm"},
9511   "name": "SDMA1_PERFCOUNTER0_HI"
9512  },
9513  {
9514   "chips": ["gfx103"],
9515   "map": {"at": 219584, "to": "mm"},
9516   "name": "SDMA1_PERFCOUNTER1_LO"
9517  },
9518  {
9519   "chips": ["gfx103"],
9520   "map": {"at": 219588, "to": "mm"},
9521   "name": "SDMA1_PERFCOUNTER1_HI"
9522  },
9523  {
9524   "chips": ["gfx103"],
9525   "map": {"at": 219616, "to": "mm"},
9526   "name": "SDMA2_PERFCNT_PERFCOUNTER_LO"
9527  },
9528  {
9529   "chips": ["gfx103"],
9530   "map": {"at": 219620, "to": "mm"},
9531   "name": "SDMA2_PERFCNT_PERFCOUNTER_HI",
9532   "type_ref": "GCEA_PERFCOUNTER_HI"
9533  },
9534  {
9535   "chips": ["gfx103"],
9536   "map": {"at": 219624, "to": "mm"},
9537   "name": "SDMA2_PERFCOUNTER0_LO"
9538  },
9539  {
9540   "chips": ["gfx103"],
9541   "map": {"at": 219628, "to": "mm"},
9542   "name": "SDMA2_PERFCOUNTER0_HI"
9543  },
9544  {
9545   "chips": ["gfx103"],
9546   "map": {"at": 219632, "to": "mm"},
9547   "name": "SDMA2_PERFCOUNTER1_LO"
9548  },
9549  {
9550   "chips": ["gfx103"],
9551   "map": {"at": 219636, "to": "mm"},
9552   "name": "SDMA2_PERFCOUNTER1_HI"
9553  },
9554  {
9555   "chips": ["gfx103"],
9556   "map": {"at": 219664, "to": "mm"},
9557   "name": "SDMA3_PERFCNT_PERFCOUNTER_LO"
9558  },
9559  {
9560   "chips": ["gfx103"],
9561   "map": {"at": 219668, "to": "mm"},
9562   "name": "SDMA3_PERFCNT_PERFCOUNTER_HI",
9563   "type_ref": "GCEA_PERFCOUNTER_HI"
9564  },
9565  {
9566   "chips": ["gfx103"],
9567   "map": {"at": 219672, "to": "mm"},
9568   "name": "SDMA3_PERFCOUNTER0_LO"
9569  },
9570  {
9571   "chips": ["gfx103"],
9572   "map": {"at": 219676, "to": "mm"},
9573   "name": "SDMA3_PERFCOUNTER0_HI"
9574  },
9575  {
9576   "chips": ["gfx103"],
9577   "map": {"at": 219680, "to": "mm"},
9578   "name": "SDMA3_PERFCOUNTER1_LO"
9579  },
9580  {
9581   "chips": ["gfx103"],
9582   "map": {"at": 219684, "to": "mm"},
9583   "name": "SDMA3_PERFCOUNTER1_HI"
9584  },
9585  {
9586   "chips": ["gfx103"],
9587   "map": {"at": 221184, "to": "mm"},
9588   "name": "CPG_PERFCOUNTER1_SELECT",
9589   "type_ref": "CPG_PERFCOUNTER1_SELECT"
9590  },
9591  {
9592   "chips": ["gfx103"],
9593   "map": {"at": 221188, "to": "mm"},
9594   "name": "CPG_PERFCOUNTER0_SELECT1",
9595   "type_ref": "CPG_PERFCOUNTER0_SELECT1"
9596  },
9597  {
9598   "chips": ["gfx103"],
9599   "map": {"at": 221192, "to": "mm"},
9600   "name": "CPG_PERFCOUNTER0_SELECT",
9601   "type_ref": "CPG_PERFCOUNTER1_SELECT"
9602  },
9603  {
9604   "chips": ["gfx103"],
9605   "map": {"at": 221196, "to": "mm"},
9606   "name": "CPC_PERFCOUNTER1_SELECT",
9607   "type_ref": "CPG_PERFCOUNTER1_SELECT"
9608  },
9609  {
9610   "chips": ["gfx103"],
9611   "map": {"at": 221200, "to": "mm"},
9612   "name": "CPC_PERFCOUNTER0_SELECT1",
9613   "type_ref": "CPG_PERFCOUNTER0_SELECT1"
9614  },
9615  {
9616   "chips": ["gfx103"],
9617   "map": {"at": 221204, "to": "mm"},
9618   "name": "CPF_PERFCOUNTER1_SELECT",
9619   "type_ref": "CPG_PERFCOUNTER1_SELECT"
9620  },
9621  {
9622   "chips": ["gfx103"],
9623   "map": {"at": 221208, "to": "mm"},
9624   "name": "CPF_PERFCOUNTER0_SELECT1",
9625   "type_ref": "CPG_PERFCOUNTER0_SELECT1"
9626  },
9627  {
9628   "chips": ["gfx103"],
9629   "map": {"at": 221212, "to": "mm"},
9630   "name": "CPF_PERFCOUNTER0_SELECT",
9631   "type_ref": "CPG_PERFCOUNTER1_SELECT"
9632  },
9633  {
9634   "chips": ["gfx103"],
9635   "map": {"at": 221216, "to": "mm"},
9636   "name": "CP_PERFMON_CNTL",
9637   "type_ref": "CP_PERFMON_CNTL"
9638  },
9639  {
9640   "chips": ["gfx103"],
9641   "map": {"at": 221220, "to": "mm"},
9642   "name": "CPC_PERFCOUNTER0_SELECT",
9643   "type_ref": "CPG_PERFCOUNTER1_SELECT"
9644  },
9645  {
9646   "chips": ["gfx103"],
9647   "map": {"at": 221224, "to": "mm"},
9648   "name": "CPF_TC_PERF_COUNTER_WINDOW_SELECT",
9649   "type_ref": "CPF_TC_PERF_COUNTER_WINDOW_SELECT"
9650  },
9651  {
9652   "chips": ["gfx103"],
9653   "map": {"at": 221228, "to": "mm"},
9654   "name": "CPG_TC_PERF_COUNTER_WINDOW_SELECT",
9655   "type_ref": "CPG_TC_PERF_COUNTER_WINDOW_SELECT"
9656  },
9657  {
9658   "chips": ["gfx103"],
9659   "map": {"at": 221232, "to": "mm"},
9660   "name": "CPF_LATENCY_STATS_SELECT",
9661   "type_ref": "CPF_LATENCY_STATS_SELECT"
9662  },
9663  {
9664   "chips": ["gfx103"],
9665   "map": {"at": 221236, "to": "mm"},
9666   "name": "CPG_LATENCY_STATS_SELECT",
9667   "type_ref": "CPG_LATENCY_STATS_SELECT"
9668  },
9669  {
9670   "chips": ["gfx103"],
9671   "map": {"at": 221240, "to": "mm"},
9672   "name": "CPC_LATENCY_STATS_SELECT",
9673   "type_ref": "CPF_LATENCY_STATS_SELECT"
9674  },
9675  {
9676   "chips": ["gfx103"],
9677   "map": {"at": 221248, "to": "mm"},
9678   "name": "CP_DRAW_OBJECT"
9679  },
9680  {
9681   "chips": ["gfx103"],
9682   "map": {"at": 221252, "to": "mm"},
9683   "name": "CP_DRAW_OBJECT_COUNTER",
9684   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
9685  },
9686  {
9687   "chips": ["gfx103"],
9688   "map": {"at": 221256, "to": "mm"},
9689   "name": "CP_DRAW_WINDOW_MASK_HI"
9690  },
9691  {
9692   "chips": ["gfx103"],
9693   "map": {"at": 221260, "to": "mm"},
9694   "name": "CP_DRAW_WINDOW_HI"
9695  },
9696  {
9697   "chips": ["gfx103"],
9698   "map": {"at": 221264, "to": "mm"},
9699   "name": "CP_DRAW_WINDOW_LO",
9700   "type_ref": "CP_DRAW_WINDOW_LO"
9701  },
9702  {
9703   "chips": ["gfx103"],
9704   "map": {"at": 221268, "to": "mm"},
9705   "name": "CP_DRAW_WINDOW_CNTL",
9706   "type_ref": "CP_DRAW_WINDOW_CNTL"
9707  },
9708  {
9709   "chips": ["gfx103"],
9710   "map": {"at": 221440, "to": "mm"},
9711   "name": "GRBM_PERFCOUNTER0_SELECT",
9712   "type_ref": "GRBM_PERFCOUNTER0_SELECT"
9713  },
9714  {
9715   "chips": ["gfx103"],
9716   "map": {"at": 221444, "to": "mm"},
9717   "name": "GRBM_PERFCOUNTER1_SELECT",
9718   "type_ref": "GRBM_PERFCOUNTER0_SELECT"
9719  },
9720  {
9721   "chips": ["gfx103"],
9722   "map": {"at": 221448, "to": "mm"},
9723   "name": "GRBM_SE0_PERFCOUNTER_SELECT",
9724   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
9725  },
9726  {
9727   "chips": ["gfx103"],
9728   "map": {"at": 221452, "to": "mm"},
9729   "name": "GRBM_SE1_PERFCOUNTER_SELECT",
9730   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
9731  },
9732  {
9733   "chips": ["gfx103"],
9734   "map": {"at": 221456, "to": "mm"},
9735   "name": "GRBM_SE2_PERFCOUNTER_SELECT",
9736   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
9737  },
9738  {
9739   "chips": ["gfx103"],
9740   "map": {"at": 221460, "to": "mm"},
9741   "name": "GRBM_SE3_PERFCOUNTER_SELECT",
9742   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
9743  },
9744  {
9745   "chips": ["gfx103"],
9746   "map": {"at": 221492, "to": "mm"},
9747   "name": "GRBM_PERFCOUNTER0_SELECT_HI",
9748   "type_ref": "GRBM_PERFCOUNTER0_SELECT_HI"
9749  },
9750  {
9751   "chips": ["gfx103"],
9752   "map": {"at": 221496, "to": "mm"},
9753   "name": "GRBM_PERFCOUNTER1_SELECT_HI",
9754   "type_ref": "GRBM_PERFCOUNTER0_SELECT_HI"
9755  },
9756  {
9757   "chips": ["gfx103"],
9758   "map": {"at": 221840, "to": "mm"},
9759   "name": "GE1_PERFCOUNTER0_SELECT",
9760   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9761  },
9762  {
9763   "chips": ["gfx103"],
9764   "map": {"at": 221844, "to": "mm"},
9765   "name": "GE1_PERFCOUNTER0_SELECT1",
9766   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
9767  },
9768  {
9769   "chips": ["gfx103"],
9770   "map": {"at": 221848, "to": "mm"},
9771   "name": "GE1_PERFCOUNTER1_SELECT",
9772   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9773  },
9774  {
9775   "chips": ["gfx103"],
9776   "map": {"at": 221852, "to": "mm"},
9777   "name": "GE1_PERFCOUNTER1_SELECT1",
9778   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
9779  },
9780  {
9781   "chips": ["gfx103"],
9782   "map": {"at": 221856, "to": "mm"},
9783   "name": "GE1_PERFCOUNTER2_SELECT",
9784   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9785  },
9786  {
9787   "chips": ["gfx103"],
9788   "map": {"at": 221860, "to": "mm"},
9789   "name": "GE1_PERFCOUNTER2_SELECT1",
9790   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
9791  },
9792  {
9793   "chips": ["gfx103"],
9794   "map": {"at": 221864, "to": "mm"},
9795   "name": "GE1_PERFCOUNTER3_SELECT",
9796   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9797  },
9798  {
9799   "chips": ["gfx103"],
9800   "map": {"at": 221868, "to": "mm"},
9801   "name": "GE1_PERFCOUNTER3_SELECT1",
9802   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
9803  },
9804  {
9805   "chips": ["gfx103"],
9806   "map": {"at": 221872, "to": "mm"},
9807   "name": "GE2_DIST_PERFCOUNTER0_SELECT",
9808   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9809  },
9810  {
9811   "chips": ["gfx103"],
9812   "map": {"at": 221876, "to": "mm"},
9813   "name": "GE2_DIST_PERFCOUNTER0_SELECT1",
9814   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
9815  },
9816  {
9817   "chips": ["gfx103"],
9818   "map": {"at": 221880, "to": "mm"},
9819   "name": "GE2_DIST_PERFCOUNTER1_SELECT",
9820   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9821  },
9822  {
9823   "chips": ["gfx103"],
9824   "map": {"at": 221884, "to": "mm"},
9825   "name": "GE2_DIST_PERFCOUNTER1_SELECT1",
9826   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
9827  },
9828  {
9829   "chips": ["gfx103"],
9830   "map": {"at": 221888, "to": "mm"},
9831   "name": "GE2_DIST_PERFCOUNTER2_SELECT",
9832   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9833  },
9834  {
9835   "chips": ["gfx103"],
9836   "map": {"at": 221892, "to": "mm"},
9837   "name": "GE2_DIST_PERFCOUNTER2_SELECT1",
9838   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
9839  },
9840  {
9841   "chips": ["gfx103"],
9842   "map": {"at": 221896, "to": "mm"},
9843   "name": "GE2_DIST_PERFCOUNTER3_SELECT",
9844   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9845  },
9846  {
9847   "chips": ["gfx103"],
9848   "map": {"at": 221900, "to": "mm"},
9849   "name": "GE2_DIST_PERFCOUNTER3_SELECT1",
9850   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
9851  },
9852  {
9853   "chips": ["gfx103"],
9854   "map": {"at": 221904, "to": "mm"},
9855   "name": "GE2_SE_PERFCOUNTER0_SELECT",
9856   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9857  },
9858  {
9859   "chips": ["gfx103"],
9860   "map": {"at": 221908, "to": "mm"},
9861   "name": "GE2_SE_PERFCOUNTER0_SELECT1",
9862   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
9863  },
9864  {
9865   "chips": ["gfx103"],
9866   "map": {"at": 221912, "to": "mm"},
9867   "name": "GE2_SE_PERFCOUNTER1_SELECT",
9868   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9869  },
9870  {
9871   "chips": ["gfx103"],
9872   "map": {"at": 221916, "to": "mm"},
9873   "name": "GE2_SE_PERFCOUNTER1_SELECT1",
9874   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
9875  },
9876  {
9877   "chips": ["gfx103"],
9878   "map": {"at": 221920, "to": "mm"},
9879   "name": "GE2_SE_PERFCOUNTER2_SELECT",
9880   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9881  },
9882  {
9883   "chips": ["gfx103"],
9884   "map": {"at": 221924, "to": "mm"},
9885   "name": "GE2_SE_PERFCOUNTER2_SELECT1",
9886   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
9887  },
9888  {
9889   "chips": ["gfx103"],
9890   "map": {"at": 221928, "to": "mm"},
9891   "name": "GE2_SE_PERFCOUNTER3_SELECT",
9892   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9893  },
9894  {
9895   "chips": ["gfx103"],
9896   "map": {"at": 221932, "to": "mm"},
9897   "name": "GE2_SE_PERFCOUNTER3_SELECT1",
9898   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
9899  },
9900  {
9901   "chips": ["gfx103"],
9902   "map": {"at": 222208, "to": "mm"},
9903   "name": "PA_SU_PERFCOUNTER0_SELECT",
9904   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
9905  },
9906  {
9907   "chips": ["gfx103"],
9908   "map": {"at": 222212, "to": "mm"},
9909   "name": "PA_SU_PERFCOUNTER0_SELECT1",
9910   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
9911  },
9912  {
9913   "chips": ["gfx103"],
9914   "map": {"at": 222216, "to": "mm"},
9915   "name": "PA_SU_PERFCOUNTER1_SELECT",
9916   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
9917  },
9918  {
9919   "chips": ["gfx103"],
9920   "map": {"at": 222220, "to": "mm"},
9921   "name": "PA_SU_PERFCOUNTER1_SELECT1",
9922   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
9923  },
9924  {
9925   "chips": ["gfx103"],
9926   "map": {"at": 222224, "to": "mm"},
9927   "name": "PA_SU_PERFCOUNTER2_SELECT",
9928   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
9929  },
9930  {
9931   "chips": ["gfx103"],
9932   "map": {"at": 222228, "to": "mm"},
9933   "name": "PA_SU_PERFCOUNTER2_SELECT1",
9934   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
9935  },
9936  {
9937   "chips": ["gfx103"],
9938   "map": {"at": 222232, "to": "mm"},
9939   "name": "PA_SU_PERFCOUNTER3_SELECT",
9940   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
9941  },
9942  {
9943   "chips": ["gfx103"],
9944   "map": {"at": 222236, "to": "mm"},
9945   "name": "PA_SU_PERFCOUNTER3_SELECT1",
9946   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
9947  },
9948  {
9949   "chips": ["gfx103"],
9950   "map": {"at": 222464, "to": "mm"},
9951   "name": "PA_SC_PERFCOUNTER0_SELECT",
9952   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
9953  },
9954  {
9955   "chips": ["gfx103"],
9956   "map": {"at": 222468, "to": "mm"},
9957   "name": "PA_SC_PERFCOUNTER0_SELECT1",
9958   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
9959  },
9960  {
9961   "chips": ["gfx103"],
9962   "map": {"at": 222472, "to": "mm"},
9963   "name": "PA_SC_PERFCOUNTER1_SELECT",
9964   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9965  },
9966  {
9967   "chips": ["gfx103"],
9968   "map": {"at": 222476, "to": "mm"},
9969   "name": "PA_SC_PERFCOUNTER2_SELECT",
9970   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9971  },
9972  {
9973   "chips": ["gfx103"],
9974   "map": {"at": 222480, "to": "mm"},
9975   "name": "PA_SC_PERFCOUNTER3_SELECT",
9976   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9977  },
9978  {
9979   "chips": ["gfx103"],
9980   "map": {"at": 222484, "to": "mm"},
9981   "name": "PA_SC_PERFCOUNTER4_SELECT",
9982   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9983  },
9984  {
9985   "chips": ["gfx103"],
9986   "map": {"at": 222488, "to": "mm"},
9987   "name": "PA_SC_PERFCOUNTER5_SELECT",
9988   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9989  },
9990  {
9991   "chips": ["gfx103"],
9992   "map": {"at": 222492, "to": "mm"},
9993   "name": "PA_SC_PERFCOUNTER6_SELECT",
9994   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9995  },
9996  {
9997   "chips": ["gfx103"],
9998   "map": {"at": 222496, "to": "mm"},
9999   "name": "PA_SC_PERFCOUNTER7_SELECT",
10000   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
10001  },
10002  {
10003   "chips": ["gfx103"],
10004   "map": {"at": 222720, "to": "mm"},
10005   "name": "SPI_PERFCOUNTER0_SELECT",
10006   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10007  },
10008  {
10009   "chips": ["gfx103"],
10010   "map": {"at": 222724, "to": "mm"},
10011   "name": "SPI_PERFCOUNTER1_SELECT",
10012   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10013  },
10014  {
10015   "chips": ["gfx103"],
10016   "map": {"at": 222728, "to": "mm"},
10017   "name": "SPI_PERFCOUNTER2_SELECT",
10018   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10019  },
10020  {
10021   "chips": ["gfx103"],
10022   "map": {"at": 222732, "to": "mm"},
10023   "name": "SPI_PERFCOUNTER3_SELECT",
10024   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10025  },
10026  {
10027   "chips": ["gfx103"],
10028   "map": {"at": 222736, "to": "mm"},
10029   "name": "SPI_PERFCOUNTER0_SELECT1",
10030   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10031  },
10032  {
10033   "chips": ["gfx103"],
10034   "map": {"at": 222740, "to": "mm"},
10035   "name": "SPI_PERFCOUNTER1_SELECT1",
10036   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10037  },
10038  {
10039   "chips": ["gfx103"],
10040   "map": {"at": 222744, "to": "mm"},
10041   "name": "SPI_PERFCOUNTER2_SELECT1",
10042   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10043  },
10044  {
10045   "chips": ["gfx103"],
10046   "map": {"at": 222748, "to": "mm"},
10047   "name": "SPI_PERFCOUNTER3_SELECT1",
10048   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10049  },
10050  {
10051   "chips": ["gfx103"],
10052   "map": {"at": 222752, "to": "mm"},
10053   "name": "SPI_PERFCOUNTER4_SELECT",
10054   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
10055  },
10056  {
10057   "chips": ["gfx103"],
10058   "map": {"at": 222756, "to": "mm"},
10059   "name": "SPI_PERFCOUNTER5_SELECT",
10060   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
10061  },
10062  {
10063   "chips": ["gfx103"],
10064   "map": {"at": 222760, "to": "mm"},
10065   "name": "SPI_PERFCOUNTER_BINS",
10066   "type_ref": "SPI_PERFCOUNTER_BINS"
10067  },
10068  {
10069   "chips": ["gfx103"],
10070   "map": {"at": 222976, "to": "mm"},
10071   "name": "SQ_PERFCOUNTER0_SELECT",
10072   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10073  },
10074  {
10075   "chips": ["gfx103"],
10076   "map": {"at": 222980, "to": "mm"},
10077   "name": "SQ_PERFCOUNTER1_SELECT",
10078   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10079  },
10080  {
10081   "chips": ["gfx103"],
10082   "map": {"at": 222984, "to": "mm"},
10083   "name": "SQ_PERFCOUNTER2_SELECT",
10084   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10085  },
10086  {
10087   "chips": ["gfx103"],
10088   "map": {"at": 222988, "to": "mm"},
10089   "name": "SQ_PERFCOUNTER3_SELECT",
10090   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10091  },
10092  {
10093   "chips": ["gfx103"],
10094   "map": {"at": 222992, "to": "mm"},
10095   "name": "SQ_PERFCOUNTER4_SELECT",
10096   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10097  },
10098  {
10099   "chips": ["gfx103"],
10100   "map": {"at": 222996, "to": "mm"},
10101   "name": "SQ_PERFCOUNTER5_SELECT",
10102   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10103  },
10104  {
10105   "chips": ["gfx103"],
10106   "map": {"at": 223000, "to": "mm"},
10107   "name": "SQ_PERFCOUNTER6_SELECT",
10108   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10109  },
10110  {
10111   "chips": ["gfx103"],
10112   "map": {"at": 223004, "to": "mm"},
10113   "name": "SQ_PERFCOUNTER7_SELECT",
10114   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10115  },
10116  {
10117   "chips": ["gfx103"],
10118   "map": {"at": 223008, "to": "mm"},
10119   "name": "SQ_PERFCOUNTER8_SELECT",
10120   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10121  },
10122  {
10123   "chips": ["gfx103"],
10124   "map": {"at": 223012, "to": "mm"},
10125   "name": "SQ_PERFCOUNTER9_SELECT",
10126   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10127  },
10128  {
10129   "chips": ["gfx103"],
10130   "map": {"at": 223016, "to": "mm"},
10131   "name": "SQ_PERFCOUNTER10_SELECT",
10132   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10133  },
10134  {
10135   "chips": ["gfx103"],
10136   "map": {"at": 223020, "to": "mm"},
10137   "name": "SQ_PERFCOUNTER11_SELECT",
10138   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10139  },
10140  {
10141   "chips": ["gfx103"],
10142   "map": {"at": 223024, "to": "mm"},
10143   "name": "SQ_PERFCOUNTER12_SELECT",
10144   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10145  },
10146  {
10147   "chips": ["gfx103"],
10148   "map": {"at": 223028, "to": "mm"},
10149   "name": "SQ_PERFCOUNTER13_SELECT",
10150   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10151  },
10152  {
10153   "chips": ["gfx103"],
10154   "map": {"at": 223032, "to": "mm"},
10155   "name": "SQ_PERFCOUNTER14_SELECT",
10156   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10157  },
10158  {
10159   "chips": ["gfx103"],
10160   "map": {"at": 223036, "to": "mm"},
10161   "name": "SQ_PERFCOUNTER15_SELECT",
10162   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10163  },
10164  {
10165   "chips": ["gfx103"],
10166   "map": {"at": 223104, "to": "mm"},
10167   "name": "SQ_PERFCOUNTER_CTRL",
10168   "type_ref": "SQ_PERFCOUNTER_CTRL"
10169  },
10170  {
10171   "chips": ["gfx103"],
10172   "map": {"at": 223112, "to": "mm"},
10173   "name": "SQ_PERFCOUNTER_CTRL2",
10174   "type_ref": "SQ_PERFCOUNTER_CTRL2"
10175  },
10176  {
10177   "chips": ["gfx103"],
10178   "map": {"at": 223232, "to": "mm"},
10179   "name": "GCEA_PERFCOUNTER2_SELECT",
10180   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10181  },
10182  {
10183   "chips": ["gfx103"],
10184   "map": {"at": 223236, "to": "mm"},
10185   "name": "GCEA_PERFCOUNTER2_SELECT1",
10186   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10187  },
10188  {
10189   "chips": ["gfx103"],
10190   "map": {"at": 223240, "to": "mm"},
10191   "name": "GCEA_PERFCOUNTER2_MODE",
10192   "type_ref": "GCEA_PERFCOUNTER2_MODE"
10193  },
10194  {
10195   "chips": ["gfx103"],
10196   "map": {"at": 223244, "to": "mm"},
10197   "name": "GCEA_PERFCOUNTER0_CFG",
10198   "type_ref": "GCEA_PERFCOUNTER0_CFG"
10199  },
10200  {
10201   "chips": ["gfx103"],
10202   "map": {"at": 223248, "to": "mm"},
10203   "name": "GCEA_PERFCOUNTER1_CFG",
10204   "type_ref": "GCEA_PERFCOUNTER0_CFG"
10205  },
10206  {
10207   "chips": ["gfx103"],
10208   "map": {"at": 223252, "to": "mm"},
10209   "name": "GCEA_PERFCOUNTER_RSLT_CNTL",
10210   "type_ref": "GCEA_PERFCOUNTER_RSLT_CNTL"
10211  },
10212  {
10213   "chips": ["gfx103"],
10214   "map": {"at": 223488, "to": "mm"},
10215   "name": "SX_PERFCOUNTER0_SELECT",
10216   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10217  },
10218  {
10219   "chips": ["gfx103"],
10220   "map": {"at": 223492, "to": "mm"},
10221   "name": "SX_PERFCOUNTER1_SELECT",
10222   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10223  },
10224  {
10225   "chips": ["gfx103"],
10226   "map": {"at": 223496, "to": "mm"},
10227   "name": "SX_PERFCOUNTER2_SELECT",
10228   "type_ref": "SX_PERFCOUNTER2_SELECT"
10229  },
10230  {
10231   "chips": ["gfx103"],
10232   "map": {"at": 223500, "to": "mm"},
10233   "name": "SX_PERFCOUNTER3_SELECT",
10234   "type_ref": "SX_PERFCOUNTER2_SELECT"
10235  },
10236  {
10237   "chips": ["gfx103"],
10238   "map": {"at": 223504, "to": "mm"},
10239   "name": "SX_PERFCOUNTER0_SELECT1",
10240   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10241  },
10242  {
10243   "chips": ["gfx103"],
10244   "map": {"at": 223508, "to": "mm"},
10245   "name": "SX_PERFCOUNTER1_SELECT1",
10246   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10247  },
10248  {
10249   "chips": ["gfx103"],
10250   "map": {"at": 223744, "to": "mm"},
10251   "name": "GDS_PERFCOUNTER0_SELECT",
10252   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10253  },
10254  {
10255   "chips": ["gfx103"],
10256   "map": {"at": 223748, "to": "mm"},
10257   "name": "GDS_PERFCOUNTER1_SELECT",
10258   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10259  },
10260  {
10261   "chips": ["gfx103"],
10262   "map": {"at": 223752, "to": "mm"},
10263   "name": "GDS_PERFCOUNTER2_SELECT",
10264   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10265  },
10266  {
10267   "chips": ["gfx103"],
10268   "map": {"at": 223756, "to": "mm"},
10269   "name": "GDS_PERFCOUNTER3_SELECT",
10270   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10271  },
10272  {
10273   "chips": ["gfx103"],
10274   "map": {"at": 223760, "to": "mm"},
10275   "name": "GDS_PERFCOUNTER0_SELECT1",
10276   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10277  },
10278  {
10279   "chips": ["gfx103"],
10280   "map": {"at": 223764, "to": "mm"},
10281   "name": "GDS_PERFCOUNTER1_SELECT1",
10282   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10283  },
10284  {
10285   "chips": ["gfx103"],
10286   "map": {"at": 223768, "to": "mm"},
10287   "name": "GDS_PERFCOUNTER2_SELECT1",
10288   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10289  },
10290  {
10291   "chips": ["gfx103"],
10292   "map": {"at": 223772, "to": "mm"},
10293   "name": "GDS_PERFCOUNTER3_SELECT1",
10294   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10295  },
10296  {
10297   "chips": ["gfx103"],
10298   "map": {"at": 224000, "to": "mm"},
10299   "name": "TA_PERFCOUNTER0_SELECT",
10300   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10301  },
10302  {
10303   "chips": ["gfx103"],
10304   "map": {"at": 224004, "to": "mm"},
10305   "name": "TA_PERFCOUNTER0_SELECT1",
10306   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10307  },
10308  {
10309   "chips": ["gfx103"],
10310   "map": {"at": 224008, "to": "mm"},
10311   "name": "TA_PERFCOUNTER1_SELECT",
10312   "type_ref": "SX_PERFCOUNTER2_SELECT"
10313  },
10314  {
10315   "chips": ["gfx103"],
10316   "map": {"at": 224256, "to": "mm"},
10317   "name": "TD_PERFCOUNTER0_SELECT",
10318   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10319  },
10320  {
10321   "chips": ["gfx103"],
10322   "map": {"at": 224260, "to": "mm"},
10323   "name": "TD_PERFCOUNTER0_SELECT1",
10324   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10325  },
10326  {
10327   "chips": ["gfx103"],
10328   "map": {"at": 224264, "to": "mm"},
10329   "name": "TD_PERFCOUNTER1_SELECT",
10330   "type_ref": "SX_PERFCOUNTER2_SELECT"
10331  },
10332  {
10333   "chips": ["gfx103"],
10334   "map": {"at": 224512, "to": "mm"},
10335   "name": "TCP_PERFCOUNTER0_SELECT",
10336   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10337  },
10338  {
10339   "chips": ["gfx103"],
10340   "map": {"at": 224516, "to": "mm"},
10341   "name": "TCP_PERFCOUNTER0_SELECT1",
10342   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10343  },
10344  {
10345   "chips": ["gfx103"],
10346   "map": {"at": 224520, "to": "mm"},
10347   "name": "TCP_PERFCOUNTER1_SELECT",
10348   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10349  },
10350  {
10351   "chips": ["gfx103"],
10352   "map": {"at": 224524, "to": "mm"},
10353   "name": "TCP_PERFCOUNTER1_SELECT1",
10354   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10355  },
10356  {
10357   "chips": ["gfx103"],
10358   "map": {"at": 224528, "to": "mm"},
10359   "name": "TCP_PERFCOUNTER2_SELECT",
10360   "type_ref": "SX_PERFCOUNTER2_SELECT"
10361  },
10362  {
10363   "chips": ["gfx103"],
10364   "map": {"at": 224532, "to": "mm"},
10365   "name": "TCP_PERFCOUNTER3_SELECT",
10366   "type_ref": "SX_PERFCOUNTER2_SELECT"
10367  },
10368  {
10369   "chips": ["gfx103"],
10370   "map": {"at": 224768, "to": "mm"},
10371   "name": "GL2C_PERFCOUNTER0_SELECT",
10372   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10373  },
10374  {
10375   "chips": ["gfx103"],
10376   "map": {"at": 224772, "to": "mm"},
10377   "name": "GL2C_PERFCOUNTER0_SELECT1",
10378   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
10379  },
10380  {
10381   "chips": ["gfx103"],
10382   "map": {"at": 224776, "to": "mm"},
10383   "name": "GL2C_PERFCOUNTER1_SELECT",
10384   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10385  },
10386  {
10387   "chips": ["gfx103"],
10388   "map": {"at": 224780, "to": "mm"},
10389   "name": "GL2C_PERFCOUNTER1_SELECT1",
10390   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
10391  },
10392  {
10393   "chips": ["gfx103"],
10394   "map": {"at": 224784, "to": "mm"},
10395   "name": "GL2C_PERFCOUNTER2_SELECT",
10396   "type_ref": "SX_PERFCOUNTER2_SELECT"
10397  },
10398  {
10399   "chips": ["gfx103"],
10400   "map": {"at": 224788, "to": "mm"},
10401   "name": "GL2C_PERFCOUNTER3_SELECT",
10402   "type_ref": "SX_PERFCOUNTER2_SELECT"
10403  },
10404  {
10405   "chips": ["gfx103"],
10406   "map": {"at": 224832, "to": "mm"},
10407   "name": "GL2A_PERFCOUNTER0_SELECT",
10408   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10409  },
10410  {
10411   "chips": ["gfx103"],
10412   "map": {"at": 224836, "to": "mm"},
10413   "name": "GL2A_PERFCOUNTER0_SELECT1",
10414   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
10415  },
10416  {
10417   "chips": ["gfx103"],
10418   "map": {"at": 224840, "to": "mm"},
10419   "name": "GL2A_PERFCOUNTER1_SELECT",
10420   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10421  },
10422  {
10423   "chips": ["gfx103"],
10424   "map": {"at": 224844, "to": "mm"},
10425   "name": "GL2A_PERFCOUNTER1_SELECT1",
10426   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
10427  },
10428  {
10429   "chips": ["gfx103"],
10430   "map": {"at": 224848, "to": "mm"},
10431   "name": "GL2A_PERFCOUNTER2_SELECT",
10432   "type_ref": "SX_PERFCOUNTER2_SELECT"
10433  },
10434  {
10435   "chips": ["gfx103"],
10436   "map": {"at": 224852, "to": "mm"},
10437   "name": "GL2A_PERFCOUNTER3_SELECT",
10438   "type_ref": "SX_PERFCOUNTER2_SELECT"
10439  },
10440  {
10441   "chips": ["gfx103"],
10442   "map": {"at": 224896, "to": "mm"},
10443   "name": "GL1C_PERFCOUNTER0_SELECT",
10444   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10445  },
10446  {
10447   "chips": ["gfx103"],
10448   "map": {"at": 224900, "to": "mm"},
10449   "name": "GL1C_PERFCOUNTER0_SELECT1",
10450   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
10451  },
10452  {
10453   "chips": ["gfx103"],
10454   "map": {"at": 224904, "to": "mm"},
10455   "name": "GL1C_PERFCOUNTER1_SELECT",
10456   "type_ref": "SX_PERFCOUNTER2_SELECT"
10457  },
10458  {
10459   "chips": ["gfx103"],
10460   "map": {"at": 224908, "to": "mm"},
10461   "name": "GL1C_PERFCOUNTER2_SELECT",
10462   "type_ref": "SX_PERFCOUNTER2_SELECT"
10463  },
10464  {
10465   "chips": ["gfx103"],
10466   "map": {"at": 224912, "to": "mm"},
10467   "name": "GL1C_PERFCOUNTER3_SELECT",
10468   "type_ref": "SX_PERFCOUNTER2_SELECT"
10469  },
10470  {
10471   "chips": ["gfx103"],
10472   "map": {"at": 225024, "to": "mm"},
10473   "name": "CHC_PERFCOUNTER0_SELECT",
10474   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10475  },
10476  {
10477   "chips": ["gfx103"],
10478   "map": {"at": 225028, "to": "mm"},
10479   "name": "CHC_PERFCOUNTER0_SELECT1",
10480   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
10481  },
10482  {
10483   "chips": ["gfx103"],
10484   "map": {"at": 225032, "to": "mm"},
10485   "name": "CHC_PERFCOUNTER1_SELECT",
10486   "type_ref": "SX_PERFCOUNTER2_SELECT"
10487  },
10488  {
10489   "chips": ["gfx103"],
10490   "map": {"at": 225036, "to": "mm"},
10491   "name": "CHC_PERFCOUNTER2_SELECT",
10492   "type_ref": "SX_PERFCOUNTER2_SELECT"
10493  },
10494  {
10495   "chips": ["gfx103"],
10496   "map": {"at": 225040, "to": "mm"},
10497   "name": "CHC_PERFCOUNTER3_SELECT",
10498   "type_ref": "SX_PERFCOUNTER2_SELECT"
10499  },
10500  {
10501   "chips": ["gfx103"],
10502   "map": {"at": 225048, "to": "mm"},
10503   "name": "CHCG_PERFCOUNTER0_SELECT",
10504   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10505  },
10506  {
10507   "chips": ["gfx103"],
10508   "map": {"at": 225052, "to": "mm"},
10509   "name": "CHCG_PERFCOUNTER0_SELECT1",
10510   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
10511  },
10512  {
10513   "chips": ["gfx103"],
10514   "map": {"at": 225056, "to": "mm"},
10515   "name": "CHCG_PERFCOUNTER1_SELECT",
10516   "type_ref": "SX_PERFCOUNTER2_SELECT"
10517  },
10518  {
10519   "chips": ["gfx103"],
10520   "map": {"at": 225060, "to": "mm"},
10521   "name": "CHCG_PERFCOUNTER2_SELECT",
10522   "type_ref": "SX_PERFCOUNTER2_SELECT"
10523  },
10524  {
10525   "chips": ["gfx103"],
10526   "map": {"at": 225064, "to": "mm"},
10527   "name": "CHCG_PERFCOUNTER3_SELECT",
10528   "type_ref": "SX_PERFCOUNTER2_SELECT"
10529  },
10530  {
10531   "chips": ["gfx103"],
10532   "map": {"at": 225280, "to": "mm"},
10533   "name": "CB_PERFCOUNTER_FILTER",
10534   "type_ref": "CB_PERFCOUNTER_FILTER"
10535  },
10536  {
10537   "chips": ["gfx103"],
10538   "map": {"at": 225284, "to": "mm"},
10539   "name": "CB_PERFCOUNTER0_SELECT",
10540   "type_ref": "CB_PERFCOUNTER0_SELECT"
10541  },
10542  {
10543   "chips": ["gfx103"],
10544   "map": {"at": 225288, "to": "mm"},
10545   "name": "CB_PERFCOUNTER0_SELECT1",
10546   "type_ref": "CB_PERFCOUNTER0_SELECT1"
10547  },
10548  {
10549   "chips": ["gfx103"],
10550   "map": {"at": 225292, "to": "mm"},
10551   "name": "CB_PERFCOUNTER1_SELECT",
10552   "type_ref": "CB_PERFCOUNTER1_SELECT"
10553  },
10554  {
10555   "chips": ["gfx103"],
10556   "map": {"at": 225296, "to": "mm"},
10557   "name": "CB_PERFCOUNTER2_SELECT",
10558   "type_ref": "CB_PERFCOUNTER1_SELECT"
10559  },
10560  {
10561   "chips": ["gfx103"],
10562   "map": {"at": 225300, "to": "mm"},
10563   "name": "CB_PERFCOUNTER3_SELECT",
10564   "type_ref": "CB_PERFCOUNTER1_SELECT"
10565  },
10566  {
10567   "chips": ["gfx103"],
10568   "map": {"at": 225536, "to": "mm"},
10569   "name": "DB_PERFCOUNTER0_SELECT",
10570   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10571  },
10572  {
10573   "chips": ["gfx103"],
10574   "map": {"at": 225540, "to": "mm"},
10575   "name": "DB_PERFCOUNTER0_SELECT1",
10576   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10577  },
10578  {
10579   "chips": ["gfx103"],
10580   "map": {"at": 225544, "to": "mm"},
10581   "name": "DB_PERFCOUNTER1_SELECT",
10582   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10583  },
10584  {
10585   "chips": ["gfx103"],
10586   "map": {"at": 225548, "to": "mm"},
10587   "name": "DB_PERFCOUNTER1_SELECT1",
10588   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10589  },
10590  {
10591   "chips": ["gfx103"],
10592   "map": {"at": 225552, "to": "mm"},
10593   "name": "DB_PERFCOUNTER2_SELECT",
10594   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10595  },
10596  {
10597   "chips": ["gfx103"],
10598   "map": {"at": 225560, "to": "mm"},
10599   "name": "DB_PERFCOUNTER3_SELECT",
10600   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10601  },
10602  {
10603   "chips": ["gfx103"],
10604   "map": {"at": 225792, "to": "mm"},
10605   "name": "RLC_SPM_PERFMON_CNTL",
10606   "type_ref": "RLC_SPM_PERFMON_CNTL"
10607  },
10608  {
10609   "chips": ["gfx103"],
10610   "map": {"at": 225796, "to": "mm"},
10611   "name": "RLC_SPM_PERFMON_RING_BASE_LO"
10612  },
10613  {
10614   "chips": ["gfx103"],
10615   "map": {"at": 225800, "to": "mm"},
10616   "name": "RLC_SPM_PERFMON_RING_BASE_HI",
10617   "type_ref": "RLC_SPM_PERFMON_RING_BASE_HI"
10618  },
10619  {
10620   "chips": ["gfx103"],
10621   "map": {"at": 225804, "to": "mm"},
10622   "name": "RLC_SPM_PERFMON_RING_SIZE"
10623  },
10624  {
10625   "chips": ["gfx103"],
10626   "map": {"at": 225808, "to": "mm"},
10627   "name": "RLC_SPM_PERFMON_SEGMENT_SIZE",
10628   "type_ref": "RLC_SPM_PERFMON_SEGMENT_SIZE"
10629  },
10630  {
10631   "chips": ["gfx103"],
10632   "map": {"at": 225812, "to": "mm"},
10633   "name": "RLC_SPM_RING_RDPTR"
10634  },
10635  {
10636   "chips": ["gfx103"],
10637   "map": {"at": 225816, "to": "mm"},
10638   "name": "RLC_SPM_SEGMENT_THRESHOLD",
10639   "type_ref": "RLC_SPM_SEGMENT_THRESHOLD"
10640  },
10641  {
10642   "chips": ["gfx103"],
10643   "map": {"at": 225820, "to": "mm"},
10644   "name": "RLC_SPM_SE_MUXSEL_ADDR",
10645   "type_ref": "RLC_SPM_SE_MUXSEL_ADDR"
10646  },
10647  {
10648   "chips": ["gfx103"],
10649   "map": {"at": 225824, "to": "mm"},
10650   "name": "RLC_SPM_SE_MUXSEL_DATA"
10651  },
10652  {
10653   "chips": ["gfx103"],
10654   "map": {"at": 225828, "to": "mm"},
10655   "name": "RLC_SPM_GLOBAL_MUXSEL_ADDR",
10656   "type_ref": "RLC_SPM_GLOBAL_MUXSEL_ADDR"
10657  },
10658  {
10659   "chips": ["gfx103"],
10660   "map": {"at": 225832, "to": "mm"},
10661   "name": "RLC_SPM_GLOBAL_MUXSEL_DATA"
10662  },
10663  {
10664   "chips": ["gfx103"],
10665   "map": {"at": 225836, "to": "mm"},
10666   "name": "RLC_SPM_DESER_START_SKEW",
10667   "type_ref": "RLC_SPM_DESER_START_SKEW"
10668  },
10669  {
10670   "chips": ["gfx103"],
10671   "map": {"at": 225840, "to": "mm"},
10672   "name": "RLC_SPM_GLOBALS_SAMPLE_SKEW",
10673   "type_ref": "RLC_SPM_GLOBALS_SAMPLE_SKEW"
10674  },
10675  {
10676   "chips": ["gfx103"],
10677   "map": {"at": 225844, "to": "mm"},
10678   "name": "RLC_SPM_GLOBALS_MUXSEL_SKEW",
10679   "type_ref": "RLC_SPM_GLOBALS_MUXSEL_SKEW"
10680  },
10681  {
10682   "chips": ["gfx103"],
10683   "map": {"at": 225848, "to": "mm"},
10684   "name": "RLC_SPM_SE_SAMPLE_SKEW",
10685   "type_ref": "RLC_SPM_SE_SAMPLE_SKEW"
10686  },
10687  {
10688   "chips": ["gfx103"],
10689   "map": {"at": 225852, "to": "mm"},
10690   "name": "RLC_SPM_SE_MUXSEL_SKEW",
10691   "type_ref": "RLC_SPM_SE_MUXSEL_SKEW"
10692  },
10693  {
10694   "chips": ["gfx103"],
10695   "map": {"at": 225856, "to": "mm"},
10696   "name": "RLC_SPM_GLB_SAMPLEDELAY_IND_ADDR"
10697  },
10698  {
10699   "chips": ["gfx103"],
10700   "map": {"at": 225860, "to": "mm"},
10701   "name": "RLC_SPM_GLB_SAMPLEDELAY_IND_DATA",
10702   "type_ref": "RLC_SPM_GLB_SAMPLEDELAY_IND_DATA"
10703  },
10704  {
10705   "chips": ["gfx103"],
10706   "map": {"at": 225864, "to": "mm"},
10707   "name": "RLC_SPM_SE_SAMPLEDELAY_IND_ADDR"
10708  },
10709  {
10710   "chips": ["gfx103"],
10711   "map": {"at": 225868, "to": "mm"},
10712   "name": "RLC_SPM_SE_SAMPLEDELAY_IND_DATA",
10713   "type_ref": "RLC_SPM_GLB_SAMPLEDELAY_IND_DATA"
10714  },
10715  {
10716   "chips": ["gfx103"],
10717   "map": {"at": 225872, "to": "mm"},
10718   "name": "RLC_SPM_RING_WRPTR",
10719   "type_ref": "RLC_SPM_RING_WRPTR"
10720  },
10721  {
10722   "chips": ["gfx103"],
10723   "map": {"at": 225876, "to": "mm"},
10724   "name": "RLC_SPM_ACCUM_DATARAM_ADDR",
10725   "type_ref": "RLC_SPM_ACCUM_DATARAM_ADDR"
10726  },
10727  {
10728   "chips": ["gfx103"],
10729   "map": {"at": 225880, "to": "mm"},
10730   "name": "RLC_SPM_ACCUM_DATARAM_DATA"
10731  },
10732  {
10733   "chips": ["gfx103"],
10734   "map": {"at": 225884, "to": "mm"},
10735   "name": "RLC_SPM_ACCUM_CTRLRAM_ADDR",
10736   "type_ref": "RLC_SPM_ACCUM_CTRLRAM_ADDR"
10737  },
10738  {
10739   "chips": ["gfx103"],
10740   "map": {"at": 225888, "to": "mm"},
10741   "name": "RLC_SPM_ACCUM_CTRLRAM_DATA",
10742   "type_ref": "RLC_SPM_ACCUM_CTRLRAM_DATA"
10743  },
10744  {
10745   "chips": ["gfx103"],
10746   "map": {"at": 225892, "to": "mm"},
10747   "name": "RLC_SPM_ACCUM_STATUS",
10748   "type_ref": "RLC_SPM_ACCUM_STATUS"
10749  },
10750  {
10751   "chips": ["gfx103"],
10752   "map": {"at": 225896, "to": "mm"},
10753   "name": "RLC_SPM_ACCUM_CTRL",
10754   "type_ref": "RLC_SPM_ACCUM_CTRL"
10755  },
10756  {
10757   "chips": ["gfx103"],
10758   "map": {"at": 225900, "to": "mm"},
10759   "name": "RLC_SPM_ACCUM_MODE",
10760   "type_ref": "RLC_SPM_ACCUM_MODE"
10761  },
10762  {
10763   "chips": ["gfx103"],
10764   "map": {"at": 225904, "to": "mm"},
10765   "name": "RLC_SPM_ACCUM_THRESHOLD",
10766   "type_ref": "RLC_SPM_ACCUM_THRESHOLD"
10767  },
10768  {
10769   "chips": ["gfx103"],
10770   "map": {"at": 225908, "to": "mm"},
10771   "name": "RLC_SPM_ACCUM_SAMPLES_REQUESTED",
10772   "type_ref": "RLC_SPM_ACCUM_SAMPLES_REQUESTED"
10773  },
10774  {
10775   "chips": ["gfx103"],
10776   "map": {"at": 225912, "to": "mm"},
10777   "name": "RLC_SPM_ACCUM_DATARAM_WRCOUNT",
10778   "type_ref": "RLC_SPM_ACCUM_DATARAM_WRCOUNT"
10779  },
10780  {
10781   "chips": ["gfx103"],
10782   "map": {"at": 225916, "to": "mm"},
10783   "name": "RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE",
10784   "type_ref": "RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE"
10785  },
10786  {
10787   "chips": ["gfx103"],
10788   "map": {"at": 225920, "to": "mm"},
10789   "name": "RLC_SPM_PERFMON_GLB_SEGMENT_SIZE",
10790   "type_ref": "RLC_SPM_PERFMON_GLB_SEGMENT_SIZE"
10791  },
10792  {
10793   "chips": ["gfx103"],
10794   "map": {"at": 225924, "to": "mm"},
10795   "name": "RLC_SPM_VIRT_CTRL",
10796   "type_ref": "RLC_SPM_VIRT_CTRL"
10797  },
10798  {
10799   "chips": ["gfx103"],
10800   "map": {"at": 225928, "to": "mm"},
10801   "name": "RLC_SPM_PERFMON_SWA_SEGMENT_SIZE",
10802   "type_ref": "RLC_SPM_PERFMON_SEGMENT_SIZE"
10803  },
10804  {
10805   "chips": ["gfx103"],
10806   "map": {"at": 225932, "to": "mm"},
10807   "name": "RLC_SPM_VIRT_STATUS",
10808   "type_ref": "RLC_SPM_VIRT_STATUS"
10809  },
10810  {
10811   "chips": ["gfx103"],
10812   "map": {"at": 225936, "to": "mm"},
10813   "name": "RLC_SPM_GFXCLOCK_HIGHCOUNT"
10814  },
10815  {
10816   "chips": ["gfx103"],
10817   "map": {"at": 225940, "to": "mm"},
10818   "name": "RLC_SPM_GFXCLOCK_LOWCOUNT"
10819  },
10820  {
10821   "chips": ["gfx103"],
10822   "map": {"at": 225944, "to": "mm"},
10823   "name": "RLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE",
10824   "type_ref": "RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE"
10825  },
10826  {
10827   "chips": ["gfx103"],
10828   "map": {"at": 225948, "to": "mm"},
10829   "name": "RLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET",
10830   "type_ref": "RLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET"
10831  },
10832  {
10833   "chips": ["gfx103"],
10834   "map": {"at": 225952, "to": "mm"},
10835   "name": "RLC_SPM_SE_MUXSEL_ADDR_OFFSET",
10836   "type_ref": "RLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET"
10837  },
10838  {
10839   "chips": ["gfx103"],
10840   "map": {"at": 225956, "to": "mm"},
10841   "name": "RLC_SPM_ACCUM_SWA_DATARAM_ADDR",
10842   "type_ref": "RLC_SPM_ACCUM_DATARAM_ADDR"
10843  },
10844  {
10845   "chips": ["gfx103"],
10846   "map": {"at": 225960, "to": "mm"},
10847   "name": "RLC_SPM_ACCUM_SWA_DATARAM_DATA"
10848  },
10849  {
10850   "chips": ["gfx103"],
10851   "map": {"at": 225964, "to": "mm"},
10852   "name": "RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET",
10853   "type_ref": "RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET"
10854  },
10855  {
10856   "chips": ["gfx103"],
10857   "map": {"at": 225968, "to": "mm"},
10858   "name": "RLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE",
10859   "type_ref": "RLC_SPM_PERFMON_GLB_SEGMENT_SIZE"
10860  },
10861  {
10862   "chips": ["gfx103"],
10863   "map": {"at": 225972, "to": "mm"},
10864   "name": "RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS",
10865   "type_ref": "RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS"
10866  },
10867  {
10868   "chips": ["gfx103"],
10869   "map": {"at": 226048, "to": "mm"},
10870   "name": "RLC_PERFMON_CNTL",
10871   "type_ref": "RLC_PERFMON_CNTL"
10872  },
10873  {
10874   "chips": ["gfx103"],
10875   "map": {"at": 226052, "to": "mm"},
10876   "name": "RLC_PERFCOUNTER0_SELECT",
10877   "type_ref": "RLC_PERFCOUNTER0_SELECT"
10878  },
10879  {
10880   "chips": ["gfx103"],
10881   "map": {"at": 226056, "to": "mm"},
10882   "name": "RLC_PERFCOUNTER1_SELECT",
10883   "type_ref": "RLC_PERFCOUNTER0_SELECT"
10884  },
10885  {
10886   "chips": ["gfx103"],
10887   "map": {"at": 226060, "to": "mm"},
10888   "name": "RLC_GPU_IOV_PERF_CNT_CNTL",
10889   "type_ref": "RLC_GPU_IOV_PERF_CNT_CNTL"
10890  },
10891  {
10892   "chips": ["gfx103"],
10893   "map": {"at": 226064, "to": "mm"},
10894   "name": "RLC_GPU_IOV_PERF_CNT_WR_ADDR",
10895   "type_ref": "RLC_GPU_IOV_PERF_CNT_WR_ADDR"
10896  },
10897  {
10898   "chips": ["gfx103"],
10899   "map": {"at": 226068, "to": "mm"},
10900   "name": "RLC_GPU_IOV_PERF_CNT_WR_DATA"
10901  },
10902  {
10903   "chips": ["gfx103"],
10904   "map": {"at": 226072, "to": "mm"},
10905   "name": "RLC_GPU_IOV_PERF_CNT_RD_ADDR",
10906   "type_ref": "RLC_GPU_IOV_PERF_CNT_WR_ADDR"
10907  },
10908  {
10909   "chips": ["gfx103"],
10910   "map": {"at": 226076, "to": "mm"},
10911   "name": "RLC_GPU_IOV_PERF_CNT_RD_DATA"
10912  },
10913  {
10914   "chips": ["gfx103"],
10915   "map": {"at": 226192, "to": "mm"},
10916   "name": "RLC_PERFMON_CLK_CNTL",
10917   "type_ref": "RLC_PERFMON_CLK_CNTL"
10918  },
10919  {
10920   "chips": ["gfx103"],
10921   "map": {"at": 226304, "to": "mm"},
10922   "name": "RMI_PERFCOUNTER0_SELECT",
10923   "type_ref": "CB_PERFCOUNTER0_SELECT"
10924  },
10925  {
10926   "chips": ["gfx103"],
10927   "map": {"at": 226308, "to": "mm"},
10928   "name": "RMI_PERFCOUNTER0_SELECT1",
10929   "type_ref": "CB_PERFCOUNTER0_SELECT1"
10930  },
10931  {
10932   "chips": ["gfx103"],
10933   "map": {"at": 226312, "to": "mm"},
10934   "name": "RMI_PERFCOUNTER1_SELECT",
10935   "type_ref": "CB_PERFCOUNTER1_SELECT"
10936  },
10937  {
10938   "chips": ["gfx103"],
10939   "map": {"at": 226316, "to": "mm"},
10940   "name": "RMI_PERFCOUNTER2_SELECT",
10941   "type_ref": "CB_PERFCOUNTER0_SELECT"
10942  },
10943  {
10944   "chips": ["gfx103"],
10945   "map": {"at": 226320, "to": "mm"},
10946   "name": "RMI_PERFCOUNTER2_SELECT1",
10947   "type_ref": "CB_PERFCOUNTER0_SELECT1"
10948  },
10949  {
10950   "chips": ["gfx103"],
10951   "map": {"at": 226324, "to": "mm"},
10952   "name": "RMI_PERFCOUNTER3_SELECT",
10953   "type_ref": "CB_PERFCOUNTER1_SELECT"
10954  },
10955  {
10956   "chips": ["gfx103"],
10957   "map": {"at": 226328, "to": "mm"},
10958   "name": "RMI_PERF_COUNTER_CNTL",
10959   "type_ref": "RMI_PERF_COUNTER_CNTL"
10960  },
10961  {
10962   "chips": ["gfx103"],
10963   "map": {"at": 226480, "to": "mm"},
10964   "name": "GCMC_VM_L2_PERFCOUNTER0_CFG",
10965   "type_ref": "GCEA_PERFCOUNTER0_CFG"
10966  },
10967  {
10968   "chips": ["gfx103"],
10969   "map": {"at": 226484, "to": "mm"},
10970   "name": "GCMC_VM_L2_PERFCOUNTER1_CFG",
10971   "type_ref": "GCEA_PERFCOUNTER0_CFG"
10972  },
10973  {
10974   "chips": ["gfx103"],
10975   "map": {"at": 226488, "to": "mm"},
10976   "name": "GCMC_VM_L2_PERFCOUNTER2_CFG",
10977   "type_ref": "GCEA_PERFCOUNTER0_CFG"
10978  },
10979  {
10980   "chips": ["gfx103"],
10981   "map": {"at": 226492, "to": "mm"},
10982   "name": "GCMC_VM_L2_PERFCOUNTER3_CFG",
10983   "type_ref": "GCEA_PERFCOUNTER0_CFG"
10984  },
10985  {
10986   "chips": ["gfx103"],
10987   "map": {"at": 226496, "to": "mm"},
10988   "name": "GCMC_VM_L2_PERFCOUNTER4_CFG",
10989   "type_ref": "GCEA_PERFCOUNTER0_CFG"
10990  },
10991  {
10992   "chips": ["gfx103"],
10993   "map": {"at": 226500, "to": "mm"},
10994   "name": "GCMC_VM_L2_PERFCOUNTER5_CFG",
10995   "type_ref": "GCEA_PERFCOUNTER0_CFG"
10996  },
10997  {
10998   "chips": ["gfx103"],
10999   "map": {"at": 226504, "to": "mm"},
11000   "name": "GCMC_VM_L2_PERFCOUNTER6_CFG",
11001   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11002  },
11003  {
11004   "chips": ["gfx103"],
11005   "map": {"at": 226508, "to": "mm"},
11006   "name": "GCMC_VM_L2_PERFCOUNTER7_CFG",
11007   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11008  },
11009  {
11010   "chips": ["gfx103"],
11011   "map": {"at": 226512, "to": "mm"},
11012   "name": "GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL",
11013   "type_ref": "GCEA_PERFCOUNTER_RSLT_CNTL"
11014  },
11015  {
11016   "chips": ["gfx103"],
11017   "map": {"at": 226516, "to": "mm"},
11018   "name": "GCUTCL2_PERFCOUNTER0_CFG",
11019   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11020  },
11021  {
11022   "chips": ["gfx103"],
11023   "map": {"at": 226520, "to": "mm"},
11024   "name": "GCUTCL2_PERFCOUNTER1_CFG",
11025   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11026  },
11027  {
11028   "chips": ["gfx103"],
11029   "map": {"at": 226524, "to": "mm"},
11030   "name": "GCUTCL2_PERFCOUNTER2_CFG",
11031   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11032  },
11033  {
11034   "chips": ["gfx103"],
11035   "map": {"at": 226528, "to": "mm"},
11036   "name": "GCUTCL2_PERFCOUNTER3_CFG",
11037   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11038  },
11039  {
11040   "chips": ["gfx103"],
11041   "map": {"at": 226532, "to": "mm"},
11042   "name": "GCUTCL2_PERFCOUNTER_RSLT_CNTL",
11043   "type_ref": "GCEA_PERFCOUNTER_RSLT_CNTL"
11044  },
11045  {
11046   "chips": ["gfx103"],
11047   "map": {"at": 226544, "to": "mm"},
11048   "name": "GCVML2_PERFCOUNTER2_0_SELECT",
11049   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11050  },
11051  {
11052   "chips": ["gfx103"],
11053   "map": {"at": 226548, "to": "mm"},
11054   "name": "GCVML2_PERFCOUNTER2_1_SELECT",
11055   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11056  },
11057  {
11058   "chips": ["gfx103"],
11059   "map": {"at": 226552, "to": "mm"},
11060   "name": "GCVML2_PERFCOUNTER2_0_SELECT1",
11061   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11062  },
11063  {
11064   "chips": ["gfx103"],
11065   "map": {"at": 226556, "to": "mm"},
11066   "name": "GCVML2_PERFCOUNTER2_1_SELECT1",
11067   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11068  },
11069  {
11070   "chips": ["gfx103"],
11071   "map": {"at": 226560, "to": "mm"},
11072   "name": "GCVML2_PERFCOUNTER2_0_MODE",
11073   "type_ref": "GCEA_PERFCOUNTER2_MODE"
11074  },
11075  {
11076   "chips": ["gfx103"],
11077   "map": {"at": 226564, "to": "mm"},
11078   "name": "GCVML2_PERFCOUNTER2_1_MODE",
11079   "type_ref": "GCEA_PERFCOUNTER2_MODE"
11080  },
11081  {
11082   "chips": ["gfx103"],
11083   "map": {"at": 226688, "to": "mm"},
11084   "name": "GCR_PERFCOUNTER0_SELECT",
11085   "type_ref": "CB_PERFCOUNTER0_SELECT"
11086  },
11087  {
11088   "chips": ["gfx103"],
11089   "map": {"at": 226692, "to": "mm"},
11090   "name": "GCR_PERFCOUNTER0_SELECT1",
11091   "type_ref": "CB_PERFCOUNTER0_SELECT1"
11092  },
11093  {
11094   "chips": ["gfx103"],
11095   "map": {"at": 226696, "to": "mm"},
11096   "name": "GCR_PERFCOUNTER1_SELECT",
11097   "type_ref": "GCR_PERFCOUNTER1_SELECT"
11098  },
11099  {
11100   "chips": ["gfx103"],
11101   "map": {"at": 226700, "to": "mm"},
11102   "name": "UTCL1_PERFCOUNTER0_SELECT",
11103   "type_ref": "UTCL1_PERFCOUNTER0_SELECT"
11104  },
11105  {
11106   "chips": ["gfx103"],
11107   "map": {"at": 226704, "to": "mm"},
11108   "name": "UTCL1_PERFCOUNTER1_SELECT",
11109   "type_ref": "UTCL1_PERFCOUNTER0_SELECT"
11110  },
11111  {
11112   "chips": ["gfx103"],
11113   "map": {"at": 226816, "to": "mm"},
11114   "name": "PA_PH_PERFCOUNTER0_SELECT",
11115   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11116  },
11117  {
11118   "chips": ["gfx103"],
11119   "map": {"at": 226820, "to": "mm"},
11120   "name": "PA_PH_PERFCOUNTER0_SELECT1",
11121   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11122  },
11123  {
11124   "chips": ["gfx103"],
11125   "map": {"at": 226824, "to": "mm"},
11126   "name": "PA_PH_PERFCOUNTER1_SELECT",
11127   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11128  },
11129  {
11130   "chips": ["gfx103"],
11131   "map": {"at": 226828, "to": "mm"},
11132   "name": "PA_PH_PERFCOUNTER2_SELECT",
11133   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11134  },
11135  {
11136   "chips": ["gfx103"],
11137   "map": {"at": 226832, "to": "mm"},
11138   "name": "PA_PH_PERFCOUNTER3_SELECT",
11139   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11140  },
11141  {
11142   "chips": ["gfx103"],
11143   "map": {"at": 226836, "to": "mm"},
11144   "name": "PA_PH_PERFCOUNTER4_SELECT",
11145   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
11146  },
11147  {
11148   "chips": ["gfx103"],
11149   "map": {"at": 226840, "to": "mm"},
11150   "name": "PA_PH_PERFCOUNTER5_SELECT",
11151   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
11152  },
11153  {
11154   "chips": ["gfx103"],
11155   "map": {"at": 226844, "to": "mm"},
11156   "name": "PA_PH_PERFCOUNTER6_SELECT",
11157   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
11158  },
11159  {
11160   "chips": ["gfx103"],
11161   "map": {"at": 226848, "to": "mm"},
11162   "name": "PA_PH_PERFCOUNTER7_SELECT",
11163   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
11164  },
11165  {
11166   "chips": ["gfx103"],
11167   "map": {"at": 226880, "to": "mm"},
11168   "name": "PA_PH_PERFCOUNTER1_SELECT1",
11169   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11170  },
11171  {
11172   "chips": ["gfx103"],
11173   "map": {"at": 226884, "to": "mm"},
11174   "name": "PA_PH_PERFCOUNTER2_SELECT1",
11175   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11176  },
11177  {
11178   "chips": ["gfx103"],
11179   "map": {"at": 226888, "to": "mm"},
11180   "name": "PA_PH_PERFCOUNTER3_SELECT1",
11181   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11182  },
11183  {
11184   "chips": ["gfx103"],
11185   "map": {"at": 227072, "to": "mm"},
11186   "name": "GL1A_PERFCOUNTER0_SELECT",
11187   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11188  },
11189  {
11190   "chips": ["gfx103"],
11191   "map": {"at": 227076, "to": "mm"},
11192   "name": "GL1A_PERFCOUNTER0_SELECT1",
11193   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
11194  },
11195  {
11196   "chips": ["gfx103"],
11197   "map": {"at": 227080, "to": "mm"},
11198   "name": "GL1A_PERFCOUNTER1_SELECT",
11199   "type_ref": "SX_PERFCOUNTER2_SELECT"
11200  },
11201  {
11202   "chips": ["gfx103"],
11203   "map": {"at": 227084, "to": "mm"},
11204   "name": "GL1A_PERFCOUNTER2_SELECT",
11205   "type_ref": "SX_PERFCOUNTER2_SELECT"
11206  },
11207  {
11208   "chips": ["gfx103"],
11209   "map": {"at": 227088, "to": "mm"},
11210   "name": "GL1A_PERFCOUNTER3_SELECT",
11211   "type_ref": "SX_PERFCOUNTER2_SELECT"
11212  },
11213  {
11214   "chips": ["gfx103"],
11215   "map": {"at": 227200, "to": "mm"},
11216   "name": "CHA_PERFCOUNTER0_SELECT",
11217   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11218  },
11219  {
11220   "chips": ["gfx103"],
11221   "map": {"at": 227204, "to": "mm"},
11222   "name": "CHA_PERFCOUNTER0_SELECT1",
11223   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
11224  },
11225  {
11226   "chips": ["gfx103"],
11227   "map": {"at": 227208, "to": "mm"},
11228   "name": "CHA_PERFCOUNTER1_SELECT",
11229   "type_ref": "SX_PERFCOUNTER2_SELECT"
11230  },
11231  {
11232   "chips": ["gfx103"],
11233   "map": {"at": 227212, "to": "mm"},
11234   "name": "CHA_PERFCOUNTER2_SELECT",
11235   "type_ref": "SX_PERFCOUNTER2_SELECT"
11236  },
11237  {
11238   "chips": ["gfx103"],
11239   "map": {"at": 227216, "to": "mm"},
11240   "name": "CHA_PERFCOUNTER3_SELECT",
11241   "type_ref": "SX_PERFCOUNTER2_SELECT"
11242  },
11243  {
11244   "chips": ["gfx103"],
11245   "map": {"at": 227328, "to": "mm"},
11246   "name": "GUS_PERFCOUNTER2_SELECT",
11247   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11248  },
11249  {
11250   "chips": ["gfx103"],
11251   "map": {"at": 227332, "to": "mm"},
11252   "name": "GUS_PERFCOUNTER2_SELECT1",
11253   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11254  },
11255  {
11256   "chips": ["gfx103"],
11257   "map": {"at": 227336, "to": "mm"},
11258   "name": "GUS_PERFCOUNTER2_MODE",
11259   "type_ref": "GCEA_PERFCOUNTER2_MODE"
11260  },
11261  {
11262   "chips": ["gfx103"],
11263   "map": {"at": 227340, "to": "mm"},
11264   "name": "GUS_PERFCOUNTER0_CFG",
11265   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11266  },
11267  {
11268   "chips": ["gfx103"],
11269   "map": {"at": 227344, "to": "mm"},
11270   "name": "GUS_PERFCOUNTER1_CFG",
11271   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11272  },
11273  {
11274   "chips": ["gfx103"],
11275   "map": {"at": 227348, "to": "mm"},
11276   "name": "GUS_PERFCOUNTER_RSLT_CNTL",
11277   "type_ref": "GCEA_PERFCOUNTER_RSLT_CNTL"
11278  },
11279  {
11280   "chips": ["gfx103"],
11281   "map": {"at": 227456, "to": "mm"},
11282   "name": "SDMA0_PERFCNT_PERFCOUNTER0_CFG",
11283   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11284  },
11285  {
11286   "chips": ["gfx103"],
11287   "map": {"at": 227460, "to": "mm"},
11288   "name": "SDMA0_PERFCNT_PERFCOUNTER1_CFG",
11289   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11290  },
11291  {
11292   "chips": ["gfx103"],
11293   "map": {"at": 227464, "to": "mm"},
11294   "name": "SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL",
11295   "type_ref": "GCEA_PERFCOUNTER_RSLT_CNTL"
11296  },
11297  {
11298   "chips": ["gfx103"],
11299   "map": {"at": 227468, "to": "mm"},
11300   "name": "SDMA0_PERFCNT_MISC_CNTL",
11301   "type_ref": "SDMA0_PERFCNT_MISC_CNTL"
11302  },
11303  {
11304   "chips": ["gfx103"],
11305   "map": {"at": 227472, "to": "mm"},
11306   "name": "SDMA0_PERFCOUNTER0_SELECT",
11307   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11308  },
11309  {
11310   "chips": ["gfx103"],
11311   "map": {"at": 227476, "to": "mm"},
11312   "name": "SDMA0_PERFCOUNTER0_SELECT1",
11313   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11314  },
11315  {
11316   "chips": ["gfx103"],
11317   "map": {"at": 227480, "to": "mm"},
11318   "name": "SDMA0_PERFCOUNTER1_SELECT",
11319   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11320  },
11321  {
11322   "chips": ["gfx103"],
11323   "map": {"at": 227484, "to": "mm"},
11324   "name": "SDMA0_PERFCOUNTER1_SELECT1",
11325   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11326  },
11327  {
11328   "chips": ["gfx103"],
11329   "map": {"at": 227504, "to": "mm"},
11330   "name": "SDMA1_PERFCNT_PERFCOUNTER0_CFG",
11331   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11332  },
11333  {
11334   "chips": ["gfx103"],
11335   "map": {"at": 227508, "to": "mm"},
11336   "name": "SDMA1_PERFCNT_PERFCOUNTER1_CFG",
11337   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11338  },
11339  {
11340   "chips": ["gfx103"],
11341   "map": {"at": 227512, "to": "mm"},
11342   "name": "SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL",
11343   "type_ref": "GCEA_PERFCOUNTER_RSLT_CNTL"
11344  },
11345  {
11346   "chips": ["gfx103"],
11347   "map": {"at": 227516, "to": "mm"},
11348   "name": "SDMA1_PERFCNT_MISC_CNTL",
11349   "type_ref": "SDMA0_PERFCNT_MISC_CNTL"
11350  },
11351  {
11352   "chips": ["gfx103"],
11353   "map": {"at": 227520, "to": "mm"},
11354   "name": "SDMA1_PERFCOUNTER0_SELECT",
11355   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11356  },
11357  {
11358   "chips": ["gfx103"],
11359   "map": {"at": 227524, "to": "mm"},
11360   "name": "SDMA1_PERFCOUNTER0_SELECT1",
11361   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11362  },
11363  {
11364   "chips": ["gfx103"],
11365   "map": {"at": 227528, "to": "mm"},
11366   "name": "SDMA1_PERFCOUNTER1_SELECT",
11367   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11368  },
11369  {
11370   "chips": ["gfx103"],
11371   "map": {"at": 227532, "to": "mm"},
11372   "name": "SDMA1_PERFCOUNTER1_SELECT1",
11373   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11374  },
11375  {
11376   "chips": ["gfx103"],
11377   "map": {"at": 227552, "to": "mm"},
11378   "name": "SDMA2_PERFCNT_PERFCOUNTER0_CFG",
11379   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11380  },
11381  {
11382   "chips": ["gfx103"],
11383   "map": {"at": 227556, "to": "mm"},
11384   "name": "SDMA2_PERFCNT_PERFCOUNTER1_CFG",
11385   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11386  },
11387  {
11388   "chips": ["gfx103"],
11389   "map": {"at": 227560, "to": "mm"},
11390   "name": "SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL",
11391   "type_ref": "GCEA_PERFCOUNTER_RSLT_CNTL"
11392  },
11393  {
11394   "chips": ["gfx103"],
11395   "map": {"at": 227564, "to": "mm"},
11396   "name": "SDMA2_PERFCNT_MISC_CNTL",
11397   "type_ref": "SDMA0_PERFCNT_MISC_CNTL"
11398  },
11399  {
11400   "chips": ["gfx103"],
11401   "map": {"at": 227568, "to": "mm"},
11402   "name": "SDMA2_PERFCOUNTER0_SELECT",
11403   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11404  },
11405  {
11406   "chips": ["gfx103"],
11407   "map": {"at": 227572, "to": "mm"},
11408   "name": "SDMA2_PERFCOUNTER0_SELECT1",
11409   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11410  },
11411  {
11412   "chips": ["gfx103"],
11413   "map": {"at": 227576, "to": "mm"},
11414   "name": "SDMA2_PERFCOUNTER1_SELECT",
11415   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11416  },
11417  {
11418   "chips": ["gfx103"],
11419   "map": {"at": 227580, "to": "mm"},
11420   "name": "SDMA2_PERFCOUNTER1_SELECT1",
11421   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11422  },
11423  {
11424   "chips": ["gfx103"],
11425   "map": {"at": 227600, "to": "mm"},
11426   "name": "SDMA3_PERFCNT_PERFCOUNTER0_CFG",
11427   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11428  },
11429  {
11430   "chips": ["gfx103"],
11431   "map": {"at": 227604, "to": "mm"},
11432   "name": "SDMA3_PERFCNT_PERFCOUNTER1_CFG",
11433   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11434  },
11435  {
11436   "chips": ["gfx103"],
11437   "map": {"at": 227608, "to": "mm"},
11438   "name": "SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL",
11439   "type_ref": "GCEA_PERFCOUNTER_RSLT_CNTL"
11440  },
11441  {
11442   "chips": ["gfx103"],
11443   "map": {"at": 227612, "to": "mm"},
11444   "name": "SDMA3_PERFCNT_MISC_CNTL",
11445   "type_ref": "SDMA0_PERFCNT_MISC_CNTL"
11446  },
11447  {
11448   "chips": ["gfx103"],
11449   "map": {"at": 227616, "to": "mm"},
11450   "name": "SDMA3_PERFCOUNTER0_SELECT",
11451   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11452  },
11453  {
11454   "chips": ["gfx103"],
11455   "map": {"at": 227620, "to": "mm"},
11456   "name": "SDMA3_PERFCOUNTER0_SELECT1",
11457   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11458  },
11459  {
11460   "chips": ["gfx103"],
11461   "map": {"at": 227624, "to": "mm"},
11462   "name": "SDMA3_PERFCOUNTER1_SELECT",
11463   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11464  },
11465  {
11466   "chips": ["gfx103"],
11467   "map": {"at": 227628, "to": "mm"},
11468   "name": "SDMA3_PERFCOUNTER1_SELECT1",
11469   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11470  }
11471 ],
11472 "register_types": {
11473  "CB_BLEND0_CONTROL": {
11474   "fields": [
11475    {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"},
11476    {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"},
11477    {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"},
11478    {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"},
11479    {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"},
11480    {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"},
11481    {"bits": [29, 29], "name": "SEPARATE_ALPHA_BLEND"},
11482    {"bits": [30, 30], "name": "ENABLE"},
11483    {"bits": [31, 31], "name": "DISABLE_ROP3"}
11484   ]
11485  },
11486  "CB_COLOR0_ATTRIB": {
11487   "fields": [
11488    {"bits": [0, 4], "name": "TILE_MODE_INDEX"},
11489    {"bits": [5, 9], "name": "FMASK_TILE_MODE_INDEX"},
11490    {"bits": [10, 11], "name": "FMASK_BANK_HEIGHT"},
11491    {"bits": [12, 14], "name": "NUM_SAMPLES"},
11492    {"bits": [15, 16], "name": "NUM_FRAGMENTS"},
11493    {"bits": [17, 17], "name": "FORCE_DST_ALPHA_1"},
11494    {"bits": [18, 18], "name": "DISABLE_FMASK_NOFETCH_OPT"},
11495    {"bits": [19, 19], "name": "LIMIT_COLOR_FETCH_TO_256B_MAX"}
11496   ]
11497  },
11498  "CB_COLOR0_ATTRIB2": {
11499   "fields": [
11500    {"bits": [0, 13], "name": "MIP0_HEIGHT"},
11501    {"bits": [14, 27], "name": "MIP0_WIDTH"},
11502    {"bits": [28, 31], "name": "MAX_MIP"}
11503   ]
11504  },
11505  "CB_COLOR0_ATTRIB3": {
11506   "fields": [
11507    {"bits": [0, 12], "name": "MIP0_DEPTH"},
11508    {"bits": [13, 13], "name": "META_LINEAR"},
11509    {"bits": [14, 18], "name": "COLOR_SW_MODE"},
11510    {"bits": [19, 23], "name": "FMASK_SW_MODE"},
11511    {"bits": [24, 25], "name": "RESOURCE_TYPE"},
11512    {"bits": [26, 26], "name": "CMASK_PIPE_ALIGNED"},
11513    {"bits": [27, 29], "name": "RESOURCE_LEVEL"},
11514    {"bits": [30, 30], "name": "DCC_PIPE_ALIGNED"},
11515    {"bits": [31, 31], "name": "VRS_RATE_HINT_ENABLE"}
11516   ]
11517  },
11518  "CB_COLOR0_BASE_EXT": {
11519   "fields": [
11520    {"bits": [0, 7], "name": "BASE_256B"}
11521   ]
11522  },
11523  "CB_COLOR0_CMASK_SLICE": {
11524   "fields": [
11525    {"bits": [0, 13], "name": "TILE_MAX"}
11526   ]
11527  },
11528  "CB_COLOR0_DCC_CONTROL": {
11529   "fields": [
11530    {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"},
11531    {"bits": [1, 1], "name": "KEY_CLEAR_ENABLE"},
11532    {"bits": [2, 3], "enum_ref": "CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE", "name": "MAX_UNCOMPRESSED_BLOCK_SIZE"},
11533    {"bits": [4, 4], "enum_ref": "CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE", "name": "MIN_COMPRESSED_BLOCK_SIZE"},
11534    {"bits": [5, 6], "name": "MAX_COMPRESSED_BLOCK_SIZE"},
11535    {"bits": [7, 8], "name": "COLOR_TRANSFORM"},
11536    {"bits": [9, 9], "name": "INDEPENDENT_64B_BLOCKS"},
11537    {"bits": [10, 13], "name": "LOSSY_RGB_PRECISION"},
11538    {"bits": [14, 17], "name": "LOSSY_ALPHA_PRECISION"},
11539    {"bits": [18, 18], "name": "DISABLE_CONSTANT_ENCODE_REG"},
11540    {"bits": [19, 19], "name": "ENABLE_CONSTANT_ENCODE_REG_WRITE"},
11541    {"bits": [20, 20], "name": "INDEPENDENT_128B_BLOCKS"},
11542    {"bits": [21, 21], "name": "SKIP_LOW_COMP_RATIO"},
11543    {"bits": [22, 22], "name": "DCC_COMPRESS_DISABLE"}
11544   ]
11545  },
11546  "CB_COLOR0_INFO": {
11547   "fields": [
11548    {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"},
11549    {"bits": [2, 6], "enum_ref": "ColorFormat", "name": "FORMAT"},
11550    {"bits": [7, 7], "name": "LINEAR_GENERAL"},
11551    {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"},
11552    {"bits": [11, 12], "enum_ref": "SurfaceSwap", "name": "COMP_SWAP"},
11553    {"bits": [13, 13], "name": "FAST_CLEAR"},
11554    {"bits": [14, 14], "name": "COMPRESSION"},
11555    {"bits": [15, 15], "name": "BLEND_CLAMP"},
11556    {"bits": [16, 16], "name": "BLEND_BYPASS"},
11557    {"bits": [17, 17], "name": "SIMPLE_FLOAT"},
11558    {"bits": [18, 18], "name": "ROUND_MODE"},
11559    {"bits": [19, 19], "name": "CMASK_IS_LINEAR"},
11560    {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"},
11561    {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"},
11562    {"bits": [26, 26], "name": "FMASK_COMPRESSION_DISABLE"},
11563    {"bits": [27, 27], "name": "FMASK_COMPRESS_1FRAG_ONLY"},
11564    {"bits": [28, 28], "name": "DCC_ENABLE"},
11565    {"bits": [29, 30], "enum_ref": "CmaskAddr", "name": "CMASK_ADDR_TYPE"},
11566    {"bits": [31, 31], "name": "NBC_TILING"}
11567   ]
11568  },
11569  "CB_COLOR0_PITCH": {
11570   "fields": [
11571    {"bits": [0, 10], "name": "TILE_MAX"},
11572    {"bits": [20, 30], "name": "FMASK_TILE_MAX"}
11573   ]
11574  },
11575  "CB_COLOR0_SLICE": {
11576   "fields": [
11577    {"bits": [0, 21], "name": "TILE_MAX"}
11578   ]
11579  },
11580  "CB_COLOR0_VIEW": {
11581   "fields": [
11582    {"bits": [0, 12], "name": "SLICE_START"},
11583    {"bits": [13, 25], "name": "SLICE_MAX"},
11584    {"bits": [26, 29], "name": "MIP_LEVEL"}
11585   ]
11586  },
11587  "CB_COLOR_CONTROL": {
11588   "fields": [
11589    {"bits": [0, 0], "name": "DISABLE_DUAL_QUAD"},
11590    {"bits": [1, 1], "name": "ENABLE_1FRAG_PS_INVOKE"},
11591    {"bits": [3, 3], "name": "DEGAMMA_ENABLE"},
11592    {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"},
11593    {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"}
11594   ]
11595  },
11596  "CB_COVERAGE_OUT_CONTROL": {
11597   "fields": [
11598    {"bits": [0, 0], "name": "COVERAGE_OUT_ENABLE"},
11599    {"bits": [1, 3], "name": "COVERAGE_OUT_MRT"},
11600    {"bits": [4, 5], "name": "COVERAGE_OUT_CHANNEL"},
11601    {"bits": [8, 11], "name": "COVERAGE_OUT_SAMPLES"}
11602   ]
11603  },
11604  "CB_DCC_CONTROL": {
11605   "fields": [
11606    {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"},
11607    {"bits": [2, 6], "name": "OVERWRITE_COMBINER_WATERMARK"},
11608    {"bits": [8, 8], "name": "DISABLE_CONSTANT_ENCODE_AC01"},
11609    {"bits": [9, 9], "name": "DISABLE_CONSTANT_ENCODE_SINGLE"},
11610    {"bits": [10, 10], "name": "DISABLE_CONSTANT_ENCODE_REG"},
11611    {"bits": [12, 12], "name": "DISABLE_ELIMFC_SKIP_OF_AC01"},
11612    {"bits": [13, 13], "name": "DISABLE_ELIMFC_SKIP_OF_SINGLE"},
11613    {"bits": [14, 14], "name": "ENABLE_ELIMFC_SKIP_OF_REG"}
11614   ]
11615  },
11616  "CB_PERFCOUNTER0_SELECT": {
11617   "fields": [
11618    {"bits": [0, 8], "name": "PERF_SEL"},
11619    {"bits": [10, 18], "name": "PERF_SEL1"},
11620    {"bits": [20, 23], "name": "CNTR_MODE"},
11621    {"bits": [24, 27], "name": "PERF_MODE1"},
11622    {"bits": [28, 31], "name": "PERF_MODE"}
11623   ]
11624  },
11625  "CB_PERFCOUNTER0_SELECT1": {
11626   "fields": [
11627    {"bits": [0, 8], "name": "PERF_SEL2"},
11628    {"bits": [10, 18], "name": "PERF_SEL3"},
11629    {"bits": [24, 27], "name": "PERF_MODE3"},
11630    {"bits": [28, 31], "name": "PERF_MODE2"}
11631   ]
11632  },
11633  "CB_PERFCOUNTER1_SELECT": {
11634   "fields": [
11635    {"bits": [0, 8], "name": "PERF_SEL"},
11636    {"bits": [28, 31], "name": "PERF_MODE"}
11637   ]
11638  },
11639  "CB_PERFCOUNTER_FILTER": {
11640   "fields": [
11641    {"bits": [0, 0], "name": "OP_FILTER_ENABLE"},
11642    {"bits": [1, 3], "enum_ref": "CBPerfOpFilterSel", "name": "OP_FILTER_SEL"},
11643    {"bits": [4, 4], "name": "FORMAT_FILTER_ENABLE"},
11644    {"bits": [5, 9], "name": "FORMAT_FILTER_SEL"},
11645    {"bits": [10, 10], "name": "CLEAR_FILTER_ENABLE"},
11646    {"bits": [11, 11], "enum_ref": "CBPerfClearFilterSel", "name": "CLEAR_FILTER_SEL"},
11647    {"bits": [12, 12], "name": "MRT_FILTER_ENABLE"},
11648    {"bits": [13, 15], "name": "MRT_FILTER_SEL"},
11649    {"bits": [17, 17], "name": "NUM_SAMPLES_FILTER_ENABLE"},
11650    {"bits": [18, 20], "name": "NUM_SAMPLES_FILTER_SEL"},
11651    {"bits": [21, 21], "name": "NUM_FRAGMENTS_FILTER_ENABLE"},
11652    {"bits": [22, 23], "name": "NUM_FRAGMENTS_FILTER_SEL"}
11653   ]
11654  },
11655  "CB_RMI_GL2_CACHE_CONTROL": {
11656   "fields": [
11657    {"bits": [0, 1], "enum_ref": "WritePolicy", "name": "CMASK_WR_POLICY"},
11658    {"bits": [2, 3], "enum_ref": "WritePolicy", "name": "FMASK_WR_POLICY"},
11659    {"bits": [4, 5], "enum_ref": "WritePolicy", "name": "DCC_WR_POLICY"},
11660    {"bits": [6, 7], "enum_ref": "WritePolicy", "name": "COLOR_WR_POLICY"},
11661    {"bits": [16, 17], "enum_ref": "ReadPolicy", "name": "CMASK_RD_POLICY"},
11662    {"bits": [18, 19], "enum_ref": "ReadPolicy", "name": "FMASK_RD_POLICY"},
11663    {"bits": [20, 21], "enum_ref": "ReadPolicy", "name": "DCC_RD_POLICY"},
11664    {"bits": [22, 23], "enum_ref": "ReadPolicy", "name": "COLOR_RD_POLICY"},
11665    {"bits": [24, 24], "name": "CMASK_L3_BYPASS"},
11666    {"bits": [25, 25], "name": "FMASK_L3_BYPASS"},
11667    {"bits": [26, 26], "name": "DCC_L3_BYPASS"},
11668    {"bits": [27, 27], "name": "COLOR_L3_BYPASS"},
11669    {"bits": [30, 30], "name": "FMASK_BIG_PAGE"},
11670    {"bits": [31, 31], "name": "COLOR_BIG_PAGE"}
11671   ]
11672  },
11673  "CB_SHADER_MASK": {
11674   "fields": [
11675    {"bits": [0, 3], "name": "OUTPUT0_ENABLE"},
11676    {"bits": [4, 7], "name": "OUTPUT1_ENABLE"},
11677    {"bits": [8, 11], "name": "OUTPUT2_ENABLE"},
11678    {"bits": [12, 15], "name": "OUTPUT3_ENABLE"},
11679    {"bits": [16, 19], "name": "OUTPUT4_ENABLE"},
11680    {"bits": [20, 23], "name": "OUTPUT5_ENABLE"},
11681    {"bits": [24, 27], "name": "OUTPUT6_ENABLE"},
11682    {"bits": [28, 31], "name": "OUTPUT7_ENABLE"}
11683   ]
11684  },
11685  "CB_TARGET_MASK": {
11686   "fields": [
11687    {"bits": [0, 3], "name": "TARGET0_ENABLE"},
11688    {"bits": [4, 7], "name": "TARGET1_ENABLE"},
11689    {"bits": [8, 11], "name": "TARGET2_ENABLE"},
11690    {"bits": [12, 15], "name": "TARGET3_ENABLE"},
11691    {"bits": [16, 19], "name": "TARGET4_ENABLE"},
11692    {"bits": [20, 23], "name": "TARGET5_ENABLE"},
11693    {"bits": [24, 27], "name": "TARGET6_ENABLE"},
11694    {"bits": [28, 31], "name": "TARGET7_ENABLE"}
11695   ]
11696  },
11697  "COHER_DEST_BASE_HI_0": {
11698   "fields": [
11699    {"bits": [0, 7], "name": "DEST_BASE_HI_256B"}
11700   ]
11701  },
11702  "COMPUTE_DDID_INDEX": {
11703   "fields": [
11704    {"bits": [0, 10], "name": "INDEX"}
11705   ]
11706  },
11707  "COMPUTE_DISPATCH_INITIATOR": {
11708   "fields": [
11709    {"bits": [0, 0], "name": "COMPUTE_SHADER_EN"},
11710    {"bits": [1, 1], "name": "PARTIAL_TG_EN"},
11711    {"bits": [2, 2], "name": "FORCE_START_AT_000"},
11712    {"bits": [3, 3], "name": "ORDERED_APPEND_ENBL"},
11713    {"bits": [4, 4], "name": "ORDERED_APPEND_MODE"},
11714    {"bits": [5, 5], "name": "USE_THREAD_DIMENSIONS"},
11715    {"bits": [6, 6], "name": "ORDER_MODE"},
11716    {"bits": [10, 10], "name": "SCALAR_L1_INV_VOL"},
11717    {"bits": [11, 11], "name": "VECTOR_L1_INV_VOL"},
11718    {"bits": [12, 12], "name": "RESERVED"},
11719    {"bits": [13, 13], "name": "TUNNEL_ENABLE"},
11720    {"bits": [14, 14], "name": "RESTORE"},
11721    {"bits": [15, 15], "name": "CS_W32_EN"}
11722   ]
11723  },
11724  "COMPUTE_DISPATCH_TUNNEL": {
11725   "fields": [
11726    {"bits": [0, 9], "name": "OFF_DELAY"},
11727    {"bits": [10, 10], "name": "IMMEDIATE"}
11728   ]
11729  },
11730  "COMPUTE_MISC_RESERVED": {
11731   "fields": [
11732    {"bits": [0, 1], "name": "SEND_SEID"},
11733    {"bits": [2, 2], "name": "RESERVED2"},
11734    {"bits": [3, 3], "name": "RESERVED3"},
11735    {"bits": [4, 4], "name": "RESERVED4"},
11736    {"bits": [5, 16], "name": "WAVE_ID_BASE"}
11737   ]
11738  },
11739  "COMPUTE_NUM_THREAD_X": {
11740   "fields": [
11741    {"bits": [0, 15], "name": "NUM_THREAD_FULL"},
11742    {"bits": [16, 31], "name": "NUM_THREAD_PARTIAL"}
11743   ]
11744  },
11745  "COMPUTE_PERFCOUNT_ENABLE": {
11746   "fields": [
11747    {"bits": [0, 0], "name": "PERFCOUNT_ENABLE"}
11748   ]
11749  },
11750  "COMPUTE_PGM_HI": {
11751   "fields": [
11752    {"bits": [0, 7], "name": "DATA"}
11753   ]
11754  },
11755  "COMPUTE_PGM_RSRC1": {
11756   "fields": [
11757    {"bits": [0, 5], "name": "VGPRS"},
11758    {"bits": [6, 9], "name": "SGPRS"},
11759    {"bits": [10, 11], "name": "PRIORITY"},
11760    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
11761    {"bits": [20, 20], "name": "PRIV"},
11762    {"bits": [21, 21], "name": "DX10_CLAMP"},
11763    {"bits": [23, 23], "name": "IEEE_MODE"},
11764    {"bits": [24, 24], "name": "BULKY"},
11765    {"bits": [26, 26], "name": "FP16_OVFL"},
11766    {"bits": [29, 29], "name": "WGP_MODE"},
11767    {"bits": [30, 30], "name": "MEM_ORDERED"},
11768    {"bits": [31, 31], "name": "FWD_PROGRESS"}
11769   ]
11770  },
11771  "COMPUTE_PGM_RSRC2": {
11772   "fields": [
11773    {"bits": [0, 0], "name": "SCRATCH_EN"},
11774    {"bits": [1, 5], "name": "USER_SGPR"},
11775    {"bits": [6, 6], "name": "TRAP_PRESENT"},
11776    {"bits": [7, 7], "name": "TGID_X_EN"},
11777    {"bits": [8, 8], "name": "TGID_Y_EN"},
11778    {"bits": [9, 9], "name": "TGID_Z_EN"},
11779    {"bits": [10, 10], "name": "TG_SIZE_EN"},
11780    {"bits": [11, 12], "name": "TIDIG_COMP_CNT"},
11781    {"bits": [13, 14], "name": "EXCP_EN_MSB"},
11782    {"bits": [15, 23], "name": "LDS_SIZE"},
11783    {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
11784   ]
11785  },
11786  "COMPUTE_PGM_RSRC3": {
11787   "fields": [
11788    {"bits": [0, 3], "name": "SHARED_VGPR_CNT"}
11789   ]
11790  },
11791  "COMPUTE_PIPELINESTAT_ENABLE": {
11792   "fields": [
11793    {"bits": [0, 0], "name": "PIPELINESTAT_ENABLE"}
11794   ]
11795  },
11796  "COMPUTE_RELAUNCH": {
11797   "fields": [
11798    {"bits": [0, 29], "name": "PAYLOAD"},
11799    {"bits": [30, 30], "name": "IS_EVENT"},
11800    {"bits": [31, 31], "name": "IS_STATE"}
11801   ]
11802  },
11803  "COMPUTE_REQ_CTRL": {
11804   "fields": [
11805    {"bits": [0, 0], "name": "SOFT_GROUPING_EN"},
11806    {"bits": [1, 4], "name": "NUMBER_OF_REQUESTS_PER_CU"},
11807    {"bits": [5, 8], "name": "SOFT_GROUPING_ALLOCATION_TIMEOUT"},
11808    {"bits": [9, 9], "name": "HARD_LOCK_HYSTERESIS"},
11809    {"bits": [10, 14], "name": "HARD_LOCK_LOW_THRESHOLD"},
11810    {"bits": [15, 15], "name": "PRODUCER_REQUEST_LOCKOUT"},
11811    {"bits": [16, 16], "name": "GLOBAL_SCANNING_EN"},
11812    {"bits": [17, 19], "name": "ALLOCATION_RATE_THROTTLING_THRESHOLD"},
11813    {"bits": [20, 26], "name": "DEDICATED_PREALLOCATION_BUFFER_LIMIT"}
11814   ]
11815  },
11816  "COMPUTE_RESOURCE_LIMITS": {
11817   "fields": [
11818    {"bits": [0, 9], "name": "WAVES_PER_SH"},
11819    {"bits": [12, 15], "name": "TG_PER_CU"},
11820    {"bits": [16, 21], "name": "LOCK_THRESHOLD"},
11821    {"bits": [22, 22], "name": "SIMD_DEST_CNTL"},
11822    {"bits": [23, 23], "name": "FORCE_SIMD_DIST"},
11823    {"bits": [24, 26], "name": "CU_GROUP_COUNT"}
11824   ]
11825  },
11826  "COMPUTE_THREAD_TRACE_ENABLE": {
11827   "fields": [
11828    {"bits": [0, 0], "name": "THREAD_TRACE_ENABLE"}
11829   ]
11830  },
11831  "COMPUTE_TMPRING_SIZE": {
11832   "fields": [
11833    {"bits": [0, 11], "name": "WAVES"},
11834    {"bits": [12, 24], "name": "WAVESIZE"}
11835   ]
11836  },
11837  "COMPUTE_VMID": {
11838   "fields": [
11839    {"bits": [0, 3], "name": "DATA"}
11840   ]
11841  },
11842  "COMPUTE_WAVE_RESTORE_ADDR_HI": {
11843   "fields": [
11844    {"bits": [0, 15], "name": "ADDR"}
11845   ]
11846  },
11847  "CPF_LATENCY_STATS_SELECT": {
11848   "fields": [
11849    {"bits": [0, 3], "name": "INDEX"},
11850    {"bits": [30, 30], "name": "CLEAR"},
11851    {"bits": [31, 31], "name": "ENABLE"}
11852   ]
11853  },
11854  "CPF_TC_PERF_COUNTER_WINDOW_SELECT": {
11855   "fields": [
11856    {"bits": [0, 2], "name": "INDEX"},
11857    {"bits": [30, 30], "name": "ALWAYS"},
11858    {"bits": [31, 31], "name": "ENABLE"}
11859   ]
11860  },
11861  "CPG_LATENCY_STATS_SELECT": {
11862   "fields": [
11863    {"bits": [0, 4], "name": "INDEX"},
11864    {"bits": [30, 30], "name": "CLEAR"},
11865    {"bits": [31, 31], "name": "ENABLE"}
11866   ]
11867  },
11868  "CPG_PERFCOUNTER0_SELECT1": {
11869   "fields": [
11870    {"bits": [0, 9], "name": "PERF_SEL2"},
11871    {"bits": [10, 19], "name": "PERF_SEL3"},
11872    {"bits": [24, 27], "name": "CNTR_MODE3"},
11873    {"bits": [28, 31], "name": "CNTR_MODE2"}
11874   ]
11875  },
11876  "CPG_PERFCOUNTER1_SELECT": {
11877   "fields": [
11878    {"bits": [0, 9], "name": "PERF_SEL"},
11879    {"bits": [10, 19], "name": "PERF_SEL1"},
11880    {"bits": [20, 23], "name": "SPM_MODE"},
11881    {"bits": [24, 27], "name": "CNTR_MODE1"},
11882    {"bits": [28, 31], "name": "CNTR_MODE0"}
11883   ]
11884  },
11885  "CPG_TC_PERF_COUNTER_WINDOW_SELECT": {
11886   "fields": [
11887    {"bits": [0, 4], "name": "INDEX"},
11888    {"bits": [30, 30], "name": "ALWAYS"},
11889    {"bits": [31, 31], "name": "ENABLE"}
11890   ]
11891  },
11892  "CP_APPEND_ADDR_HI": {
11893   "fields": [
11894    {"bits": [0, 15], "name": "MEM_ADDR_HI"},
11895    {"bits": [16, 16], "name": "CS_PS_SEL"},
11896    {"bits": [25, 26], "name": "CACHE_POLICY"},
11897    {"bits": [29, 31], "name": "COMMAND"}
11898   ]
11899  },
11900  "CP_APPEND_ADDR_LO": {
11901   "fields": [
11902    {"bits": [2, 31], "name": "MEM_ADDR_LO"}
11903   ]
11904  },
11905  "CP_CE_IB1_BASE_HI": {
11906   "fields": [
11907    {"bits": [0, 15], "name": "IB1_BASE_HI"}
11908   ]
11909  },
11910  "CP_CE_IB1_BASE_LO": {
11911   "fields": [
11912    {"bits": [2, 31], "name": "IB1_BASE_LO"}
11913   ]
11914  },
11915  "CP_CE_IB1_BUFSZ": {
11916   "fields": [
11917    {"bits": [0, 19], "name": "IB1_BUFSZ"}
11918   ]
11919  },
11920  "CP_CE_IB1_CMD_BUFSZ": {
11921   "fields": [
11922    {"bits": [0, 19], "name": "IB1_CMD_REQSZ"}
11923   ]
11924  },
11925  "CP_CE_IB1_OFFSET": {
11926   "fields": [
11927    {"bits": [0, 19], "name": "IB1_OFFSET"}
11928   ]
11929  },
11930  "CP_CE_IB2_BASE_HI": {
11931   "fields": [
11932    {"bits": [0, 15], "name": "IB2_BASE_HI"}
11933   ]
11934  },
11935  "CP_CE_IB2_BASE_LO": {
11936   "fields": [
11937    {"bits": [2, 31], "name": "IB2_BASE_LO"}
11938   ]
11939  },
11940  "CP_CE_IB2_BUFSZ": {
11941   "fields": [
11942    {"bits": [0, 19], "name": "IB2_BUFSZ"}
11943   ]
11944  },
11945  "CP_CE_IB2_CMD_BUFSZ": {
11946   "fields": [
11947    {"bits": [0, 19], "name": "IB2_CMD_REQSZ"}
11948   ]
11949  },
11950  "CP_CE_INIT_BASE_HI": {
11951   "fields": [
11952    {"bits": [0, 15], "name": "INIT_BASE_HI"}
11953   ]
11954  },
11955  "CP_CE_INIT_BASE_LO": {
11956   "fields": [
11957    {"bits": [5, 31], "name": "INIT_BASE_LO"}
11958   ]
11959  },
11960  "CP_CE_INIT_BUFSZ": {
11961   "fields": [
11962    {"bits": [0, 11], "name": "INIT_BUFSZ"}
11963   ]
11964  },
11965  "CP_CE_INIT_CMD_BUFSZ": {
11966   "fields": [
11967    {"bits": [0, 11], "name": "INIT_CMD_REQSZ"}
11968   ]
11969  },
11970  "CP_COHER_BASE_HI": {
11971   "fields": [
11972    {"bits": [0, 7], "name": "COHER_BASE_HI_256B"}
11973   ]
11974  },
11975  "CP_COHER_CNTL": {
11976   "fields": [
11977    {"bits": [3, 3], "name": "TC_NC_ACTION_ENA"},
11978    {"bits": [4, 4], "name": "TC_WC_ACTION_ENA"},
11979    {"bits": [5, 5], "name": "TC_INV_METADATA_ACTION_ENA"},
11980    {"bits": [15, 15], "name": "TCL1_VOL_ACTION_ENA"},
11981    {"bits": [18, 18], "name": "TC_WB_ACTION_ENA"},
11982    {"bits": [22, 22], "name": "TCL1_ACTION_ENA"},
11983    {"bits": [23, 23], "name": "TC_ACTION_ENA"},
11984    {"bits": [25, 25], "name": "CB_ACTION_ENA"},
11985    {"bits": [26, 26], "name": "DB_ACTION_ENA"},
11986    {"bits": [27, 27], "name": "SH_KCACHE_ACTION_ENA"},
11987    {"bits": [28, 28], "name": "SH_KCACHE_VOL_ACTION_ENA"},
11988    {"bits": [29, 29], "name": "SH_ICACHE_ACTION_ENA"},
11989    {"bits": [30, 30], "name": "SH_KCACHE_WB_ACTION_ENA"}
11990   ]
11991  },
11992  "CP_COHER_SIZE_HI": {
11993   "fields": [
11994    {"bits": [0, 7], "name": "COHER_SIZE_HI_256B"}
11995   ]
11996  },
11997  "CP_COHER_START_DELAY": {
11998   "fields": [
11999    {"bits": [0, 5], "name": "START_DELAY_COUNT"}
12000   ]
12001  },
12002  "CP_COHER_STATUS": {
12003   "fields": [
12004    {"bits": [24, 25], "name": "MEID"},
12005    {"bits": [31, 31], "name": "STATUS"}
12006   ]
12007  },
12008  "CP_CPC_BUSY_STAT": {
12009   "fields": [
12010    {"bits": [0, 0], "name": "MEC1_LOAD_BUSY"},
12011    {"bits": [1, 1], "name": "MEC1_SEMAPOHRE_BUSY"},
12012    {"bits": [2, 2], "name": "MEC1_MUTEX_BUSY"},
12013    {"bits": [3, 3], "name": "MEC1_MESSAGE_BUSY"},
12014    {"bits": [4, 4], "name": "MEC1_EOP_QUEUE_BUSY"},
12015    {"bits": [5, 5], "name": "MEC1_IQ_QUEUE_BUSY"},
12016    {"bits": [6, 6], "name": "MEC1_IB_QUEUE_BUSY"},
12017    {"bits": [7, 7], "name": "MEC1_TC_BUSY"},
12018    {"bits": [8, 8], "name": "MEC1_DMA_BUSY"},
12019    {"bits": [9, 9], "name": "MEC1_PARTIAL_FLUSH_BUSY"},
12020    {"bits": [10, 10], "name": "MEC1_PIPE0_BUSY"},
12021    {"bits": [11, 11], "name": "MEC1_PIPE1_BUSY"},
12022    {"bits": [12, 12], "name": "MEC1_PIPE2_BUSY"},
12023    {"bits": [13, 13], "name": "MEC1_PIPE3_BUSY"},
12024    {"bits": [16, 16], "name": "MEC2_LOAD_BUSY"},
12025    {"bits": [17, 17], "name": "MEC2_SEMAPOHRE_BUSY"},
12026    {"bits": [18, 18], "name": "MEC2_MUTEX_BUSY"},
12027    {"bits": [19, 19], "name": "MEC2_MESSAGE_BUSY"},
12028    {"bits": [20, 20], "name": "MEC2_EOP_QUEUE_BUSY"},
12029    {"bits": [21, 21], "name": "MEC2_IQ_QUEUE_BUSY"},
12030    {"bits": [22, 22], "name": "MEC2_IB_QUEUE_BUSY"},
12031    {"bits": [23, 23], "name": "MEC2_TC_BUSY"},
12032    {"bits": [24, 24], "name": "MEC2_DMA_BUSY"},
12033    {"bits": [25, 25], "name": "MEC2_PARTIAL_FLUSH_BUSY"},
12034    {"bits": [26, 26], "name": "MEC2_PIPE0_BUSY"},
12035    {"bits": [27, 27], "name": "MEC2_PIPE1_BUSY"},
12036    {"bits": [28, 28], "name": "MEC2_PIPE2_BUSY"},
12037    {"bits": [29, 29], "name": "MEC2_PIPE3_BUSY"}
12038   ]
12039  },
12040  "CP_CPC_BUSY_STAT2": {
12041   "fields": [
12042    {"bits": [0, 0], "name": "MES_LOAD_BUSY"},
12043    {"bits": [2, 2], "name": "MES_MUTEX_BUSY"},
12044    {"bits": [3, 3], "name": "MES_MESSAGE_BUSY"},
12045    {"bits": [7, 7], "name": "MES_TC_BUSY"},
12046    {"bits": [8, 8], "name": "MES_DMA_BUSY"},
12047    {"bits": [10, 10], "name": "MES_PIPE0_BUSY"},
12048    {"bits": [11, 11], "name": "MES_PIPE1_BUSY"},
12049    {"bits": [12, 12], "name": "MES_PIPE2_BUSY"},
12050    {"bits": [13, 13], "name": "MES_PIPE3_BUSY"}
12051   ]
12052  },
12053  "CP_CPC_GRBM_FREE_COUNT": {
12054   "fields": [
12055    {"bits": [0, 5], "name": "FREE_COUNT"}
12056   ]
12057  },
12058  "CP_CPC_HALT_HYST_COUNT": {
12059   "fields": [
12060    {"bits": [0, 3], "name": "COUNT"}
12061   ]
12062  },
12063  "CP_CPC_PRIV_VIOLATION_ADDR": {
12064   "fields": [
12065    {"bits": [0, 15], "name": "PRIV_VIOLATION_ADDR"}
12066   ]
12067  },
12068  "CP_CPC_SCRATCH_INDEX": {
12069   "fields": [
12070    {"bits": [0, 8], "name": "SCRATCH_INDEX"},
12071    {"bits": [31, 31], "name": "SCRATCH_INDEX_64BIT_MODE"}
12072   ]
12073  },
12074  "CP_CPC_STALLED_STAT1": {
12075   "fields": [
12076    {"bits": [3, 3], "name": "RCIU_TX_FREE_STALL"},
12077    {"bits": [4, 4], "name": "RCIU_PRIV_VIOLATION"},
12078    {"bits": [6, 6], "name": "TCIU_TX_FREE_STALL"},
12079    {"bits": [8, 8], "name": "MEC1_DECODING_PACKET"},
12080    {"bits": [9, 9], "name": "MEC1_WAIT_ON_RCIU"},
12081    {"bits": [10, 10], "name": "MEC1_WAIT_ON_RCIU_READ"},
12082    {"bits": [13, 13], "name": "MEC1_WAIT_ON_ROQ_DATA"},
12083    {"bits": [16, 16], "name": "MEC2_DECODING_PACKET"},
12084    {"bits": [17, 17], "name": "MEC2_WAIT_ON_RCIU"},
12085    {"bits": [18, 18], "name": "MEC2_WAIT_ON_RCIU_READ"},
12086    {"bits": [21, 21], "name": "MEC2_WAIT_ON_ROQ_DATA"},
12087    {"bits": [22, 22], "name": "UTCL2IU_WAITING_ON_FREE"},
12088    {"bits": [23, 23], "name": "UTCL2IU_WAITING_ON_TAGS"},
12089    {"bits": [24, 24], "name": "UTCL1_WAITING_ON_TRANS"},
12090    {"bits": [25, 25], "name": "GCRIU_WAITING_ON_FREE"}
12091   ]
12092  },
12093  "CP_CPC_STATUS": {
12094   "fields": [
12095    {"bits": [0, 0], "name": "MEC1_BUSY"},
12096    {"bits": [1, 1], "name": "MEC2_BUSY"},
12097    {"bits": [2, 2], "name": "DC0_BUSY"},
12098    {"bits": [3, 3], "name": "DC1_BUSY"},
12099    {"bits": [4, 4], "name": "RCIU1_BUSY"},
12100    {"bits": [5, 5], "name": "RCIU2_BUSY"},
12101    {"bits": [6, 6], "name": "ROQ1_BUSY"},
12102    {"bits": [7, 7], "name": "ROQ2_BUSY"},
12103    {"bits": [10, 10], "name": "TCIU_BUSY"},
12104    {"bits": [11, 11], "name": "SCRATCH_RAM_BUSY"},
12105    {"bits": [12, 12], "name": "QU_BUSY"},
12106    {"bits": [13, 13], "name": "UTCL2IU_BUSY"},
12107    {"bits": [14, 14], "name": "SAVE_RESTORE_BUSY"},
12108    {"bits": [15, 15], "name": "GCRIU_BUSY"},
12109    {"bits": [16, 16], "name": "MES_BUSY"},
12110    {"bits": [17, 17], "name": "MES_SCRATCH_RAM_BUSY"},
12111    {"bits": [18, 18], "name": "RCIU3_BUSY"},
12112    {"bits": [19, 19], "name": "MES_INSTRUCTION_CACHE_BUSY"},
12113    {"bits": [29, 29], "name": "CPG_CPC_BUSY"},
12114    {"bits": [30, 30], "name": "CPF_CPC_BUSY"},
12115    {"bits": [31, 31], "name": "CPC_BUSY"}
12116   ]
12117  },
12118  "CP_CPF_BUSY_STAT": {
12119   "fields": [
12120    {"bits": [0, 0], "name": "REG_BUS_FIFO_BUSY"},
12121    {"bits": [1, 1], "name": "CSF_RING_BUSY"},
12122    {"bits": [2, 2], "name": "CSF_INDIRECT1_BUSY"},
12123    {"bits": [3, 3], "name": "CSF_INDIRECT2_BUSY"},
12124    {"bits": [4, 4], "name": "CSF_STATE_BUSY"},
12125    {"bits": [5, 5], "name": "CSF_CE_INDR1_BUSY"},
12126    {"bits": [6, 6], "name": "CSF_CE_INDR2_BUSY"},
12127    {"bits": [7, 7], "name": "CSF_ARBITER_BUSY"},
12128    {"bits": [8, 8], "name": "CSF_INPUT_BUSY"},
12129    {"bits": [9, 9], "name": "CSF_DATA_BUSY"},
12130    {"bits": [10, 10], "name": "CSF_CE_DATA_BUSY"},
12131    {"bits": [11, 11], "name": "HPD_PROCESSING_EOP_BUSY"},
12132    {"bits": [12, 12], "name": "HQD_DISPATCH_BUSY"},
12133    {"bits": [13, 13], "name": "HQD_IQ_TIMER_BUSY"},
12134    {"bits": [14, 14], "name": "HQD_DMA_OFFLOAD_BUSY"},
12135    {"bits": [15, 15], "name": "HQD_WAIT_SEMAPHORE_BUSY"},
12136    {"bits": [16, 16], "name": "HQD_SIGNAL_SEMAPHORE_BUSY"},
12137    {"bits": [17, 17], "name": "HQD_MESSAGE_BUSY"},
12138    {"bits": [18, 18], "name": "HQD_PQ_FETCHER_BUSY"},
12139    {"bits": [19, 19], "name": "HQD_IB_FETCHER_BUSY"},
12140    {"bits": [20, 20], "name": "HQD_IQ_FETCHER_BUSY"},
12141    {"bits": [21, 21], "name": "HQD_EOP_FETCHER_BUSY"},
12142    {"bits": [22, 22], "name": "HQD_CONSUMED_RPTR_BUSY"},
12143    {"bits": [23, 23], "name": "HQD_FETCHER_ARB_BUSY"},
12144    {"bits": [24, 24], "name": "HQD_ROQ_ALIGN_BUSY"},
12145    {"bits": [25, 25], "name": "HQD_ROQ_EOP_BUSY"},
12146    {"bits": [26, 26], "name": "HQD_ROQ_IQ_BUSY"},
12147    {"bits": [27, 27], "name": "HQD_ROQ_PQ_BUSY"},
12148    {"bits": [28, 28], "name": "HQD_ROQ_IB_BUSY"},
12149    {"bits": [29, 29], "name": "HQD_WPTR_POLL_BUSY"},
12150    {"bits": [30, 30], "name": "HQD_PQ_BUSY"},
12151    {"bits": [31, 31], "name": "HQD_IB_BUSY"}
12152   ]
12153  },
12154  "CP_CPF_BUSY_STAT2": {
12155   "fields": [
12156    {"bits": [12, 12], "name": "MES_HQD_DISPATCH_BUSY"},
12157    {"bits": [14, 14], "name": "MES_HQD_DMA_OFFLOAD_BUSY"},
12158    {"bits": [17, 17], "name": "MES_HQD_MESSAGE_BUSY"},
12159    {"bits": [18, 18], "name": "MES_HQD_PQ_FETCHER_BUSY"},
12160    {"bits": [22, 22], "name": "MES_HQD_CONSUMED_RPTR_BUSY"},
12161    {"bits": [23, 23], "name": "MES_HQD_FETCHER_ARB_BUSY"},
12162    {"bits": [24, 24], "name": "MES_HQD_ROQ_ALIGN_BUSY"},
12163    {"bits": [27, 27], "name": "MES_HQD_ROQ_PQ_BUSY"},
12164    {"bits": [30, 30], "name": "MES_HQD_PQ_BUSY"}
12165   ]
12166  },
12167  "CP_CPF_GRBM_FREE_COUNT": {
12168   "fields": [
12169    {"bits": [0, 2], "name": "FREE_COUNT"}
12170   ]
12171  },
12172  "CP_CPF_STALLED_STAT1": {
12173   "fields": [
12174    {"bits": [0, 0], "name": "RING_FETCHING_DATA"},
12175    {"bits": [1, 1], "name": "INDR1_FETCHING_DATA"},
12176    {"bits": [2, 2], "name": "INDR2_FETCHING_DATA"},
12177    {"bits": [3, 3], "name": "STATE_FETCHING_DATA"},
12178    {"bits": [5, 5], "name": "TCIU_WAITING_ON_FREE"},
12179    {"bits": [6, 6], "name": "TCIU_WAITING_ON_TAGS"},
12180    {"bits": [7, 7], "name": "UTCL2IU_WAITING_ON_FREE"},
12181    {"bits": [8, 8], "name": "UTCL2IU_WAITING_ON_TAGS"},
12182    {"bits": [9, 9], "name": "GFX_UTCL1_WAITING_ON_TRANS"},
12183    {"bits": [10, 10], "name": "CMP_UTCL1_WAITING_ON_TRANS"},
12184    {"bits": [11, 11], "name": "RCIU_WAITING_ON_FREE"},
12185    {"bits": [12, 12], "name": "DATA_FETCHING_DATA"},
12186    {"bits": [13, 13], "name": "GCRIU_WAIT_ON_FREE"}
12187   ]
12188  },
12189  "CP_CPF_STATUS": {
12190   "fields": [
12191    {"bits": [0, 0], "name": "POST_WPTR_GFX_BUSY"},
12192    {"bits": [1, 1], "name": "CSF_BUSY"},
12193    {"bits": [4, 4], "name": "ROQ_ALIGN_BUSY"},
12194    {"bits": [5, 5], "name": "ROQ_RING_BUSY"},
12195    {"bits": [6, 6], "name": "ROQ_INDIRECT1_BUSY"},
12196    {"bits": [7, 7], "name": "ROQ_INDIRECT2_BUSY"},
12197    {"bits": [8, 8], "name": "ROQ_STATE_BUSY"},
12198    {"bits": [9, 9], "name": "ROQ_CE_RING_BUSY"},
12199    {"bits": [10, 10], "name": "ROQ_CE_INDIRECT1_BUSY"},
12200    {"bits": [11, 11], "name": "ROQ_CE_INDIRECT2_BUSY"},
12201    {"bits": [12, 12], "name": "SEMAPHORE_BUSY"},
12202    {"bits": [13, 13], "name": "INTERRUPT_BUSY"},
12203    {"bits": [14, 14], "name": "TCIU_BUSY"},
12204    {"bits": [15, 15], "name": "HQD_BUSY"},
12205    {"bits": [16, 16], "name": "PRT_BUSY"},
12206    {"bits": [17, 17], "name": "UTCL2IU_BUSY"},
12207    {"bits": [18, 18], "name": "RCIU_BUSY"},
12208    {"bits": [19, 19], "name": "RCIU_GFX_BUSY"},
12209    {"bits": [20, 20], "name": "RCIU_CMP_BUSY"},
12210    {"bits": [21, 21], "name": "ROQ_DATA_BUSY"},
12211    {"bits": [22, 22], "name": "ROQ_CE_DATA_BUSY"},
12212    {"bits": [23, 23], "name": "GCRIU_BUSY"},
12213    {"bits": [24, 24], "name": "MES_HQD_BUSY"},
12214    {"bits": [26, 26], "name": "CPF_GFX_BUSY"},
12215    {"bits": [27, 27], "name": "CPF_CMP_BUSY"},
12216    {"bits": [28, 29], "name": "GRBM_CPF_STAT_BUSY"},
12217    {"bits": [30, 30], "name": "CPC_CPF_BUSY"},
12218    {"bits": [31, 31], "name": "CPF_BUSY"}
12219   ]
12220  },
12221  "CP_DB_BASE_HI": {
12222   "fields": [
12223    {"bits": [0, 15], "name": "DB_BASE_HI"}
12224   ]
12225  },
12226  "CP_DB_BASE_LO": {
12227   "fields": [
12228    {"bits": [2, 31], "name": "DB_BASE_LO"}
12229   ]
12230  },
12231  "CP_DB_BUFSZ": {
12232   "fields": [
12233    {"bits": [0, 19], "name": "DB_BUFSZ"}
12234   ]
12235  },
12236  "CP_DB_CMD_BUFSZ": {
12237   "fields": [
12238    {"bits": [0, 19], "name": "DB_CMD_REQSZ"}
12239   ]
12240  },
12241  "CP_DMA_CNTL": {
12242   "fields": [
12243    {"bits": [0, 0], "name": "UTCL1_FAULT_CONTROL"},
12244    {"bits": [1, 1], "name": "WATCH_CONTROL"},
12245    {"bits": [4, 5], "name": "MIN_AVAILSZ"},
12246    {"bits": [16, 24], "name": "BUFFER_DEPTH"},
12247    {"bits": [28, 28], "name": "PIO_FIFO_EMPTY"},
12248    {"bits": [29, 29], "name": "PIO_FIFO_FULL"},
12249    {"bits": [30, 31], "name": "PIO_COUNT"}
12250   ]
12251  },
12252  "CP_DMA_ME_CMD_ADDR_HI": {
12253   "fields": [
12254    {"bits": [0, 15], "name": "ADDR_HI"},
12255    {"bits": [16, 31], "name": "RSVD"}
12256   ]
12257  },
12258  "CP_DMA_ME_CMD_ADDR_LO": {
12259   "fields": [
12260    {"bits": [0, 1], "name": "RSVD"},
12261    {"bits": [2, 31], "name": "ADDR_LO"}
12262   ]
12263  },
12264  "CP_DMA_ME_COMMAND": {
12265   "fields": [
12266    {"bits": [0, 25], "name": "BYTE_COUNT"},
12267    {"bits": [26, 26], "name": "SAS"},
12268    {"bits": [27, 27], "name": "DAS"},
12269    {"bits": [28, 28], "name": "SAIC"},
12270    {"bits": [29, 29], "name": "DAIC"},
12271    {"bits": [30, 30], "name": "RAW_WAIT"},
12272    {"bits": [31, 31], "name": "DIS_WC"}
12273   ]
12274  },
12275  "CP_DMA_ME_DST_ADDR_HI": {
12276   "fields": [
12277    {"bits": [0, 15], "name": "DST_ADDR_HI"}
12278   ]
12279  },
12280  "CP_DMA_ME_SRC_ADDR_HI": {
12281   "fields": [
12282    {"bits": [0, 15], "name": "SRC_ADDR_HI"}
12283   ]
12284  },
12285  "CP_DMA_PFP_CONTROL": {
12286   "fields": [
12287    {"bits": [10, 10], "name": "MEMLOG_CLEAR"},
12288    {"bits": [13, 14], "name": "SRC_CACHE_POLICY"},
12289    {"bits": [15, 15], "name": "SRC_VOLATLE"},
12290    {"bits": [20, 21], "name": "DST_SELECT"},
12291    {"bits": [25, 26], "name": "DST_CACHE_POLICY"},
12292    {"bits": [27, 27], "name": "DST_VOLATLE"},
12293    {"bits": [29, 30], "name": "SRC_SELECT"}
12294   ]
12295  },
12296  "CP_DMA_READ_TAGS": {
12297   "fields": [
12298    {"bits": [0, 25], "name": "DMA_READ_TAG"},
12299    {"bits": [28, 28], "name": "DMA_READ_TAG_VALID"}
12300   ]
12301  },
12302  "CP_DRAW_WINDOW_CNTL": {
12303   "fields": [
12304    {"bits": [0, 0], "name": "DISABLE_DRAW_WINDOW_LO_MAX"},
12305    {"bits": [1, 1], "name": "DISABLE_DRAW_WINDOW_LO_MIN"},
12306    {"bits": [2, 2], "name": "DISABLE_DRAW_WINDOW_HI"},
12307    {"bits": [8, 8], "name": "MODE"}
12308   ]
12309  },
12310  "CP_DRAW_WINDOW_LO": {
12311   "fields": [
12312    {"bits": [0, 15], "name": "MIN"},
12313    {"bits": [16, 31], "name": "MAX"}
12314   ]
12315  },
12316  "CP_EOP_DONE_ADDR_HI": {
12317   "fields": [
12318    {"bits": [0, 15], "name": "ADDR_HI"}
12319   ]
12320  },
12321  "CP_EOP_DONE_ADDR_LO": {
12322   "fields": [
12323    {"bits": [2, 31], "name": "ADDR_LO"}
12324   ]
12325  },
12326  "CP_EOP_DONE_DATA_CNTL": {
12327   "fields": [
12328    {"bits": [16, 17], "name": "DST_SEL"},
12329    {"bits": [20, 21], "name": "ACTION_PIPE_ID"},
12330    {"bits": [22, 23], "name": "ACTION_ID"},
12331    {"bits": [24, 26], "name": "INT_SEL"},
12332    {"bits": [29, 31], "name": "DATA_SEL"}
12333   ]
12334  },
12335  "CP_EOP_DONE_EVENT_CNTL": {
12336   "fields": [
12337    {"bits": [12, 23], "name": "GCR_CNTL"},
12338    {"bits": [25, 26], "name": "CACHE_POLICY"},
12339    {"bits": [27, 27], "name": "EOP_VOLATILE"},
12340    {"bits": [28, 28], "name": "EXECUTE"}
12341   ]
12342  },
12343  "CP_IB2_OFFSET": {
12344   "fields": [
12345    {"bits": [0, 19], "name": "IB2_OFFSET"}
12346   ]
12347  },
12348  "CP_IB2_PREAMBLE_BEGIN": {
12349   "fields": [
12350    {"bits": [0, 19], "name": "IB2_PREAMBLE_BEGIN"}
12351   ]
12352  },
12353  "CP_IB2_PREAMBLE_END": {
12354   "fields": [
12355    {"bits": [0, 19], "name": "IB2_PREAMBLE_END"}
12356   ]
12357  },
12358  "CP_INDEX_TYPE": {
12359   "fields": [
12360    {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}
12361   ]
12362  },
12363  "CP_ME_COHER_CNTL": {
12364   "fields": [
12365    {"bits": [0, 0], "name": "DEST_BASE_0_ENA"},
12366    {"bits": [1, 1], "name": "DEST_BASE_1_ENA"},
12367    {"bits": [6, 6], "name": "CB0_DEST_BASE_ENA"},
12368    {"bits": [7, 7], "name": "CB1_DEST_BASE_ENA"},
12369    {"bits": [8, 8], "name": "CB2_DEST_BASE_ENA"},
12370    {"bits": [9, 9], "name": "CB3_DEST_BASE_ENA"},
12371    {"bits": [10, 10], "name": "CB4_DEST_BASE_ENA"},
12372    {"bits": [11, 11], "name": "CB5_DEST_BASE_ENA"},
12373    {"bits": [12, 12], "name": "CB6_DEST_BASE_ENA"},
12374    {"bits": [13, 13], "name": "CB7_DEST_BASE_ENA"},
12375    {"bits": [14, 14], "name": "DB_DEST_BASE_ENA"},
12376    {"bits": [19, 19], "name": "DEST_BASE_2_ENA"},
12377    {"bits": [21, 21], "name": "DEST_BASE_3_ENA"}
12378   ]
12379  },
12380  "CP_ME_COHER_STATUS": {
12381   "fields": [
12382    {"bits": [0, 7], "name": "MATCHING_GFX_CNTX"},
12383    {"bits": [31, 31], "name": "STATUS"}
12384   ]
12385  },
12386  "CP_ME_MC_RADDR_HI": {
12387   "fields": [
12388    {"bits": [0, 15], "name": "ME_MC_RADDR_HI"},
12389    {"bits": [22, 23], "name": "CACHE_POLICY"}
12390   ]
12391  },
12392  "CP_ME_MC_RADDR_LO": {
12393   "fields": [
12394    {"bits": [2, 31], "name": "ME_MC_RADDR_LO"}
12395   ]
12396  },
12397  "CP_ME_MC_WADDR_HI": {
12398   "fields": [
12399    {"bits": [0, 15], "name": "ME_MC_WADDR_HI"},
12400    {"bits": [22, 23], "name": "CACHE_POLICY"}
12401   ]
12402  },
12403  "CP_ME_MC_WADDR_LO": {
12404   "fields": [
12405    {"bits": [2, 31], "name": "ME_MC_WADDR_LO"}
12406   ]
12407  },
12408  "CP_PERFMON_CNTL": {
12409   "fields": [
12410    {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"},
12411    {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"},
12412    {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"},
12413    {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"}
12414   ]
12415  },
12416  "CP_PERFMON_CNTX_CNTL": {
12417   "fields": [
12418    {"bits": [31, 31], "name": "PERFMON_ENABLE"}
12419   ]
12420  },
12421  "CP_PFP_COMPLETION_STATUS": {
12422   "fields": [
12423    {"bits": [0, 1], "name": "STATUS"}
12424   ]
12425  },
12426  "CP_PFP_IB_CONTROL": {
12427   "fields": [
12428    {"bits": [0, 7], "name": "IB_EN"}
12429   ]
12430  },
12431  "CP_PFP_LOAD_CONTROL": {
12432   "fields": [
12433    {"bits": [0, 0], "name": "CONFIG_REG_EN"},
12434    {"bits": [1, 1], "name": "CNTX_REG_EN"},
12435    {"bits": [15, 15], "name": "UCONFIG_REG_EN"},
12436    {"bits": [16, 16], "name": "SH_GFX_REG_EN"},
12437    {"bits": [24, 24], "name": "SH_CS_REG_EN"}
12438   ]
12439  },
12440  "CP_PIPEID": {
12441   "fields": [
12442    {"bits": [0, 1], "name": "PIPE_ID"}
12443   ]
12444  },
12445  "CP_PIPE_STATS_ADDR_HI": {
12446   "fields": [
12447    {"bits": [0, 15], "name": "PIPE_STATS_ADDR_HI"}
12448   ]
12449  },
12450  "CP_PIPE_STATS_ADDR_LO": {
12451   "fields": [
12452    {"bits": [2, 31], "name": "PIPE_STATS_ADDR_LO"}
12453   ]
12454  },
12455  "CP_PIPE_STATS_CONTROL": {
12456   "fields": [
12457    {"bits": [25, 26], "name": "CACHE_POLICY"}
12458   ]
12459  },
12460  "CP_PRED_NOT_VISIBLE": {
12461   "fields": [
12462    {"bits": [0, 0], "name": "NOT_VISIBLE"}
12463   ]
12464  },
12465  "CP_RB_OFFSET": {
12466   "fields": [
12467    {"bits": [0, 19], "name": "RB_OFFSET"}
12468   ]
12469  },
12470  "CP_SAMPLE_STATUS": {
12471   "fields": [
12472    {"bits": [0, 0], "name": "Z_PASS_ACITVE"},
12473    {"bits": [1, 1], "name": "STREAMOUT_ACTIVE"},
12474    {"bits": [2, 2], "name": "PIPELINE_ACTIVE"},
12475    {"bits": [3, 3], "name": "STIPPLE_ACTIVE"},
12476    {"bits": [4, 4], "name": "VGT_BUFFERS_ACTIVE"},
12477    {"bits": [5, 5], "name": "SCREEN_EXT_ACTIVE"},
12478    {"bits": [6, 6], "name": "DRAW_INDIRECT_ACTIVE"},
12479    {"bits": [7, 7], "name": "DISP_INDIRECT_ACTIVE"}
12480   ]
12481  },
12482  "CP_SIG_SEM_ADDR_HI": {
12483   "fields": [
12484    {"bits": [0, 15], "name": "SEM_ADDR_HI"},
12485    {"bits": [16, 16], "name": "SEM_USE_MAILBOX"},
12486    {"bits": [20, 20], "name": "SEM_SIGNAL_TYPE"},
12487    {"bits": [24, 25], "name": "SEM_CLIENT_CODE"},
12488    {"bits": [29, 31], "name": "SEM_SELECT"}
12489   ]
12490  },
12491  "CP_SIG_SEM_ADDR_LO": {
12492   "fields": [
12493    {"bits": [0, 0], "name": "SEM_PRIV"},
12494    {"bits": [3, 31], "name": "SEM_ADDR_LO"}
12495   ]
12496  },
12497  "CP_STREAM_OUT_ADDR_HI": {
12498   "fields": [
12499    {"bits": [0, 15], "name": "STREAM_OUT_ADDR_HI"}
12500   ]
12501  },
12502  "CP_STREAM_OUT_ADDR_LO": {
12503   "fields": [
12504    {"bits": [2, 31], "name": "STREAM_OUT_ADDR_LO"}
12505   ]
12506  },
12507  "CP_STRMOUT_CNTL": {
12508   "fields": [
12509    {"bits": [0, 0], "name": "OFFSET_UPDATE_DONE"}
12510   ]
12511  },
12512  "CP_ST_BASE_HI": {
12513   "fields": [
12514    {"bits": [0, 15], "name": "ST_BASE_HI"}
12515   ]
12516  },
12517  "CP_ST_BASE_LO": {
12518   "fields": [
12519    {"bits": [2, 31], "name": "ST_BASE_LO"}
12520   ]
12521  },
12522  "CP_ST_BUFSZ": {
12523   "fields": [
12524    {"bits": [0, 19], "name": "ST_BUFSZ"}
12525   ]
12526  },
12527  "CP_ST_CMD_BUFSZ": {
12528   "fields": [
12529    {"bits": [0, 19], "name": "ST_CMD_REQSZ"}
12530   ]
12531  },
12532  "CP_VMID": {
12533   "fields": [
12534    {"bits": [0, 3], "name": "VMID"}
12535   ]
12536  },
12537  "CS_COPY_STATE": {
12538   "fields": [
12539    {"bits": [0, 2], "name": "SRC_STATE_ID"}
12540   ]
12541  },
12542  "DB_ALPHA_TO_MASK": {
12543   "fields": [
12544    {"bits": [0, 0], "name": "ALPHA_TO_MASK_ENABLE"},
12545    {"bits": [8, 9], "name": "ALPHA_TO_MASK_OFFSET0"},
12546    {"bits": [10, 11], "name": "ALPHA_TO_MASK_OFFSET1"},
12547    {"bits": [12, 13], "name": "ALPHA_TO_MASK_OFFSET2"},
12548    {"bits": [14, 15], "name": "ALPHA_TO_MASK_OFFSET3"},
12549    {"bits": [16, 16], "name": "OFFSET_ROUND"}
12550   ]
12551  },
12552  "DB_COUNT_CONTROL": {
12553   "fields": [
12554    {"bits": [0, 0], "name": "ZPASS_INCREMENT_DISABLE"},
12555    {"bits": [1, 1], "name": "PERFECT_ZPASS_COUNTS"},
12556    {"bits": [2, 2], "name": "DISABLE_CONSERVATIVE_ZPASS_COUNTS"},
12557    {"bits": [3, 3], "name": "ENHANCED_CONSERVATIVE_ZPASS_COUNTS"},
12558    {"bits": [4, 6], "name": "SAMPLE_RATE"},
12559    {"bits": [8, 11], "name": "ZPASS_ENABLE"},
12560    {"bits": [12, 15], "name": "ZFAIL_ENABLE"},
12561    {"bits": [16, 19], "name": "SFAIL_ENABLE"},
12562    {"bits": [20, 23], "name": "DBFAIL_ENABLE"},
12563    {"bits": [24, 27], "name": "SLICE_EVEN_ENABLE"},
12564    {"bits": [28, 31], "name": "SLICE_ODD_ENABLE"}
12565   ]
12566  },
12567  "DB_DEPTH_CONTROL": {
12568   "fields": [
12569    {"bits": [0, 0], "name": "STENCIL_ENABLE"},
12570    {"bits": [1, 1], "name": "Z_ENABLE"},
12571    {"bits": [2, 2], "name": "Z_WRITE_ENABLE"},
12572    {"bits": [3, 3], "name": "DEPTH_BOUNDS_ENABLE"},
12573    {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"},
12574    {"bits": [7, 7], "name": "BACKFACE_ENABLE"},
12575    {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"},
12576    {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"},
12577    {"bits": [30, 30], "name": "ENABLE_COLOR_WRITES_ON_DEPTH_FAIL"},
12578    {"bits": [31, 31], "name": "DISABLE_COLOR_WRITES_ON_DEPTH_PASS"}
12579   ]
12580  },
12581  "DB_DEPTH_SIZE_XY": {
12582   "fields": [
12583    {"bits": [0, 13], "name": "X_MAX"},
12584    {"bits": [16, 29], "name": "Y_MAX"}
12585   ]
12586  },
12587  "DB_DEPTH_VIEW": {
12588   "fields": [
12589    {"bits": [0, 10], "name": "SLICE_START"},
12590    {"bits": [11, 12], "name": "SLICE_START_HI"},
12591    {"bits": [13, 23], "name": "SLICE_MAX"},
12592    {"bits": [24, 24], "name": "Z_READ_ONLY"},
12593    {"bits": [25, 25], "name": "STENCIL_READ_ONLY"},
12594    {"bits": [26, 29], "name": "MIPID"},
12595    {"bits": [30, 31], "name": "SLICE_MAX_HI"}
12596   ]
12597  },
12598  "DB_DFSM_CONTROL": {
12599   "fields": [
12600    {"bits": [0, 1], "enum_ref": "DB_DFSM_CONTROL__PUNCHOUT_MODE", "name": "PUNCHOUT_MODE"},
12601    {"bits": [2, 2], "name": "POPS_DRAIN_PS_ON_OVERLAP"},
12602    {"bits": [3, 3], "name": "DISALLOW_OVERFLOW"}
12603   ]
12604  },
12605  "DB_EQAA": {
12606   "fields": [
12607    {"bits": [0, 2], "name": "MAX_ANCHOR_SAMPLES"},
12608    {"bits": [4, 6], "name": "PS_ITER_SAMPLES"},
12609    {"bits": [8, 10], "name": "MASK_EXPORT_NUM_SAMPLES"},
12610    {"bits": [12, 14], "name": "ALPHA_TO_MASK_NUM_SAMPLES"},
12611    {"bits": [16, 16], "name": "HIGH_QUALITY_INTERSECTIONS"},
12612    {"bits": [17, 17], "name": "INCOHERENT_EQAA_READS"},
12613    {"bits": [18, 18], "name": "INTERPOLATE_COMP_Z"},
12614    {"bits": [19, 19], "name": "INTERPOLATE_SRC_Z"},
12615    {"bits": [20, 20], "name": "STATIC_ANCHOR_ASSOCIATIONS"},
12616    {"bits": [21, 21], "name": "ALPHA_TO_MASK_EQAA_DISABLE"},
12617    {"bits": [24, 26], "name": "OVERRASTERIZATION_AMOUNT"},
12618    {"bits": [27, 27], "name": "ENABLE_POSTZ_OVERRASTERIZATION"}
12619   ]
12620  },
12621  "DB_HTILE_SURFACE": {
12622   "fields": [
12623    {"bits": [0, 0], "name": "RESERVED_FIELD_1"},
12624    {"bits": [1, 1], "name": "FULL_CACHE"},
12625    {"bits": [2, 2], "name": "RESERVED_FIELD_2"},
12626    {"bits": [3, 3], "name": "RESERVED_FIELD_3"},
12627    {"bits": [4, 9], "name": "RESERVED_FIELD_4"},
12628    {"bits": [10, 15], "name": "RESERVED_FIELD_5"},
12629    {"bits": [16, 16], "name": "DST_OUTSIDE_ZERO_TO_ONE"},
12630    {"bits": [17, 17], "name": "RESERVED_FIELD_6"},
12631    {"bits": [18, 18], "name": "PIPE_ALIGNED"},
12632    {"bits": [19, 20], "enum_ref": "VRSHtileEncoding", "name": "VRS_HTILE_ENCODING"}
12633   ]
12634  },
12635  "DB_OCCLUSION_COUNT0_HI": {
12636   "fields": [
12637    {"bits": [0, 30], "name": "COUNT_HI"}
12638   ]
12639  },
12640  "DB_PRELOAD_CONTROL": {
12641   "fields": [
12642    {"bits": [0, 7], "name": "START_X"},
12643    {"bits": [8, 15], "name": "START_Y"},
12644    {"bits": [16, 23], "name": "MAX_X"},
12645    {"bits": [24, 31], "name": "MAX_Y"}
12646   ]
12647  },
12648  "DB_RENDER_CONTROL": {
12649   "fields": [
12650    {"bits": [0, 0], "name": "DEPTH_CLEAR_ENABLE"},
12651    {"bits": [1, 1], "name": "STENCIL_CLEAR_ENABLE"},
12652    {"bits": [2, 2], "name": "DEPTH_COPY"},
12653    {"bits": [3, 3], "name": "STENCIL_COPY"},
12654    {"bits": [4, 4], "name": "RESUMMARIZE_ENABLE"},
12655    {"bits": [5, 5], "name": "STENCIL_COMPRESS_DISABLE"},
12656    {"bits": [6, 6], "name": "DEPTH_COMPRESS_DISABLE"},
12657    {"bits": [7, 7], "name": "COPY_CENTROID"},
12658    {"bits": [8, 11], "name": "COPY_SAMPLE"},
12659    {"bits": [12, 12], "name": "DECOMPRESS_ENABLE"},
12660    {"bits": [13, 13], "name": "PS_INVOKE_DISABLE"}
12661   ]
12662  },
12663  "DB_RENDER_OVERRIDE": {
12664   "fields": [
12665    {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"},
12666    {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"},
12667    {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"},
12668    {"bits": [6, 6], "name": "FORCE_SHADER_Z_ORDER"},
12669    {"bits": [7, 7], "name": "FAST_Z_DISABLE"},
12670    {"bits": [8, 8], "name": "FAST_STENCIL_DISABLE"},
12671    {"bits": [9, 9], "name": "NOOP_CULL_DISABLE"},
12672    {"bits": [10, 10], "name": "FORCE_COLOR_KILL"},
12673    {"bits": [11, 11], "name": "FORCE_Z_READ"},
12674    {"bits": [12, 12], "name": "FORCE_STENCIL_READ"},
12675    {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"},
12676    {"bits": [15, 15], "name": "FORCE_QC_SMASK_CONFLICT"},
12677    {"bits": [16, 16], "name": "DISABLE_VIEWPORT_CLAMP"},
12678    {"bits": [17, 17], "name": "IGNORE_SC_ZRANGE"},
12679    {"bits": [18, 18], "name": "DISABLE_FULLY_COVERED"},
12680    {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"},
12681    {"bits": [21, 25], "name": "MAX_TILES_IN_DTT"},
12682    {"bits": [26, 26], "name": "DISABLE_TILE_RATE_TILES"},
12683    {"bits": [27, 27], "name": "FORCE_Z_DIRTY"},
12684    {"bits": [28, 28], "name": "FORCE_STENCIL_DIRTY"},
12685    {"bits": [29, 29], "name": "FORCE_Z_VALID"},
12686    {"bits": [30, 30], "name": "FORCE_STENCIL_VALID"},
12687    {"bits": [31, 31], "name": "PRESERVE_COMPRESSION"}
12688   ]
12689  },
12690  "DB_RENDER_OVERRIDE2": {
12691   "fields": [
12692    {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"},
12693    {"bits": [2, 4], "name": "PARTIAL_SQUAD_LAUNCH_COUNTDOWN"},
12694    {"bits": [5, 5], "name": "DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION"},
12695    {"bits": [6, 6], "name": "DISABLE_SMEM_EXPCLEAR_OPTIMIZATION"},
12696    {"bits": [7, 7], "name": "DISABLE_COLOR_ON_VALIDATION"},
12697    {"bits": [8, 8], "name": "DECOMPRESS_Z_ON_FLUSH"},
12698    {"bits": [9, 9], "name": "DISABLE_REG_SNOOP"},
12699    {"bits": [10, 10], "name": "DEPTH_BOUNDS_HIER_DEPTH_DISABLE"},
12700    {"bits": [11, 11], "name": "SEPARATE_HIZS_FUNC_ENABLE"},
12701    {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"},
12702    {"bits": [15, 17], "name": "HIS_SFUNC_FF"},
12703    {"bits": [18, 20], "name": "HIS_SFUNC_BF"},
12704    {"bits": [21, 21], "name": "PRESERVE_ZRANGE"},
12705    {"bits": [22, 22], "name": "PRESERVE_SRESULTS"},
12706    {"bits": [23, 23], "name": "DISABLE_FAST_PASS"},
12707    {"bits": [25, 25], "name": "ALLOW_PARTIAL_RES_HIER_KILL"},
12708    {"bits": [26, 26], "name": "FORCE_VRS_RATE_FINE"},
12709    {"bits": [27, 28], "name": "CENTROID_COMPUTATION_MODE"}
12710   ]
12711  },
12712  "DB_RESERVED_REG_1": {
12713   "fields": [
12714    {"bits": [0, 10], "name": "FIELD_1"},
12715    {"bits": [11, 21], "name": "FIELD_2"}
12716   ]
12717  },
12718  "DB_RESERVED_REG_2": {
12719   "fields": [
12720    {"bits": [0, 3], "name": "FIELD_1"},
12721    {"bits": [4, 7], "name": "FIELD_2"},
12722    {"bits": [8, 12], "name": "FIELD_3"},
12723    {"bits": [13, 14], "name": "FIELD_4"},
12724    {"bits": [15, 16], "name": "FIELD_5"},
12725    {"bits": [17, 18], "name": "FIELD_6"},
12726    {"bits": [19, 20], "name": "FIELD_7"},
12727    {"bits": [28, 31], "name": "RESOURCE_LEVEL"}
12728   ]
12729  },
12730  "DB_RESERVED_REG_3": {
12731   "fields": [
12732    {"bits": [0, 21], "name": "FIELD_1"}
12733   ]
12734  },
12735  "DB_RMI_L2_CACHE_CONTROL": {
12736   "fields": [
12737    {"bits": [0, 1], "enum_ref": "WritePolicy", "name": "Z_WR_POLICY"},
12738    {"bits": [2, 3], "enum_ref": "WritePolicy", "name": "S_WR_POLICY"},
12739    {"bits": [4, 5], "enum_ref": "WritePolicy", "name": "HTILE_WR_POLICY"},
12740    {"bits": [6, 7], "enum_ref": "WritePolicy", "name": "ZPCPSD_WR_POLICY"},
12741    {"bits": [16, 17], "enum_ref": "ReadPolicy", "name": "Z_RD_POLICY"},
12742    {"bits": [18, 19], "enum_ref": "ReadPolicy", "name": "S_RD_POLICY"},
12743    {"bits": [20, 21], "enum_ref": "ReadPolicy", "name": "HTILE_RD_POLICY"},
12744    {"bits": [24, 24], "name": "Z_BIG_PAGE"},
12745    {"bits": [25, 25], "name": "S_BIG_PAGE"},
12746    {"bits": [26, 26], "name": "Z_NOALLOC"},
12747    {"bits": [27, 27], "name": "S_NOALLOC"},
12748    {"bits": [28, 28], "name": "HTILE_NOALLOC"},
12749    {"bits": [29, 29], "name": "ZPCPSD_NOALLOC"}
12750   ]
12751  },
12752  "DB_SHADER_CONTROL": {
12753   "fields": [
12754    {"bits": [0, 0], "name": "Z_EXPORT_ENABLE"},
12755    {"bits": [1, 1], "name": "STENCIL_TEST_VAL_EXPORT_ENABLE"},
12756    {"bits": [2, 2], "name": "STENCIL_OP_VAL_EXPORT_ENABLE"},
12757    {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"},
12758    {"bits": [6, 6], "name": "KILL_ENABLE"},
12759    {"bits": [7, 7], "name": "COVERAGE_TO_MASK_ENABLE"},
12760    {"bits": [8, 8], "name": "MASK_EXPORT_ENABLE"},
12761    {"bits": [9, 9], "name": "EXEC_ON_HIER_FAIL"},
12762    {"bits": [10, 10], "name": "EXEC_ON_NOOP"},
12763    {"bits": [11, 11], "name": "ALPHA_TO_MASK_DISABLE"},
12764    {"bits": [12, 12], "name": "DEPTH_BEFORE_SHADER"},
12765    {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"},
12766    {"bits": [15, 15], "name": "DUAL_QUAD_DISABLE"},
12767    {"bits": [16, 16], "name": "PRIMITIVE_ORDERED_PIXEL_SHADER"},
12768    {"bits": [17, 17], "name": "EXEC_IF_OVERLAPPED"},
12769    {"bits": [20, 22], "name": "POPS_OVERLAP_NUM_SAMPLES"},
12770    {"bits": [23, 23], "name": "PRE_SHADER_DEPTH_COVERAGE_ENABLE"}
12771   ]
12772  },
12773  "DB_SRESULTS_COMPARE_STATE0": {
12774   "fields": [
12775    {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"},
12776    {"bits": [4, 11], "name": "COMPAREVALUE0"},
12777    {"bits": [12, 19], "name": "COMPAREMASK0"},
12778    {"bits": [24, 24], "name": "ENABLE0"}
12779   ]
12780  },
12781  "DB_SRESULTS_COMPARE_STATE1": {
12782   "fields": [
12783    {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"},
12784    {"bits": [4, 11], "name": "COMPAREVALUE1"},
12785    {"bits": [12, 19], "name": "COMPAREMASK1"},
12786    {"bits": [24, 24], "name": "ENABLE1"}
12787   ]
12788  },
12789  "DB_STENCILREFMASK": {
12790   "fields": [
12791    {"bits": [0, 7], "name": "STENCILTESTVAL"},
12792    {"bits": [8, 15], "name": "STENCILMASK"},
12793    {"bits": [16, 23], "name": "STENCILWRITEMASK"},
12794    {"bits": [24, 31], "name": "STENCILOPVAL"}
12795   ]
12796  },
12797  "DB_STENCILREFMASK_BF": {
12798   "fields": [
12799    {"bits": [0, 7], "name": "STENCILTESTVAL_BF"},
12800    {"bits": [8, 15], "name": "STENCILMASK_BF"},
12801    {"bits": [16, 23], "name": "STENCILWRITEMASK_BF"},
12802    {"bits": [24, 31], "name": "STENCILOPVAL_BF"}
12803   ]
12804  },
12805  "DB_STENCIL_CLEAR": {
12806   "fields": [
12807    {"bits": [0, 7], "name": "CLEAR"}
12808   ]
12809  },
12810  "DB_STENCIL_CONTROL": {
12811   "fields": [
12812    {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"},
12813    {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"},
12814    {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"},
12815    {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"},
12816    {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"},
12817    {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"}
12818   ]
12819  },
12820  "DB_STENCIL_INFO": {
12821   "fields": [
12822    {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"},
12823    {"bits": [4, 8], "name": "SW_MODE"},
12824    {"bits": [9, 10], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"},
12825    {"bits": [11, 11], "name": "ITERATE_FLUSH"},
12826    {"bits": [12, 12], "name": "PARTIALLY_RESIDENT"},
12827    {"bits": [13, 15], "name": "RESERVED_FIELD_1"},
12828    {"bits": [20, 20], "name": "ITERATE_256"},
12829    {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"},
12830    {"bits": [29, 29], "name": "TILE_STENCIL_DISABLE"}
12831   ]
12832  },
12833  "DB_VRS_OVERRIDE_CNTL": {
12834   "fields": [
12835    {"bits": [0, 2], "enum_ref": "VRSCombinerModeSC", "name": "VRS_OVERRIDE_RATE_COMBINER_MODE"},
12836    {"bits": [4, 5], "name": "VRS_OVERRIDE_RATE_X"},
12837    {"bits": [6, 7], "name": "VRS_OVERRIDE_RATE_Y"}
12838   ]
12839  },
12840  "DB_Z_INFO": {
12841   "fields": [
12842    {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"},
12843    {"bits": [2, 3], "name": "NUM_SAMPLES"},
12844    {"bits": [4, 8], "name": "SW_MODE"},
12845    {"bits": [9, 10], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"},
12846    {"bits": [11, 11], "name": "ITERATE_FLUSH"},
12847    {"bits": [12, 12], "name": "PARTIALLY_RESIDENT"},
12848    {"bits": [13, 15], "name": "RESERVED_FIELD_1"},
12849    {"bits": [16, 19], "name": "MAXMIP"},
12850    {"bits": [20, 20], "name": "ITERATE_256"},
12851    {"bits": [23, 26], "name": "DECOMPRESS_ON_N_ZPLANES"},
12852    {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"},
12853    {"bits": [28, 28], "name": "READ_SIZE"},
12854    {"bits": [29, 29], "name": "TILE_SURFACE_ENABLE"},
12855    {"bits": [31, 31], "name": "ZRANGE_PRECISION"}
12856   ]
12857  },
12858  "DB_Z_READ_BASE_HI": {
12859   "fields": [
12860    {"bits": [0, 7], "name": "BASE_HI"}
12861   ]
12862  },
12863  "GB_ADDR_CONFIG": {
12864   "fields": [
12865    {"bits": [0, 2], "name": "NUM_PIPES"},
12866    {"bits": [3, 5], "name": "PIPE_INTERLEAVE_SIZE"},
12867    {"bits": [6, 7], "name": "MAX_COMPRESSED_FRAGS"},
12868    {"bits": [8, 10], "name": "NUM_PKRS"},
12869    {"bits": [19, 20], "name": "NUM_SHADER_ENGINES"},
12870    {"bits": [26, 27], "name": "NUM_RB_PER_SE"}
12871   ]
12872  },
12873  "GCEA_PERFCOUNTER0_CFG": {
12874   "fields": [
12875    {"bits": [0, 7], "name": "PERF_SEL"},
12876    {"bits": [8, 15], "name": "PERF_SEL_END"},
12877    {"bits": [24, 27], "name": "PERF_MODE"},
12878    {"bits": [28, 28], "name": "ENABLE"},
12879    {"bits": [29, 29], "name": "CLEAR"}
12880   ]
12881  },
12882  "GCEA_PERFCOUNTER2_MODE": {
12883   "fields": [
12884    {"bits": [0, 1], "name": "COMPARE_MODE0"},
12885    {"bits": [2, 3], "name": "COMPARE_MODE1"},
12886    {"bits": [4, 5], "name": "COMPARE_MODE2"},
12887    {"bits": [6, 7], "name": "COMPARE_MODE3"},
12888    {"bits": [8, 11], "name": "COMPARE_VALUE0"},
12889    {"bits": [12, 15], "name": "COMPARE_VALUE1"},
12890    {"bits": [16, 19], "name": "COMPARE_VALUE2"},
12891    {"bits": [20, 23], "name": "COMPARE_VALUE3"}
12892   ]
12893  },
12894  "GCEA_PERFCOUNTER_HI": {
12895   "fields": [
12896    {"bits": [0, 15], "name": "COUNTER_HI"},
12897    {"bits": [16, 31], "name": "COMPARE_VALUE"}
12898   ]
12899  },
12900  "GCEA_PERFCOUNTER_RSLT_CNTL": {
12901   "fields": [
12902    {"bits": [0, 3], "name": "PERF_COUNTER_SELECT"},
12903    {"bits": [8, 15], "name": "START_TRIGGER"},
12904    {"bits": [16, 23], "name": "STOP_TRIGGER"},
12905    {"bits": [24, 24], "name": "ENABLE_ANY"},
12906    {"bits": [25, 25], "name": "CLEAR_ALL"},
12907    {"bits": [26, 26], "name": "STOP_ALL_ON_SATURATE"}
12908   ]
12909  },
12910  "GCR_PERFCOUNTER1_SELECT": {
12911   "fields": [
12912    {"bits": [0, 8], "name": "PERF_SEL"},
12913    {"bits": [24, 27], "name": "PERF_MODE"},
12914    {"bits": [28, 31], "name": "CNTL_MODE"}
12915   ]
12916  },
12917  "GDS_ATOM_BASE": {
12918   "fields": [
12919    {"bits": [0, 15], "name": "BASE"},
12920    {"bits": [16, 31], "name": "UNUSED"}
12921   ]
12922  },
12923  "GDS_ATOM_CNTL": {
12924   "fields": [
12925    {"bits": [0, 5], "name": "AINC"},
12926    {"bits": [6, 7], "name": "UNUSED1"},
12927    {"bits": [8, 9], "name": "DMODE"},
12928    {"bits": [10, 31], "name": "UNUSED2"}
12929   ]
12930  },
12931  "GDS_ATOM_COMPLETE": {
12932   "fields": [
12933    {"bits": [0, 0], "name": "COMPLETE"},
12934    {"bits": [1, 31], "name": "UNUSED"}
12935   ]
12936  },
12937  "GDS_ATOM_OFFSET0": {
12938   "fields": [
12939    {"bits": [0, 7], "name": "OFFSET0"},
12940    {"bits": [8, 31], "name": "UNUSED"}
12941   ]
12942  },
12943  "GDS_ATOM_OFFSET1": {
12944   "fields": [
12945    {"bits": [0, 7], "name": "OFFSET1"},
12946    {"bits": [8, 31], "name": "UNUSED"}
12947   ]
12948  },
12949  "GDS_ATOM_OP": {
12950   "fields": [
12951    {"bits": [0, 7], "name": "OP"},
12952    {"bits": [8, 31], "name": "UNUSED"}
12953   ]
12954  },
12955  "GDS_ATOM_SIZE": {
12956   "fields": [
12957    {"bits": [0, 15], "name": "SIZE"},
12958    {"bits": [16, 31], "name": "UNUSED"}
12959   ]
12960  },
12961  "GDS_GWS_RESOURCE": {
12962   "fields": [
12963    {"bits": [0, 0], "name": "FLAG"},
12964    {"bits": [1, 12], "name": "COUNTER"},
12965    {"bits": [13, 13], "name": "TYPE"},
12966    {"bits": [14, 14], "name": "DED"},
12967    {"bits": [15, 15], "name": "RELEASE_ALL"},
12968    {"bits": [16, 26], "name": "HEAD_QUEUE"},
12969    {"bits": [27, 27], "name": "HEAD_VALID"},
12970    {"bits": [28, 28], "name": "HEAD_FLAG"},
12971    {"bits": [29, 29], "name": "HALTED"},
12972    {"bits": [30, 30], "name": "HEAD_QUEUE1"},
12973    {"bits": [31, 31], "name": "UNUSED1"}
12974   ]
12975  },
12976  "GDS_GWS_RESOURCE_CNT": {
12977   "fields": [
12978    {"bits": [0, 15], "name": "RESOURCE_CNT"},
12979    {"bits": [16, 31], "name": "UNUSED"}
12980   ]
12981  },
12982  "GDS_GWS_RESOURCE_CNTL": {
12983   "fields": [
12984    {"bits": [0, 5], "name": "INDEX"},
12985    {"bits": [6, 31], "name": "UNUSED"}
12986   ]
12987  },
12988  "GDS_OA_ADDRESS": {
12989   "fields": [
12990    {"bits": [0, 15], "name": "DS_ADDRESS"},
12991    {"bits": [16, 19], "name": "CRAWLER_TYPE"},
12992    {"bits": [20, 23], "name": "CRAWLER"},
12993    {"bits": [24, 29], "name": "UNUSED"},
12994    {"bits": [30, 30], "name": "NO_ALLOC"},
12995    {"bits": [31, 31], "name": "ENABLE"}
12996   ]
12997  },
12998  "GDS_OA_CNTL": {
12999   "fields": [
13000    {"bits": [0, 3], "name": "INDEX"},
13001    {"bits": [4, 31], "name": "UNUSED"}
13002   ]
13003  },
13004  "GDS_OA_INCDEC": {
13005   "fields": [
13006    {"bits": [0, 30], "name": "VALUE"},
13007    {"bits": [31, 31], "name": "INCDEC"}
13008   ]
13009  },
13010  "GE1_PERFCOUNTER0_SELECT": {
13011   "fields": [
13012    {"bits": [0, 9], "name": "PERF_SEL0"},
13013    {"bits": [10, 19], "name": "PERF_SEL1"},
13014    {"bits": [20, 23], "name": "CNTR_MODE"},
13015    {"bits": [24, 27], "name": "PERF_MODE0"},
13016    {"bits": [28, 31], "name": "PERF_MODE1"}
13017   ]
13018  },
13019  "GE1_PERFCOUNTER0_SELECT1": {
13020   "fields": [
13021    {"bits": [0, 9], "name": "PERF_SEL2"},
13022    {"bits": [10, 19], "name": "PERF_SEL3"},
13023    {"bits": [24, 27], "name": "PERF_MODE2"},
13024    {"bits": [28, 31], "name": "PERF_MODE3"}
13025   ]
13026  },
13027  "GE_CNTL": {
13028   "fields": [
13029    {"bits": [0, 8], "name": "PRIM_GRP_SIZE"},
13030    {"bits": [9, 17], "name": "VERT_GRP_SIZE"},
13031    {"bits": [18, 18], "name": "BREAK_WAVE_AT_EOI"},
13032    {"bits": [19, 19], "name": "PACKET_TO_ONE_PA"}
13033   ]
13034  },
13035  "GE_MAX_OUTPUT_PER_SUBGROUP": {
13036   "fields": [
13037    {"bits": [0, 9], "name": "MAX_VERTS_PER_SUBGROUP"}
13038   ]
13039  },
13040  "GE_NGG_SUBGRP_CNTL": {
13041   "fields": [
13042    {"bits": [0, 8], "name": "PRIM_AMP_FACTOR"},
13043    {"bits": [9, 17], "name": "THDS_PER_SUBGRP"}
13044   ]
13045  },
13046  "GE_PC_ALLOC": {
13047   "fields": [
13048    {"bits": [0, 0], "name": "OVERSUB_EN"},
13049    {"bits": [1, 10], "name": "NUM_PC_LINES"}
13050   ]
13051  },
13052  "GE_STEREO_CNTL": {
13053   "fields": [
13054    {"bits": [0, 2], "name": "RT_SLICE"},
13055    {"bits": [3, 6], "name": "VIEWPORT"},
13056    {"bits": [8, 8], "name": "EN_STEREO"}
13057   ]
13058  },
13059  "GE_USER_VGPR_EN": {
13060   "fields": [
13061    {"bits": [0, 0], "name": "EN_USER_VGPR1"},
13062    {"bits": [1, 1], "name": "EN_USER_VGPR2"},
13063    {"bits": [2, 2], "name": "EN_USER_VGPR3"}
13064   ]
13065  },
13066  "GRBM_GFX_INDEX": {
13067   "fields": [
13068    {"bits": [0, 7], "name": "INSTANCE_INDEX"},
13069    {"bits": [8, 15], "name": "SA_INDEX"},
13070    {"bits": [16, 23], "name": "SE_INDEX"},
13071    {"bits": [29, 29], "name": "SA_BROADCAST_WRITES"},
13072    {"bits": [30, 30], "name": "INSTANCE_BROADCAST_WRITES"},
13073    {"bits": [31, 31], "name": "SE_BROADCAST_WRITES"}
13074   ]
13075  },
13076  "GRBM_PERFCOUNTER0_SELECT": {
13077   "fields": [
13078    {"bits": [0, 5], "name": "PERF_SEL"},
13079    {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"},
13080    {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"},
13081    {"bits": [13, 13], "name": "TA_BUSY_USER_DEFINED_MASK"},
13082    {"bits": [14, 14], "name": "SX_BUSY_USER_DEFINED_MASK"},
13083    {"bits": [16, 16], "name": "SPI_BUSY_USER_DEFINED_MASK"},
13084    {"bits": [17, 17], "name": "SC_BUSY_USER_DEFINED_MASK"},
13085    {"bits": [18, 18], "name": "PA_BUSY_USER_DEFINED_MASK"},
13086    {"bits": [19, 19], "name": "GRBM_BUSY_USER_DEFINED_MASK"},
13087    {"bits": [20, 20], "name": "DB_BUSY_USER_DEFINED_MASK"},
13088    {"bits": [21, 21], "name": "CB_BUSY_USER_DEFINED_MASK"},
13089    {"bits": [22, 22], "name": "CP_BUSY_USER_DEFINED_MASK"},
13090    {"bits": [24, 24], "name": "GDS_BUSY_USER_DEFINED_MASK"},
13091    {"bits": [25, 25], "name": "BCI_BUSY_USER_DEFINED_MASK"},
13092    {"bits": [26, 26], "name": "RLC_BUSY_USER_DEFINED_MASK"},
13093    {"bits": [27, 27], "name": "TCP_BUSY_USER_DEFINED_MASK"},
13094    {"bits": [28, 28], "name": "GE_BUSY_USER_DEFINED_MASK"},
13095    {"bits": [29, 29], "name": "UTCL2_BUSY_USER_DEFINED_MASK"},
13096    {"bits": [30, 30], "name": "EA_BUSY_USER_DEFINED_MASK"},
13097    {"bits": [31, 31], "name": "RMI_BUSY_USER_DEFINED_MASK"}
13098   ]
13099  },
13100  "GRBM_PERFCOUNTER0_SELECT_HI": {
13101   "fields": [
13102    {"bits": [1, 1], "name": "UTCL1_BUSY_USER_DEFINED_MASK"},
13103    {"bits": [2, 2], "name": "GL2CC_BUSY_USER_DEFINED_MASK"},
13104    {"bits": [3, 3], "name": "SDMA_BUSY_USER_DEFINED_MASK"},
13105    {"bits": [4, 4], "name": "CH_BUSY_USER_DEFINED_MASK"},
13106    {"bits": [5, 5], "name": "PH_BUSY_USER_DEFINED_MASK"},
13107    {"bits": [6, 6], "name": "PMM_BUSY_USER_DEFINED_MASK"},
13108    {"bits": [7, 7], "name": "GUS_BUSY_USER_DEFINED_MASK"},
13109    {"bits": [8, 8], "name": "GL1CC_BUSY_USER_DEFINED_MASK"}
13110   ]
13111  },
13112  "GRBM_SE0_PERFCOUNTER_SELECT": {
13113   "fields": [
13114    {"bits": [0, 5], "name": "PERF_SEL"},
13115    {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"},
13116    {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"},
13117    {"bits": [12, 12], "name": "TA_BUSY_USER_DEFINED_MASK"},
13118    {"bits": [13, 13], "name": "SX_BUSY_USER_DEFINED_MASK"},
13119    {"bits": [15, 15], "name": "SPI_BUSY_USER_DEFINED_MASK"},
13120    {"bits": [16, 16], "name": "SC_BUSY_USER_DEFINED_MASK"},
13121    {"bits": [17, 17], "name": "DB_BUSY_USER_DEFINED_MASK"},
13122    {"bits": [18, 18], "name": "CB_BUSY_USER_DEFINED_MASK"},
13123    {"bits": [20, 20], "name": "PA_BUSY_USER_DEFINED_MASK"},
13124    {"bits": [21, 21], "name": "BCI_BUSY_USER_DEFINED_MASK"},
13125    {"bits": [22, 22], "name": "RMI_BUSY_USER_DEFINED_MASK"},
13126    {"bits": [23, 23], "name": "UTCL1_BUSY_USER_DEFINED_MASK"},
13127    {"bits": [24, 24], "name": "TCP_BUSY_USER_DEFINED_MASK"},
13128    {"bits": [25, 25], "name": "GL1CC_BUSY_USER_DEFINED_MASK"}
13129   ]
13130  },
13131  "GRBM_STATUS": {
13132   "fields": [
13133    {"bits": [0, 3], "name": "ME0PIPE0_CMDFIFO_AVAIL"},
13134    {"bits": [7, 7], "name": "ME0PIPE0_CF_RQ_PENDING"},
13135    {"bits": [8, 8], "name": "ME0PIPE0_PF_RQ_PENDING"},
13136    {"bits": [9, 9], "name": "GDS_DMA_RQ_PENDING"},
13137    {"bits": [12, 12], "name": "DB_CLEAN"},
13138    {"bits": [13, 13], "name": "CB_CLEAN"},
13139    {"bits": [14, 14], "name": "TA_BUSY"},
13140    {"bits": [15, 15], "name": "GDS_BUSY"},
13141    {"bits": [16, 16], "name": "GE_BUSY_NO_DMA"},
13142    {"bits": [20, 20], "name": "SX_BUSY"},
13143    {"bits": [21, 21], "name": "GE_BUSY"},
13144    {"bits": [22, 22], "name": "SPI_BUSY"},
13145    {"bits": [23, 23], "name": "BCI_BUSY"},
13146    {"bits": [24, 24], "name": "SC_BUSY"},
13147    {"bits": [25, 25], "name": "PA_BUSY"},
13148    {"bits": [26, 26], "name": "DB_BUSY"},
13149    {"bits": [28, 28], "name": "CP_COHERENCY_BUSY"},
13150    {"bits": [29, 29], "name": "CP_BUSY"},
13151    {"bits": [30, 30], "name": "CB_BUSY"},
13152    {"bits": [31, 31], "name": "GUI_ACTIVE"}
13153   ]
13154  },
13155  "GRBM_STATUS2": {
13156   "fields": [
13157    {"bits": [0, 3], "name": "ME0PIPE1_CMDFIFO_AVAIL"},
13158    {"bits": [4, 4], "name": "ME0PIPE1_CF_RQ_PENDING"},
13159    {"bits": [5, 5], "name": "ME0PIPE1_PF_RQ_PENDING"},
13160    {"bits": [6, 6], "name": "ME1PIPE0_RQ_PENDING"},
13161    {"bits": [7, 7], "name": "ME1PIPE1_RQ_PENDING"},
13162    {"bits": [8, 8], "name": "ME1PIPE2_RQ_PENDING"},
13163    {"bits": [9, 9], "name": "ME1PIPE3_RQ_PENDING"},
13164    {"bits": [10, 10], "name": "ME2PIPE0_RQ_PENDING"},
13165    {"bits": [11, 11], "name": "ME2PIPE1_RQ_PENDING"},
13166    {"bits": [12, 12], "name": "ME2PIPE2_RQ_PENDING"},
13167    {"bits": [13, 13], "name": "ME2PIPE3_RQ_PENDING"},
13168    {"bits": [14, 14], "name": "RLC_RQ_PENDING"},
13169    {"bits": [15, 15], "name": "UTCL2_BUSY"},
13170    {"bits": [16, 16], "name": "EA_BUSY"},
13171    {"bits": [17, 17], "name": "RMI_BUSY"},
13172    {"bits": [18, 18], "name": "UTCL2_RQ_PENDING"},
13173    {"bits": [19, 19], "name": "SDMA_SCH_RQ_PENDING"},
13174    {"bits": [20, 20], "name": "EA_LINK_BUSY"},
13175    {"bits": [21, 21], "name": "SDMA_BUSY"},
13176    {"bits": [22, 22], "name": "SDMA0_RQ_PENDING"},
13177    {"bits": [23, 23], "name": "SDMA1_RQ_PENDING"},
13178    {"bits": [24, 24], "name": "SDMA2_RQ_PENDING"},
13179    {"bits": [25, 25], "name": "SDMA3_RQ_PENDING"},
13180    {"bits": [26, 26], "name": "RLC_BUSY"},
13181    {"bits": [27, 27], "name": "TCP_BUSY"},
13182    {"bits": [28, 28], "name": "CPF_BUSY"},
13183    {"bits": [29, 29], "name": "CPC_BUSY"},
13184    {"bits": [30, 30], "name": "CPG_BUSY"},
13185    {"bits": [31, 31], "name": "CPAXI_BUSY"}
13186   ]
13187  },
13188  "GRBM_STATUS3": {
13189   "fields": [
13190    {"bits": [5, 5], "name": "GRBM_RLC_INTR_CREDIT_PENDING"},
13191    {"bits": [6, 6], "name": "GRBM_UTCL2_INTR_CREDIT_PENDING"},
13192    {"bits": [7, 7], "name": "GRBM_CPF_INTR_CREDIT_PENDING"},
13193    {"bits": [8, 8], "name": "MESPIPE0_RQ_PENDING"},
13194    {"bits": [9, 9], "name": "MESPIPE1_RQ_PENDING"},
13195    {"bits": [10, 10], "name": "MESPIPE2_RQ_PENDING"},
13196    {"bits": [11, 11], "name": "MESPIPE3_RQ_PENDING"},
13197    {"bits": [13, 13], "name": "PH_BUSY"},
13198    {"bits": [14, 14], "name": "CH_BUSY"},
13199    {"bits": [15, 15], "name": "GL2CC_BUSY"},
13200    {"bits": [16, 16], "name": "GL1CC_BUSY"},
13201    {"bits": [28, 28], "name": "GUS_LINK_BUSY"},
13202    {"bits": [29, 29], "name": "GUS_BUSY"},
13203    {"bits": [30, 30], "name": "UTCL1_BUSY"},
13204    {"bits": [31, 31], "name": "PMM_BUSY"}
13205   ]
13206  },
13207  "GRBM_STATUS_SE0": {
13208   "fields": [
13209    {"bits": [1, 1], "name": "DB_CLEAN"},
13210    {"bits": [2, 2], "name": "CB_CLEAN"},
13211    {"bits": [3, 3], "name": "UTCL1_BUSY"},
13212    {"bits": [4, 4], "name": "TCP_BUSY"},
13213    {"bits": [5, 5], "name": "GL1CC_BUSY"},
13214    {"bits": [21, 21], "name": "RMI_BUSY"},
13215    {"bits": [22, 22], "name": "BCI_BUSY"},
13216    {"bits": [24, 24], "name": "PA_BUSY"},
13217    {"bits": [25, 25], "name": "TA_BUSY"},
13218    {"bits": [26, 26], "name": "SX_BUSY"},
13219    {"bits": [27, 27], "name": "SPI_BUSY"},
13220    {"bits": [29, 29], "name": "SC_BUSY"},
13221    {"bits": [30, 30], "name": "DB_BUSY"},
13222    {"bits": [31, 31], "name": "CB_BUSY"}
13223   ]
13224  },
13225  "IA_MULTI_VGT_PARAM": {
13226   "fields": [
13227    {"bits": [0, 15], "name": "PRIMGROUP_SIZE"},
13228    {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"},
13229    {"bits": [17, 17], "name": "SWITCH_ON_EOP"},
13230    {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"},
13231    {"bits": [19, 19], "name": "SWITCH_ON_EOI"},
13232    {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"}
13233   ]
13234  },
13235  "IA_MULTI_VGT_PARAM_PIPED": {
13236   "fields": [
13237    {"bits": [0, 15], "name": "PRIMGROUP_SIZE"},
13238    {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"},
13239    {"bits": [17, 17], "name": "SWITCH_ON_EOP"},
13240    {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"},
13241    {"bits": [19, 19], "name": "SWITCH_ON_EOI"},
13242    {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"},
13243    {"bits": [21, 21], "name": "EN_INST_OPT_BASIC"},
13244    {"bits": [22, 22], "name": "EN_INST_OPT_ADV"},
13245    {"bits": [23, 23], "name": "HW_USE_ONLY"}
13246   ]
13247  },
13248  "PA_CL_CLIP_CNTL": {
13249   "fields": [
13250    {"bits": [0, 0], "name": "UCP_ENA_0"},
13251    {"bits": [1, 1], "name": "UCP_ENA_1"},
13252    {"bits": [2, 2], "name": "UCP_ENA_2"},
13253    {"bits": [3, 3], "name": "UCP_ENA_3"},
13254    {"bits": [4, 4], "name": "UCP_ENA_4"},
13255    {"bits": [5, 5], "name": "UCP_ENA_5"},
13256    {"bits": [13, 13], "name": "PS_UCP_Y_SCALE_NEG"},
13257    {"bits": [14, 15], "name": "PS_UCP_MODE"},
13258    {"bits": [16, 16], "name": "CLIP_DISABLE"},
13259    {"bits": [17, 17], "name": "UCP_CULL_ONLY_ENA"},
13260    {"bits": [18, 18], "name": "BOUNDARY_EDGE_FLAG_ENA"},
13261    {"bits": [19, 19], "name": "DX_CLIP_SPACE_DEF"},
13262    {"bits": [20, 20], "name": "DIS_CLIP_ERR_DETECT"},
13263    {"bits": [21, 21], "name": "VTX_KILL_OR"},
13264    {"bits": [22, 22], "name": "DX_RASTERIZATION_KILL"},
13265    {"bits": [24, 24], "name": "DX_LINEAR_ATTR_CLIP_ENA"},
13266    {"bits": [25, 25], "name": "VTE_VPORT_PROVOKE_DISABLE"},
13267    {"bits": [26, 26], "name": "ZCLIP_NEAR_DISABLE"},
13268    {"bits": [27, 27], "name": "ZCLIP_FAR_DISABLE"},
13269    {"bits": [28, 28], "name": "ZCLIP_PROG_NEAR_ENA"}
13270   ]
13271  },
13272  "PA_CL_NANINF_CNTL": {
13273   "fields": [
13274    {"bits": [0, 0], "name": "VTE_XY_INF_DISCARD"},
13275    {"bits": [1, 1], "name": "VTE_Z_INF_DISCARD"},
13276    {"bits": [2, 2], "name": "VTE_W_INF_DISCARD"},
13277    {"bits": [3, 3], "name": "VTE_0XNANINF_IS_0"},
13278    {"bits": [4, 4], "name": "VTE_XY_NAN_RETAIN"},
13279    {"bits": [5, 5], "name": "VTE_Z_NAN_RETAIN"},
13280    {"bits": [6, 6], "name": "VTE_W_NAN_RETAIN"},
13281    {"bits": [7, 7], "name": "VTE_W_RECIP_NAN_IS_0"},
13282    {"bits": [8, 8], "name": "VS_XY_NAN_TO_INF"},
13283    {"bits": [9, 9], "name": "VS_XY_INF_RETAIN"},
13284    {"bits": [10, 10], "name": "VS_Z_NAN_TO_INF"},
13285    {"bits": [11, 11], "name": "VS_Z_INF_RETAIN"},
13286    {"bits": [12, 12], "name": "VS_W_NAN_TO_INF"},
13287    {"bits": [13, 13], "name": "VS_W_INF_RETAIN"},
13288    {"bits": [14, 14], "name": "VS_CLIP_DIST_INF_DISCARD"},
13289    {"bits": [20, 20], "name": "VTE_NO_OUTPUT_NEG_0"}
13290   ]
13291  },
13292  "PA_CL_NGG_CNTL": {
13293   "fields": [
13294    {"bits": [0, 0], "name": "VERTEX_REUSE_OFF"},
13295    {"bits": [1, 1], "name": "INDEX_BUF_EDGE_FLAG_ENA"},
13296    {"bits": [2, 9], "name": "VERTEX_REUSE_DEPTH"}
13297   ]
13298  },
13299  "PA_CL_VRS_CNTL": {
13300   "fields": [
13301    {"bits": [0, 2], "enum_ref": "VRSCombinerModeSC", "name": "VERTEX_RATE_COMBINER_MODE"},
13302    {"bits": [3, 5], "enum_ref": "VRSCombinerModeSC", "name": "PRIMITIVE_RATE_COMBINER_MODE"},
13303    {"bits": [6, 8], "enum_ref": "VRSCombinerModeSC", "name": "HTILE_RATE_COMBINER_MODE"},
13304    {"bits": [9, 11], "enum_ref": "VRSCombinerModeSC", "name": "SAMPLE_ITER_COMBINER_MODE"},
13305    {"bits": [13, 13], "name": "EXPOSE_VRS_PIXELS_MASK"},
13306    {"bits": [14, 14], "name": "CMASK_RATE_HINT_FORCE_ZERO"}
13307   ]
13308  },
13309  "PA_CL_VS_OUT_CNTL": {
13310   "fields": [
13311    {"bits": [0, 0], "name": "CLIP_DIST_ENA_0"},
13312    {"bits": [1, 1], "name": "CLIP_DIST_ENA_1"},
13313    {"bits": [2, 2], "name": "CLIP_DIST_ENA_2"},
13314    {"bits": [3, 3], "name": "CLIP_DIST_ENA_3"},
13315    {"bits": [4, 4], "name": "CLIP_DIST_ENA_4"},
13316    {"bits": [5, 5], "name": "CLIP_DIST_ENA_5"},
13317    {"bits": [6, 6], "name": "CLIP_DIST_ENA_6"},
13318    {"bits": [7, 7], "name": "CLIP_DIST_ENA_7"},
13319    {"bits": [8, 8], "name": "CULL_DIST_ENA_0"},
13320    {"bits": [9, 9], "name": "CULL_DIST_ENA_1"},
13321    {"bits": [10, 10], "name": "CULL_DIST_ENA_2"},
13322    {"bits": [11, 11], "name": "CULL_DIST_ENA_3"},
13323    {"bits": [12, 12], "name": "CULL_DIST_ENA_4"},
13324    {"bits": [13, 13], "name": "CULL_DIST_ENA_5"},
13325    {"bits": [14, 14], "name": "CULL_DIST_ENA_6"},
13326    {"bits": [15, 15], "name": "CULL_DIST_ENA_7"},
13327    {"bits": [16, 16], "name": "USE_VTX_POINT_SIZE"},
13328    {"bits": [17, 17], "name": "USE_VTX_EDGE_FLAG"},
13329    {"bits": [18, 18], "name": "USE_VTX_RENDER_TARGET_INDX"},
13330    {"bits": [19, 19], "name": "USE_VTX_VIEWPORT_INDX"},
13331    {"bits": [20, 20], "name": "USE_VTX_KILL_FLAG"},
13332    {"bits": [21, 21], "name": "VS_OUT_MISC_VEC_ENA"},
13333    {"bits": [22, 22], "name": "VS_OUT_CCDIST0_VEC_ENA"},
13334    {"bits": [23, 23], "name": "VS_OUT_CCDIST1_VEC_ENA"},
13335    {"bits": [24, 24], "name": "VS_OUT_MISC_SIDE_BUS_ENA"},
13336    {"bits": [25, 25], "name": "USE_VTX_GS_CUT_FLAG"},
13337    {"bits": [27, 27], "name": "USE_VTX_LINE_WIDTH"},
13338    {"bits": [28, 28], "name": "USE_VTX_VRS_RATE"},
13339    {"bits": [29, 29], "name": "BYPASS_VTX_RATE_COMBINER"},
13340    {"bits": [30, 30], "name": "BYPASS_PRIM_RATE_COMBINER"}
13341   ]
13342  },
13343  "PA_CL_VTE_CNTL": {
13344   "fields": [
13345    {"bits": [0, 0], "name": "VPORT_X_SCALE_ENA"},
13346    {"bits": [1, 1], "name": "VPORT_X_OFFSET_ENA"},
13347    {"bits": [2, 2], "name": "VPORT_Y_SCALE_ENA"},
13348    {"bits": [3, 3], "name": "VPORT_Y_OFFSET_ENA"},
13349    {"bits": [4, 4], "name": "VPORT_Z_SCALE_ENA"},
13350    {"bits": [5, 5], "name": "VPORT_Z_OFFSET_ENA"},
13351    {"bits": [8, 8], "name": "VTX_XY_FMT"},
13352    {"bits": [9, 9], "name": "VTX_Z_FMT"},
13353    {"bits": [10, 10], "name": "VTX_W0_FMT"},
13354    {"bits": [11, 11], "name": "PERFCOUNTER_REF"}
13355   ]
13356  },
13357  "PA_SC_AA_CONFIG": {
13358   "fields": [
13359    {"bits": [0, 2], "name": "MSAA_NUM_SAMPLES"},
13360    {"bits": [4, 4], "name": "AA_MASK_CENTROID_DTMN"},
13361    {"bits": [13, 16], "name": "MAX_SAMPLE_DIST"},
13362    {"bits": [20, 22], "name": "MSAA_EXPOSED_SAMPLES"},
13363    {"bits": [24, 25], "name": "DETAIL_TO_EXPOSED_MODE"},
13364    {"bits": [26, 27], "enum_ref": "CovToShaderSel", "name": "COVERAGE_TO_SHADER_SELECT"},
13365    {"bits": [28, 28], "name": "SAMPLE_COVERAGE_ENCODING"},
13366    {"bits": [29, 29], "name": "COVERED_CENTROID_IS_CENTER"}
13367   ]
13368  },
13369  "PA_SC_AA_MASK_X0Y0_X1Y0": {
13370   "fields": [
13371    {"bits": [0, 15], "name": "AA_MASK_X0Y0"},
13372    {"bits": [16, 31], "name": "AA_MASK_X1Y0"}
13373   ]
13374  },
13375  "PA_SC_AA_MASK_X0Y1_X1Y1": {
13376   "fields": [
13377    {"bits": [0, 15], "name": "AA_MASK_X0Y1"},
13378    {"bits": [16, 31], "name": "AA_MASK_X1Y1"}
13379   ]
13380  },
13381  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0": {
13382   "fields": [
13383    {"bits": [0, 3], "name": "S0_X"},
13384    {"bits": [4, 7], "name": "S0_Y"},
13385    {"bits": [8, 11], "name": "S1_X"},
13386    {"bits": [12, 15], "name": "S1_Y"},
13387    {"bits": [16, 19], "name": "S2_X"},
13388    {"bits": [20, 23], "name": "S2_Y"},
13389    {"bits": [24, 27], "name": "S3_X"},
13390    {"bits": [28, 31], "name": "S3_Y"}
13391   ]
13392  },
13393  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1": {
13394   "fields": [
13395    {"bits": [0, 3], "name": "S4_X"},
13396    {"bits": [4, 7], "name": "S4_Y"},
13397    {"bits": [8, 11], "name": "S5_X"},
13398    {"bits": [12, 15], "name": "S5_Y"},
13399    {"bits": [16, 19], "name": "S6_X"},
13400    {"bits": [20, 23], "name": "S6_Y"},
13401    {"bits": [24, 27], "name": "S7_X"},
13402    {"bits": [28, 31], "name": "S7_Y"}
13403   ]
13404  },
13405  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2": {
13406   "fields": [
13407    {"bits": [0, 3], "name": "S8_X"},
13408    {"bits": [4, 7], "name": "S8_Y"},
13409    {"bits": [8, 11], "name": "S9_X"},
13410    {"bits": [12, 15], "name": "S9_Y"},
13411    {"bits": [16, 19], "name": "S10_X"},
13412    {"bits": [20, 23], "name": "S10_Y"},
13413    {"bits": [24, 27], "name": "S11_X"},
13414    {"bits": [28, 31], "name": "S11_Y"}
13415   ]
13416  },
13417  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3": {
13418   "fields": [
13419    {"bits": [0, 3], "name": "S12_X"},
13420    {"bits": [4, 7], "name": "S12_Y"},
13421    {"bits": [8, 11], "name": "S13_X"},
13422    {"bits": [12, 15], "name": "S13_Y"},
13423    {"bits": [16, 19], "name": "S14_X"},
13424    {"bits": [20, 23], "name": "S14_Y"},
13425    {"bits": [24, 27], "name": "S15_X"},
13426    {"bits": [28, 31], "name": "S15_Y"}
13427   ]
13428  },
13429  "PA_SC_BINNER_CNTL_0": {
13430   "fields": [
13431    {"bits": [0, 1], "enum_ref": "BinningMode", "name": "BINNING_MODE"},
13432    {"bits": [2, 2], "name": "BIN_SIZE_X"},
13433    {"bits": [3, 3], "name": "BIN_SIZE_Y"},
13434    {"bits": [4, 6], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_X_EXTEND"},
13435    {"bits": [7, 9], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_Y_EXTEND"},
13436    {"bits": [10, 12], "name": "CONTEXT_STATES_PER_BIN"},
13437    {"bits": [13, 17], "name": "PERSISTENT_STATES_PER_BIN"},
13438    {"bits": [18, 18], "name": "DISABLE_START_OF_PRIM"},
13439    {"bits": [19, 26], "name": "FPOVS_PER_BATCH"},
13440    {"bits": [27, 27], "name": "OPTIMAL_BIN_SELECTION"},
13441    {"bits": [28, 28], "name": "FLUSH_ON_BINNING_TRANSITION"},
13442    {"bits": [29, 30], "enum_ref": "BinMapMode", "name": "BIN_MAPPING_MODE"}
13443   ]
13444  },
13445  "PA_SC_BINNER_CNTL_1": {
13446   "fields": [
13447    {"bits": [0, 15], "name": "MAX_ALLOC_COUNT"},
13448    {"bits": [16, 31], "name": "MAX_PRIM_PER_BATCH"}
13449   ]
13450  },
13451  "PA_SC_CENTROID_PRIORITY_0": {
13452   "fields": [
13453    {"bits": [0, 3], "name": "DISTANCE_0"},
13454    {"bits": [4, 7], "name": "DISTANCE_1"},
13455    {"bits": [8, 11], "name": "DISTANCE_2"},
13456    {"bits": [12, 15], "name": "DISTANCE_3"},
13457    {"bits": [16, 19], "name": "DISTANCE_4"},
13458    {"bits": [20, 23], "name": "DISTANCE_5"},
13459    {"bits": [24, 27], "name": "DISTANCE_6"},
13460    {"bits": [28, 31], "name": "DISTANCE_7"}
13461   ]
13462  },
13463  "PA_SC_CENTROID_PRIORITY_1": {
13464   "fields": [
13465    {"bits": [0, 3], "name": "DISTANCE_8"},
13466    {"bits": [4, 7], "name": "DISTANCE_9"},
13467    {"bits": [8, 11], "name": "DISTANCE_10"},
13468    {"bits": [12, 15], "name": "DISTANCE_11"},
13469    {"bits": [16, 19], "name": "DISTANCE_12"},
13470    {"bits": [20, 23], "name": "DISTANCE_13"},
13471    {"bits": [24, 27], "name": "DISTANCE_14"},
13472    {"bits": [28, 31], "name": "DISTANCE_15"}
13473   ]
13474  },
13475  "PA_SC_CLIPRECT_0_TL": {
13476   "fields": [
13477    {"bits": [0, 14], "name": "TL_X"},
13478    {"bits": [16, 30], "name": "TL_Y"}
13479   ]
13480  },
13481  "PA_SC_CLIPRECT_RULE": {
13482   "fields": [
13483    {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"}
13484   ]
13485  },
13486  "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL": {
13487   "fields": [
13488    {"bits": [0, 0], "name": "OVER_RAST_ENABLE"},
13489    {"bits": [1, 4], "name": "OVER_RAST_SAMPLE_SELECT"},
13490    {"bits": [5, 5], "name": "UNDER_RAST_ENABLE"},
13491    {"bits": [6, 9], "name": "UNDER_RAST_SAMPLE_SELECT"},
13492    {"bits": [10, 10], "name": "PBB_UNCERTAINTY_REGION_ENABLE"},
13493    {"bits": [11, 11], "name": "ZMM_TRI_EXTENT"},
13494    {"bits": [12, 12], "name": "ZMM_TRI_OFFSET"},
13495    {"bits": [13, 13], "name": "OVERRIDE_OVER_RAST_INNER_TO_NORMAL"},
13496    {"bits": [14, 14], "name": "OVERRIDE_UNDER_RAST_INNER_TO_NORMAL"},
13497    {"bits": [15, 15], "name": "DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE"},
13498    {"bits": [16, 17], "enum_ref": "ScUncertaintyRegionMode", "name": "UNCERTAINTY_REGION_MODE"},
13499    {"bits": [18, 18], "name": "OUTER_UNCERTAINTY_EDGERULE_OVERRIDE"},
13500    {"bits": [19, 19], "name": "INNER_UNCERTAINTY_EDGERULE_OVERRIDE"},
13501    {"bits": [20, 20], "name": "NULL_SQUAD_AA_MASK_ENABLE"},
13502    {"bits": [21, 21], "name": "COVERAGE_AA_MASK_ENABLE"},
13503    {"bits": [22, 22], "name": "PREZ_AA_MASK_ENABLE"},
13504    {"bits": [23, 23], "name": "POSTZ_AA_MASK_ENABLE"},
13505    {"bits": [24, 24], "name": "CENTROID_SAMPLE_OVERRIDE"},
13506    {"bits": [25, 26], "name": "UNCERTAINTY_REGION_MULT"},
13507    {"bits": [27, 28], "name": "UNCERTAINTY_REGION_PBB_MULT"}
13508   ]
13509  },
13510  "PA_SC_EDGERULE": {
13511   "fields": [
13512    {"bits": [0, 3], "name": "ER_TRI"},
13513    {"bits": [4, 7], "name": "ER_POINT"},
13514    {"bits": [8, 11], "name": "ER_RECT"},
13515    {"bits": [12, 17], "name": "ER_LINE_LR"},
13516    {"bits": [18, 23], "name": "ER_LINE_RL"},
13517    {"bits": [24, 27], "name": "ER_LINE_TB"},
13518    {"bits": [28, 31], "name": "ER_LINE_BT"}
13519   ]
13520  },
13521  "PA_SC_LINE_CNTL": {
13522   "fields": [
13523    {"bits": [9, 9], "name": "EXPAND_LINE_WIDTH"},
13524    {"bits": [10, 10], "name": "LAST_PIXEL"},
13525    {"bits": [11, 11], "name": "PERPENDICULAR_ENDCAP_ENA"},
13526    {"bits": [12, 12], "name": "DX10_DIAMOND_TEST_ENA"},
13527    {"bits": [13, 13], "name": "EXTRA_DX_DY_PRECISION"}
13528   ]
13529  },
13530  "PA_SC_LINE_STIPPLE": {
13531   "fields": [
13532    {"bits": [0, 15], "name": "LINE_PATTERN"},
13533    {"bits": [16, 23], "name": "REPEAT_COUNT"},
13534    {"bits": [28, 28], "name": "PATTERN_BIT_ORDER"},
13535    {"bits": [29, 30], "name": "AUTO_RESET_CNTL"}
13536   ]
13537  },
13538  "PA_SC_LINE_STIPPLE_STATE": {
13539   "fields": [
13540    {"bits": [0, 3], "name": "CURRENT_PTR"},
13541    {"bits": [8, 15], "name": "CURRENT_COUNT"}
13542   ]
13543  },
13544  "PA_SC_MODE_CNTL_0": {
13545   "fields": [
13546    {"bits": [0, 0], "name": "MSAA_ENABLE"},
13547    {"bits": [1, 1], "name": "VPORT_SCISSOR_ENABLE"},
13548    {"bits": [2, 2], "name": "LINE_STIPPLE_ENABLE"},
13549    {"bits": [3, 3], "name": "SEND_UNLIT_STILES_TO_PKR"},
13550    {"bits": [5, 5], "name": "ALTERNATE_RBS_PER_TILE"},
13551    {"bits": [6, 6], "name": "COARSE_TILE_STARTS_ON_EVEN_RB"}
13552   ]
13553  },
13554  "PA_SC_MODE_CNTL_1": {
13555   "fields": [
13556    {"bits": [0, 0], "name": "WALK_SIZE"},
13557    {"bits": [1, 1], "name": "WALK_ALIGNMENT"},
13558    {"bits": [2, 2], "name": "WALK_ALIGN8_PRIM_FITS_ST"},
13559    {"bits": [3, 3], "name": "WALK_FENCE_ENABLE"},
13560    {"bits": [4, 6], "name": "WALK_FENCE_SIZE"},
13561    {"bits": [7, 7], "name": "SUPERTILE_WALK_ORDER_ENABLE"},
13562    {"bits": [8, 8], "name": "TILE_WALK_ORDER_ENABLE"},
13563    {"bits": [9, 9], "name": "TILE_COVER_DISABLE"},
13564    {"bits": [10, 10], "name": "TILE_COVER_NO_SCISSOR"},
13565    {"bits": [11, 11], "name": "ZMM_LINE_EXTENT"},
13566    {"bits": [12, 12], "name": "ZMM_LINE_OFFSET"},
13567    {"bits": [13, 13], "name": "ZMM_RECT_EXTENT"},
13568    {"bits": [14, 14], "name": "KILL_PIX_POST_HI_Z"},
13569    {"bits": [15, 15], "name": "KILL_PIX_POST_DETAIL_MASK"},
13570    {"bits": [16, 16], "name": "PS_ITER_SAMPLE"},
13571    {"bits": [17, 17], "name": "MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE"},
13572    {"bits": [18, 18], "name": "MULTI_GPU_SUPERTILE_ENABLE"},
13573    {"bits": [19, 19], "name": "GPU_ID_OVERRIDE_ENABLE"},
13574    {"bits": [20, 23], "name": "GPU_ID_OVERRIDE"},
13575    {"bits": [24, 24], "name": "MULTI_GPU_PRIM_DISCARD_ENABLE"},
13576    {"bits": [25, 25], "name": "FORCE_EOV_CNTDWN_ENABLE"},
13577    {"bits": [26, 26], "name": "FORCE_EOV_REZ_ENABLE"},
13578    {"bits": [27, 27], "name": "OUT_OF_ORDER_PRIMITIVE_ENABLE"},
13579    {"bits": [28, 30], "name": "OUT_OF_ORDER_WATER_MARK"}
13580   ]
13581  },
13582  "PA_SC_NGG_MODE_CNTL": {
13583   "fields": [
13584    {"bits": [0, 10], "name": "MAX_DEALLOCS_IN_WAVE"},
13585    {"bits": [16, 23], "name": "MAX_FPOVS_IN_WAVE"}
13586   ]
13587  },
13588  "PA_SC_P3D_TRAP_SCREEN_H": {
13589   "fields": [
13590    {"bits": [0, 13], "name": "X_COORD"}
13591   ]
13592  },
13593  "PA_SC_P3D_TRAP_SCREEN_HV_EN": {
13594   "fields": [
13595    {"bits": [0, 0], "name": "ENABLE_HV_PRE_SHADER"},
13596    {"bits": [1, 1], "name": "FORCE_PRE_SHADER_ALL_PIXELS"}
13597   ]
13598  },
13599  "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE": {
13600   "fields": [
13601    {"bits": [0, 15], "name": "COUNT"}
13602   ]
13603  },
13604  "PA_SC_P3D_TRAP_SCREEN_V": {
13605   "fields": [
13606    {"bits": [0, 13], "name": "Y_COORD"}
13607   ]
13608  },
13609  "PA_SC_PERFCOUNTER1_SELECT": {
13610   "fields": [
13611    {"bits": [0, 9], "name": "PERF_SEL"}
13612   ]
13613  },
13614  "PA_SC_RASTER_CONFIG": {
13615   "fields": [
13616    {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"},
13617    {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"},
13618    {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"},
13619    {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"},
13620    {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"},
13621    {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"},
13622    {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"},
13623    {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"},
13624    {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"},
13625    {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"},
13626    {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"},
13627    {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"},
13628    {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"},
13629    {"bits": [26, 27], "enum_ref": "SeXsel", "name": "SE_XSEL"},
13630    {"bits": [28, 29], "enum_ref": "SeYsel", "name": "SE_YSEL"}
13631   ]
13632  },
13633  "PA_SC_RASTER_CONFIG_1": {
13634   "fields": [
13635    {"bits": [0, 1], "enum_ref": "SePairMap", "name": "SE_PAIR_MAP"},
13636    {"bits": [2, 3], "enum_ref": "SePairXsel", "name": "SE_PAIR_XSEL"},
13637    {"bits": [4, 5], "enum_ref": "SePairYsel", "name": "SE_PAIR_YSEL"}
13638   ]
13639  },
13640  "PA_SC_SCREEN_EXTENT_CONTROL": {
13641   "fields": [
13642    {"bits": [0, 1], "name": "SLICE_EVEN_ENABLE"},
13643    {"bits": [2, 3], "name": "SLICE_ODD_ENABLE"}
13644   ]
13645  },
13646  "PA_SC_SCREEN_EXTENT_MIN_0": {
13647   "fields": [
13648    {"bits": [0, 15], "name": "X"},
13649    {"bits": [16, 31], "name": "Y"}
13650   ]
13651  },
13652  "PA_SC_SCREEN_SCISSOR_BR": {
13653   "fields": [
13654    {"bits": [0, 15], "name": "BR_X"},
13655    {"bits": [16, 31], "name": "BR_Y"}
13656   ]
13657  },
13658  "PA_SC_SCREEN_SCISSOR_TL": {
13659   "fields": [
13660    {"bits": [0, 15], "name": "TL_X"},
13661    {"bits": [16, 31], "name": "TL_Y"}
13662   ]
13663  },
13664  "PA_SC_SHADER_CONTROL": {
13665   "fields": [
13666    {"bits": [0, 1], "name": "REALIGN_DQUADS_AFTER_N_WAVES"},
13667    {"bits": [2, 2], "name": "LOAD_COLLISION_WAVEID"},
13668    {"bits": [3, 3], "name": "LOAD_INTRAWAVE_COLLISION"},
13669    {"bits": [5, 6], "name": "WAVE_BREAK_REGION_SIZE"}
13670   ]
13671  },
13672  "PA_SC_TILE_STEERING_OVERRIDE": {
13673   "fields": [
13674    {"bits": [0, 0], "name": "ENABLE"},
13675    {"bits": [1, 2], "name": "NUM_SE"},
13676    {"bits": [5, 6], "name": "NUM_RB_PER_SE"},
13677    {"bits": [12, 13], "name": "NUM_SC"},
13678    {"bits": [16, 17], "name": "NUM_RB_PER_SC"},
13679    {"bits": [20, 21], "name": "NUM_PACKER_PER_SC"}
13680   ]
13681  },
13682  "PA_SC_WINDOW_OFFSET": {
13683   "fields": [
13684    {"bits": [0, 15], "name": "WINDOW_X_OFFSET"},
13685    {"bits": [16, 31], "name": "WINDOW_Y_OFFSET"}
13686   ]
13687  },
13688  "PA_SC_WINDOW_SCISSOR_BR": {
13689   "fields": [
13690    {"bits": [0, 14], "name": "BR_X"},
13691    {"bits": [16, 30], "name": "BR_Y"}
13692   ]
13693  },
13694  "PA_SC_WINDOW_SCISSOR_TL": {
13695   "fields": [
13696    {"bits": [0, 14], "name": "TL_X"},
13697    {"bits": [16, 30], "name": "TL_Y"},
13698    {"bits": [31, 31], "name": "WINDOW_OFFSET_DISABLE"}
13699   ]
13700  },
13701  "PA_STEREO_CNTL": {
13702   "fields": [
13703    {"bits": [1, 4], "name": "STEREO_MODE"},
13704    {"bits": [5, 7], "name": "RT_SLICE_MODE"},
13705    {"bits": [8, 11], "name": "RT_SLICE_OFFSET"},
13706    {"bits": [16, 18], "name": "VP_ID_MODE"},
13707    {"bits": [19, 22], "name": "VP_ID_OFFSET"}
13708   ]
13709  },
13710  "PA_SU_HARDWARE_SCREEN_OFFSET": {
13711   "fields": [
13712    {"bits": [0, 8], "name": "HW_SCREEN_OFFSET_X"},
13713    {"bits": [16, 24], "name": "HW_SCREEN_OFFSET_Y"}
13714   ]
13715  },
13716  "PA_SU_LINE_CNTL": {
13717   "fields": [
13718    {"bits": [0, 15], "name": "WIDTH"}
13719   ]
13720  },
13721  "PA_SU_LINE_STIPPLE_CNTL": {
13722   "fields": [
13723    {"bits": [0, 1], "name": "LINE_STIPPLE_RESET"},
13724    {"bits": [2, 2], "name": "EXPAND_FULL_LENGTH"},
13725    {"bits": [3, 3], "name": "FRACTIONAL_ACCUM"},
13726    {"bits": [4, 4], "name": "DIAMOND_ADJUST"}
13727   ]
13728  },
13729  "PA_SU_LINE_STIPPLE_VALUE": {
13730   "fields": [
13731    {"bits": [0, 23], "name": "LINE_STIPPLE_VALUE"}
13732   ]
13733  },
13734  "PA_SU_OVER_RASTERIZATION_CNTL": {
13735   "fields": [
13736    {"bits": [0, 0], "name": "DISCARD_0_AREA_TRIANGLES"},
13737    {"bits": [1, 1], "name": "DISCARD_0_AREA_LINES"},
13738    {"bits": [2, 2], "name": "DISCARD_0_AREA_POINTS"},
13739    {"bits": [3, 3], "name": "DISCARD_0_AREA_RECTANGLES"},
13740    {"bits": [4, 4], "name": "USE_PROVOKING_ZW"}
13741   ]
13742  },
13743  "PA_SU_PERFCOUNTER0_SELECT": {
13744   "fields": [
13745    {"bits": [0, 9], "name": "PERF_SEL"},
13746    {"bits": [10, 19], "name": "PERF_SEL1"},
13747    {"bits": [20, 23], "name": "CNTR_MODE"},
13748    {"bits": [24, 27], "name": "PERF_MODE1"},
13749    {"bits": [28, 31], "name": "PERF_MODE"}
13750   ]
13751  },
13752  "PA_SU_PERFCOUNTER0_SELECT1": {
13753   "fields": [
13754    {"bits": [0, 9], "name": "PERF_SEL2"},
13755    {"bits": [10, 19], "name": "PERF_SEL3"},
13756    {"bits": [24, 27], "name": "PERF_MODE3"},
13757    {"bits": [28, 31], "name": "PERF_MODE2"}
13758   ]
13759  },
13760  "PA_SU_POINT_MINMAX": {
13761   "fields": [
13762    {"bits": [0, 15], "name": "MIN_SIZE"},
13763    {"bits": [16, 31], "name": "MAX_SIZE"}
13764   ]
13765  },
13766  "PA_SU_POINT_SIZE": {
13767   "fields": [
13768    {"bits": [0, 15], "name": "HEIGHT"},
13769    {"bits": [16, 31], "name": "WIDTH"}
13770   ]
13771  },
13772  "PA_SU_POLY_OFFSET_DB_FMT_CNTL": {
13773   "fields": [
13774    {"bits": [0, 7], "name": "POLY_OFFSET_NEG_NUM_DB_BITS"},
13775    {"bits": [8, 8], "name": "POLY_OFFSET_DB_IS_FLOAT_FMT"}
13776   ]
13777  },
13778  "PA_SU_PRIM_FILTER_CNTL": {
13779   "fields": [
13780    {"bits": [0, 0], "name": "TRIANGLE_FILTER_DISABLE"},
13781    {"bits": [1, 1], "name": "LINE_FILTER_DISABLE"},
13782    {"bits": [2, 2], "name": "POINT_FILTER_DISABLE"},
13783    {"bits": [3, 3], "name": "RECTANGLE_FILTER_DISABLE"},
13784    {"bits": [4, 4], "name": "TRIANGLE_EXPAND_ENA"},
13785    {"bits": [5, 5], "name": "LINE_EXPAND_ENA"},
13786    {"bits": [6, 6], "name": "POINT_EXPAND_ENA"},
13787    {"bits": [7, 7], "name": "RECTANGLE_EXPAND_ENA"},
13788    {"bits": [8, 15], "name": "PRIM_EXPAND_CONSTANT"},
13789    {"bits": [30, 30], "name": "XMAX_RIGHT_EXCLUSION"},
13790    {"bits": [31, 31], "name": "YMAX_BOTTOM_EXCLUSION"}
13791   ]
13792  },
13793  "PA_SU_SC_MODE_CNTL": {
13794   "fields": [
13795    {"bits": [0, 0], "name": "CULL_FRONT"},
13796    {"bits": [1, 1], "name": "CULL_BACK"},
13797    {"bits": [2, 2], "name": "FACE"},
13798    {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"},
13799    {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_FRONT_PTYPE"},
13800    {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_BACK_PTYPE"},
13801    {"bits": [11, 11], "name": "POLY_OFFSET_FRONT_ENABLE"},
13802    {"bits": [12, 12], "name": "POLY_OFFSET_BACK_ENABLE"},
13803    {"bits": [13, 13], "name": "POLY_OFFSET_PARA_ENABLE"},
13804    {"bits": [16, 16], "name": "VTX_WINDOW_OFFSET_ENABLE"},
13805    {"bits": [19, 19], "name": "PROVOKING_VTX_LAST"},
13806    {"bits": [20, 20], "name": "PERSP_CORR_DIS"},
13807    {"bits": [21, 21], "name": "MULTI_PRIM_IB_ENA"},
13808    {"bits": [22, 22], "name": "RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF"},
13809    {"bits": [23, 23], "name": "NEW_QUAD_DECOMPOSITION"},
13810    {"bits": [24, 24], "name": "KEEP_TOGETHER_ENABLE"}
13811   ]
13812  },
13813  "PA_SU_SMALL_PRIM_FILTER_CNTL": {
13814   "fields": [
13815    {"bits": [0, 0], "name": "SMALL_PRIM_FILTER_ENABLE"},
13816    {"bits": [1, 1], "name": "TRIANGLE_FILTER_DISABLE"},
13817    {"bits": [2, 2], "name": "LINE_FILTER_DISABLE"},
13818    {"bits": [3, 3], "name": "POINT_FILTER_DISABLE"},
13819    {"bits": [4, 4], "name": "RECTANGLE_FILTER_DISABLE"}
13820   ]
13821  },
13822  "PA_SU_VTX_CNTL": {
13823   "fields": [
13824    {"bits": [0, 0], "name": "PIX_CENTER"},
13825    {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"},
13826    {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"}
13827   ]
13828  },
13829  "RLC_GPM_PERF_COUNT_0": {
13830   "fields": [
13831    {"bits": [0, 3], "name": "FEATURE_SEL"},
13832    {"bits": [4, 7], "name": "SE_INDEX"},
13833    {"bits": [8, 11], "name": "SA_INDEX"},
13834    {"bits": [12, 15], "name": "WGP_INDEX"},
13835    {"bits": [16, 17], "name": "EVENT_SEL"},
13836    {"bits": [18, 19], "name": "UNUSED"},
13837    {"bits": [20, 20], "name": "ENABLE"},
13838    {"bits": [21, 31], "name": "RESERVED"}
13839   ]
13840  },
13841  "RLC_GPU_IOV_PERF_CNT_CNTL": {
13842   "fields": [
13843    {"bits": [0, 0], "name": "ENABLE"},
13844    {"bits": [1, 1], "name": "MODE_SELECT"},
13845    {"bits": [2, 2], "name": "RESET"},
13846    {"bits": [3, 31], "name": "RESERVED"}
13847   ]
13848  },
13849  "RLC_GPU_IOV_PERF_CNT_WR_ADDR": {
13850   "fields": [
13851    {"bits": [0, 3], "name": "VFID"},
13852    {"bits": [4, 5], "name": "CNT_ID"},
13853    {"bits": [6, 31], "name": "RESERVED"}
13854   ]
13855  },
13856  "RLC_PERFCOUNTER0_SELECT": {
13857   "fields": [
13858    {"bits": [0, 7], "name": "PERFCOUNTER_SELECT"}
13859   ]
13860  },
13861  "RLC_PERFMON_CLK_CNTL": {
13862   "fields": [
13863    {"bits": [0, 0], "name": "PERFMON_CLOCK_STATE"}
13864   ]
13865  },
13866  "RLC_PERFMON_CNTL": {
13867   "fields": [
13868    {"bits": [0, 2], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"},
13869    {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"}
13870   ]
13871  },
13872  "RLC_SPM_ACCUM_CTRL": {
13873   "fields": [
13874    {"bits": [0, 0], "name": "StrobeResetPerfMonitors"},
13875    {"bits": [1, 1], "name": "StrobeStartAccumulation"},
13876    {"bits": [2, 2], "name": "StrobeRearmAccum"},
13877    {"bits": [3, 3], "name": "StrobeResetSpmBlock"},
13878    {"bits": [4, 7], "name": "StrobeStartSpm"},
13879    {"bits": [8, 8], "name": "StrobeRearmSwaAccum"},
13880    {"bits": [9, 9], "name": "StrobeStartSwa"},
13881    {"bits": [10, 10], "name": "StrobePerfmonSampleWires"},
13882    {"bits": [11, 31], "name": "RESERVED"}
13883   ]
13884  },
13885  "RLC_SPM_ACCUM_CTRLRAM_ADDR": {
13886   "fields": [
13887    {"bits": [0, 10], "name": "addr"},
13888    {"bits": [11, 31], "name": "RESERVED"}
13889   ]
13890  },
13891  "RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET": {
13892   "fields": [
13893    {"bits": [0, 7], "name": "global_offset"},
13894    {"bits": [8, 15], "name": "spmwithaccum_se_offset"},
13895    {"bits": [16, 23], "name": "spmwithaccum_global_offset"},
13896    {"bits": [24, 31], "name": "RESERVED"}
13897   ]
13898  },
13899  "RLC_SPM_ACCUM_CTRLRAM_DATA": {
13900   "fields": [
13901    {"bits": [0, 7], "name": "data"},
13902    {"bits": [8, 31], "name": "RESERVED"}
13903   ]
13904  },
13905  "RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS": {
13906   "fields": [
13907    {"bits": [0, 7], "name": "spp_addr_region"},
13908    {"bits": [8, 15], "name": "swa_addr_region"},
13909    {"bits": [16, 31], "name": "RESERVED"}
13910   ]
13911  },
13912  "RLC_SPM_ACCUM_DATARAM_ADDR": {
13913   "fields": [
13914    {"bits": [0, 6], "name": "addr"},
13915    {"bits": [7, 31], "name": "RESERVED"}
13916   ]
13917  },
13918  "RLC_SPM_ACCUM_DATARAM_WRCOUNT": {
13919   "fields": [
13920    {"bits": [0, 18], "name": "DataRamWrCount"},
13921    {"bits": [19, 31], "name": "RESERVED"}
13922   ]
13923  },
13924  "RLC_SPM_ACCUM_MODE": {
13925   "fields": [
13926    {"bits": [0, 0], "name": "EnableAccum"},
13927    {"bits": [1, 1], "name": "EnableSpmWithAccumMode"},
13928    {"bits": [2, 2], "name": "EnableSPPMode"},
13929    {"bits": [3, 3], "name": "AutoResetPerfmonDisable"},
13930    {"bits": [4, 4], "name": "SwaAutoResetPerfmonDisable"},
13931    {"bits": [5, 5], "name": "AutoAccumEn"},
13932    {"bits": [6, 6], "name": "SwaAutoAccumEn"},
13933    {"bits": [7, 7], "name": "AutoSpmEn"},
13934    {"bits": [8, 8], "name": "SwaAutoSpmEn"},
13935    {"bits": [9, 9], "name": "Globals_LoadOverride"},
13936    {"bits": [10, 10], "name": "Globals_SwaLoadOverride"},
13937    {"bits": [11, 11], "name": "SE0_LoadOverride"},
13938    {"bits": [12, 12], "name": "SE0_SwaLoadOverride"},
13939    {"bits": [13, 13], "name": "SE1_LoadOverride"},
13940    {"bits": [14, 14], "name": "SE1_SwaLoadOverride"},
13941    {"bits": [15, 15], "name": "SE2_LoadOverride"},
13942    {"bits": [16, 16], "name": "SE2_SwaLoadOverride"},
13943    {"bits": [17, 17], "name": "SE3_LoadOverride"},
13944    {"bits": [18, 18], "name": "SE3_SwaLoadOverride"}
13945   ]
13946  },
13947  "RLC_SPM_ACCUM_SAMPLES_REQUESTED": {
13948   "fields": [
13949    {"bits": [0, 7], "name": "SamplesRequested"}
13950   ]
13951  },
13952  "RLC_SPM_ACCUM_STATUS": {
13953   "fields": [
13954    {"bits": [0, 7], "name": "NumbSamplesCompleted"},
13955    {"bits": [8, 8], "name": "AccumDone"},
13956    {"bits": [9, 9], "name": "SpmDone"},
13957    {"bits": [10, 10], "name": "AccumOverflow"},
13958    {"bits": [11, 11], "name": "AccumArmed"},
13959    {"bits": [12, 12], "name": "SequenceInProgress"},
13960    {"bits": [13, 13], "name": "FinalSequenceInProgress"},
13961    {"bits": [14, 14], "name": "AllFifosEmpty"},
13962    {"bits": [15, 15], "name": "FSMIsIdle"},
13963    {"bits": [16, 16], "name": "SwaAccumDone"},
13964    {"bits": [17, 17], "name": "SwaSpmDone"},
13965    {"bits": [18, 18], "name": "SwaAccumOverflow"},
13966    {"bits": [19, 19], "name": "SwaAccumArmed"},
13967    {"bits": [20, 20], "name": "AllSegsDone"},
13968    {"bits": [21, 21], "name": "RearmSwaPending"},
13969    {"bits": [22, 22], "name": "RearmSppPending"},
13970    {"bits": [23, 31], "name": "RESERVED"}
13971   ]
13972  },
13973  "RLC_SPM_ACCUM_THRESHOLD": {
13974   "fields": [
13975    {"bits": [0, 15], "name": "Threshold"}
13976   ]
13977  },
13978  "RLC_SPM_DESER_START_SKEW": {
13979   "fields": [
13980    {"bits": [0, 6], "name": "DESER_START_SKEW"},
13981    {"bits": [7, 31], "name": "RESERVED"}
13982   ]
13983  },
13984  "RLC_SPM_GLB_SAMPLEDELAY_IND_DATA": {
13985   "fields": [
13986    {"bits": [0, 6], "name": "data"},
13987    {"bits": [7, 31], "name": "RESERVED"}
13988   ]
13989  },
13990  "RLC_SPM_GLOBALS_MUXSEL_SKEW": {
13991   "fields": [
13992    {"bits": [0, 6], "name": "GLOBALS_MUXSEL_SKEW"},
13993    {"bits": [7, 31], "name": "RESERVED"}
13994   ]
13995  },
13996  "RLC_SPM_GLOBALS_SAMPLE_SKEW": {
13997   "fields": [
13998    {"bits": [0, 6], "name": "GLOBALS_SAMPLE_SKEW"},
13999    {"bits": [7, 31], "name": "RESERVED"}
14000   ]
14001  },
14002  "RLC_SPM_GLOBAL_MUXSEL_ADDR": {
14003   "fields": [
14004    {"bits": [0, 7], "name": "PERFMON_SEL_ADDR"},
14005    {"bits": [8, 31], "name": "RESERVED"}
14006   ]
14007  },
14008  "RLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET": {
14009   "fields": [
14010    {"bits": [0, 15], "name": "OFFSET"},
14011    {"bits": [16, 31], "name": "RESERVED"}
14012   ]
14013  },
14014  "RLC_SPM_PERFMON_CNTL": {
14015   "fields": [
14016    {"bits": [0, 11], "name": "RESERVED1"},
14017    {"bits": [12, 13], "name": "PERFMON_RING_MODE"},
14018    {"bits": [14, 15], "name": "RESERVED"},
14019    {"bits": [16, 31], "name": "PERFMON_SAMPLE_INTERVAL"}
14020   ]
14021  },
14022  "RLC_SPM_PERFMON_GLB_SEGMENT_SIZE": {
14023   "fields": [
14024    {"bits": [0, 7], "name": "PERFMON_SEGMENT_SIZE"},
14025    {"bits": [8, 15], "name": "GLOBAL_NUM_LINE"},
14026    {"bits": [16, 31], "name": "RESERVED"}
14027   ]
14028  },
14029  "RLC_SPM_PERFMON_RING_BASE_HI": {
14030   "fields": [
14031    {"bits": [0, 15], "name": "RING_BASE_HI"},
14032    {"bits": [16, 31], "name": "RESERVED"}
14033   ]
14034  },
14035  "RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE": {
14036   "fields": [
14037    {"bits": [0, 7], "name": "SE0_NUM_LINE"},
14038    {"bits": [8, 15], "name": "SE1_NUM_LINE"},
14039    {"bits": [16, 23], "name": "SE2_NUM_LINE"},
14040    {"bits": [24, 31], "name": "SE3_NUM_LINE"}
14041   ]
14042  },
14043  "RLC_SPM_PERFMON_SEGMENT_SIZE": {
14044   "fields": [
14045    {"bits": [0, 7], "name": "PERFMON_SEGMENT_SIZE"},
14046    {"bits": [8, 10], "name": "RESERVED1"},
14047    {"bits": [11, 15], "name": "GLOBAL_NUM_LINE"},
14048    {"bits": [16, 20], "name": "SE0_NUM_LINE"},
14049    {"bits": [21, 25], "name": "SE1_NUM_LINE"},
14050    {"bits": [26, 30], "name": "SE2_NUM_LINE"},
14051    {"bits": [31, 31], "name": "RESERVED"}
14052   ]
14053  },
14054  "RLC_SPM_RING_WRPTR": {
14055   "fields": [
14056    {"bits": [0, 4], "name": "RESERVED"},
14057    {"bits": [5, 31], "name": "PERFMON_RING_WRPTR"}
14058   ]
14059  },
14060  "RLC_SPM_SEGMENT_THRESHOLD": {
14061   "fields": [
14062    {"bits": [0, 7], "name": "NUM_SEGMENT_THRESHOLD"},
14063    {"bits": [8, 31], "name": "RESERVED"}
14064   ]
14065  },
14066  "RLC_SPM_SE_MUXSEL_ADDR": {
14067   "fields": [
14068    {"bits": [0, 8], "name": "PERFMON_SEL_ADDR"},
14069    {"bits": [9, 31], "name": "RESERVED"}
14070   ]
14071  },
14072  "RLC_SPM_SE_MUXSEL_SKEW": {
14073   "fields": [
14074    {"bits": [0, 6], "name": "SE_MUXSEL_SKEW"},
14075    {"bits": [7, 31], "name": "RESERVED"}
14076   ]
14077  },
14078  "RLC_SPM_SE_SAMPLE_SKEW": {
14079   "fields": [
14080    {"bits": [0, 6], "name": "SE_SAMPLE_SKEW"},
14081    {"bits": [7, 31], "name": "RESERVED"}
14082   ]
14083  },
14084  "RLC_SPM_VIRT_CTRL": {
14085   "fields": [
14086    {"bits": [0, 0], "name": "PauseSpmSamplingRequest"}
14087   ]
14088  },
14089  "RLC_SPM_VIRT_STATUS": {
14090   "fields": [
14091    {"bits": [0, 0], "name": "SpmSamplingPaused"}
14092   ]
14093  },
14094  "RMI_PERF_COUNTER_CNTL": {
14095   "fields": [
14096    {"bits": [0, 1], "name": "TRANS_BASED_PERF_EN_SEL"},
14097    {"bits": [2, 3], "name": "EVENT_BASED_PERF_EN_SEL"},
14098    {"bits": [4, 5], "name": "TC_PERF_EN_SEL"},
14099    {"bits": [6, 7], "name": "PERF_EVENT_WINDOW_MASK0"},
14100    {"bits": [8, 9], "name": "PERF_EVENT_WINDOW_MASK1"},
14101    {"bits": [10, 13], "name": "PERF_COUNTER_CID"},
14102    {"bits": [14, 18], "name": "PERF_COUNTER_VMID"},
14103    {"bits": [19, 24], "name": "PERF_COUNTER_BURST_LENGTH_THRESHOLD"},
14104    {"bits": [25, 25], "name": "PERF_SOFT_RESET"},
14105    {"bits": [26, 26], "name": "PERF_CNTR_SPM_SEL"}
14106   ]
14107  },
14108  "SCRATCH_REG_ATOMIC": {
14109   "fields": [
14110    {"bits": [0, 23], "name": "IMMED"},
14111    {"bits": [24, 26], "name": "ID"},
14112    {"bits": [27, 27], "name": "reserved27"},
14113    {"bits": [28, 30], "name": "OP"},
14114    {"bits": [31, 31], "name": "reserved31"}
14115   ]
14116  },
14117  "SCRATCH_UMSK": {
14118   "fields": [
14119    {"bits": [0, 7], "name": "OBSOLETE_UMSK"},
14120    {"bits": [16, 17], "name": "OBSOLETE_SWAP"}
14121   ]
14122  },
14123  "SDMA0_PERFCNT_MISC_CNTL": {
14124   "fields": [
14125    {"bits": [0, 15], "name": "CMD_OP"}
14126   ]
14127  },
14128  "SPI_BARYC_CNTL": {
14129   "fields": [
14130    {"bits": [0, 0], "name": "PERSP_CENTER_CNTL"},
14131    {"bits": [4, 4], "name": "PERSP_CENTROID_CNTL"},
14132    {"bits": [8, 8], "name": "LINEAR_CENTER_CNTL"},
14133    {"bits": [12, 12], "name": "LINEAR_CENTROID_CNTL"},
14134    {"bits": [16, 17], "name": "POS_FLOAT_LOCATION"},
14135    {"bits": [20, 20], "name": "POS_FLOAT_ULC"},
14136    {"bits": [24, 24], "name": "FRONT_FACE_ALL_BITS"}
14137   ]
14138  },
14139  "SPI_CONFIG_CNTL": {
14140   "fields": [
14141    {"bits": [0, 20], "name": "GPR_WRITE_PRIORITY"},
14142    {"bits": [21, 23], "name": "EXP_PRIORITY_ORDER"},
14143    {"bits": [24, 24], "name": "ENABLE_SQG_TOP_EVENTS"},
14144    {"bits": [25, 25], "name": "ENABLE_SQG_BOP_EVENTS"},
14145    {"bits": [26, 26], "name": "FORCE_HALF_RATE_PC_EXP"},
14146    {"bits": [27, 27], "name": "TTRACE_STALL_ALL"},
14147    {"bits": [28, 28], "name": "ALLOC_ARB_LRU_ENA"},
14148    {"bits": [29, 29], "name": "EXP_ARB_LRU_ENA"},
14149    {"bits": [30, 31], "name": "PS_PKR_PRIORITY_CNTL"}
14150   ]
14151  },
14152  "SPI_INTERP_CONTROL_0": {
14153   "fields": [
14154    {"bits": [0, 0], "name": "FLAT_SHADE_ENA"},
14155    {"bits": [1, 1], "name": "PNT_SPRITE_ENA"},
14156    {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"},
14157    {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"},
14158    {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"},
14159    {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"},
14160    {"bits": [14, 14], "name": "PNT_SPRITE_TOP_1"}
14161   ]
14162  },
14163  "SPI_PERFCOUNTER_BINS": {
14164   "fields": [
14165    {"bits": [0, 3], "name": "BIN0_MIN"},
14166    {"bits": [4, 7], "name": "BIN0_MAX"},
14167    {"bits": [8, 11], "name": "BIN1_MIN"},
14168    {"bits": [12, 15], "name": "BIN1_MAX"},
14169    {"bits": [16, 19], "name": "BIN2_MIN"},
14170    {"bits": [20, 23], "name": "BIN2_MAX"},
14171    {"bits": [24, 27], "name": "BIN3_MIN"},
14172    {"bits": [28, 31], "name": "BIN3_MAX"}
14173   ]
14174  },
14175  "SPI_PS_INPUT_CNTL_0": {
14176   "fields": [
14177    {"bits": [0, 5], "name": "OFFSET"},
14178    {"bits": [8, 9], "name": "DEFAULT_VAL"},
14179    {"bits": [10, 10], "name": "FLAT_SHADE"},
14180    {"bits": [11, 11], "name": "ROTATE_PC_PTR"},
14181    {"bits": [13, 16], "name": "CYL_WRAP"},
14182    {"bits": [17, 17], "name": "PT_SPRITE_TEX"},
14183    {"bits": [18, 18], "name": "DUP"},
14184    {"bits": [19, 19], "name": "FP16_INTERP_MODE"},
14185    {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"},
14186    {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"},
14187    {"bits": [23, 23], "name": "PT_SPRITE_TEX_ATTR1"},
14188    {"bits": [24, 24], "name": "ATTR0_VALID"},
14189    {"bits": [25, 25], "name": "ATTR1_VALID"}
14190   ]
14191  },
14192  "SPI_PS_INPUT_CNTL_20": {
14193   "fields": [
14194    {"bits": [0, 5], "name": "OFFSET"},
14195    {"bits": [8, 9], "name": "DEFAULT_VAL"},
14196    {"bits": [10, 10], "name": "FLAT_SHADE"},
14197    {"bits": [11, 11], "name": "ROTATE_PC_PTR"},
14198    {"bits": [18, 18], "name": "DUP"},
14199    {"bits": [19, 19], "name": "FP16_INTERP_MODE"},
14200    {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"},
14201    {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"},
14202    {"bits": [24, 24], "name": "ATTR0_VALID"},
14203    {"bits": [25, 25], "name": "ATTR1_VALID"}
14204   ]
14205  },
14206  "SPI_PS_INPUT_ENA": {
14207   "fields": [
14208    {"bits": [0, 0], "name": "PERSP_SAMPLE_ENA"},
14209    {"bits": [1, 1], "name": "PERSP_CENTER_ENA"},
14210    {"bits": [2, 2], "name": "PERSP_CENTROID_ENA"},
14211    {"bits": [3, 3], "name": "PERSP_PULL_MODEL_ENA"},
14212    {"bits": [4, 4], "name": "LINEAR_SAMPLE_ENA"},
14213    {"bits": [5, 5], "name": "LINEAR_CENTER_ENA"},
14214    {"bits": [6, 6], "name": "LINEAR_CENTROID_ENA"},
14215    {"bits": [7, 7], "name": "LINE_STIPPLE_TEX_ENA"},
14216    {"bits": [8, 8], "name": "POS_X_FLOAT_ENA"},
14217    {"bits": [9, 9], "name": "POS_Y_FLOAT_ENA"},
14218    {"bits": [10, 10], "name": "POS_Z_FLOAT_ENA"},
14219    {"bits": [11, 11], "name": "POS_W_FLOAT_ENA"},
14220    {"bits": [12, 12], "name": "FRONT_FACE_ENA"},
14221    {"bits": [13, 13], "name": "ANCILLARY_ENA"},
14222    {"bits": [14, 14], "name": "SAMPLE_COVERAGE_ENA"},
14223    {"bits": [15, 15], "name": "POS_FIXED_PT_ENA"}
14224   ]
14225  },
14226  "SPI_PS_IN_CONTROL": {
14227   "fields": [
14228    {"bits": [0, 5], "name": "NUM_INTERP"},
14229    {"bits": [7, 7], "name": "OFFCHIP_PARAM_EN"},
14230    {"bits": [8, 8], "name": "LATE_PC_DEALLOC"},
14231    {"bits": [9, 13], "name": "NUM_PRIM_INTERP"},
14232    {"bits": [14, 14], "name": "BC_OPTIMIZE_DISABLE"},
14233    {"bits": [15, 15], "name": "PS_W32_EN"}
14234   ]
14235  },
14236  "SPI_SHADER_COL_FORMAT": {
14237   "fields": [
14238    {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"},
14239    {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"},
14240    {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"},
14241    {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"},
14242    {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"},
14243    {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"},
14244    {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"},
14245    {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"}
14246   ]
14247  },
14248  "SPI_SHADER_IDX_FORMAT": {
14249   "fields": [
14250    {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "IDX0_EXPORT_FORMAT"}
14251   ]
14252  },
14253  "SPI_SHADER_LATE_ALLOC_VS": {
14254   "fields": [
14255    {"bits": [0, 5], "name": "LIMIT"}
14256   ]
14257  },
14258  "SPI_SHADER_PGM_HI_PS": {
14259   "fields": [
14260    {"bits": [0, 7], "name": "MEM_BASE"}
14261   ]
14262  },
14263  "SPI_SHADER_PGM_RSRC1_GS": {
14264   "fields": [
14265    {"bits": [0, 5], "name": "VGPRS"},
14266    {"bits": [6, 9], "name": "SGPRS"},
14267    {"bits": [10, 11], "name": "PRIORITY"},
14268    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
14269    {"bits": [20, 20], "name": "PRIV"},
14270    {"bits": [21, 21], "name": "DX10_CLAMP"},
14271    {"bits": [23, 23], "name": "IEEE_MODE"},
14272    {"bits": [24, 24], "name": "CU_GROUP_ENABLE"},
14273    {"bits": [25, 25], "name": "MEM_ORDERED"},
14274    {"bits": [26, 26], "name": "FWD_PROGRESS"},
14275    {"bits": [27, 27], "name": "WGP_MODE"},
14276    {"bits": [29, 30], "name": "GS_VGPR_COMP_CNT"},
14277    {"bits": [31, 31], "name": "FP16_OVFL"}
14278   ]
14279  },
14280  "SPI_SHADER_PGM_RSRC1_HS": {
14281   "fields": [
14282    {"bits": [0, 5], "name": "VGPRS"},
14283    {"bits": [6, 9], "name": "SGPRS"},
14284    {"bits": [10, 11], "name": "PRIORITY"},
14285    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
14286    {"bits": [20, 20], "name": "PRIV"},
14287    {"bits": [21, 21], "name": "DX10_CLAMP"},
14288    {"bits": [23, 23], "name": "IEEE_MODE"},
14289    {"bits": [24, 24], "name": "MEM_ORDERED"},
14290    {"bits": [25, 25], "name": "FWD_PROGRESS"},
14291    {"bits": [26, 26], "name": "WGP_MODE"},
14292    {"bits": [28, 29], "name": "LS_VGPR_COMP_CNT"},
14293    {"bits": [30, 30], "name": "FP16_OVFL"}
14294   ]
14295  },
14296  "SPI_SHADER_PGM_RSRC1_PS": {
14297   "fields": [
14298    {"bits": [0, 5], "name": "VGPRS"},
14299    {"bits": [6, 9], "name": "SGPRS"},
14300    {"bits": [10, 11], "name": "PRIORITY"},
14301    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
14302    {"bits": [20, 20], "name": "PRIV"},
14303    {"bits": [21, 21], "name": "DX10_CLAMP"},
14304    {"bits": [23, 23], "name": "IEEE_MODE"},
14305    {"bits": [24, 24], "name": "CU_GROUP_DISABLE"},
14306    {"bits": [25, 25], "name": "MEM_ORDERED"},
14307    {"bits": [26, 26], "name": "FWD_PROGRESS"},
14308    {"bits": [27, 27], "name": "LOAD_PROVOKING_VTX"},
14309    {"bits": [29, 29], "name": "FP16_OVFL"}
14310   ]
14311  },
14312  "SPI_SHADER_PGM_RSRC1_VS": {
14313   "fields": [
14314    {"bits": [0, 5], "name": "VGPRS"},
14315    {"bits": [6, 9], "name": "SGPRS"},
14316    {"bits": [10, 11], "name": "PRIORITY"},
14317    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
14318    {"bits": [20, 20], "name": "PRIV"},
14319    {"bits": [21, 21], "name": "DX10_CLAMP"},
14320    {"bits": [23, 23], "name": "IEEE_MODE"},
14321    {"bits": [24, 25], "name": "VGPR_COMP_CNT"},
14322    {"bits": [26, 26], "name": "CU_GROUP_ENABLE"},
14323    {"bits": [27, 27], "name": "MEM_ORDERED"},
14324    {"bits": [28, 28], "name": "FWD_PROGRESS"},
14325    {"bits": [31, 31], "name": "FP16_OVFL"}
14326   ]
14327  },
14328  "SPI_SHADER_PGM_RSRC2_GS": {
14329   "fields": [
14330    {"bits": [0, 0], "name": "SCRATCH_EN"},
14331    {"bits": [1, 5], "name": "USER_SGPR"},
14332    {"bits": [6, 6], "name": "TRAP_PRESENT"},
14333    {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14334    {"bits": [16, 17], "name": "ES_VGPR_COMP_CNT"},
14335    {"bits": [18, 18], "name": "OC_LDS_EN"},
14336    {"bits": [19, 26], "name": "LDS_SIZE"},
14337    {"bits": [27, 27], "name": "USER_SGPR_MSB"},
14338    {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
14339   ]
14340  },
14341  "SPI_SHADER_PGM_RSRC2_GS_VS": {
14342   "fields": [
14343    {"bits": [0, 0], "name": "SCRATCH_EN"},
14344    {"bits": [1, 5], "name": "USER_SGPR"},
14345    {"bits": [6, 6], "name": "TRAP_PRESENT"},
14346    {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14347    {"bits": [16, 17], "name": "VGPR_COMP_CNT"},
14348    {"bits": [18, 18], "name": "OC_LDS_EN"},
14349    {"bits": [19, 26], "name": "LDS_SIZE"},
14350    {"bits": [27, 27], "name": "SKIP_USGPR0"},
14351    {"bits": [28, 28], "name": "USER_SGPR_MSB"}
14352   ]
14353  },
14354  "SPI_SHADER_PGM_RSRC2_HS": {
14355   "fields": [
14356    {"bits": [0, 0], "name": "SCRATCH_EN"},
14357    {"bits": [1, 5], "name": "USER_SGPR"},
14358    {"bits": [6, 6], "name": "TRAP_PRESENT"},
14359    {"bits": [7, 7], "name": "OC_LDS_EN"},
14360    {"bits": [8, 8], "name": "TG_SIZE_EN"},
14361    {"bits": [9, 17], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14362    {"bits": [18, 26], "name": "LDS_SIZE"},
14363    {"bits": [27, 27], "name": "USER_SGPR_MSB"},
14364    {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
14365   ]
14366  },
14367  "SPI_SHADER_PGM_RSRC2_PS": {
14368   "fields": [
14369    {"bits": [0, 0], "name": "SCRATCH_EN"},
14370    {"bits": [1, 5], "name": "USER_SGPR"},
14371    {"bits": [6, 6], "name": "TRAP_PRESENT"},
14372    {"bits": [7, 7], "name": "WAVE_CNT_EN"},
14373    {"bits": [8, 15], "name": "EXTRA_LDS_SIZE"},
14374    {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14375    {"bits": [25, 25], "name": "LOAD_COLLISION_WAVEID"},
14376    {"bits": [26, 26], "name": "LOAD_INTRAWAVE_COLLISION"},
14377    {"bits": [27, 27], "name": "USER_SGPR_MSB"},
14378    {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
14379   ]
14380  },
14381  "SPI_SHADER_PGM_RSRC2_VS": {
14382   "fields": [
14383    {"bits": [0, 0], "name": "SCRATCH_EN"},
14384    {"bits": [1, 5], "name": "USER_SGPR"},
14385    {"bits": [6, 6], "name": "TRAP_PRESENT"},
14386    {"bits": [7, 7], "name": "OC_LDS_EN"},
14387    {"bits": [8, 8], "name": "SO_BASE0_EN"},
14388    {"bits": [9, 9], "name": "SO_BASE1_EN"},
14389    {"bits": [10, 10], "name": "SO_BASE2_EN"},
14390    {"bits": [11, 11], "name": "SO_BASE3_EN"},
14391    {"bits": [12, 12], "name": "SO_EN"},
14392    {"bits": [13, 21], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14393    {"bits": [22, 22], "name": "PC_BASE_EN"},
14394    {"bits": [24, 24], "name": "DISPATCH_DRAW_EN"},
14395    {"bits": [27, 27], "name": "USER_SGPR_MSB"},
14396    {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
14397   ]
14398  },
14399  "SPI_SHADER_PGM_RSRC3_GS": {
14400   "fields": [
14401    {"bits": [0, 15], "name": "CU_EN"},
14402    {"bits": [16, 21], "name": "WAVE_LIMIT"},
14403    {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"},
14404    {"bits": [26, 31], "name": "GROUP_FIFO_DEPTH"}
14405   ]
14406  },
14407  "SPI_SHADER_PGM_RSRC3_HS": {
14408   "fields": [
14409    {"bits": [0, 5], "name": "WAVE_LIMIT"},
14410    {"bits": [6, 9], "name": "LOCK_LOW_THRESHOLD"},
14411    {"bits": [10, 15], "name": "GROUP_FIFO_DEPTH"},
14412    {"bits": [16, 31], "name": "CU_EN"}
14413   ]
14414  },
14415  "SPI_SHADER_PGM_RSRC3_PS": {
14416   "fields": [
14417    {"bits": [0, 15], "name": "CU_EN"},
14418    {"bits": [16, 21], "name": "WAVE_LIMIT"},
14419    {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"}
14420   ]
14421  },
14422  "SPI_SHADER_PGM_RSRC4_GS": {
14423   "fields": [
14424    {"bits": [0, 15], "name": "CU_EN"},
14425    {"bits": [16, 22], "name": "SPI_SHADER_LATE_ALLOC_GS"}
14426   ]
14427  },
14428  "SPI_SHADER_PGM_RSRC4_PS": {
14429   "fields": [
14430    {"bits": [0, 15], "name": "CU_EN"}
14431   ]
14432  },
14433  "SPI_SHADER_POS_FORMAT": {
14434   "fields": [
14435    {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"},
14436    {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"},
14437    {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"},
14438    {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"},
14439    {"bits": [16, 19], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS4_EXPORT_FORMAT"}
14440   ]
14441  },
14442  "SPI_SHADER_REQ_CTRL_PS": {
14443   "fields": [
14444    {"bits": [0, 0], "name": "SOFT_GROUPING_EN"},
14445    {"bits": [1, 4], "name": "NUMBER_OF_REQUESTS_PER_CU"},
14446    {"bits": [5, 8], "name": "SOFT_GROUPING_ALLOCATION_TIMEOUT"},
14447    {"bits": [9, 9], "name": "HARD_LOCK_HYSTERESIS"},
14448    {"bits": [10, 14], "name": "HARD_LOCK_LOW_THRESHOLD"},
14449    {"bits": [15, 15], "name": "PRODUCER_REQUEST_LOCKOUT"},
14450    {"bits": [16, 16], "name": "GLOBAL_SCANNING_EN"},
14451    {"bits": [17, 19], "name": "ALLOCATION_RATE_THROTTLING_THRESHOLD"}
14452   ]
14453  },
14454  "SPI_SHADER_USER_ACCUM_PS_0": {
14455   "fields": [
14456    {"bits": [0, 6], "name": "CONTRIBUTION"}
14457   ]
14458  },
14459  "SPI_SHADER_Z_FORMAT": {
14460   "fields": [
14461    {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"}
14462   ]
14463  },
14464  "SPI_VS_OUT_CONFIG": {
14465   "fields": [
14466    {"bits": [1, 5], "name": "VS_EXPORT_COUNT"},
14467    {"bits": [6, 6], "name": "VS_HALF_PACK"},
14468    {"bits": [7, 7], "name": "NO_PC_EXPORT"},
14469    {"bits": [8, 12], "name": "PRIM_EXPORT_COUNT"}
14470   ]
14471  },
14472  "SQC_CACHES": {
14473   "fields": [
14474    {"bits": [0, 0], "name": "TARGET_INST"},
14475    {"bits": [1, 1], "name": "TARGET_DATA"},
14476    {"bits": [2, 2], "name": "INVALIDATE"},
14477    {"bits": [16, 16], "name": "COMPLETE"},
14478    {"bits": [17, 18], "name": "L2_WB_POLICY"}
14479   ]
14480  },
14481  "SQ_PERFCOUNTER0_SELECT": {
14482   "fields": [
14483    {"bits": [0, 8], "name": "PERF_SEL"},
14484    {"bits": [20, 23], "name": "SPM_MODE"},
14485    {"bits": [28, 31], "name": "PERF_MODE"}
14486   ]
14487  },
14488  "SQ_PERFCOUNTER_CTRL": {
14489   "fields": [
14490    {"bits": [0, 0], "name": "PS_EN"},
14491    {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"},
14492    {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},
14493    {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"},
14494    {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},
14495    {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"},
14496    {"bits": [6, 6], "name": "CS_EN"},
14497    {"bits": [8, 9], "name": "CNTR_RATE"},
14498    {"bits": [13, 13], "name": "DISABLE_FLUSH"},
14499    {"bits": [14, 14], "name": "DISABLE_ME0PIPE0_PERF"},
14500    {"bits": [15, 15], "name": "DISABLE_ME0PIPE1_PERF"},
14501    {"bits": [16, 16], "name": "DISABLE_ME1PIPE0_PERF"},
14502    {"bits": [17, 17], "name": "DISABLE_ME1PIPE1_PERF"},
14503    {"bits": [18, 18], "name": "DISABLE_ME1PIPE2_PERF"},
14504    {"bits": [19, 19], "name": "DISABLE_ME1PIPE3_PERF"}
14505   ]
14506  },
14507  "SQ_PERFCOUNTER_CTRL2": {
14508   "fields": [
14509    {"bits": [0, 0], "name": "FORCE_EN"}
14510   ]
14511  },
14512  "SQ_THREAD_TRACE_BUF0_SIZE": {
14513   "fields": [
14514    {"bits": [0, 3], "name": "BASE_HI"},
14515    {"bits": [8, 29], "name": "SIZE"}
14516   ]
14517  },
14518  "SQ_THREAD_TRACE_CTRL": {
14519   "fields": [
14520    {"bits": [0, 1], "name": "MODE"},
14521    {"bits": [2, 2], "name": "ALL_VMID"},
14522    {"bits": [3, 3], "name": "CH_PERF_EN"},
14523    {"bits": [4, 4], "name": "INTERRUPT_EN"},
14524    {"bits": [5, 5], "name": "DOUBLE_BUFFER"},
14525    {"bits": [6, 8], "name": "HIWATER"},
14526    {"bits": [9, 9], "name": "REG_STALL_EN"},
14527    {"bits": [10, 10], "name": "SPI_STALL_EN"},
14528    {"bits": [11, 11], "name": "SQ_STALL_EN"},
14529    {"bits": [12, 12], "name": "REG_DROP_ON_STALL"},
14530    {"bits": [13, 13], "name": "UTIL_TIMER"},
14531    {"bits": [14, 15], "name": "WAVESTART_MODE"},
14532    {"bits": [16, 17], "name": "RT_FREQ"},
14533    {"bits": [18, 18], "name": "SYNC_COUNT_MARKERS"},
14534    {"bits": [19, 19], "name": "SYNC_COUNT_DRAWS"},
14535    {"bits": [20, 22], "name": "LOWATER_OFFSET"},
14536    {"bits": [28, 28], "name": "AUTO_FLUSH_PADDING_DIS"},
14537    {"bits": [29, 29], "name": "AUTO_FLUSH_MODE"},
14538    {"bits": [30, 30], "name": "CAPTURE_ALL"},
14539    {"bits": [31, 31], "name": "DRAW_EVENT_EN"}
14540   ]
14541  },
14542  "SQ_THREAD_TRACE_MASK": {
14543   "fields": [
14544    {"bits": [0, 1], "name": "SIMD_SEL"},
14545    {"bits": [4, 7], "name": "WGP_SEL"},
14546    {"bits": [9, 9], "name": "SA_SEL"},
14547    {"bits": [10, 16], "name": "WTYPE_INCLUDE"}
14548   ]
14549  },
14550  "SQ_THREAD_TRACE_STATUS": {
14551   "fields": [
14552    {"bits": [0, 11], "name": "FINISH_PENDING"},
14553    {"bits": [12, 23], "name": "FINISH_DONE"},
14554    {"bits": [24, 24], "name": "UTC_ERR"},
14555    {"bits": [25, 25], "name": "BUSY"},
14556    {"bits": [26, 26], "name": "EVENT_CNTR_OVERFLOW"},
14557    {"bits": [27, 27], "name": "EVENT_CNTR_STALL"},
14558    {"bits": [28, 31], "name": "OWNER_VMID"}
14559   ]
14560  },
14561  "SQ_THREAD_TRACE_STATUS2": {
14562   "fields": [
14563    {"bits": [0, 0], "name": "BUF0_FULL"},
14564    {"bits": [1, 1], "name": "BUF1_FULL"},
14565    {"bits": [4, 4], "name": "PACKET_LOST_BUF_NO_LOCKDOWN"}
14566   ]
14567  },
14568  "SQ_THREAD_TRACE_TOKEN_MASK": {
14569   "fields": [
14570    {"bits": [0, 10], "enum_ref": "ThreadTraceTokenExclude", "name": "TOKEN_EXCLUDE"},
14571    {"bits": [12, 12], "name": "BOP_EVENTS_TOKEN_INCLUDE"},
14572    {"bits": [16, 23], "enum_ref": "ThreadTraceRegInclude", "name": "REG_INCLUDE"},
14573    {"bits": [24, 25], "name": "INST_EXCLUDE"},
14574    {"bits": [26, 28], "name": "REG_EXCLUDE"},
14575    {"bits": [31, 31], "name": "REG_DETAIL_ALL"}
14576   ]
14577  },
14578  "SQ_THREAD_TRACE_WPTR": {
14579   "fields": [
14580    {"bits": [0, 28], "name": "OFFSET"},
14581    {"bits": [31, 31], "name": "BUFFER_ID"}
14582   ]
14583  },
14584  "SQ_WAVE_ACTIVE": {
14585   "fields": [
14586    {"bits": [0, 19], "name": "WAVE_SLOT"}
14587   ]
14588  },
14589  "SQ_WAVE_GPR_ALLOC": {
14590   "fields": [
14591    {"bits": [0, 7], "name": "VGPR_BASE"},
14592    {"bits": [8, 15], "name": "VGPR_SIZE"},
14593    {"bits": [16, 23], "name": "SGPR_BASE"},
14594    {"bits": [24, 27], "name": "SGPR_SIZE"}
14595   ]
14596  },
14597  "SQ_WAVE_HW_ID1": {
14598   "fields": [
14599    {"bits": [0, 4], "name": "WAVE_ID"},
14600    {"bits": [8, 9], "name": "SIMD_ID"},
14601    {"bits": [10, 13], "name": "WGP_ID"},
14602    {"bits": [16, 16], "name": "SA_ID"},
14603    {"bits": [18, 19], "name": "SE_ID"}
14604   ]
14605  },
14606  "SQ_WAVE_HW_ID2": {
14607   "fields": [
14608    {"bits": [0, 3], "name": "QUEUE_ID"},
14609    {"bits": [4, 5], "name": "PIPE_ID"},
14610    {"bits": [8, 9], "name": "ME_ID"},
14611    {"bits": [12, 14], "name": "STATE_ID"},
14612    {"bits": [16, 20], "name": "WG_ID"},
14613    {"bits": [24, 27], "name": "VM_ID"}
14614   ]
14615  },
14616  "SQ_WAVE_HW_ID_LEGACY": {
14617   "fields": [
14618    {"bits": [0, 3], "name": "WAVE_ID"},
14619    {"bits": [4, 5], "name": "SIMD_ID"},
14620    {"bits": [6, 7], "name": "PIPE_ID"},
14621    {"bits": [8, 11], "name": "CU_ID"},
14622    {"bits": [12, 12], "name": "SH_ID"},
14623    {"bits": [13, 14], "name": "SE_ID"},
14624    {"bits": [15, 15], "name": "WAVE_ID_MSB"},
14625    {"bits": [16, 19], "name": "TG_ID"},
14626    {"bits": [20, 23], "name": "VM_ID"},
14627    {"bits": [24, 26], "name": "QUEUE_ID"},
14628    {"bits": [27, 29], "name": "STATE_ID"},
14629    {"bits": [30, 31], "name": "ME_ID"}
14630   ]
14631  },
14632  "SQ_WAVE_IB_DBG1": {
14633   "fields": [
14634    {"bits": [24, 24], "name": "WAVE_IDLE"},
14635    {"bits": [25, 31], "name": "MISC_CNT"}
14636   ]
14637  },
14638  "SQ_WAVE_IB_STS": {
14639   "fields": [
14640    {"bits": [0, 3], "name": "VM_CNT"},
14641    {"bits": [4, 6], "name": "EXP_CNT"},
14642    {"bits": [7, 7], "name": "LGKM_CNT_BIT4"},
14643    {"bits": [8, 11], "name": "LGKM_CNT"},
14644    {"bits": [12, 14], "name": "VALU_CNT"},
14645    {"bits": [22, 23], "name": "VM_CNT_HI"},
14646    {"bits": [24, 24], "name": "LGKM_CNT_BIT5"},
14647    {"bits": [26, 31], "name": "VS_CNT"}
14648   ]
14649  },
14650  "SQ_WAVE_IB_STS2": {
14651   "fields": [
14652    {"bits": [0, 1], "name": "INST_PREFETCH"},
14653    {"bits": [7, 7], "name": "RESOURCE_OVERRIDE"},
14654    {"bits": [8, 9], "name": "MEM_ORDER"},
14655    {"bits": [10, 10], "name": "FWD_PROGRESS"},
14656    {"bits": [11, 11], "name": "WAVE64"}
14657   ]
14658  },
14659  "SQ_WAVE_LDS_ALLOC": {
14660   "fields": [
14661    {"bits": [0, 8], "name": "LDS_BASE"},
14662    {"bits": [12, 20], "name": "LDS_SIZE"},
14663    {"bits": [24, 27], "name": "VGPR_SHARED_SIZE"}
14664   ]
14665  },
14666  "SQ_WAVE_MODE": {
14667   "fields": [
14668    {"bits": [0, 3], "name": "FP_ROUND"},
14669    {"bits": [4, 7], "name": "FP_DENORM"},
14670    {"bits": [8, 8], "name": "DX10_CLAMP"},
14671    {"bits": [9, 9], "name": "IEEE"},
14672    {"bits": [10, 10], "name": "LOD_CLAMPED"},
14673    {"bits": [12, 20], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14674    {"bits": [23, 23], "name": "FP16_OVFL"},
14675    {"bits": [27, 27], "name": "DISABLE_PERF"}
14676   ]
14677  },
14678  "SQ_WAVE_PC_HI": {
14679   "fields": [
14680    {"bits": [0, 15], "name": "PC_HI"}
14681   ]
14682  },
14683  "SQ_WAVE_POPS_PACKER": {
14684   "fields": [
14685    {"bits": [0, 0], "name": "POPS_EN"},
14686    {"bits": [1, 2], "name": "POPS_PACKER_ID"}
14687   ]
14688  },
14689  "SQ_WAVE_SCHED_MODE": {
14690   "fields": [
14691    {"bits": [0, 1], "name": "DEP_MODE"}
14692   ]
14693  },
14694  "SQ_WAVE_SHADER_CYCLES": {
14695   "fields": [
14696    {"bits": [0, 19], "name": "CYCLES"}
14697   ]
14698  },
14699  "SQ_WAVE_STATUS": {
14700   "fields": [
14701    {"bits": [0, 0], "name": "SCC"},
14702    {"bits": [1, 2], "name": "SPI_PRIO"},
14703    {"bits": [3, 4], "name": "USER_PRIO"},
14704    {"bits": [5, 5], "name": "PRIV"},
14705    {"bits": [6, 6], "name": "TRAP_EN"},
14706    {"bits": [7, 7], "name": "TTRACE_EN"},
14707    {"bits": [8, 8], "name": "EXPORT_RDY"},
14708    {"bits": [9, 9], "name": "EXECZ"},
14709    {"bits": [10, 10], "name": "VCCZ"},
14710    {"bits": [11, 11], "name": "IN_TG"},
14711    {"bits": [12, 12], "name": "IN_BARRIER"},
14712    {"bits": [13, 13], "name": "HALT"},
14713    {"bits": [14, 14], "name": "TRAP"},
14714    {"bits": [15, 15], "name": "TTRACE_SIMD_EN"},
14715    {"bits": [16, 16], "name": "VALID"},
14716    {"bits": [17, 17], "name": "ECC_ERR"},
14717    {"bits": [18, 18], "name": "SKIP_EXPORT"},
14718    {"bits": [19, 19], "name": "PERF_EN"},
14719    {"bits": [23, 23], "name": "FATAL_HALT"},
14720    {"bits": [27, 27], "name": "MUST_EXPORT"}
14721   ]
14722  },
14723  "SQ_WAVE_TRAPSTS": {
14724   "fields": [
14725    {"bits": [0, 8], "enum_ref": "EXCP_EN", "name": "EXCP"},
14726    {"bits": [10, 10], "name": "SAVECTX"},
14727    {"bits": [11, 11], "name": "ILLEGAL_INST"},
14728    {"bits": [12, 14], "name": "EXCP_HI"},
14729    {"bits": [15, 15], "name": "BUFFER_OOB"},
14730    {"bits": [16, 19], "name": "EXCP_CYCLE"},
14731    {"bits": [20, 23], "name": "EXCP_GROUP_MASK"},
14732    {"bits": [24, 24], "name": "EXCP_WAVE64HI"},
14733    {"bits": [28, 28], "name": "UTC_ERROR"},
14734    {"bits": [29, 31], "name": "DP_RATE"}
14735   ]
14736  },
14737  "SQ_WAVE_VGPR_OFFSET": {
14738   "fields": [
14739    {"bits": [0, 5], "name": "SRC0"},
14740    {"bits": [6, 11], "name": "SRC1"},
14741    {"bits": [12, 17], "name": "SRC2"},
14742    {"bits": [18, 23], "name": "DST"}
14743   ]
14744  },
14745  "SX_BLEND_OPT_CONTROL": {
14746   "fields": [
14747    {"bits": [0, 0], "name": "MRT0_COLOR_OPT_DISABLE"},
14748    {"bits": [1, 1], "name": "MRT0_ALPHA_OPT_DISABLE"},
14749    {"bits": [4, 4], "name": "MRT1_COLOR_OPT_DISABLE"},
14750    {"bits": [5, 5], "name": "MRT1_ALPHA_OPT_DISABLE"},
14751    {"bits": [8, 8], "name": "MRT2_COLOR_OPT_DISABLE"},
14752    {"bits": [9, 9], "name": "MRT2_ALPHA_OPT_DISABLE"},
14753    {"bits": [12, 12], "name": "MRT3_COLOR_OPT_DISABLE"},
14754    {"bits": [13, 13], "name": "MRT3_ALPHA_OPT_DISABLE"},
14755    {"bits": [16, 16], "name": "MRT4_COLOR_OPT_DISABLE"},
14756    {"bits": [17, 17], "name": "MRT4_ALPHA_OPT_DISABLE"},
14757    {"bits": [20, 20], "name": "MRT5_COLOR_OPT_DISABLE"},
14758    {"bits": [21, 21], "name": "MRT5_ALPHA_OPT_DISABLE"},
14759    {"bits": [24, 24], "name": "MRT6_COLOR_OPT_DISABLE"},
14760    {"bits": [25, 25], "name": "MRT6_ALPHA_OPT_DISABLE"},
14761    {"bits": [28, 28], "name": "MRT7_COLOR_OPT_DISABLE"},
14762    {"bits": [29, 29], "name": "MRT7_ALPHA_OPT_DISABLE"},
14763    {"bits": [31, 31], "name": "PIXEN_ZERO_OPT_DISABLE"}
14764   ]
14765  },
14766  "SX_BLEND_OPT_EPSILON": {
14767   "fields": [
14768    {"bits": [0, 3], "enum_ref": "SX_BLEND_OPT_EPSILON__MRT0_EPSILON", "name": "MRT0_EPSILON"},
14769    {"bits": [4, 7], "name": "MRT1_EPSILON"},
14770    {"bits": [8, 11], "name": "MRT2_EPSILON"},
14771    {"bits": [12, 15], "name": "MRT3_EPSILON"},
14772    {"bits": [16, 19], "name": "MRT4_EPSILON"},
14773    {"bits": [20, 23], "name": "MRT5_EPSILON"},
14774    {"bits": [24, 27], "name": "MRT6_EPSILON"},
14775    {"bits": [28, 31], "name": "MRT7_EPSILON"}
14776   ]
14777  },
14778  "SX_MRT0_BLEND_OPT": {
14779   "fields": [
14780    {"bits": [0, 2], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_SRC_OPT"},
14781    {"bits": [4, 6], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_DST_OPT"},
14782    {"bits": [8, 10], "enum_ref": "SX_OPT_COMB_FCN", "name": "COLOR_COMB_FCN"},
14783    {"bits": [16, 18], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_SRC_OPT"},
14784    {"bits": [20, 22], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_DST_OPT"},
14785    {"bits": [24, 26], "enum_ref": "SX_OPT_COMB_FCN", "name": "ALPHA_COMB_FCN"}
14786   ]
14787  },
14788  "SX_PERFCOUNTER2_SELECT": {
14789   "fields": [
14790    {"bits": [0, 9], "name": "PERF_SEL"},
14791    {"bits": [20, 23], "name": "CNTR_MODE"},
14792    {"bits": [28, 31], "name": "PERF_MODE"}
14793   ]
14794  },
14795  "SX_PS_DOWNCONVERT": {
14796   "fields": [
14797    {"bits": [0, 3], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT0"},
14798    {"bits": [4, 7], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT1"},
14799    {"bits": [8, 11], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT2"},
14800    {"bits": [12, 15], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT3"},
14801    {"bits": [16, 19], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT4"},
14802    {"bits": [20, 23], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT5"},
14803    {"bits": [24, 27], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT6"},
14804    {"bits": [28, 31], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT7"}
14805   ]
14806  },
14807  "SX_PS_DOWNCONVERT_CONTROL": {
14808   "fields": [
14809    {"bits": [0, 0], "name": "MRT0_FMT_MAPPING_DISABLE"},
14810    {"bits": [1, 1], "name": "MRT1_FMT_MAPPING_DISABLE"},
14811    {"bits": [2, 2], "name": "MRT2_FMT_MAPPING_DISABLE"},
14812    {"bits": [3, 3], "name": "MRT3_FMT_MAPPING_DISABLE"},
14813    {"bits": [4, 4], "name": "MRT4_FMT_MAPPING_DISABLE"},
14814    {"bits": [5, 5], "name": "MRT5_FMT_MAPPING_DISABLE"},
14815    {"bits": [6, 6], "name": "MRT6_FMT_MAPPING_DISABLE"},
14816    {"bits": [7, 7], "name": "MRT7_FMT_MAPPING_DISABLE"}
14817   ]
14818  },
14819  "TA_BC_BASE_ADDR_HI": {
14820   "fields": [
14821    {"bits": [0, 7], "name": "ADDRESS"}
14822   ]
14823  },
14824  "UTCL1_PERFCOUNTER0_SELECT": {
14825   "fields": [
14826    {"bits": [0, 9], "name": "PERF_SEL"},
14827    {"bits": [28, 31], "name": "COUNTER_MODE"}
14828   ]
14829  },
14830  "VGT_DMA_BASE_HI": {
14831   "fields": [
14832    {"bits": [0, 15], "name": "BASE_ADDR"}
14833   ]
14834  },
14835  "VGT_DMA_INDEX_TYPE": {
14836   "fields": [
14837    {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"},
14838    {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"},
14839    {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"},
14840    {"bits": [6, 7], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"},
14841    {"bits": [8, 8], "name": "ATC"},
14842    {"bits": [9, 9], "name": "NOT_EOP"},
14843    {"bits": [10, 10], "name": "REQ_PATH"},
14844    {"bits": [11, 13], "name": "MTYPE"},
14845    {"bits": [14, 14], "name": "DISABLE_INSTANCE_PACKING"}
14846   ]
14847  },
14848  "VGT_DRAW_INITIATOR": {
14849   "fields": [
14850    {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"},
14851    {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"},
14852    {"bits": [4, 4], "name": "SPRITE_EN_R6XX"},
14853    {"bits": [5, 5], "name": "NOT_EOP"},
14854    {"bits": [6, 6], "name": "USE_OPAQUE"},
14855    {"bits": [29, 31], "name": "REG_RT_INDEX"}
14856   ]
14857  },
14858  "VGT_DRAW_PAYLOAD_CNTL": {
14859   "fields": [
14860    {"bits": [1, 1], "name": "EN_REG_RT_INDEX"},
14861    {"bits": [3, 3], "name": "EN_PRIM_PAYLOAD"},
14862    {"bits": [4, 4], "name": "EN_DRAW_VP"},
14863    {"bits": [6, 6], "name": "EN_VRS_RATE"}
14864   ]
14865  },
14866  "VGT_ESGS_RING_ITEMSIZE": {
14867   "fields": [
14868    {"bits": [0, 14], "name": "ITEMSIZE"}
14869   ]
14870  },
14871  "VGT_ES_PER_GS": {
14872   "fields": [
14873    {"bits": [0, 10], "name": "ES_PER_GS"}
14874   ]
14875  },
14876  "VGT_EVENT_ADDRESS_REG": {
14877   "fields": [
14878    {"bits": [0, 27], "name": "ADDRESS_LOW"}
14879   ]
14880  },
14881  "VGT_EVENT_INITIATOR": {
14882   "fields": [
14883    {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"},
14884    {"bits": [10, 26], "name": "ADDRESS_HI"},
14885    {"bits": [27, 27], "name": "EXTENDED_EVENT"}
14886   ]
14887  },
14888  "VGT_GROUP_DECR": {
14889   "fields": [
14890    {"bits": [0, 3], "name": "DECR"}
14891   ]
14892  },
14893  "VGT_GROUP_FIRST_DECR": {
14894   "fields": [
14895    {"bits": [0, 3], "name": "FIRST_DECR"}
14896   ]
14897  },
14898  "VGT_GROUP_PRIM_TYPE": {
14899   "fields": [
14900    {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"},
14901    {"bits": [14, 14], "name": "RETAIN_ORDER"},
14902    {"bits": [15, 15], "name": "RETAIN_QUADS"},
14903    {"bits": [16, 18], "name": "PRIM_ORDER"}
14904   ]
14905  },
14906  "VGT_GROUP_VECT_0_CNTL": {
14907   "fields": [
14908    {"bits": [0, 0], "name": "COMP_X_EN"},
14909    {"bits": [1, 1], "name": "COMP_Y_EN"},
14910    {"bits": [2, 2], "name": "COMP_Z_EN"},
14911    {"bits": [3, 3], "name": "COMP_W_EN"},
14912    {"bits": [8, 15], "name": "STRIDE"},
14913    {"bits": [16, 23], "name": "SHIFT"}
14914   ]
14915  },
14916  "VGT_GROUP_VECT_0_FMT_CNTL": {
14917   "fields": [
14918    {"bits": [0, 3], "name": "X_CONV"},
14919    {"bits": [4, 7], "name": "X_OFFSET"},
14920    {"bits": [8, 11], "name": "Y_CONV"},
14921    {"bits": [12, 15], "name": "Y_OFFSET"},
14922    {"bits": [16, 19], "name": "Z_CONV"},
14923    {"bits": [20, 23], "name": "Z_OFFSET"},
14924    {"bits": [24, 27], "name": "W_CONV"},
14925    {"bits": [28, 31], "name": "W_OFFSET"}
14926   ]
14927  },
14928  "VGT_GSVS_RING_OFFSET_1": {
14929   "fields": [
14930    {"bits": [0, 14], "name": "OFFSET"}
14931   ]
14932  },
14933  "VGT_GS_INSTANCE_CNT": {
14934   "fields": [
14935    {"bits": [0, 0], "name": "ENABLE"},
14936    {"bits": [2, 8], "name": "CNT"},
14937    {"bits": [31, 31], "name": "EN_MAX_VERT_OUT_PER_GS_INSTANCE"}
14938   ]
14939  },
14940  "VGT_GS_MAX_VERT_OUT": {
14941   "fields": [
14942    {"bits": [0, 10], "name": "MAX_VERT_OUT"}
14943   ]
14944  },
14945  "VGT_GS_MODE": {
14946   "fields": [
14947    {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"},
14948    {"bits": [3, 3], "name": "RESERVED_0"},
14949    {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"},
14950    {"bits": [6, 10], "name": "RESERVED_1"},
14951    {"bits": [11, 11], "name": "GS_C_PACK_EN"},
14952    {"bits": [12, 12], "name": "RESERVED_2"},
14953    {"bits": [13, 13], "name": "ES_PASSTHRU"},
14954    {"bits": [14, 14], "name": "COMPUTE_MODE"},
14955    {"bits": [15, 15], "name": "FAST_COMPUTE_MODE"},
14956    {"bits": [16, 16], "name": "ELEMENT_INFO_EN"},
14957    {"bits": [17, 17], "name": "PARTIAL_THD_AT_EOI"},
14958    {"bits": [18, 18], "name": "SUPPRESS_CUTS"},
14959    {"bits": [19, 19], "name": "ES_WRITE_OPTIMIZE"},
14960    {"bits": [20, 20], "name": "GS_WRITE_OPTIMIZE"},
14961    {"bits": [21, 22], "name": "ONCHIP"}
14962   ]
14963  },
14964  "VGT_GS_ONCHIP_CNTL": {
14965   "fields": [
14966    {"bits": [0, 10], "name": "ES_VERTS_PER_SUBGRP"},
14967    {"bits": [11, 21], "name": "GS_PRIMS_PER_SUBGRP"},
14968    {"bits": [22, 31], "name": "GS_INST_PRIMS_IN_SUBGRP"}
14969   ]
14970  },
14971  "VGT_GS_OUT_PRIM_TYPE": {
14972   "fields": [
14973    {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"},
14974    {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"},
14975    {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"},
14976    {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"},
14977    {"bits": [31, 31], "name": "UNIQUE_TYPE_PER_STREAM"}
14978   ]
14979  },
14980  "VGT_GS_PER_ES": {
14981   "fields": [
14982    {"bits": [0, 10], "name": "GS_PER_ES"}
14983   ]
14984  },
14985  "VGT_GS_PER_VS": {
14986   "fields": [
14987    {"bits": [0, 3], "name": "GS_PER_VS"}
14988   ]
14989  },
14990  "VGT_HOS_CNTL": {
14991   "fields": [
14992    {"bits": [0, 1], "name": "TESS_MODE"}
14993   ]
14994  },
14995  "VGT_HOS_REUSE_DEPTH": {
14996   "fields": [
14997    {"bits": [0, 7], "name": "REUSE_DEPTH"}
14998   ]
14999  },
15000  "VGT_HS_OFFCHIP_PARAM": {
15001   "fields": [
15002    {"bits": [0, 9], "name": "OFFCHIP_BUFFERING"},
15003    {"bits": [10, 11], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP_GRANULARITY"}
15004   ]
15005  },
15006  "VGT_INDEX_TYPE": {
15007   "fields": [
15008    {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"},
15009    {"bits": [14, 14], "name": "DISABLE_INSTANCE_PACKING"}
15010   ]
15011  },
15012  "VGT_LS_HS_CONFIG": {
15013   "fields": [
15014    {"bits": [0, 7], "name": "NUM_PATCHES"},
15015    {"bits": [8, 13], "name": "HS_NUM_INPUT_CP"},
15016    {"bits": [14, 19], "name": "HS_NUM_OUTPUT_CP"}
15017   ]
15018  },
15019  "VGT_MULTI_PRIM_IB_RESET_EN": {
15020   "fields": [
15021    {"bits": [0, 0], "name": "RESET_EN"},
15022    {"bits": [1, 1], "name": "MATCH_ALL_BITS"}
15023   ]
15024  },
15025  "VGT_OUTPUT_PATH_CNTL": {
15026   "fields": [
15027    {"bits": [0, 2], "name": "PATH_SELECT"}
15028   ]
15029  },
15030  "VGT_OUT_DEALLOC_CNTL": {
15031   "fields": [
15032    {"bits": [0, 6], "name": "DEALLOC_DIST"}
15033   ]
15034  },
15035  "VGT_PRIMITIVEID_EN": {
15036   "fields": [
15037    {"bits": [0, 0], "name": "PRIMITIVEID_EN"},
15038    {"bits": [1, 1], "name": "DISABLE_RESET_ON_EOI"},
15039    {"bits": [2, 2], "name": "NGG_DISABLE_PROVOK_REUSE"}
15040   ]
15041  },
15042  "VGT_PRIMITIVE_TYPE": {
15043   "fields": [
15044    {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}
15045   ]
15046  },
15047  "VGT_REUSE_OFF": {
15048   "fields": [
15049    {"bits": [0, 0], "name": "REUSE_OFF"}
15050   ]
15051  },
15052  "VGT_SHADER_STAGES_EN": {
15053   "fields": [
15054    {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"},
15055    {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},
15056    {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"},
15057    {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},
15058    {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"},
15059    {"bits": [8, 8], "name": "DYNAMIC_HS"},
15060    {"bits": [9, 9], "name": "DISPATCH_DRAW_EN"},
15061    {"bits": [10, 10], "name": "DIS_DEALLOC_ACCUM_0"},
15062    {"bits": [11, 11], "name": "DIS_DEALLOC_ACCUM_1"},
15063    {"bits": [12, 12], "name": "VS_WAVE_ID_EN"},
15064    {"bits": [13, 13], "name": "PRIMGEN_EN"},
15065    {"bits": [14, 14], "name": "ORDERED_ID_MODE"},
15066    {"bits": [15, 18], "name": "MAX_PRIMGRP_IN_WAVE"},
15067    {"bits": [19, 20], "name": "GS_FAST_LAUNCH"},
15068    {"bits": [21, 21], "name": "HS_W32_EN"},
15069    {"bits": [22, 22], "name": "GS_W32_EN"},
15070    {"bits": [23, 23], "name": "VS_W32_EN"},
15071    {"bits": [24, 24], "name": "NGG_WAVE_ID_EN"},
15072    {"bits": [25, 25], "name": "PRIMGEN_PASSTHRU_EN"},
15073    {"bits": [26, 26], "name": "PRIMGEN_PASSTHRU_NO_MSG"}
15074   ]
15075  },
15076  "VGT_STRMOUT_BUFFER_CONFIG": {
15077   "fields": [
15078    {"bits": [0, 3], "name": "STREAM_0_BUFFER_EN"},
15079    {"bits": [4, 7], "name": "STREAM_1_BUFFER_EN"},
15080    {"bits": [8, 11], "name": "STREAM_2_BUFFER_EN"},
15081    {"bits": [12, 15], "name": "STREAM_3_BUFFER_EN"}
15082   ]
15083  },
15084  "VGT_STRMOUT_CONFIG": {
15085   "fields": [
15086    {"bits": [0, 0], "name": "STREAMOUT_0_EN"},
15087    {"bits": [1, 1], "name": "STREAMOUT_1_EN"},
15088    {"bits": [2, 2], "name": "STREAMOUT_2_EN"},
15089    {"bits": [3, 3], "name": "STREAMOUT_3_EN"},
15090    {"bits": [4, 6], "name": "RAST_STREAM"},
15091    {"bits": [7, 7], "name": "EN_PRIMS_NEEDED_CNT"},
15092    {"bits": [8, 11], "name": "RAST_STREAM_MASK"},
15093    {"bits": [31, 31], "name": "USE_RAST_STREAM_MASK"}
15094   ]
15095  },
15096  "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE": {
15097   "fields": [
15098    {"bits": [0, 8], "name": "VERTEX_STRIDE"}
15099   ]
15100  },
15101  "VGT_STRMOUT_VTX_STRIDE_0": {
15102   "fields": [
15103    {"bits": [0, 9], "name": "STRIDE"}
15104   ]
15105  },
15106  "VGT_TESS_DISTRIBUTION": {
15107   "fields": [
15108    {"bits": [0, 7], "name": "ACCUM_ISOLINE"},
15109    {"bits": [8, 15], "name": "ACCUM_TRI"},
15110    {"bits": [16, 23], "name": "ACCUM_QUAD"},
15111    {"bits": [24, 28], "name": "DONUT_SPLIT"},
15112    {"bits": [29, 31], "name": "TRAP_SPLIT"}
15113   ]
15114  },
15115  "VGT_TF_PARAM": {
15116   "fields": [
15117    {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"},
15118    {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"},
15119    {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"},
15120    {"bits": [8, 8], "name": "RESERVED_REDUC_AXIS"},
15121    {"bits": [9, 9], "name": "DEPRECATED"},
15122    {"bits": [10, 13], "name": "NUM_DS_WAVES_PER_SIMD"},
15123    {"bits": [14, 14], "name": "DISABLE_DONUTS"},
15124    {"bits": [15, 16], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"},
15125    {"bits": [17, 18], "enum_ref": "VGT_DIST_MODE", "name": "DISTRIBUTION_MODE"},
15126    {"bits": [19, 19], "enum_ref": "VGT_DETECT_ONE", "name": "DETECT_ONE"},
15127    {"bits": [20, 20], "enum_ref": "VGT_DETECT_ZERO", "name": "DETECT_ZERO"},
15128    {"bits": [23, 25], "name": "MTYPE"}
15129   ]
15130  },
15131  "VGT_TF_RING_SIZE": {
15132   "fields": [
15133    {"bits": [0, 15], "name": "SIZE"}
15134   ]
15135  },
15136  "VGT_VERTEX_REUSE_BLOCK_CNTL": {
15137   "fields": [
15138    {"bits": [0, 7], "name": "VTX_REUSE_DEPTH"}
15139   ]
15140  },
15141  "VGT_VTX_CNT_EN": {
15142   "fields": [
15143    {"bits": [0, 0], "name": "VTX_CNT_EN"}
15144   ]
15145  }
15146 }
15147}
15148