1{
2 "enums": {
3  "ArrayMode": {
4   "entries": [
5    {"name": "ARRAY_LINEAR_GENERAL", "value": 0},
6    {"name": "ARRAY_LINEAR_ALIGNED", "value": 1},
7    {"name": "ARRAY_1D_TILED_THIN1", "value": 2},
8    {"name": "ARRAY_1D_TILED_THICK", "value": 3},
9    {"name": "ARRAY_2D_TILED_THIN1", "value": 4},
10    {"name": "ARRAY_PRT_TILED_THIN1", "value": 5},
11    {"name": "ARRAY_PRT_2D_TILED_THIN1", "value": 6},
12    {"name": "ARRAY_2D_TILED_THICK", "value": 7},
13    {"name": "ARRAY_2D_TILED_XTHICK", "value": 8},
14    {"name": "ARRAY_PRT_TILED_THICK", "value": 9},
15    {"name": "ARRAY_PRT_2D_TILED_THICK", "value": 10},
16    {"name": "ARRAY_PRT_3D_TILED_THIN1", "value": 11},
17    {"name": "ARRAY_3D_TILED_THIN1", "value": 12},
18    {"name": "ARRAY_3D_TILED_THICK", "value": 13},
19    {"name": "ARRAY_3D_TILED_XTHICK", "value": 14},
20    {"name": "ARRAY_PRT_3D_TILED_THICK", "value": 15}
21   ]
22  },
23  "BankHeight": {
24   "entries": [
25    {"name": "ADDR_SURF_BANK_HEIGHT_1", "value": 0},
26    {"name": "ADDR_SURF_BANK_HEIGHT_2", "value": 1},
27    {"name": "ADDR_SURF_BANK_HEIGHT_4", "value": 2},
28    {"name": "ADDR_SURF_BANK_HEIGHT_8", "value": 3}
29   ]
30  },
31  "BankWidth": {
32   "entries": [
33    {"name": "ADDR_SURF_BANK_WIDTH_1", "value": 0},
34    {"name": "ADDR_SURF_BANK_WIDTH_2", "value": 1},
35    {"name": "ADDR_SURF_BANK_WIDTH_4", "value": 2},
36    {"name": "ADDR_SURF_BANK_WIDTH_8", "value": 3}
37   ]
38  },
39  "BinMapMode": {
40   "entries": [
41    {"name": "BIN_MAP_MODE_NONE", "value": 0},
42    {"name": "BIN_MAP_MODE_RTA_INDEX", "value": 1},
43    {"name": "BIN_MAP_MODE_POPS", "value": 2}
44   ]
45  },
46  "BinSizeExtend": {
47   "entries": [
48    {"name": "BIN_SIZE_32_PIXELS", "value": 0},
49    {"name": "BIN_SIZE_64_PIXELS", "value": 1},
50    {"name": "BIN_SIZE_128_PIXELS", "value": 2},
51    {"name": "BIN_SIZE_256_PIXELS", "value": 3},
52    {"name": "BIN_SIZE_512_PIXELS", "value": 4}
53   ]
54  },
55  "BinningMode": {
56   "entries": [
57    {"name": "BINNING_ALLOWED", "value": 0},
58    {"name": "FORCE_BINNING_ON", "value": 1},
59    {"name": "DISABLE_BINNING_USE_NEW_SC", "value": 2},
60    {"name": "DISABLE_BINNING_USE_LEGACY_SC", "value": 3}
61   ]
62  },
63  "BlendOp": {
64   "entries": [
65    {"name": "BLEND_ZERO", "value": 0},
66    {"name": "BLEND_ONE", "value": 1},
67    {"name": "BLEND_SRC_COLOR", "value": 2},
68    {"name": "BLEND_ONE_MINUS_SRC_COLOR", "value": 3},
69    {"name": "BLEND_SRC_ALPHA", "value": 4},
70    {"name": "BLEND_ONE_MINUS_SRC_ALPHA", "value": 5},
71    {"name": "BLEND_DST_ALPHA", "value": 6},
72    {"name": "BLEND_ONE_MINUS_DST_ALPHA", "value": 7},
73    {"name": "BLEND_DST_COLOR", "value": 8},
74    {"name": "BLEND_ONE_MINUS_DST_COLOR", "value": 9},
75    {"name": "BLEND_SRC_ALPHA_SATURATE", "value": 10},
76    {"name": "BLEND_BOTH_SRC_ALPHA", "value": 11},
77    {"name": "BLEND_BOTH_INV_SRC_ALPHA", "value": 12},
78    {"name": "BLEND_CONSTANT_COLOR", "value": 13},
79    {"name": "BLEND_ONE_MINUS_CONSTANT_COLOR", "value": 14},
80    {"name": "BLEND_SRC1_COLOR", "value": 15},
81    {"name": "BLEND_INV_SRC1_COLOR", "value": 16},
82    {"name": "BLEND_SRC1_ALPHA", "value": 17},
83    {"name": "BLEND_INV_SRC1_ALPHA", "value": 18},
84    {"name": "BLEND_CONSTANT_ALPHA", "value": 19},
85    {"name": "BLEND_ONE_MINUS_CONSTANT_ALPHA", "value": 20}
86   ]
87  },
88  "BlendOpt": {
89   "entries": [
90    {"name": "FORCE_OPT_AUTO", "value": 0},
91    {"name": "FORCE_OPT_DISABLE", "value": 1},
92    {"name": "FORCE_OPT_ENABLE_IF_SRC_A_0", "value": 2},
93    {"name": "FORCE_OPT_ENABLE_IF_SRC_RGB_0", "value": 3},
94    {"name": "FORCE_OPT_ENABLE_IF_SRC_ARGB_0", "value": 4},
95    {"name": "FORCE_OPT_ENABLE_IF_SRC_A_1", "value": 5},
96    {"name": "FORCE_OPT_ENABLE_IF_SRC_RGB_1", "value": 6},
97    {"name": "FORCE_OPT_ENABLE_IF_SRC_ARGB_1", "value": 7}
98   ]
99  },
100  "CBMode": {
101   "entries": [
102    {"name": "CB_DISABLE", "value": 0},
103    {"name": "CB_NORMAL", "value": 1},
104    {"name": "CB_ELIMINATE_FAST_CLEAR", "value": 2},
105    {"name": "CB_RESOLVE", "value": 3},
106    {"name": "CB_DECOMPRESS", "value": 4},
107    {"name": "CB_FMASK_DECOMPRESS", "value": 5},
108    {"name": "CB_DCC_DECOMPRESS", "value": 6},
109    {"name": "CB_RESERVED", "value": 7}
110   ]
111  },
112  "CBPerfClearFilterSel": {
113   "entries": [
114    {"name": "CB_PERF_CLEAR_FILTER_SEL_NONCLEAR", "value": 0},
115    {"name": "CB_PERF_CLEAR_FILTER_SEL_CLEAR", "value": 1}
116   ]
117  },
118  "CBPerfOpFilterSel": {
119   "entries": [
120    {"name": "CB_PERF_OP_FILTER_SEL_WRITE_ONLY", "value": 0},
121    {"name": "CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION", "value": 1},
122    {"name": "CB_PERF_OP_FILTER_SEL_RESOLVE", "value": 2},
123    {"name": "CB_PERF_OP_FILTER_SEL_DECOMPRESS", "value": 3},
124    {"name": "CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS", "value": 4},
125    {"name": "CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR", "value": 5}
126   ]
127  },
128  "CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE": {
129   "entries": [
130    {"name": "MAX_BLOCK_SIZE_64B", "value": 0},
131    {"name": "MAX_BLOCK_SIZE_128B", "value": 1},
132    {"name": "MAX_BLOCK_SIZE_256B", "value": 2}
133   ]
134  },
135  "CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE": {
136   "entries": [
137    {"name": "MIN_BLOCK_SIZE_32B", "value": 0},
138    {"name": "MIN_BLOCK_SIZE_64B", "value": 1}
139   ]
140  },
141  "CLIP_RULE": {
142   "entries": [
143    {"name": "OUT", "value": 1},
144    {"name": "IN_0", "value": 2},
145    {"name": "IN_1", "value": 4},
146    {"name": "IN_10", "value": 8},
147    {"name": "IN_2", "value": 16},
148    {"name": "IN_20", "value": 32},
149    {"name": "IN_21", "value": 64},
150    {"name": "IN_210", "value": 128},
151    {"name": "IN_3", "value": 256},
152    {"name": "IN_30", "value": 512},
153    {"name": "IN_31", "value": 1024},
154    {"name": "IN_310", "value": 2048},
155    {"name": "IN_32", "value": 4096},
156    {"name": "IN_320", "value": 8192},
157    {"name": "IN_321", "value": 16384},
158    {"name": "IN_3210", "value": 32768}
159   ]
160  },
161  "CP_PERFMON_ENABLE_MODE": {
162   "entries": [
163    {"name": "CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT", "value": 0},
164    {"name": "CP_PERFMON_ENABLE_MODE_RESERVED_1", "value": 1},
165    {"name": "CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE", "value": 2},
166    {"name": "CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE", "value": 3}
167   ]
168  },
169  "CP_PERFMON_STATE": {
170   "entries": [
171    {"name": "CP_PERFMON_STATE_DISABLE_AND_RESET", "value": 0},
172    {"name": "CP_PERFMON_STATE_START_COUNTING", "value": 1},
173    {"name": "CP_PERFMON_STATE_STOP_COUNTING", "value": 2},
174    {"name": "CP_PERFMON_STATE_RESERVED_3", "value": 3},
175    {"name": "CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM", "value": 4},
176    {"name": "CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM", "value": 5}
177   ]
178  },
179  "CmaskAddr": {
180   "entries": [
181    {"name": "CMASK_ADDR_TILED", "value": 0},
182    {"name": "CMASK_ADDR_LINEAR", "value": 1},
183    {"name": "CMASK_ADDR_COMPATIBLE", "value": 2}
184   ]
185  },
186  "ColorFormat": {
187   "entries": [
188    {"name": "COLOR_INVALID", "value": 0},
189    {"name": "COLOR_8", "value": 1},
190    {"name": "COLOR_16", "value": 2},
191    {"name": "COLOR_8_8", "value": 3},
192    {"name": "COLOR_32", "value": 4},
193    {"name": "COLOR_16_16", "value": 5},
194    {"name": "COLOR_10_11_11", "value": 6},
195    {"name": "COLOR_11_11_10", "value": 7},
196    {"name": "COLOR_10_10_10_2", "value": 8},
197    {"name": "COLOR_2_10_10_10", "value": 9},
198    {"name": "COLOR_8_8_8_8", "value": 10},
199    {"name": "COLOR_32_32", "value": 11},
200    {"name": "COLOR_16_16_16_16", "value": 12},
201    {"name": "COLOR_RESERVED_13", "value": 13},
202    {"name": "COLOR_32_32_32_32", "value": 14},
203    {"name": "COLOR_RESERVED_15", "value": 15},
204    {"name": "COLOR_5_6_5", "value": 16},
205    {"name": "COLOR_1_5_5_5", "value": 17},
206    {"name": "COLOR_5_5_5_1", "value": 18},
207    {"name": "COLOR_4_4_4_4", "value": 19},
208    {"name": "COLOR_8_24", "value": 20},
209    {"name": "COLOR_24_8", "value": 21},
210    {"name": "COLOR_X24_8_32_FLOAT", "value": 22},
211    {"name": "COLOR_RESERVED_23", "value": 23},
212    {"name": "COLOR_RESERVED_24", "value": 24},
213    {"name": "COLOR_RESERVED_25", "value": 25},
214    {"name": "COLOR_RESERVED_26", "value": 26},
215    {"name": "COLOR_RESERVED_27", "value": 27},
216    {"name": "COLOR_RESERVED_28", "value": 28},
217    {"name": "COLOR_RESERVED_29", "value": 29},
218    {"name": "COLOR_RESERVED_30", "value": 30},
219    {"name": "COLOR_2_10_10_10_6E4", "value": 31}
220   ]
221  },
222  "CombFunc": {
223   "entries": [
224    {"name": "COMB_DST_PLUS_SRC", "value": 0},
225    {"name": "COMB_SRC_MINUS_DST", "value": 1},
226    {"name": "COMB_MIN_DST_SRC", "value": 2},
227    {"name": "COMB_MAX_DST_SRC", "value": 3},
228    {"name": "COMB_DST_MINUS_SRC", "value": 4}
229   ]
230  },
231  "CompareFrag": {
232   "entries": [
233    {"name": "FRAG_NEVER", "value": 0},
234    {"name": "FRAG_LESS", "value": 1},
235    {"name": "FRAG_EQUAL", "value": 2},
236    {"name": "FRAG_LEQUAL", "value": 3},
237    {"name": "FRAG_GREATER", "value": 4},
238    {"name": "FRAG_NOTEQUAL", "value": 5},
239    {"name": "FRAG_GEQUAL", "value": 6},
240    {"name": "FRAG_ALWAYS", "value": 7}
241   ]
242  },
243  "ConservativeZExport": {
244   "entries": [
245    {"name": "EXPORT_ANY_Z", "value": 0},
246    {"name": "EXPORT_LESS_THAN_Z", "value": 1},
247    {"name": "EXPORT_GREATER_THAN_Z", "value": 2},
248    {"name": "EXPORT_RESERVED", "value": 3}
249   ]
250  },
251  "CovToShaderSel": {
252   "entries": [
253    {"name": "INPUT_COVERAGE", "value": 0},
254    {"name": "INPUT_INNER_COVERAGE", "value": 1},
255    {"name": "INPUT_DEPTH_COVERAGE", "value": 2},
256    {"name": "RAW", "value": 3}
257   ]
258  },
259  "DB_DFSM_CONTROL__PUNCHOUT_MODE": {
260   "entries": [
261    {"name": "AUTO", "value": 0},
262    {"name": "FORCE_ON", "value": 1},
263    {"name": "FORCE_OFF", "value": 2},
264    {"name": "RESERVED", "value": 3}
265   ]
266  },
267  "DbPRTFaultBehavior": {
268   "entries": [
269    {"name": "FAULT_ZERO", "value": 0},
270    {"name": "FAULT_ONE", "value": 1},
271    {"name": "FAULT_FAIL", "value": 2},
272    {"name": "FAULT_PASS", "value": 3}
273   ]
274  },
275  "DbPSLControl": {
276   "entries": [
277    {"name": "PSLC_AUTO", "value": 0},
278    {"name": "PSLC_ON_HANG_ONLY", "value": 1},
279    {"name": "PSLC_ASAP", "value": 2},
280    {"name": "PSLC_COUNTDOWN", "value": 3}
281   ]
282  },
283  "EXCP_EN": {
284   "entries": [
285    {"name": "INVALID", "value": 1},
286    {"name": "INPUT_DENORMAL", "value": 2},
287    {"name": "DIVIDE_BY_ZERO", "value": 4},
288    {"name": "OVERFLOW", "value": 8},
289    {"name": "UNDERFLOW", "value": 16},
290    {"name": "INEXACT", "value": 32},
291    {"name": "INT_DIVIDE_BY_ZERO", "value": 64},
292    {"name": "ADDRESS_WATCH", "value": 128},
293    {"name": "MEMORY_VIOLATION", "value": 256}
294   ]
295  },
296  "FLOAT_MODE": {
297   "entries": [
298    {"name": "FP_32_ROUND_TOWARDS_ZERO", "value": 3},
299    {"name": "FP_16_64_ROUND_TOWARDS_ZERO", "value": 12},
300    {"name": "FP_32_DENORMS", "value": 48},
301    {"name": "FP_16_64_DENORMS", "value": 192}
302   ]
303  },
304  "ForceControl": {
305   "entries": [
306    {"name": "FORCE_OFF", "value": 0},
307    {"name": "FORCE_ENABLE", "value": 1},
308    {"name": "FORCE_DISABLE", "value": 2},
309    {"name": "FORCE_RESERVED", "value": 3}
310   ]
311  },
312  "MacroTileAspect": {
313   "entries": [
314    {"name": "ADDR_SURF_MACRO_ASPECT_1", "value": 0},
315    {"name": "ADDR_SURF_MACRO_ASPECT_2", "value": 1},
316    {"name": "ADDR_SURF_MACRO_ASPECT_4", "value": 2},
317    {"name": "ADDR_SURF_MACRO_ASPECT_8", "value": 3}
318   ]
319  },
320  "MicroTileMode": {
321   "entries": [
322    {"name": "ADDR_SURF_DISPLAY_MICRO_TILING", "value": 0},
323    {"name": "ADDR_SURF_THIN_MICRO_TILING", "value": 1},
324    {"name": "ADDR_SURF_DEPTH_MICRO_TILING", "value": 2},
325    {"name": "ADDR_SURF_ROTATED_MICRO_TILING", "value": 3},
326    {"name": "ADDR_SURF_THICK_MICRO_TILING", "value": 4}
327   ]
328  },
329  "NumBanks": {
330   "entries": [
331    {"name": "ADDR_SURF_2_BANK", "value": 0},
332    {"name": "ADDR_SURF_4_BANK", "value": 1},
333    {"name": "ADDR_SURF_8_BANK", "value": 2},
334    {"name": "ADDR_SURF_16_BANK", "value": 3}
335   ]
336  },
337  "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE": {
338   "entries": [
339    {"name": "X_DRAW_POINTS", "value": 0},
340    {"name": "X_DRAW_LINES", "value": 1},
341    {"name": "X_DRAW_TRIANGLES", "value": 2}
342   ]
343  },
344  "PA_SU_SC_MODE_CNTL__POLY_MODE": {
345   "entries": [
346    {"name": "X_DISABLE_POLY_MODE", "value": 0},
347    {"name": "X_DUAL_MODE", "value": 1}
348   ]
349  },
350  "PA_SU_VTX_CNTL__ROUND_MODE": {
351   "entries": [
352    {"name": "X_TRUNCATE", "value": 0},
353    {"name": "X_ROUND", "value": 1},
354    {"name": "X_ROUND_TO_EVEN", "value": 2},
355    {"name": "X_ROUND_TO_ODD", "value": 3}
356   ]
357  },
358  "PipeConfig": {
359   "entries": [
360    {"name": "ADDR_SURF_P2", "value": 0},
361    {"name": "ADDR_SURF_P2_RESERVED0", "value": 1},
362    {"name": "ADDR_SURF_P2_RESERVED1", "value": 2},
363    {"name": "ADDR_SURF_P2_RESERVED2", "value": 3},
364    {"name": "ADDR_SURF_P4_8x16", "value": 4},
365    {"name": "ADDR_SURF_P4_16x16", "value": 5},
366    {"name": "ADDR_SURF_P4_16x32", "value": 6},
367    {"name": "ADDR_SURF_P4_32x32", "value": 7},
368    {"name": "ADDR_SURF_P8_16x16_8x16", "value": 8},
369    {"name": "ADDR_SURF_P8_16x32_8x16", "value": 9},
370    {"name": "ADDR_SURF_P8_32x32_8x16", "value": 10},
371    {"name": "ADDR_SURF_P8_16x32_16x16", "value": 11},
372    {"name": "ADDR_SURF_P8_32x32_16x16", "value": 12},
373    {"name": "ADDR_SURF_P8_32x32_16x32", "value": 13},
374    {"name": "ADDR_SURF_P8_32x64_32x32", "value": 14},
375    {"name": "ADDR_SURF_P8_RESERVED0", "value": 15},
376    {"name": "ADDR_SURF_P16_32x32_8x16", "value": 16},
377    {"name": "ADDR_SURF_P16_32x32_16x16", "value": 17},
378    {"name": "ADDR_SURF_P16", "value": 18}
379   ]
380  },
381  "PkrMap": {
382   "entries": [
383    {"name": "RASTER_CONFIG_PKR_MAP_0", "value": 0},
384    {"name": "RASTER_CONFIG_PKR_MAP_1", "value": 1},
385    {"name": "RASTER_CONFIG_PKR_MAP_2", "value": 2},
386    {"name": "RASTER_CONFIG_PKR_MAP_3", "value": 3}
387   ]
388  },
389  "PkrXsel": {
390   "entries": [
391    {"name": "RASTER_CONFIG_PKR_XSEL_0", "value": 0},
392    {"name": "RASTER_CONFIG_PKR_XSEL_1", "value": 1},
393    {"name": "RASTER_CONFIG_PKR_XSEL_2", "value": 2},
394    {"name": "RASTER_CONFIG_PKR_XSEL_3", "value": 3}
395   ]
396  },
397  "PkrXsel2": {
398   "entries": [
399    {"name": "RASTER_CONFIG_PKR_XSEL2_0", "value": 0},
400    {"name": "RASTER_CONFIG_PKR_XSEL2_1", "value": 1},
401    {"name": "RASTER_CONFIG_PKR_XSEL2_2", "value": 2},
402    {"name": "RASTER_CONFIG_PKR_XSEL2_3", "value": 3}
403   ]
404  },
405  "PkrYsel": {
406   "entries": [
407    {"name": "RASTER_CONFIG_PKR_YSEL_0", "value": 0},
408    {"name": "RASTER_CONFIG_PKR_YSEL_1", "value": 1},
409    {"name": "RASTER_CONFIG_PKR_YSEL_2", "value": 2},
410    {"name": "RASTER_CONFIG_PKR_YSEL_3", "value": 3}
411   ]
412  },
413  "QUANT_MODE": {
414   "entries": [
415    {"name": "X_16_8_FIXED_POINT_1_16TH", "value": 0},
416    {"name": "X_16_8_FIXED_POINT_1_8TH", "value": 1},
417    {"name": "X_16_8_FIXED_POINT_1_4TH", "value": 2},
418    {"name": "X_16_8_FIXED_POINT_1_2", "value": 3},
419    {"name": "X_16_8_FIXED_POINT_1", "value": 4},
420    {"name": "X_16_8_FIXED_POINT_1_256TH", "value": 5},
421    {"name": "X_14_10_FIXED_POINT_1_1024TH", "value": 6},
422    {"name": "X_12_12_FIXED_POINT_1_4096TH", "value": 7}
423   ]
424  },
425  "ROP3": {
426   "entries": [
427    {"name": "ROP3_CLEAR", "value": 0},
428    {"name": "X_0X05", "value": 5},
429    {"name": "X_0X0A", "value": 10},
430    {"name": "X_0X0F", "value": 15},
431    {"name": "ROP3_NOR", "value": 17},
432    {"name": "ROP3_AND_INVERTED", "value": 34},
433    {"name": "ROP3_COPY_INVERTED", "value": 51},
434    {"name": "ROP3_AND_REVERSE", "value": 68},
435    {"name": "X_0X50", "value": 80},
436    {"name": "ROP3_INVERT", "value": 85},
437    {"name": "X_0X5A", "value": 90},
438    {"name": "X_0X5F", "value": 95},
439    {"name": "ROP3_XOR", "value": 102},
440    {"name": "ROP3_NAND", "value": 119},
441    {"name": "ROP3_AND", "value": 136},
442    {"name": "ROP3_EQUIVALENT", "value": 153},
443    {"name": "X_0XA0", "value": 160},
444    {"name": "X_0XA5", "value": 165},
445    {"name": "ROP3_NO_OP", "value": 170},
446    {"name": "X_0XAF", "value": 175},
447    {"name": "ROP3_OR_INVERTED", "value": 187},
448    {"name": "ROP3_COPY", "value": 204},
449    {"name": "ROP3_OR_REVERSE", "value": 221},
450    {"name": "ROP3_OR", "value": 238},
451    {"name": "X_0XF0", "value": 240},
452    {"name": "X_0XF5", "value": 245},
453    {"name": "X_0XFA", "value": 250},
454    {"name": "ROP3_SET", "value": 255}
455   ]
456  },
457  "RbMap": {
458   "entries": [
459    {"name": "RASTER_CONFIG_RB_MAP_0", "value": 0},
460    {"name": "RASTER_CONFIG_RB_MAP_1", "value": 1},
461    {"name": "RASTER_CONFIG_RB_MAP_2", "value": 2},
462    {"name": "RASTER_CONFIG_RB_MAP_3", "value": 3}
463   ]
464  },
465  "RbXsel": {
466   "entries": [
467    {"name": "RASTER_CONFIG_RB_XSEL_0", "value": 0},
468    {"name": "RASTER_CONFIG_RB_XSEL_1", "value": 1}
469   ]
470  },
471  "RbXsel2": {
472   "entries": [
473    {"name": "RASTER_CONFIG_RB_XSEL2_0", "value": 0},
474    {"name": "RASTER_CONFIG_RB_XSEL2_1", "value": 1},
475    {"name": "RASTER_CONFIG_RB_XSEL2_2", "value": 2},
476    {"name": "RASTER_CONFIG_RB_XSEL2_3", "value": 3}
477   ]
478  },
479  "RbYsel": {
480   "entries": [
481    {"name": "RASTER_CONFIG_RB_YSEL_0", "value": 0},
482    {"name": "RASTER_CONFIG_RB_YSEL_1", "value": 1}
483   ]
484  },
485  "ReadPolicy": {
486   "entries": [
487    {"name": "CACHE_LRU_RD", "value": 0},
488    {"name": "CACHE_NOA", "value": 1},
489    {"name": "UNCACHED_RD", "value": 2},
490    {"name": "RESERVED_RDPOLICY", "value": 3}
491   ]
492  },
493  "SPI_PNT_SPRITE_OVERRIDE": {
494   "entries": [
495    {"name": "SPI_PNT_SPRITE_SEL_0", "value": 0},
496    {"name": "SPI_PNT_SPRITE_SEL_1", "value": 1},
497    {"name": "SPI_PNT_SPRITE_SEL_S", "value": 2},
498    {"name": "SPI_PNT_SPRITE_SEL_T", "value": 3},
499    {"name": "SPI_PNT_SPRITE_SEL_NONE", "value": 4}
500   ]
501  },
502  "SPI_SHADER_EX_FORMAT": {
503   "entries": [
504    {"name": "SPI_SHADER_ZERO", "value": 0},
505    {"name": "SPI_SHADER_32_R", "value": 1},
506    {"name": "SPI_SHADER_32_GR", "value": 2},
507    {"name": "SPI_SHADER_32_AR", "value": 3},
508    {"name": "SPI_SHADER_FP16_ABGR", "value": 4},
509    {"name": "SPI_SHADER_UNORM16_ABGR", "value": 5},
510    {"name": "SPI_SHADER_SNORM16_ABGR", "value": 6},
511    {"name": "SPI_SHADER_UINT16_ABGR", "value": 7},
512    {"name": "SPI_SHADER_SINT16_ABGR", "value": 8},
513    {"name": "SPI_SHADER_32_ABGR", "value": 9}
514   ]
515  },
516  "SPI_SHADER_FORMAT": {
517   "entries": [
518    {"name": "SPI_SHADER_NONE", "value": 0},
519    {"name": "SPI_SHADER_1COMP", "value": 1},
520    {"name": "SPI_SHADER_2COMP", "value": 2},
521    {"name": "SPI_SHADER_4COMPRESS", "value": 3},
522    {"name": "SPI_SHADER_4COMP", "value": 4}
523   ]
524  },
525  "SPM_PERFMON_STATE": {
526   "entries": [
527    {"name": "STRM_PERFMON_STATE_DISABLE_AND_RESET", "value": 0},
528    {"name": "STRM_PERFMON_STATE_START_COUNTING", "value": 1},
529    {"name": "STRM_PERFMON_STATE_STOP_COUNTING", "value": 2},
530    {"name": "STRM_PERFMON_STATE_RESERVED_3", "value": 3},
531    {"name": "STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM", "value": 4},
532    {"name": "STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM", "value": 5}
533   ]
534  },
535  "SX_BLEND_OPT": {
536   "entries": [
537    {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_ALL", "value": 0},
538    {"name": "BLEND_OPT_PRESERVE_ALL_IGNORE_NONE", "value": 1},
539    {"name": "BLEND_OPT_PRESERVE_C1_IGNORE_C0", "value": 2},
540    {"name": "BLEND_OPT_PRESERVE_C0_IGNORE_C1", "value": 3},
541    {"name": "BLEND_OPT_PRESERVE_A1_IGNORE_A0", "value": 4},
542    {"name": "BLEND_OPT_PRESERVE_A0_IGNORE_A1", "value": 5},
543    {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_A0", "value": 6},
544    {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_NONE", "value": 7}
545   ]
546  },
547  "SX_BLEND_OPT_EPSILON__MRT0_EPSILON": {
548   "entries": [
549    {"name": "EXACT", "value": 0},
550    {"name": "11BIT_FORMAT", "value": 1},
551    {"name": "10BIT_FORMAT", "value": 3},
552    {"name": "8BIT_FORMAT", "value": 6},
553    {"name": "6BIT_FORMAT", "value": 11},
554    {"name": "5BIT_FORMAT", "value": 13},
555    {"name": "4BIT_FORMAT", "value": 15}
556   ]
557  },
558  "SX_DOWNCONVERT_FORMAT": {
559   "entries": [
560    {"name": "SX_RT_EXPORT_NO_CONVERSION", "value": 0},
561    {"name": "SX_RT_EXPORT_32_R", "value": 1},
562    {"name": "SX_RT_EXPORT_32_A", "value": 2},
563    {"name": "SX_RT_EXPORT_10_11_11", "value": 3},
564    {"name": "SX_RT_EXPORT_2_10_10_10", "value": 4},
565    {"name": "SX_RT_EXPORT_8_8_8_8", "value": 5},
566    {"name": "SX_RT_EXPORT_5_6_5", "value": 6},
567    {"name": "SX_RT_EXPORT_1_5_5_5", "value": 7},
568    {"name": "SX_RT_EXPORT_4_4_4_4", "value": 8},
569    {"name": "SX_RT_EXPORT_16_16_GR", "value": 9},
570    {"name": "SX_RT_EXPORT_16_16_AR", "value": 10}
571   ]
572  },
573  "SX_OPT_COMB_FCN": {
574   "entries": [
575    {"name": "OPT_COMB_NONE", "value": 0},
576    {"name": "OPT_COMB_ADD", "value": 1},
577    {"name": "OPT_COMB_SUBTRACT", "value": 2},
578    {"name": "OPT_COMB_MIN", "value": 3},
579    {"name": "OPT_COMB_MAX", "value": 4},
580    {"name": "OPT_COMB_REVSUBTRACT", "value": 5},
581    {"name": "OPT_COMB_BLEND_DISABLED", "value": 6},
582    {"name": "OPT_COMB_SAFE_ADD", "value": 7}
583   ]
584  },
585  "ScMap": {
586   "entries": [
587    {"name": "RASTER_CONFIG_SC_MAP_0", "value": 0},
588    {"name": "RASTER_CONFIG_SC_MAP_1", "value": 1},
589    {"name": "RASTER_CONFIG_SC_MAP_2", "value": 2},
590    {"name": "RASTER_CONFIG_SC_MAP_3", "value": 3}
591   ]
592  },
593  "ScUncertaintyRegionMode": {
594   "entries": [
595    {"name": "SC_HALF_LSB", "value": 0},
596    {"name": "SC_LSB_ONE_SIDED", "value": 1},
597    {"name": "SC_LSB_TWO_SIDED", "value": 2}
598   ]
599  },
600  "ScXsel": {
601   "entries": [
602    {"name": "RASTER_CONFIG_SC_XSEL_8_WIDE_TILE", "value": 0},
603    {"name": "RASTER_CONFIG_SC_XSEL_16_WIDE_TILE", "value": 1},
604    {"name": "RASTER_CONFIG_SC_XSEL_32_WIDE_TILE", "value": 2},
605    {"name": "RASTER_CONFIG_SC_XSEL_64_WIDE_TILE", "value": 3}
606   ]
607  },
608  "ScYsel": {
609   "entries": [
610    {"name": "RASTER_CONFIG_SC_YSEL_8_WIDE_TILE", "value": 0},
611    {"name": "RASTER_CONFIG_SC_YSEL_16_WIDE_TILE", "value": 1},
612    {"name": "RASTER_CONFIG_SC_YSEL_32_WIDE_TILE", "value": 2},
613    {"name": "RASTER_CONFIG_SC_YSEL_64_WIDE_TILE", "value": 3}
614   ]
615  },
616  "SeMap": {
617   "entries": [
618    {"name": "RASTER_CONFIG_SE_MAP_0", "value": 0},
619    {"name": "RASTER_CONFIG_SE_MAP_1", "value": 1},
620    {"name": "RASTER_CONFIG_SE_MAP_2", "value": 2},
621    {"name": "RASTER_CONFIG_SE_MAP_3", "value": 3}
622   ]
623  },
624  "SePairMap": {
625   "entries": [
626    {"name": "RASTER_CONFIG_SE_PAIR_MAP_0", "value": 0},
627    {"name": "RASTER_CONFIG_SE_PAIR_MAP_1", "value": 1},
628    {"name": "RASTER_CONFIG_SE_PAIR_MAP_2", "value": 2},
629    {"name": "RASTER_CONFIG_SE_PAIR_MAP_3", "value": 3}
630   ]
631  },
632  "SePairXsel": {
633   "entries": [
634    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE", "value": 0},
635    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE", "value": 1},
636    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE", "value": 2},
637    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE", "value": 3}
638   ]
639  },
640  "SePairYsel": {
641   "entries": [
642    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE", "value": 0},
643    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE", "value": 1},
644    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE", "value": 2},
645    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE", "value": 3}
646   ]
647  },
648  "SeXsel": {
649   "entries": [
650    {"name": "RASTER_CONFIG_SE_XSEL_8_WIDE_TILE", "value": 0},
651    {"name": "RASTER_CONFIG_SE_XSEL_16_WIDE_TILE", "value": 1},
652    {"name": "RASTER_CONFIG_SE_XSEL_32_WIDE_TILE", "value": 2},
653    {"name": "RASTER_CONFIG_SE_XSEL_64_WIDE_TILE", "value": 3}
654   ]
655  },
656  "SeYsel": {
657   "entries": [
658    {"name": "RASTER_CONFIG_SE_YSEL_8_WIDE_TILE", "value": 0},
659    {"name": "RASTER_CONFIG_SE_YSEL_16_WIDE_TILE", "value": 1},
660    {"name": "RASTER_CONFIG_SE_YSEL_32_WIDE_TILE", "value": 2},
661    {"name": "RASTER_CONFIG_SE_YSEL_64_WIDE_TILE", "value": 3}
662   ]
663  },
664  "StencilFormat": {
665   "entries": [
666    {"name": "STENCIL_INVALID", "value": 0},
667    {"name": "STENCIL_8", "value": 1}
668   ]
669  },
670  "StencilOp": {
671   "entries": [
672    {"name": "STENCIL_KEEP", "value": 0},
673    {"name": "STENCIL_ZERO", "value": 1},
674    {"name": "STENCIL_ONES", "value": 2},
675    {"name": "STENCIL_REPLACE_TEST", "value": 3},
676    {"name": "STENCIL_REPLACE_OP", "value": 4},
677    {"name": "STENCIL_ADD_CLAMP", "value": 5},
678    {"name": "STENCIL_SUB_CLAMP", "value": 6},
679    {"name": "STENCIL_INVERT", "value": 7},
680    {"name": "STENCIL_ADD_WRAP", "value": 8},
681    {"name": "STENCIL_SUB_WRAP", "value": 9},
682    {"name": "STENCIL_AND", "value": 10},
683    {"name": "STENCIL_OR", "value": 11},
684    {"name": "STENCIL_XOR", "value": 12},
685    {"name": "STENCIL_NAND", "value": 13},
686    {"name": "STENCIL_NOR", "value": 14},
687    {"name": "STENCIL_XNOR", "value": 15}
688   ]
689  },
690  "SurfaceEndian": {
691   "entries": [
692    {"name": "ENDIAN_NONE", "value": 0},
693    {"name": "ENDIAN_8IN16", "value": 1},
694    {"name": "ENDIAN_8IN32", "value": 2},
695    {"name": "ENDIAN_8IN64", "value": 3}
696   ]
697  },
698  "SurfaceNumber": {
699   "entries": [
700    {"name": "NUMBER_UNORM", "value": 0},
701    {"name": "NUMBER_SNORM", "value": 1},
702    {"name": "NUMBER_USCALED", "value": 2},
703    {"name": "NUMBER_SSCALED", "value": 3},
704    {"name": "NUMBER_UINT", "value": 4},
705    {"name": "NUMBER_SINT", "value": 5},
706    {"name": "NUMBER_SRGB", "value": 6},
707    {"name": "NUMBER_FLOAT", "value": 7}
708   ]
709  },
710  "SurfaceSwap": {
711   "entries": [
712    {"name": "SWAP_STD", "value": 0},
713    {"name": "SWAP_ALT", "value": 1},
714    {"name": "SWAP_STD_REV", "value": 2},
715    {"name": "SWAP_ALT_REV", "value": 3}
716   ]
717  },
718  "ThreadTraceRegInclude": {
719   "entries": [
720    {"name": "REG_INCLUDE_SQDEC", "value": 1},
721    {"name": "REG_INCLUDE_SHDEC", "value": 2},
722    {"name": "REG_INCLUDE_GFXUDEC", "value": 4},
723    {"name": "REG_INCLUDE_COMP", "value": 8},
724    {"name": "REG_INCLUDE_CONTEXT", "value": 16},
725    {"name": "REG_INCLUDE_CONFIG", "value": 32},
726    {"name": "REG_INCLUDE_OTHER", "value": 64},
727    {"name": "REG_INCLUDE_READS", "value": 128}
728   ]
729  },
730  "ThreadTraceTokenExclude": {
731   "entries": [
732    {"name": "TOKEN_EXCLUDE_VMEMEXEC", "value": 1},
733    {"name": "TOKEN_EXCLUDE_ALUEXEC", "value": 2},
734    {"name": "TOKEN_EXCLUDE_VALUINST", "value": 4},
735    {"name": "TOKEN_EXCLUDE_WAVERDY", "value": 8},
736    {"name": "TOKEN_EXCLUDE_IMMED1", "value": 16},
737    {"name": "TOKEN_EXCLUDE_IMMEDIATE", "value": 32},
738    {"name": "TOKEN_EXCLUDE_REG", "value": 64},
739    {"name": "TOKEN_EXCLUDE_EVENT", "value": 128},
740    {"name": "TOKEN_EXCLUDE_INST", "value": 256},
741    {"name": "TOKEN_EXCLUDE_UTILCTR", "value": 512},
742    {"name": "TOKEN_EXCLUDE_WAVEALLOC", "value": 1024},
743    {"name": "TOKEN_EXCLUDE_PERF", "value": 2048}
744   ]
745  },
746  "TileSplit": {
747   "entries": [
748    {"name": "ADDR_SURF_TILE_SPLIT_64B", "value": 0},
749    {"name": "ADDR_SURF_TILE_SPLIT_128B", "value": 1},
750    {"name": "ADDR_SURF_TILE_SPLIT_256B", "value": 2},
751    {"name": "ADDR_SURF_TILE_SPLIT_512B", "value": 3},
752    {"name": "ADDR_SURF_TILE_SPLIT_1KB", "value": 4},
753    {"name": "ADDR_SURF_TILE_SPLIT_2KB", "value": 5},
754    {"name": "ADDR_SURF_TILE_SPLIT_4KB", "value": 6}
755   ]
756  },
757  "VGT_DETECT_ONE": {
758   "entries": [
759    {"name": "PRE_CLAMP_TF1", "value": 0},
760    {"name": "POST_CLAMP_TF1", "value": 1},
761    {"name": "DISABLE_TF1", "value": 2}
762   ]
763  },
764  "VGT_DETECT_ZERO": {
765   "entries": [
766    {"name": "PRE_CLAMP_TF0", "value": 0},
767    {"name": "POST_CLAMP_TF0", "value": 1},
768    {"name": "DISABLE_TF0", "value": 2}
769   ]
770  },
771  "VGT_DIST_MODE": {
772   "entries": [
773    {"name": "NO_DIST", "value": 0},
774    {"name": "PATCHES", "value": 1},
775    {"name": "DONUTS", "value": 2},
776    {"name": "TRAPEZOIDS", "value": 3}
777   ]
778  },
779  "VGT_DI_MAJOR_MODE_SELECT": {
780   "entries": [
781    {"name": "DI_MAJOR_MODE_0", "value": 0},
782    {"name": "DI_MAJOR_MODE_1", "value": 1}
783   ]
784  },
785  "VGT_DI_PRIM_TYPE": {
786   "entries": [
787    {"name": "DI_PT_NONE", "value": 0},
788    {"name": "DI_PT_POINTLIST", "value": 1},
789    {"name": "DI_PT_LINELIST", "value": 2},
790    {"name": "DI_PT_LINESTRIP", "value": 3},
791    {"name": "DI_PT_TRILIST", "value": 4},
792    {"name": "DI_PT_TRIFAN", "value": 5},
793    {"name": "DI_PT_TRISTRIP", "value": 6},
794    {"name": "DI_PT_2D_RECTANGLE", "value": 7},
795    {"name": "DI_PT_UNUSED_1", "value": 8},
796    {"name": "DI_PT_PATCH", "value": 9},
797    {"name": "DI_PT_LINELIST_ADJ", "value": 10},
798    {"name": "DI_PT_LINESTRIP_ADJ", "value": 11},
799    {"name": "DI_PT_TRILIST_ADJ", "value": 12},
800    {"name": "DI_PT_TRISTRIP_ADJ", "value": 13},
801    {"name": "DI_PT_UNUSED_3", "value": 14},
802    {"name": "DI_PT_UNUSED_4", "value": 15},
803    {"name": "DI_PT_TRI_WITH_WFLAGS", "value": 16},
804    {"name": "DI_PT_RECTLIST", "value": 17},
805    {"name": "DI_PT_LINELOOP", "value": 18},
806    {"name": "DI_PT_QUADLIST", "value": 19},
807    {"name": "DI_PT_QUADSTRIP", "value": 20},
808    {"name": "DI_PT_POLYGON", "value": 21}
809   ]
810  },
811  "VGT_DI_SOURCE_SELECT": {
812   "entries": [
813    {"name": "DI_SRC_SEL_DMA", "value": 0},
814    {"name": "DI_SRC_SEL_IMMEDIATE", "value": 1},
815    {"name": "DI_SRC_SEL_AUTO_INDEX", "value": 2},
816    {"name": "DI_SRC_SEL_RESERVED", "value": 3}
817   ]
818  },
819  "VGT_DMA_BUF_TYPE": {
820   "entries": [
821    {"name": "VGT_DMA_BUF_MEM", "value": 0},
822    {"name": "VGT_DMA_BUF_RING", "value": 1},
823    {"name": "VGT_DMA_BUF_SETUP", "value": 2},
824    {"name": "VGT_DMA_PTR_UPDATE", "value": 3}
825   ]
826  },
827  "VGT_DMA_SWAP_MODE": {
828   "entries": [
829    {"name": "VGT_DMA_SWAP_NONE", "value": 0},
830    {"name": "VGT_DMA_SWAP_16_BIT", "value": 1},
831    {"name": "VGT_DMA_SWAP_32_BIT", "value": 2},
832    {"name": "VGT_DMA_SWAP_WORD", "value": 3}
833   ]
834  },
835  "VGT_EVENT_TYPE": {
836   "entries": [
837    {"name": "Reserved_0x00", "value": 0},
838    {"name": "SAMPLE_STREAMOUTSTATS1", "value": 1},
839    {"name": "SAMPLE_STREAMOUTSTATS2", "value": 2},
840    {"name": "SAMPLE_STREAMOUTSTATS3", "value": 3},
841    {"name": "CACHE_FLUSH_TS", "value": 4},
842    {"name": "CONTEXT_DONE", "value": 5},
843    {"name": "CACHE_FLUSH", "value": 6},
844    {"name": "CS_PARTIAL_FLUSH", "value": 7},
845    {"name": "VGT_STREAMOUT_SYNC", "value": 8},
846    {"name": "SET_FE_ID", "value": 9},
847    {"name": "VGT_STREAMOUT_RESET", "value": 10},
848    {"name": "END_OF_PIPE_INCR_DE", "value": 11},
849    {"name": "END_OF_PIPE_IB_END", "value": 12},
850    {"name": "RST_PIX_CNT", "value": 13},
851    {"name": "BREAK_BATCH", "value": 14},
852    {"name": "VS_PARTIAL_FLUSH", "value": 15},
853    {"name": "PS_PARTIAL_FLUSH", "value": 16},
854    {"name": "FLUSH_HS_OUTPUT", "value": 17},
855    {"name": "FLUSH_DFSM", "value": 18},
856    {"name": "RESET_TO_LOWEST_VGT", "value": 19},
857    {"name": "CACHE_FLUSH_AND_INV_TS_EVENT", "value": 20},
858    {"name": "ZPASS_DONE", "value": 21},
859    {"name": "CACHE_FLUSH_AND_INV_EVENT", "value": 22},
860    {"name": "PERFCOUNTER_START", "value": 23},
861    {"name": "PERFCOUNTER_STOP", "value": 24},
862    {"name": "PIPELINESTAT_START", "value": 25},
863    {"name": "PIPELINESTAT_STOP", "value": 26},
864    {"name": "PERFCOUNTER_SAMPLE", "value": 27},
865    {"name": "FLUSH_ES_OUTPUT", "value": 28},
866    {"name": "BIN_CONF_OVERRIDE_CHECK", "value": 29},
867    {"name": "SAMPLE_PIPELINESTAT", "value": 30},
868    {"name": "SO_VGTSTREAMOUT_FLUSH", "value": 31},
869    {"name": "SAMPLE_STREAMOUTSTATS", "value": 32},
870    {"name": "RESET_VTX_CNT", "value": 33},
871    {"name": "BLOCK_CONTEXT_DONE", "value": 34},
872    {"name": "CS_CONTEXT_DONE", "value": 35},
873    {"name": "VGT_FLUSH", "value": 36},
874    {"name": "TGID_ROLLOVER", "value": 37},
875    {"name": "SQ_NON_EVENT", "value": 38},
876    {"name": "SC_SEND_DB_VPZ", "value": 39},
877    {"name": "BOTTOM_OF_PIPE_TS", "value": 40},
878    {"name": "FLUSH_SX_TS", "value": 41},
879    {"name": "DB_CACHE_FLUSH_AND_INV", "value": 42},
880    {"name": "FLUSH_AND_INV_DB_DATA_TS", "value": 43},
881    {"name": "FLUSH_AND_INV_DB_META", "value": 44},
882    {"name": "FLUSH_AND_INV_CB_DATA_TS", "value": 45},
883    {"name": "FLUSH_AND_INV_CB_META", "value": 46},
884    {"name": "CS_DONE", "value": 47},
885    {"name": "PS_DONE", "value": 48},
886    {"name": "FLUSH_AND_INV_CB_PIXEL_DATA", "value": 49},
887    {"name": "SX_CB_RAT_ACK_REQUEST", "value": 50},
888    {"name": "THREAD_TRACE_START", "value": 51},
889    {"name": "THREAD_TRACE_STOP", "value": 52},
890    {"name": "THREAD_TRACE_MARKER", "value": 53},
891    {"name": "THREAD_TRACE_DRAW", "value": 54},
892    {"name": "THREAD_TRACE_FINISH", "value": 55},
893    {"name": "PIXEL_PIPE_STAT_CONTROL", "value": 56},
894    {"name": "PIXEL_PIPE_STAT_DUMP", "value": 57},
895    {"name": "PIXEL_PIPE_STAT_RESET", "value": 58},
896    {"name": "CONTEXT_SUSPEND", "value": 59},
897    {"name": "OFFCHIP_HS_DEALLOC", "value": 60},
898    {"name": "ENABLE_NGG_PIPELINE", "value": 61},
899    {"name": "ENABLE_LEGACY_PIPELINE", "value": 62},
900    {"name": "DRAW_DONE", "value": 63}
901   ]
902  },
903  "VGT_GS_CUT_MODE": {
904   "entries": [
905    {"name": "GS_CUT_1024", "value": 0},
906    {"name": "GS_CUT_512", "value": 1},
907    {"name": "GS_CUT_256", "value": 2},
908    {"name": "GS_CUT_128", "value": 3}
909   ]
910  },
911  "VGT_GS_MODE_TYPE": {
912   "entries": [
913    {"name": "GS_OFF", "value": 0},
914    {"name": "GS_SCENARIO_A", "value": 1},
915    {"name": "GS_SCENARIO_B", "value": 2},
916    {"name": "GS_SCENARIO_G", "value": 3},
917    {"name": "GS_SCENARIO_C", "value": 4},
918    {"name": "SPRITE_EN", "value": 5}
919   ]
920  },
921  "VGT_GS_OUTPRIM_TYPE": {
922   "entries": [
923    {"name": "POINTLIST", "value": 0},
924    {"name": "LINESTRIP", "value": 1},
925    {"name": "TRISTRIP", "value": 2},
926    {"name": "RECTLIST", "value": 3}
927   ]
928  },
929  "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY": {
930   "entries": [
931    {"name": "X_8K_DWORDS", "value": 0},
932    {"name": "X_4K_DWORDS", "value": 1},
933    {"name": "X_2K_DWORDS", "value": 2},
934    {"name": "X_1K_DWORDS", "value": 3}
935   ]
936  },
937  "VGT_INDEX_TYPE_MODE": {
938   "entries": [
939    {"name": "VGT_INDEX_16", "value": 0},
940    {"name": "VGT_INDEX_32", "value": 1},
941    {"name": "VGT_INDEX_8", "value": 2}
942   ]
943  },
944  "VGT_RDREQ_POLICY": {
945   "entries": [
946    {"name": "VGT_POLICY_LRU", "value": 0},
947    {"name": "VGT_POLICY_STREAM", "value": 1},
948    {"name": "VGT_POLICY_BYPASS", "value": 2}
949   ]
950  },
951  "VGT_STAGES_ES_EN": {
952   "entries": [
953    {"name": "ES_STAGE_OFF", "value": 0},
954    {"name": "ES_STAGE_DS", "value": 1},
955    {"name": "ES_STAGE_REAL", "value": 2},
956    {"name": "RESERVED_ES", "value": 3}
957   ]
958  },
959  "VGT_STAGES_GS_EN": {
960   "entries": [
961    {"name": "GS_STAGE_OFF", "value": 0},
962    {"name": "GS_STAGE_ON", "value": 1}
963   ]
964  },
965  "VGT_STAGES_HS_EN": {
966   "entries": [
967    {"name": "HS_STAGE_OFF", "value": 0},
968    {"name": "HS_STAGE_ON", "value": 1}
969   ]
970  },
971  "VGT_STAGES_LS_EN": {
972   "entries": [
973    {"name": "LS_STAGE_OFF", "value": 0},
974    {"name": "LS_STAGE_ON", "value": 1},
975    {"name": "CS_STAGE_ON", "value": 2},
976    {"name": "RESERVED_LS", "value": 3}
977   ]
978  },
979  "VGT_STAGES_VS_EN": {
980   "entries": [
981    {"name": "VS_STAGE_REAL", "value": 0},
982    {"name": "VS_STAGE_DS", "value": 1},
983    {"name": "VS_STAGE_COPY_SHADER", "value": 2},
984    {"name": "RESERVED_VS", "value": 3}
985   ]
986  },
987  "VGT_TESS_PARTITION": {
988   "entries": [
989    {"name": "PART_INTEGER", "value": 0},
990    {"name": "PART_POW2", "value": 1},
991    {"name": "PART_FRAC_ODD", "value": 2},
992    {"name": "PART_FRAC_EVEN", "value": 3}
993   ]
994  },
995  "VGT_TESS_TOPOLOGY": {
996   "entries": [
997    {"name": "OUTPUT_POINT", "value": 0},
998    {"name": "OUTPUT_LINE", "value": 1},
999    {"name": "OUTPUT_TRIANGLE_CW", "value": 2},
1000    {"name": "OUTPUT_TRIANGLE_CCW", "value": 3}
1001   ]
1002  },
1003  "VGT_TESS_TYPE": {
1004   "entries": [
1005    {"name": "TESS_ISOLINE", "value": 0},
1006    {"name": "TESS_TRIANGLE", "value": 1},
1007    {"name": "TESS_QUAD", "value": 2}
1008   ]
1009  },
1010  "WritePolicy": {
1011   "entries": [
1012    {"name": "CACHE_LRU_WR", "value": 0},
1013    {"name": "CACHE_STREAM", "value": 1},
1014    {"name": "CACHE_BYPASS", "value": 2},
1015    {"name": "UNCACHED_WR", "value": 3}
1016   ]
1017  },
1018  "ZFormat": {
1019   "entries": [
1020    {"name": "Z_INVALID", "value": 0},
1021    {"name": "Z_16", "value": 1},
1022    {"name": "Z_24", "value": 2},
1023    {"name": "Z_32_FLOAT", "value": 3}
1024   ]
1025  },
1026  "ZLimitSumm": {
1027   "entries": [
1028    {"name": "FORCE_SUMM_OFF", "value": 0},
1029    {"name": "FORCE_SUMM_MINZ", "value": 1},
1030    {"name": "FORCE_SUMM_MAXZ", "value": 2},
1031    {"name": "FORCE_SUMM_BOTH", "value": 3}
1032   ]
1033  },
1034  "ZOrder": {
1035   "entries": [
1036    {"name": "LATE_Z", "value": 0},
1037    {"name": "EARLY_Z_THEN_LATE_Z", "value": 1},
1038    {"name": "RE_Z", "value": 2},
1039    {"name": "EARLY_Z_THEN_RE_Z", "value": 3}
1040   ]
1041  }
1042 },
1043 "register_mappings": [
1044  {
1045   "chips": ["gfx10"],
1046   "map": {"at": 1028, "to": "mm"},
1047   "name": "SQ_WAVE_MODE",
1048   "type_ref": "SQ_WAVE_MODE"
1049  },
1050  {
1051   "chips": ["gfx10"],
1052   "map": {"at": 1032, "to": "mm"},
1053   "name": "SQ_WAVE_STATUS",
1054   "type_ref": "SQ_WAVE_STATUS"
1055  },
1056  {
1057   "chips": ["gfx10"],
1058   "map": {"at": 1036, "to": "mm"},
1059   "name": "SQ_WAVE_TRAPSTS",
1060   "type_ref": "SQ_WAVE_TRAPSTS"
1061  },
1062  {
1063   "chips": ["gfx10"],
1064   "map": {"at": 1040, "to": "mm"},
1065   "name": "SQ_WAVE_HW_ID_LEGACY",
1066   "type_ref": "SQ_WAVE_HW_ID_LEGACY"
1067  },
1068  {
1069   "chips": ["gfx10"],
1070   "map": {"at": 1044, "to": "mm"},
1071   "name": "SQ_WAVE_GPR_ALLOC",
1072   "type_ref": "SQ_WAVE_GPR_ALLOC"
1073  },
1074  {
1075   "chips": ["gfx10"],
1076   "map": {"at": 1048, "to": "mm"},
1077   "name": "SQ_WAVE_LDS_ALLOC",
1078   "type_ref": "SQ_WAVE_LDS_ALLOC"
1079  },
1080  {
1081   "chips": ["gfx10"],
1082   "map": {"at": 1052, "to": "mm"},
1083   "name": "SQ_WAVE_IB_STS",
1084   "type_ref": "SQ_WAVE_IB_STS"
1085  },
1086  {
1087   "chips": ["gfx10"],
1088   "map": {"at": 1056, "to": "mm"},
1089   "name": "SQ_WAVE_PC_LO"
1090  },
1091  {
1092   "chips": ["gfx10"],
1093   "map": {"at": 1060, "to": "mm"},
1094   "name": "SQ_WAVE_PC_HI",
1095   "type_ref": "SQ_WAVE_PC_HI"
1096  },
1097  {
1098   "chips": ["gfx10"],
1099   "map": {"at": 1064, "to": "mm"},
1100   "name": "SQ_WAVE_INST_DW0"
1101  },
1102  {
1103   "chips": ["gfx10"],
1104   "map": {"at": 1076, "to": "mm"},
1105   "name": "SQ_WAVE_IB_DBG1",
1106   "type_ref": "SQ_WAVE_IB_DBG1"
1107  },
1108  {
1109   "chips": ["gfx10"],
1110   "map": {"at": 1080, "to": "mm"},
1111   "name": "SQ_WAVE_FLUSH_IB"
1112  },
1113  {
1114   "chips": ["gfx10"],
1115   "map": {"at": 1116, "to": "mm"},
1116   "name": "SQ_WAVE_HW_ID1",
1117   "type_ref": "SQ_WAVE_HW_ID1"
1118  },
1119  {
1120   "chips": ["gfx10"],
1121   "map": {"at": 1120, "to": "mm"},
1122   "name": "SQ_WAVE_HW_ID2",
1123   "type_ref": "SQ_WAVE_HW_ID2"
1124  },
1125  {
1126   "chips": ["gfx10"],
1127   "map": {"at": 1124, "to": "mm"},
1128   "name": "SQ_WAVE_POPS_PACKER",
1129   "type_ref": "SQ_WAVE_POPS_PACKER"
1130  },
1131  {
1132   "chips": ["gfx10"],
1133   "map": {"at": 1128, "to": "mm"},
1134   "name": "SQ_WAVE_SCHED_MODE",
1135   "type_ref": "SQ_WAVE_SCHED_MODE"
1136  },
1137  {
1138   "chips": ["gfx10"],
1139   "map": {"at": 1132, "to": "mm"},
1140   "name": "SQ_WAVE_VGPR_OFFSET",
1141   "type_ref": "SQ_WAVE_VGPR_OFFSET"
1142  },
1143  {
1144   "chips": ["gfx10"],
1145   "map": {"at": 1136, "to": "mm"},
1146   "name": "SQ_WAVE_IB_STS2",
1147   "type_ref": "SQ_WAVE_IB_STS2"
1148  },
1149  {
1150   "chips": ["gfx10"],
1151   "map": {"at": 2480, "to": "mm"},
1152   "name": "SQ_WAVE_TTMP0"
1153  },
1154  {
1155   "chips": ["gfx10"],
1156   "map": {"at": 2484, "to": "mm"},
1157   "name": "SQ_WAVE_TTMP1"
1158  },
1159  {
1160   "chips": ["gfx10"],
1161   "map": {"at": 2488, "to": "mm"},
1162   "name": "SQ_WAVE_TTMP2"
1163  },
1164  {
1165   "chips": ["gfx10"],
1166   "map": {"at": 2492, "to": "mm"},
1167   "name": "SQ_WAVE_TTMP3"
1168  },
1169  {
1170   "chips": ["gfx10"],
1171   "map": {"at": 2496, "to": "mm"},
1172   "name": "SQ_WAVE_TTMP4"
1173  },
1174  {
1175   "chips": ["gfx10"],
1176   "map": {"at": 2500, "to": "mm"},
1177   "name": "SQ_WAVE_TTMP5"
1178  },
1179  {
1180   "chips": ["gfx10"],
1181   "map": {"at": 2504, "to": "mm"},
1182   "name": "SQ_WAVE_TTMP6"
1183  },
1184  {
1185   "chips": ["gfx10"],
1186   "map": {"at": 2508, "to": "mm"},
1187   "name": "SQ_WAVE_TTMP7"
1188  },
1189  {
1190   "chips": ["gfx10"],
1191   "map": {"at": 2512, "to": "mm"},
1192   "name": "SQ_WAVE_TTMP8"
1193  },
1194  {
1195   "chips": ["gfx10"],
1196   "map": {"at": 2516, "to": "mm"},
1197   "name": "SQ_WAVE_TTMP9"
1198  },
1199  {
1200   "chips": ["gfx10"],
1201   "map": {"at": 2520, "to": "mm"},
1202   "name": "SQ_WAVE_TTMP10"
1203  },
1204  {
1205   "chips": ["gfx10"],
1206   "map": {"at": 2524, "to": "mm"},
1207   "name": "SQ_WAVE_TTMP11"
1208  },
1209  {
1210   "chips": ["gfx10"],
1211   "map": {"at": 2528, "to": "mm"},
1212   "name": "SQ_WAVE_TTMP12"
1213  },
1214  {
1215   "chips": ["gfx10"],
1216   "map": {"at": 2532, "to": "mm"},
1217   "name": "SQ_WAVE_TTMP13"
1218  },
1219  {
1220   "chips": ["gfx10"],
1221   "map": {"at": 2536, "to": "mm"},
1222   "name": "SQ_WAVE_TTMP14"
1223  },
1224  {
1225   "chips": ["gfx10"],
1226   "map": {"at": 2540, "to": "mm"},
1227   "name": "SQ_WAVE_TTMP15"
1228  },
1229  {
1230   "chips": ["gfx10"],
1231   "map": {"at": 2544, "to": "mm"},
1232   "name": "SQ_WAVE_M0"
1233  },
1234  {
1235   "chips": ["gfx10"],
1236   "map": {"at": 2552, "to": "mm"},
1237   "name": "SQ_WAVE_EXEC_LO"
1238  },
1239  {
1240   "chips": ["gfx10"],
1241   "map": {"at": 2556, "to": "mm"},
1242   "name": "SQ_WAVE_EXEC_HI"
1243  },
1244  {
1245   "chips": ["gfx10"],
1246   "map": {"at": 2560, "to": "mm"},
1247   "name": "SQ_WAVE_FLAT_SCRATCH_LO"
1248  },
1249  {
1250   "chips": ["gfx10"],
1251   "map": {"at": 2564, "to": "mm"},
1252   "name": "SQ_WAVE_FLAT_SCRATCH_HI"
1253  },
1254  {
1255   "chips": ["gfx10"],
1256   "map": {"at": 2568, "to": "mm"},
1257   "name": "SQ_WAVE_FLAT_XNACK_MASK"
1258  },
1259  {
1260   "chips": ["gfx10"],
1261   "map": {"at": 32776, "to": "mm"},
1262   "name": "GRBM_STATUS2",
1263   "type_ref": "GRBM_STATUS2"
1264  },
1265  {
1266   "chips": ["gfx10"],
1267   "map": {"at": 32784, "to": "mm"},
1268   "name": "GRBM_STATUS",
1269   "type_ref": "GRBM_STATUS"
1270  },
1271  {
1272   "chips": ["gfx10"],
1273   "map": {"at": 32788, "to": "mm"},
1274   "name": "GRBM_STATUS_SE0",
1275   "type_ref": "GRBM_STATUS_SE0"
1276  },
1277  {
1278   "chips": ["gfx10"],
1279   "map": {"at": 32792, "to": "mm"},
1280   "name": "GRBM_STATUS_SE1",
1281   "type_ref": "GRBM_STATUS_SE0"
1282  },
1283  {
1284   "chips": ["gfx10"],
1285   "map": {"at": 32796, "to": "mm"},
1286   "name": "GRBM_STATUS3",
1287   "type_ref": "GRBM_STATUS3"
1288  },
1289  {
1290   "chips": ["gfx10"],
1291   "map": {"at": 32824, "to": "mm"},
1292   "name": "GRBM_STATUS_SE2",
1293   "type_ref": "GRBM_STATUS_SE0"
1294  },
1295  {
1296   "chips": ["gfx10"],
1297   "map": {"at": 32828, "to": "mm"},
1298   "name": "GRBM_STATUS_SE3",
1299   "type_ref": "GRBM_STATUS_SE0"
1300  },
1301  {
1302   "chips": ["gfx10"],
1303   "map": {"at": 33296, "to": "mm"},
1304   "name": "CP_CPC_STATUS",
1305   "type_ref": "CP_CPC_STATUS"
1306  },
1307  {
1308   "chips": ["gfx10"],
1309   "map": {"at": 33300, "to": "mm"},
1310   "name": "CP_CPC_BUSY_STAT",
1311   "type_ref": "CP_CPC_BUSY_STAT"
1312  },
1313  {
1314   "chips": ["gfx10"],
1315   "map": {"at": 33304, "to": "mm"},
1316   "name": "CP_CPC_STALLED_STAT1",
1317   "type_ref": "CP_CPC_STALLED_STAT1"
1318  },
1319  {
1320   "chips": ["gfx10"],
1321   "map": {"at": 33308, "to": "mm"},
1322   "name": "CP_CPF_STATUS",
1323   "type_ref": "CP_CPF_STATUS"
1324  },
1325  {
1326   "chips": ["gfx10"],
1327   "map": {"at": 33312, "to": "mm"},
1328   "name": "CP_CPF_BUSY_STAT",
1329   "type_ref": "CP_CPF_BUSY_STAT"
1330  },
1331  {
1332   "chips": ["gfx10"],
1333   "map": {"at": 33316, "to": "mm"},
1334   "name": "CP_CPF_STALLED_STAT1",
1335   "type_ref": "CP_CPF_STALLED_STAT1"
1336  },
1337  {
1338   "chips": ["gfx10"],
1339   "map": {"at": 33320, "to": "mm"},
1340   "name": "CP_CPC_BUSY_STAT2",
1341   "type_ref": "CP_CPC_BUSY_STAT2"
1342  },
1343  {
1344   "chips": ["gfx10"],
1345   "map": {"at": 33324, "to": "mm"},
1346   "name": "CP_CPC_GRBM_FREE_COUNT",
1347   "type_ref": "CP_CPC_GRBM_FREE_COUNT"
1348  },
1349  {
1350   "chips": ["gfx10"],
1351   "map": {"at": 33344, "to": "mm"},
1352   "name": "CP_CPC_SCRATCH_INDEX",
1353   "type_ref": "CP_CPC_SCRATCH_INDEX"
1354  },
1355  {
1356   "chips": ["gfx10"],
1357   "map": {"at": 33348, "to": "mm"},
1358   "name": "CP_CPC_SCRATCH_DATA"
1359  },
1360  {
1361   "chips": ["gfx10"],
1362   "map": {"at": 33352, "to": "mm"},
1363   "name": "CP_CPF_GRBM_FREE_COUNT",
1364   "type_ref": "CP_CPF_GRBM_FREE_COUNT"
1365  },
1366  {
1367   "chips": ["gfx10"],
1368   "map": {"at": 33356, "to": "mm"},
1369   "name": "CP_CPF_BUSY_STAT2",
1370   "type_ref": "CP_CPF_BUSY_STAT2"
1371  },
1372  {
1373   "chips": ["gfx10"],
1374   "map": {"at": 33436, "to": "mm"},
1375   "name": "CP_CPC_HALT_HYST_COUNT",
1376   "type_ref": "CP_CPC_HALT_HYST_COUNT"
1377  },
1378  {
1379   "chips": ["gfx10"],
1380   "map": {"at": 36096, "to": "mm"},
1381   "name": "SQ_THREAD_TRACE_BUF0_BASE"
1382  },
1383  {
1384   "chips": ["gfx10"],
1385   "map": {"at": 36100, "to": "mm"},
1386   "name": "SQ_THREAD_TRACE_BUF0_SIZE",
1387   "type_ref": "SQ_THREAD_TRACE_BUF0_SIZE"
1388  },
1389  {
1390   "chips": ["gfx10"],
1391   "map": {"at": 36104, "to": "mm"},
1392   "name": "SQ_THREAD_TRACE_BUF1_BASE"
1393  },
1394  {
1395   "chips": ["gfx10"],
1396   "map": {"at": 36108, "to": "mm"},
1397   "name": "SQ_THREAD_TRACE_BUF1_SIZE",
1398   "type_ref": "SQ_THREAD_TRACE_BUF0_SIZE"
1399  },
1400  {
1401   "chips": ["gfx10"],
1402   "map": {"at": 36112, "to": "mm"},
1403   "name": "SQ_THREAD_TRACE_WPTR",
1404   "type_ref": "SQ_THREAD_TRACE_WPTR"
1405  },
1406  {
1407   "chips": ["gfx10"],
1408   "map": {"at": 36116, "to": "mm"},
1409   "name": "SQ_THREAD_TRACE_MASK",
1410   "type_ref": "SQ_THREAD_TRACE_MASK"
1411  },
1412  {
1413   "chips": ["gfx10"],
1414   "map": {"at": 36120, "to": "mm"},
1415   "name": "SQ_THREAD_TRACE_TOKEN_MASK",
1416   "type_ref": "SQ_THREAD_TRACE_TOKEN_MASK"
1417  },
1418  {
1419   "chips": ["gfx10"],
1420   "map": {"at": 36124, "to": "mm"},
1421   "name": "SQ_THREAD_TRACE_CTRL",
1422   "type_ref": "SQ_THREAD_TRACE_CTRL"
1423  },
1424  {
1425   "chips": ["gfx10"],
1426   "map": {"at": 36128, "to": "mm"},
1427   "name": "SQ_THREAD_TRACE_STATUS",
1428   "type_ref": "SQ_THREAD_TRACE_STATUS"
1429  },
1430  {
1431   "chips": ["gfx10"],
1432   "map": {"at": 36132, "to": "mm"},
1433   "name": "SQ_THREAD_TRACE_DROPPED_CNTR"
1434  },
1435  {
1436   "chips": ["gfx10"],
1437   "map": {"at": 36140, "to": "mm"},
1438   "name": "SQ_THREAD_TRACE_GFX_DRAW_CNTR"
1439  },
1440  {
1441   "chips": ["gfx10"],
1442   "map": {"at": 36144, "to": "mm"},
1443   "name": "SQ_THREAD_TRACE_GFX_MARKER_CNTR"
1444  },
1445  {
1446   "chips": ["gfx10"],
1447   "map": {"at": 36148, "to": "mm"},
1448   "name": "SQ_THREAD_TRACE_HP3D_DRAW_CNTR"
1449  },
1450  {
1451   "chips": ["gfx10"],
1452   "map": {"at": 36152, "to": "mm"},
1453   "name": "SQ_THREAD_TRACE_HP3D_MARKER_CNTR"
1454  },
1455  {
1456   "chips": ["gfx10"],
1457   "map": {"at": 37120, "to": "mm"},
1458   "name": "SPI_CONFIG_CNTL",
1459   "type_ref": "SPI_CONFIG_CNTL"
1460  },
1461  {
1462   "chips": ["gfx10"],
1463   "map": {"at": 39160, "to": "mm"},
1464   "name": "GB_ADDR_CONFIG",
1465   "type_ref": "GB_ADDR_CONFIG"
1466  },
1467  {
1468   "chips": ["gfx10"],
1469   "map": {"at": 39184, "to": "mm"},
1470   "name": "GB_TILE_MODE0",
1471   "type_ref": "GB_TILE_MODE0"
1472  },
1473  {
1474   "chips": ["gfx10"],
1475   "map": {"at": 39188, "to": "mm"},
1476   "name": "GB_TILE_MODE1",
1477   "type_ref": "GB_TILE_MODE0"
1478  },
1479  {
1480   "chips": ["gfx10"],
1481   "map": {"at": 39192, "to": "mm"},
1482   "name": "GB_TILE_MODE2",
1483   "type_ref": "GB_TILE_MODE0"
1484  },
1485  {
1486   "chips": ["gfx10"],
1487   "map": {"at": 39196, "to": "mm"},
1488   "name": "GB_TILE_MODE3",
1489   "type_ref": "GB_TILE_MODE0"
1490  },
1491  {
1492   "chips": ["gfx10"],
1493   "map": {"at": 39200, "to": "mm"},
1494   "name": "GB_TILE_MODE4",
1495   "type_ref": "GB_TILE_MODE0"
1496  },
1497  {
1498   "chips": ["gfx10"],
1499   "map": {"at": 39204, "to": "mm"},
1500   "name": "GB_TILE_MODE5",
1501   "type_ref": "GB_TILE_MODE0"
1502  },
1503  {
1504   "chips": ["gfx10"],
1505   "map": {"at": 39208, "to": "mm"},
1506   "name": "GB_TILE_MODE6",
1507   "type_ref": "GB_TILE_MODE0"
1508  },
1509  {
1510   "chips": ["gfx10"],
1511   "map": {"at": 39212, "to": "mm"},
1512   "name": "GB_TILE_MODE7",
1513   "type_ref": "GB_TILE_MODE0"
1514  },
1515  {
1516   "chips": ["gfx10"],
1517   "map": {"at": 39216, "to": "mm"},
1518   "name": "GB_TILE_MODE8",
1519   "type_ref": "GB_TILE_MODE0"
1520  },
1521  {
1522   "chips": ["gfx10"],
1523   "map": {"at": 39220, "to": "mm"},
1524   "name": "GB_TILE_MODE9",
1525   "type_ref": "GB_TILE_MODE0"
1526  },
1527  {
1528   "chips": ["gfx10"],
1529   "map": {"at": 39224, "to": "mm"},
1530   "name": "GB_TILE_MODE10",
1531   "type_ref": "GB_TILE_MODE0"
1532  },
1533  {
1534   "chips": ["gfx10"],
1535   "map": {"at": 39228, "to": "mm"},
1536   "name": "GB_TILE_MODE11",
1537   "type_ref": "GB_TILE_MODE0"
1538  },
1539  {
1540   "chips": ["gfx10"],
1541   "map": {"at": 39232, "to": "mm"},
1542   "name": "GB_TILE_MODE12",
1543   "type_ref": "GB_TILE_MODE0"
1544  },
1545  {
1546   "chips": ["gfx10"],
1547   "map": {"at": 39236, "to": "mm"},
1548   "name": "GB_TILE_MODE13",
1549   "type_ref": "GB_TILE_MODE0"
1550  },
1551  {
1552   "chips": ["gfx10"],
1553   "map": {"at": 39240, "to": "mm"},
1554   "name": "GB_TILE_MODE14",
1555   "type_ref": "GB_TILE_MODE0"
1556  },
1557  {
1558   "chips": ["gfx10"],
1559   "map": {"at": 39244, "to": "mm"},
1560   "name": "GB_TILE_MODE15",
1561   "type_ref": "GB_TILE_MODE0"
1562  },
1563  {
1564   "chips": ["gfx10"],
1565   "map": {"at": 39248, "to": "mm"},
1566   "name": "GB_TILE_MODE16",
1567   "type_ref": "GB_TILE_MODE0"
1568  },
1569  {
1570   "chips": ["gfx10"],
1571   "map": {"at": 39252, "to": "mm"},
1572   "name": "GB_TILE_MODE17",
1573   "type_ref": "GB_TILE_MODE0"
1574  },
1575  {
1576   "chips": ["gfx10"],
1577   "map": {"at": 39256, "to": "mm"},
1578   "name": "GB_TILE_MODE18",
1579   "type_ref": "GB_TILE_MODE0"
1580  },
1581  {
1582   "chips": ["gfx10"],
1583   "map": {"at": 39260, "to": "mm"},
1584   "name": "GB_TILE_MODE19",
1585   "type_ref": "GB_TILE_MODE0"
1586  },
1587  {
1588   "chips": ["gfx10"],
1589   "map": {"at": 39264, "to": "mm"},
1590   "name": "GB_TILE_MODE20",
1591   "type_ref": "GB_TILE_MODE0"
1592  },
1593  {
1594   "chips": ["gfx10"],
1595   "map": {"at": 39268, "to": "mm"},
1596   "name": "GB_TILE_MODE21",
1597   "type_ref": "GB_TILE_MODE0"
1598  },
1599  {
1600   "chips": ["gfx10"],
1601   "map": {"at": 39272, "to": "mm"},
1602   "name": "GB_TILE_MODE22",
1603   "type_ref": "GB_TILE_MODE0"
1604  },
1605  {
1606   "chips": ["gfx10"],
1607   "map": {"at": 39276, "to": "mm"},
1608   "name": "GB_TILE_MODE23",
1609   "type_ref": "GB_TILE_MODE0"
1610  },
1611  {
1612   "chips": ["gfx10"],
1613   "map": {"at": 39280, "to": "mm"},
1614   "name": "GB_TILE_MODE24",
1615   "type_ref": "GB_TILE_MODE0"
1616  },
1617  {
1618   "chips": ["gfx10"],
1619   "map": {"at": 39284, "to": "mm"},
1620   "name": "GB_TILE_MODE25",
1621   "type_ref": "GB_TILE_MODE0"
1622  },
1623  {
1624   "chips": ["gfx10"],
1625   "map": {"at": 39288, "to": "mm"},
1626   "name": "GB_TILE_MODE26",
1627   "type_ref": "GB_TILE_MODE0"
1628  },
1629  {
1630   "chips": ["gfx10"],
1631   "map": {"at": 39292, "to": "mm"},
1632   "name": "GB_TILE_MODE27",
1633   "type_ref": "GB_TILE_MODE0"
1634  },
1635  {
1636   "chips": ["gfx10"],
1637   "map": {"at": 39296, "to": "mm"},
1638   "name": "GB_TILE_MODE28",
1639   "type_ref": "GB_TILE_MODE0"
1640  },
1641  {
1642   "chips": ["gfx10"],
1643   "map": {"at": 39300, "to": "mm"},
1644   "name": "GB_TILE_MODE29",
1645   "type_ref": "GB_TILE_MODE0"
1646  },
1647  {
1648   "chips": ["gfx10"],
1649   "map": {"at": 39304, "to": "mm"},
1650   "name": "GB_TILE_MODE30",
1651   "type_ref": "GB_TILE_MODE0"
1652  },
1653  {
1654   "chips": ["gfx10"],
1655   "map": {"at": 39308, "to": "mm"},
1656   "name": "GB_TILE_MODE31",
1657   "type_ref": "GB_TILE_MODE0"
1658  },
1659  {
1660   "chips": ["gfx10"],
1661   "map": {"at": 39312, "to": "mm"},
1662   "name": "GB_MACROTILE_MODE0",
1663   "type_ref": "GB_MACROTILE_MODE0"
1664  },
1665  {
1666   "chips": ["gfx10"],
1667   "map": {"at": 39316, "to": "mm"},
1668   "name": "GB_MACROTILE_MODE1",
1669   "type_ref": "GB_MACROTILE_MODE0"
1670  },
1671  {
1672   "chips": ["gfx10"],
1673   "map": {"at": 39320, "to": "mm"},
1674   "name": "GB_MACROTILE_MODE2",
1675   "type_ref": "GB_MACROTILE_MODE0"
1676  },
1677  {
1678   "chips": ["gfx10"],
1679   "map": {"at": 39324, "to": "mm"},
1680   "name": "GB_MACROTILE_MODE3",
1681   "type_ref": "GB_MACROTILE_MODE0"
1682  },
1683  {
1684   "chips": ["gfx10"],
1685   "map": {"at": 39328, "to": "mm"},
1686   "name": "GB_MACROTILE_MODE4",
1687   "type_ref": "GB_MACROTILE_MODE0"
1688  },
1689  {
1690   "chips": ["gfx10"],
1691   "map": {"at": 39332, "to": "mm"},
1692   "name": "GB_MACROTILE_MODE5",
1693   "type_ref": "GB_MACROTILE_MODE0"
1694  },
1695  {
1696   "chips": ["gfx10"],
1697   "map": {"at": 39336, "to": "mm"},
1698   "name": "GB_MACROTILE_MODE6",
1699   "type_ref": "GB_MACROTILE_MODE0"
1700  },
1701  {
1702   "chips": ["gfx10"],
1703   "map": {"at": 39340, "to": "mm"},
1704   "name": "GB_MACROTILE_MODE7",
1705   "type_ref": "GB_MACROTILE_MODE0"
1706  },
1707  {
1708   "chips": ["gfx10"],
1709   "map": {"at": 39344, "to": "mm"},
1710   "name": "GB_MACROTILE_MODE8",
1711   "type_ref": "GB_MACROTILE_MODE0"
1712  },
1713  {
1714   "chips": ["gfx10"],
1715   "map": {"at": 39348, "to": "mm"},
1716   "name": "GB_MACROTILE_MODE9",
1717   "type_ref": "GB_MACROTILE_MODE0"
1718  },
1719  {
1720   "chips": ["gfx10"],
1721   "map": {"at": 39352, "to": "mm"},
1722   "name": "GB_MACROTILE_MODE10",
1723   "type_ref": "GB_MACROTILE_MODE0"
1724  },
1725  {
1726   "chips": ["gfx10"],
1727   "map": {"at": 39356, "to": "mm"},
1728   "name": "GB_MACROTILE_MODE11",
1729   "type_ref": "GB_MACROTILE_MODE0"
1730  },
1731  {
1732   "chips": ["gfx10"],
1733   "map": {"at": 39360, "to": "mm"},
1734   "name": "GB_MACROTILE_MODE12",
1735   "type_ref": "GB_MACROTILE_MODE0"
1736  },
1737  {
1738   "chips": ["gfx10"],
1739   "map": {"at": 39364, "to": "mm"},
1740   "name": "GB_MACROTILE_MODE13",
1741   "type_ref": "GB_MACROTILE_MODE0"
1742  },
1743  {
1744   "chips": ["gfx10"],
1745   "map": {"at": 39368, "to": "mm"},
1746   "name": "GB_MACROTILE_MODE14",
1747   "type_ref": "GB_MACROTILE_MODE0"
1748  },
1749  {
1750   "chips": ["gfx10"],
1751   "map": {"at": 39372, "to": "mm"},
1752   "name": "GB_MACROTILE_MODE15",
1753   "type_ref": "GB_MACROTILE_MODE0"
1754  },
1755  {
1756   "chips": ["gfx10"],
1757   "map": {"at": 45060, "to": "mm"},
1758   "name": "SPI_SHADER_PGM_RSRC4_PS",
1759   "type_ref": "SPI_SHADER_PGM_RSRC4_PS"
1760  },
1761  {
1762   "chips": ["gfx10"],
1763   "map": {"at": 45080, "to": "mm"},
1764   "name": "SPI_SHADER_PGM_CHKSUM_PS"
1765  },
1766  {
1767   "chips": ["gfx10"],
1768   "map": {"at": 45084, "to": "mm"},
1769   "name": "SPI_SHADER_PGM_RSRC3_PS",
1770   "type_ref": "SPI_SHADER_PGM_RSRC3_PS"
1771  },
1772  {
1773   "chips": ["gfx10"],
1774   "map": {"at": 45088, "to": "mm"},
1775   "name": "SPI_SHADER_PGM_LO_PS"
1776  },
1777  {
1778   "chips": ["gfx10"],
1779   "map": {"at": 45092, "to": "mm"},
1780   "name": "SPI_SHADER_PGM_HI_PS",
1781   "type_ref": "SPI_SHADER_PGM_HI_PS"
1782  },
1783  {
1784   "chips": ["gfx10"],
1785   "map": {"at": 45096, "to": "mm"},
1786   "name": "SPI_SHADER_PGM_RSRC1_PS",
1787   "type_ref": "SPI_SHADER_PGM_RSRC1_PS"
1788  },
1789  {
1790   "chips": ["gfx10"],
1791   "map": {"at": 45100, "to": "mm"},
1792   "name": "SPI_SHADER_PGM_RSRC2_PS",
1793   "type_ref": "SPI_SHADER_PGM_RSRC2_PS"
1794  },
1795  {
1796   "chips": ["gfx10"],
1797   "map": {"at": 45104, "to": "mm"},
1798   "name": "SPI_SHADER_USER_DATA_PS_0"
1799  },
1800  {
1801   "chips": ["gfx10"],
1802   "map": {"at": 45108, "to": "mm"},
1803   "name": "SPI_SHADER_USER_DATA_PS_1"
1804  },
1805  {
1806   "chips": ["gfx10"],
1807   "map": {"at": 45112, "to": "mm"},
1808   "name": "SPI_SHADER_USER_DATA_PS_2"
1809  },
1810  {
1811   "chips": ["gfx10"],
1812   "map": {"at": 45116, "to": "mm"},
1813   "name": "SPI_SHADER_USER_DATA_PS_3"
1814  },
1815  {
1816   "chips": ["gfx10"],
1817   "map": {"at": 45120, "to": "mm"},
1818   "name": "SPI_SHADER_USER_DATA_PS_4"
1819  },
1820  {
1821   "chips": ["gfx10"],
1822   "map": {"at": 45124, "to": "mm"},
1823   "name": "SPI_SHADER_USER_DATA_PS_5"
1824  },
1825  {
1826   "chips": ["gfx10"],
1827   "map": {"at": 45128, "to": "mm"},
1828   "name": "SPI_SHADER_USER_DATA_PS_6"
1829  },
1830  {
1831   "chips": ["gfx10"],
1832   "map": {"at": 45132, "to": "mm"},
1833   "name": "SPI_SHADER_USER_DATA_PS_7"
1834  },
1835  {
1836   "chips": ["gfx10"],
1837   "map": {"at": 45136, "to": "mm"},
1838   "name": "SPI_SHADER_USER_DATA_PS_8"
1839  },
1840  {
1841   "chips": ["gfx10"],
1842   "map": {"at": 45140, "to": "mm"},
1843   "name": "SPI_SHADER_USER_DATA_PS_9"
1844  },
1845  {
1846   "chips": ["gfx10"],
1847   "map": {"at": 45144, "to": "mm"},
1848   "name": "SPI_SHADER_USER_DATA_PS_10"
1849  },
1850  {
1851   "chips": ["gfx10"],
1852   "map": {"at": 45148, "to": "mm"},
1853   "name": "SPI_SHADER_USER_DATA_PS_11"
1854  },
1855  {
1856   "chips": ["gfx10"],
1857   "map": {"at": 45152, "to": "mm"},
1858   "name": "SPI_SHADER_USER_DATA_PS_12"
1859  },
1860  {
1861   "chips": ["gfx10"],
1862   "map": {"at": 45156, "to": "mm"},
1863   "name": "SPI_SHADER_USER_DATA_PS_13"
1864  },
1865  {
1866   "chips": ["gfx10"],
1867   "map": {"at": 45160, "to": "mm"},
1868   "name": "SPI_SHADER_USER_DATA_PS_14"
1869  },
1870  {
1871   "chips": ["gfx10"],
1872   "map": {"at": 45164, "to": "mm"},
1873   "name": "SPI_SHADER_USER_DATA_PS_15"
1874  },
1875  {
1876   "chips": ["gfx10"],
1877   "map": {"at": 45168, "to": "mm"},
1878   "name": "SPI_SHADER_USER_DATA_PS_16"
1879  },
1880  {
1881   "chips": ["gfx10"],
1882   "map": {"at": 45172, "to": "mm"},
1883   "name": "SPI_SHADER_USER_DATA_PS_17"
1884  },
1885  {
1886   "chips": ["gfx10"],
1887   "map": {"at": 45176, "to": "mm"},
1888   "name": "SPI_SHADER_USER_DATA_PS_18"
1889  },
1890  {
1891   "chips": ["gfx10"],
1892   "map": {"at": 45180, "to": "mm"},
1893   "name": "SPI_SHADER_USER_DATA_PS_19"
1894  },
1895  {
1896   "chips": ["gfx10"],
1897   "map": {"at": 45184, "to": "mm"},
1898   "name": "SPI_SHADER_USER_DATA_PS_20"
1899  },
1900  {
1901   "chips": ["gfx10"],
1902   "map": {"at": 45188, "to": "mm"},
1903   "name": "SPI_SHADER_USER_DATA_PS_21"
1904  },
1905  {
1906   "chips": ["gfx10"],
1907   "map": {"at": 45192, "to": "mm"},
1908   "name": "SPI_SHADER_USER_DATA_PS_22"
1909  },
1910  {
1911   "chips": ["gfx10"],
1912   "map": {"at": 45196, "to": "mm"},
1913   "name": "SPI_SHADER_USER_DATA_PS_23"
1914  },
1915  {
1916   "chips": ["gfx10"],
1917   "map": {"at": 45200, "to": "mm"},
1918   "name": "SPI_SHADER_USER_DATA_PS_24"
1919  },
1920  {
1921   "chips": ["gfx10"],
1922   "map": {"at": 45204, "to": "mm"},
1923   "name": "SPI_SHADER_USER_DATA_PS_25"
1924  },
1925  {
1926   "chips": ["gfx10"],
1927   "map": {"at": 45208, "to": "mm"},
1928   "name": "SPI_SHADER_USER_DATA_PS_26"
1929  },
1930  {
1931   "chips": ["gfx10"],
1932   "map": {"at": 45212, "to": "mm"},
1933   "name": "SPI_SHADER_USER_DATA_PS_27"
1934  },
1935  {
1936   "chips": ["gfx10"],
1937   "map": {"at": 45216, "to": "mm"},
1938   "name": "SPI_SHADER_USER_DATA_PS_28"
1939  },
1940  {
1941   "chips": ["gfx10"],
1942   "map": {"at": 45220, "to": "mm"},
1943   "name": "SPI_SHADER_USER_DATA_PS_29"
1944  },
1945  {
1946   "chips": ["gfx10"],
1947   "map": {"at": 45224, "to": "mm"},
1948   "name": "SPI_SHADER_USER_DATA_PS_30"
1949  },
1950  {
1951   "chips": ["gfx10"],
1952   "map": {"at": 45228, "to": "mm"},
1953   "name": "SPI_SHADER_USER_DATA_PS_31"
1954  },
1955  {
1956   "chips": ["gfx10"],
1957   "map": {"at": 45248, "to": "mm"},
1958   "name": "SPI_SHADER_REQ_CTRL_PS",
1959   "type_ref": "SPI_SHADER_REQ_CTRL_PS"
1960  },
1961  {
1962   "chips": ["gfx10"],
1963   "map": {"at": 45252, "to": "mm"},
1964   "name": "SPI_SHADER_PREF_PRI_CNTR_CTRL_PS",
1965   "type_ref": "SPI_SHADER_PREF_PRI_CNTR_CTRL_PS"
1966  },
1967  {
1968   "chips": ["gfx10"],
1969   "map": {"at": 45256, "to": "mm"},
1970   "name": "SPI_SHADER_USER_ACCUM_PS_0",
1971   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
1972  },
1973  {
1974   "chips": ["gfx10"],
1975   "map": {"at": 45260, "to": "mm"},
1976   "name": "SPI_SHADER_USER_ACCUM_PS_1",
1977   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
1978  },
1979  {
1980   "chips": ["gfx10"],
1981   "map": {"at": 45264, "to": "mm"},
1982   "name": "SPI_SHADER_USER_ACCUM_PS_2",
1983   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
1984  },
1985  {
1986   "chips": ["gfx10"],
1987   "map": {"at": 45268, "to": "mm"},
1988   "name": "SPI_SHADER_USER_ACCUM_PS_3",
1989   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
1990  },
1991  {
1992   "chips": ["gfx10"],
1993   "map": {"at": 45316, "to": "mm"},
1994   "name": "SPI_SHADER_PGM_RSRC4_VS",
1995   "type_ref": "SPI_SHADER_PGM_RSRC4_PS"
1996  },
1997  {
1998   "chips": ["gfx10"],
1999   "map": {"at": 45332, "to": "mm"},
2000   "name": "SPI_SHADER_PGM_CHKSUM_VS"
2001  },
2002  {
2003   "chips": ["gfx10"],
2004   "map": {"at": 45336, "to": "mm"},
2005   "name": "SPI_SHADER_PGM_RSRC3_VS",
2006   "type_ref": "SPI_SHADER_PGM_RSRC3_PS"
2007  },
2008  {
2009   "chips": ["gfx10"],
2010   "map": {"at": 45340, "to": "mm"},
2011   "name": "SPI_SHADER_LATE_ALLOC_VS",
2012   "type_ref": "SPI_SHADER_LATE_ALLOC_VS"
2013  },
2014  {
2015   "chips": ["gfx10"],
2016   "map": {"at": 45344, "to": "mm"},
2017   "name": "SPI_SHADER_PGM_LO_VS"
2018  },
2019  {
2020   "chips": ["gfx10"],
2021   "map": {"at": 45348, "to": "mm"},
2022   "name": "SPI_SHADER_PGM_HI_VS",
2023   "type_ref": "SPI_SHADER_PGM_HI_PS"
2024  },
2025  {
2026   "chips": ["gfx10"],
2027   "map": {"at": 45352, "to": "mm"},
2028   "name": "SPI_SHADER_PGM_RSRC1_VS",
2029   "type_ref": "SPI_SHADER_PGM_RSRC1_VS"
2030  },
2031  {
2032   "chips": ["gfx10"],
2033   "map": {"at": 45356, "to": "mm"},
2034   "name": "SPI_SHADER_PGM_RSRC2_VS",
2035   "type_ref": "SPI_SHADER_PGM_RSRC2_VS"
2036  },
2037  {
2038   "chips": ["gfx10"],
2039   "map": {"at": 45360, "to": "mm"},
2040   "name": "SPI_SHADER_USER_DATA_VS_0"
2041  },
2042  {
2043   "chips": ["gfx10"],
2044   "map": {"at": 45364, "to": "mm"},
2045   "name": "SPI_SHADER_USER_DATA_VS_1"
2046  },
2047  {
2048   "chips": ["gfx10"],
2049   "map": {"at": 45368, "to": "mm"},
2050   "name": "SPI_SHADER_USER_DATA_VS_2"
2051  },
2052  {
2053   "chips": ["gfx10"],
2054   "map": {"at": 45372, "to": "mm"},
2055   "name": "SPI_SHADER_USER_DATA_VS_3"
2056  },
2057  {
2058   "chips": ["gfx10"],
2059   "map": {"at": 45376, "to": "mm"},
2060   "name": "SPI_SHADER_USER_DATA_VS_4"
2061  },
2062  {
2063   "chips": ["gfx10"],
2064   "map": {"at": 45380, "to": "mm"},
2065   "name": "SPI_SHADER_USER_DATA_VS_5"
2066  },
2067  {
2068   "chips": ["gfx10"],
2069   "map": {"at": 45384, "to": "mm"},
2070   "name": "SPI_SHADER_USER_DATA_VS_6"
2071  },
2072  {
2073   "chips": ["gfx10"],
2074   "map": {"at": 45388, "to": "mm"},
2075   "name": "SPI_SHADER_USER_DATA_VS_7"
2076  },
2077  {
2078   "chips": ["gfx10"],
2079   "map": {"at": 45392, "to": "mm"},
2080   "name": "SPI_SHADER_USER_DATA_VS_8"
2081  },
2082  {
2083   "chips": ["gfx10"],
2084   "map": {"at": 45396, "to": "mm"},
2085   "name": "SPI_SHADER_USER_DATA_VS_9"
2086  },
2087  {
2088   "chips": ["gfx10"],
2089   "map": {"at": 45400, "to": "mm"},
2090   "name": "SPI_SHADER_USER_DATA_VS_10"
2091  },
2092  {
2093   "chips": ["gfx10"],
2094   "map": {"at": 45404, "to": "mm"},
2095   "name": "SPI_SHADER_USER_DATA_VS_11"
2096  },
2097  {
2098   "chips": ["gfx10"],
2099   "map": {"at": 45408, "to": "mm"},
2100   "name": "SPI_SHADER_USER_DATA_VS_12"
2101  },
2102  {
2103   "chips": ["gfx10"],
2104   "map": {"at": 45412, "to": "mm"},
2105   "name": "SPI_SHADER_USER_DATA_VS_13"
2106  },
2107  {
2108   "chips": ["gfx10"],
2109   "map": {"at": 45416, "to": "mm"},
2110   "name": "SPI_SHADER_USER_DATA_VS_14"
2111  },
2112  {
2113   "chips": ["gfx10"],
2114   "map": {"at": 45420, "to": "mm"},
2115   "name": "SPI_SHADER_USER_DATA_VS_15"
2116  },
2117  {
2118   "chips": ["gfx10"],
2119   "map": {"at": 45424, "to": "mm"},
2120   "name": "SPI_SHADER_USER_DATA_VS_16"
2121  },
2122  {
2123   "chips": ["gfx10"],
2124   "map": {"at": 45428, "to": "mm"},
2125   "name": "SPI_SHADER_USER_DATA_VS_17"
2126  },
2127  {
2128   "chips": ["gfx10"],
2129   "map": {"at": 45432, "to": "mm"},
2130   "name": "SPI_SHADER_USER_DATA_VS_18"
2131  },
2132  {
2133   "chips": ["gfx10"],
2134   "map": {"at": 45436, "to": "mm"},
2135   "name": "SPI_SHADER_USER_DATA_VS_19"
2136  },
2137  {
2138   "chips": ["gfx10"],
2139   "map": {"at": 45440, "to": "mm"},
2140   "name": "SPI_SHADER_USER_DATA_VS_20"
2141  },
2142  {
2143   "chips": ["gfx10"],
2144   "map": {"at": 45444, "to": "mm"},
2145   "name": "SPI_SHADER_USER_DATA_VS_21"
2146  },
2147  {
2148   "chips": ["gfx10"],
2149   "map": {"at": 45448, "to": "mm"},
2150   "name": "SPI_SHADER_USER_DATA_VS_22"
2151  },
2152  {
2153   "chips": ["gfx10"],
2154   "map": {"at": 45452, "to": "mm"},
2155   "name": "SPI_SHADER_USER_DATA_VS_23"
2156  },
2157  {
2158   "chips": ["gfx10"],
2159   "map": {"at": 45456, "to": "mm"},
2160   "name": "SPI_SHADER_USER_DATA_VS_24"
2161  },
2162  {
2163   "chips": ["gfx10"],
2164   "map": {"at": 45460, "to": "mm"},
2165   "name": "SPI_SHADER_USER_DATA_VS_25"
2166  },
2167  {
2168   "chips": ["gfx10"],
2169   "map": {"at": 45464, "to": "mm"},
2170   "name": "SPI_SHADER_USER_DATA_VS_26"
2171  },
2172  {
2173   "chips": ["gfx10"],
2174   "map": {"at": 45468, "to": "mm"},
2175   "name": "SPI_SHADER_USER_DATA_VS_27"
2176  },
2177  {
2178   "chips": ["gfx10"],
2179   "map": {"at": 45472, "to": "mm"},
2180   "name": "SPI_SHADER_USER_DATA_VS_28"
2181  },
2182  {
2183   "chips": ["gfx10"],
2184   "map": {"at": 45476, "to": "mm"},
2185   "name": "SPI_SHADER_USER_DATA_VS_29"
2186  },
2187  {
2188   "chips": ["gfx10"],
2189   "map": {"at": 45480, "to": "mm"},
2190   "name": "SPI_SHADER_USER_DATA_VS_30"
2191  },
2192  {
2193   "chips": ["gfx10"],
2194   "map": {"at": 45484, "to": "mm"},
2195   "name": "SPI_SHADER_USER_DATA_VS_31"
2196  },
2197  {
2198   "chips": ["gfx10"],
2199   "map": {"at": 45504, "to": "mm"},
2200   "name": "SPI_SHADER_REQ_CTRL_VS",
2201   "type_ref": "SPI_SHADER_REQ_CTRL_PS"
2202  },
2203  {
2204   "chips": ["gfx10"],
2205   "map": {"at": 45508, "to": "mm"},
2206   "name": "SPI_SHADER_PREF_PRI_CNTR_CTRL_VS",
2207   "type_ref": "SPI_SHADER_PREF_PRI_CNTR_CTRL_PS"
2208  },
2209  {
2210   "chips": ["gfx10"],
2211   "map": {"at": 45512, "to": "mm"},
2212   "name": "SPI_SHADER_USER_ACCUM_VS_0",
2213   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2214  },
2215  {
2216   "chips": ["gfx10"],
2217   "map": {"at": 45516, "to": "mm"},
2218   "name": "SPI_SHADER_USER_ACCUM_VS_1",
2219   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2220  },
2221  {
2222   "chips": ["gfx10"],
2223   "map": {"at": 45520, "to": "mm"},
2224   "name": "SPI_SHADER_USER_ACCUM_VS_2",
2225   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2226  },
2227  {
2228   "chips": ["gfx10"],
2229   "map": {"at": 45524, "to": "mm"},
2230   "name": "SPI_SHADER_USER_ACCUM_VS_3",
2231   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2232  },
2233  {
2234   "chips": ["gfx10"],
2235   "map": {"at": 45548, "to": "mm"},
2236   "name": "SPI_SHADER_PGM_RSRC2_GS_VS",
2237   "type_ref": "SPI_SHADER_PGM_RSRC2_GS_VS"
2238  },
2239  {
2240   "chips": ["gfx10"],
2241   "map": {"at": 45552, "to": "mm"},
2242   "name": "SPI_SHADER_PGM_RSRC2_ES_VS",
2243   "type_ref": "SPI_SHADER_PGM_RSRC2_ES_VS"
2244  },
2245  {
2246   "chips": ["gfx10"],
2247   "map": {"at": 45556, "to": "mm"},
2248   "name": "SPI_SHADER_PGM_RSRC2_LS_VS",
2249   "type_ref": "SPI_SHADER_PGM_RSRC2_LS_VS"
2250  },
2251  {
2252   "chips": ["gfx10"],
2253   "map": {"at": 45568, "to": "mm"},
2254   "name": "SPI_SHADER_PGM_CHKSUM_GS"
2255  },
2256  {
2257   "chips": ["gfx10"],
2258   "map": {"at": 45572, "to": "mm"},
2259   "name": "SPI_SHADER_PGM_RSRC4_GS",
2260   "type_ref": "SPI_SHADER_PGM_RSRC4_GS"
2261  },
2262  {
2263   "chips": ["gfx10"],
2264   "map": {"at": 45576, "to": "mm"},
2265   "name": "SPI_SHADER_USER_DATA_ADDR_LO_GS"
2266  },
2267  {
2268   "chips": ["gfx10"],
2269   "map": {"at": 45580, "to": "mm"},
2270   "name": "SPI_SHADER_USER_DATA_ADDR_HI_GS"
2271  },
2272  {
2273   "chips": ["gfx10"],
2274   "map": {"at": 45584, "to": "mm"},
2275   "name": "SPI_SHADER_PGM_LO_ES_GS"
2276  },
2277  {
2278   "chips": ["gfx10"],
2279   "map": {"at": 45588, "to": "mm"},
2280   "name": "SPI_SHADER_PGM_HI_ES_GS",
2281   "type_ref": "SPI_SHADER_PGM_HI_PS"
2282  },
2283  {
2284   "chips": ["gfx10"],
2285   "map": {"at": 45596, "to": "mm"},
2286   "name": "SPI_SHADER_PGM_RSRC3_GS",
2287   "type_ref": "SPI_SHADER_PGM_RSRC3_GS"
2288  },
2289  {
2290   "chips": ["gfx10"],
2291   "map": {"at": 45600, "to": "mm"},
2292   "name": "SPI_SHADER_PGM_LO_GS"
2293  },
2294  {
2295   "chips": ["gfx10"],
2296   "map": {"at": 45604, "to": "mm"},
2297   "name": "SPI_SHADER_PGM_HI_GS",
2298   "type_ref": "SPI_SHADER_PGM_HI_PS"
2299  },
2300  {
2301   "chips": ["gfx10"],
2302   "map": {"at": 45608, "to": "mm"},
2303   "name": "SPI_SHADER_PGM_RSRC1_GS",
2304   "type_ref": "SPI_SHADER_PGM_RSRC1_GS"
2305  },
2306  {
2307   "chips": ["gfx10"],
2308   "map": {"at": 45612, "to": "mm"},
2309   "name": "SPI_SHADER_PGM_RSRC2_GS",
2310   "type_ref": "SPI_SHADER_PGM_RSRC2_GS"
2311  },
2312  {
2313   "chips": ["gfx10"],
2314   "map": {"at": 45616, "to": "mm"},
2315   "name": "SPI_SHADER_USER_DATA_GS_0"
2316  },
2317  {
2318   "chips": ["gfx10"],
2319   "map": {"at": 45620, "to": "mm"},
2320   "name": "SPI_SHADER_USER_DATA_GS_1"
2321  },
2322  {
2323   "chips": ["gfx10"],
2324   "map": {"at": 45624, "to": "mm"},
2325   "name": "SPI_SHADER_USER_DATA_GS_2"
2326  },
2327  {
2328   "chips": ["gfx10"],
2329   "map": {"at": 45628, "to": "mm"},
2330   "name": "SPI_SHADER_USER_DATA_GS_3"
2331  },
2332  {
2333   "chips": ["gfx10"],
2334   "map": {"at": 45632, "to": "mm"},
2335   "name": "SPI_SHADER_USER_DATA_GS_4"
2336  },
2337  {
2338   "chips": ["gfx10"],
2339   "map": {"at": 45636, "to": "mm"},
2340   "name": "SPI_SHADER_USER_DATA_GS_5"
2341  },
2342  {
2343   "chips": ["gfx10"],
2344   "map": {"at": 45640, "to": "mm"},
2345   "name": "SPI_SHADER_USER_DATA_GS_6"
2346  },
2347  {
2348   "chips": ["gfx10"],
2349   "map": {"at": 45644, "to": "mm"},
2350   "name": "SPI_SHADER_USER_DATA_GS_7"
2351  },
2352  {
2353   "chips": ["gfx10"],
2354   "map": {"at": 45648, "to": "mm"},
2355   "name": "SPI_SHADER_USER_DATA_GS_8"
2356  },
2357  {
2358   "chips": ["gfx10"],
2359   "map": {"at": 45652, "to": "mm"},
2360   "name": "SPI_SHADER_USER_DATA_GS_9"
2361  },
2362  {
2363   "chips": ["gfx10"],
2364   "map": {"at": 45656, "to": "mm"},
2365   "name": "SPI_SHADER_USER_DATA_GS_10"
2366  },
2367  {
2368   "chips": ["gfx10"],
2369   "map": {"at": 45660, "to": "mm"},
2370   "name": "SPI_SHADER_USER_DATA_GS_11"
2371  },
2372  {
2373   "chips": ["gfx10"],
2374   "map": {"at": 45664, "to": "mm"},
2375   "name": "SPI_SHADER_USER_DATA_GS_12"
2376  },
2377  {
2378   "chips": ["gfx10"],
2379   "map": {"at": 45668, "to": "mm"},
2380   "name": "SPI_SHADER_USER_DATA_GS_13"
2381  },
2382  {
2383   "chips": ["gfx10"],
2384   "map": {"at": 45672, "to": "mm"},
2385   "name": "SPI_SHADER_USER_DATA_GS_14"
2386  },
2387  {
2388   "chips": ["gfx10"],
2389   "map": {"at": 45676, "to": "mm"},
2390   "name": "SPI_SHADER_USER_DATA_GS_15"
2391  },
2392  {
2393   "chips": ["gfx10"],
2394   "map": {"at": 45680, "to": "mm"},
2395   "name": "SPI_SHADER_USER_DATA_GS_16"
2396  },
2397  {
2398   "chips": ["gfx10"],
2399   "map": {"at": 45684, "to": "mm"},
2400   "name": "SPI_SHADER_USER_DATA_GS_17"
2401  },
2402  {
2403   "chips": ["gfx10"],
2404   "map": {"at": 45688, "to": "mm"},
2405   "name": "SPI_SHADER_USER_DATA_GS_18"
2406  },
2407  {
2408   "chips": ["gfx10"],
2409   "map": {"at": 45692, "to": "mm"},
2410   "name": "SPI_SHADER_USER_DATA_GS_19"
2411  },
2412  {
2413   "chips": ["gfx10"],
2414   "map": {"at": 45696, "to": "mm"},
2415   "name": "SPI_SHADER_USER_DATA_GS_20"
2416  },
2417  {
2418   "chips": ["gfx10"],
2419   "map": {"at": 45700, "to": "mm"},
2420   "name": "SPI_SHADER_USER_DATA_GS_21"
2421  },
2422  {
2423   "chips": ["gfx10"],
2424   "map": {"at": 45704, "to": "mm"},
2425   "name": "SPI_SHADER_USER_DATA_GS_22"
2426  },
2427  {
2428   "chips": ["gfx10"],
2429   "map": {"at": 45708, "to": "mm"},
2430   "name": "SPI_SHADER_USER_DATA_GS_23"
2431  },
2432  {
2433   "chips": ["gfx10"],
2434   "map": {"at": 45712, "to": "mm"},
2435   "name": "SPI_SHADER_USER_DATA_GS_24"
2436  },
2437  {
2438   "chips": ["gfx10"],
2439   "map": {"at": 45716, "to": "mm"},
2440   "name": "SPI_SHADER_USER_DATA_GS_25"
2441  },
2442  {
2443   "chips": ["gfx10"],
2444   "map": {"at": 45720, "to": "mm"},
2445   "name": "SPI_SHADER_USER_DATA_GS_26"
2446  },
2447  {
2448   "chips": ["gfx10"],
2449   "map": {"at": 45724, "to": "mm"},
2450   "name": "SPI_SHADER_USER_DATA_GS_27"
2451  },
2452  {
2453   "chips": ["gfx10"],
2454   "map": {"at": 45728, "to": "mm"},
2455   "name": "SPI_SHADER_USER_DATA_GS_28"
2456  },
2457  {
2458   "chips": ["gfx10"],
2459   "map": {"at": 45732, "to": "mm"},
2460   "name": "SPI_SHADER_USER_DATA_GS_29"
2461  },
2462  {
2463   "chips": ["gfx10"],
2464   "map": {"at": 45736, "to": "mm"},
2465   "name": "SPI_SHADER_USER_DATA_GS_30"
2466  },
2467  {
2468   "chips": ["gfx10"],
2469   "map": {"at": 45740, "to": "mm"},
2470   "name": "SPI_SHADER_USER_DATA_GS_31"
2471  },
2472  {
2473   "chips": ["gfx10"],
2474   "map": {"at": 45760, "to": "mm"},
2475   "name": "SPI_SHADER_REQ_CTRL_ESGS",
2476   "type_ref": "SPI_SHADER_REQ_CTRL_PS"
2477  },
2478  {
2479   "chips": ["gfx10"],
2480   "map": {"at": 45764, "to": "mm"},
2481   "name": "SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS",
2482   "type_ref": "SPI_SHADER_PREF_PRI_CNTR_CTRL_PS"
2483  },
2484  {
2485   "chips": ["gfx10"],
2486   "map": {"at": 45768, "to": "mm"},
2487   "name": "SPI_SHADER_USER_ACCUM_ESGS_0",
2488   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2489  },
2490  {
2491   "chips": ["gfx10"],
2492   "map": {"at": 45772, "to": "mm"},
2493   "name": "SPI_SHADER_USER_ACCUM_ESGS_1",
2494   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2495  },
2496  {
2497   "chips": ["gfx10"],
2498   "map": {"at": 45776, "to": "mm"},
2499   "name": "SPI_SHADER_USER_ACCUM_ESGS_2",
2500   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2501  },
2502  {
2503   "chips": ["gfx10"],
2504   "map": {"at": 45780, "to": "mm"},
2505   "name": "SPI_SHADER_USER_ACCUM_ESGS_3",
2506   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2507  },
2508  {
2509   "chips": ["gfx10"],
2510   "map": {"at": 45808, "to": "mm"},
2511   "name": "SPI_SHADER_PGM_RSRC2_ES_GS",
2512   "type_ref": "SPI_SHADER_PGM_RSRC2_ES_VS"
2513  },
2514  {
2515   "chips": ["gfx10"],
2516   "map": {"at": 45852, "to": "mm"},
2517   "name": "SPI_SHADER_PGM_RSRC3_ES",
2518   "type_ref": "SPI_SHADER_PGM_RSRC3_GS"
2519  },
2520  {
2521   "chips": ["gfx10"],
2522   "map": {"at": 45856, "to": "mm"},
2523   "name": "SPI_SHADER_PGM_LO_ES"
2524  },
2525  {
2526   "chips": ["gfx10"],
2527   "map": {"at": 45860, "to": "mm"},
2528   "name": "SPI_SHADER_PGM_HI_ES",
2529   "type_ref": "SPI_SHADER_PGM_HI_PS"
2530  },
2531  {
2532   "chips": ["gfx10"],
2533   "map": {"at": 45864, "to": "mm"},
2534   "name": "SPI_SHADER_PGM_RSRC1_ES",
2535   "type_ref": "SPI_SHADER_PGM_RSRC1_ES"
2536  },
2537  {
2538   "chips": ["gfx10"],
2539   "map": {"at": 45868, "to": "mm"},
2540   "name": "SPI_SHADER_PGM_RSRC2_ES",
2541   "type_ref": "SPI_SHADER_PGM_RSRC2_ES_VS"
2542  },
2543  {
2544   "chips": ["gfx10"],
2545   "map": {"at": 45872, "to": "mm"},
2546   "name": "SPI_SHADER_USER_DATA_ES_0"
2547  },
2548  {
2549   "chips": ["gfx10"],
2550   "map": {"at": 45876, "to": "mm"},
2551   "name": "SPI_SHADER_USER_DATA_ES_1"
2552  },
2553  {
2554   "chips": ["gfx10"],
2555   "map": {"at": 45880, "to": "mm"},
2556   "name": "SPI_SHADER_USER_DATA_ES_2"
2557  },
2558  {
2559   "chips": ["gfx10"],
2560   "map": {"at": 45884, "to": "mm"},
2561   "name": "SPI_SHADER_USER_DATA_ES_3"
2562  },
2563  {
2564   "chips": ["gfx10"],
2565   "map": {"at": 45888, "to": "mm"},
2566   "name": "SPI_SHADER_USER_DATA_ES_4"
2567  },
2568  {
2569   "chips": ["gfx10"],
2570   "map": {"at": 45892, "to": "mm"},
2571   "name": "SPI_SHADER_USER_DATA_ES_5"
2572  },
2573  {
2574   "chips": ["gfx10"],
2575   "map": {"at": 45896, "to": "mm"},
2576   "name": "SPI_SHADER_USER_DATA_ES_6"
2577  },
2578  {
2579   "chips": ["gfx10"],
2580   "map": {"at": 45900, "to": "mm"},
2581   "name": "SPI_SHADER_USER_DATA_ES_7"
2582  },
2583  {
2584   "chips": ["gfx10"],
2585   "map": {"at": 45904, "to": "mm"},
2586   "name": "SPI_SHADER_USER_DATA_ES_8"
2587  },
2588  {
2589   "chips": ["gfx10"],
2590   "map": {"at": 45908, "to": "mm"},
2591   "name": "SPI_SHADER_USER_DATA_ES_9"
2592  },
2593  {
2594   "chips": ["gfx10"],
2595   "map": {"at": 45912, "to": "mm"},
2596   "name": "SPI_SHADER_USER_DATA_ES_10"
2597  },
2598  {
2599   "chips": ["gfx10"],
2600   "map": {"at": 45916, "to": "mm"},
2601   "name": "SPI_SHADER_USER_DATA_ES_11"
2602  },
2603  {
2604   "chips": ["gfx10"],
2605   "map": {"at": 45920, "to": "mm"},
2606   "name": "SPI_SHADER_USER_DATA_ES_12"
2607  },
2608  {
2609   "chips": ["gfx10"],
2610   "map": {"at": 45924, "to": "mm"},
2611   "name": "SPI_SHADER_USER_DATA_ES_13"
2612  },
2613  {
2614   "chips": ["gfx10"],
2615   "map": {"at": 45928, "to": "mm"},
2616   "name": "SPI_SHADER_USER_DATA_ES_14"
2617  },
2618  {
2619   "chips": ["gfx10"],
2620   "map": {"at": 45932, "to": "mm"},
2621   "name": "SPI_SHADER_USER_DATA_ES_15"
2622  },
2623  {
2624   "chips": ["gfx10"],
2625   "map": {"at": 46068, "to": "mm"},
2626   "name": "SPI_SHADER_PGM_RSRC2_LS_ES",
2627   "type_ref": "SPI_SHADER_PGM_RSRC2_LS_VS"
2628  },
2629  {
2630   "chips": ["gfx10"],
2631   "map": {"at": 46080, "to": "mm"},
2632   "name": "SPI_SHADER_PGM_CHKSUM_HS"
2633  },
2634  {
2635   "chips": ["gfx10"],
2636   "map": {"at": 46084, "to": "mm"},
2637   "name": "SPI_SHADER_PGM_RSRC4_HS",
2638   "type_ref": "SPI_SHADER_PGM_RSRC4_PS"
2639  },
2640  {
2641   "chips": ["gfx10"],
2642   "map": {"at": 46088, "to": "mm"},
2643   "name": "SPI_SHADER_USER_DATA_ADDR_LO_HS"
2644  },
2645  {
2646   "chips": ["gfx10"],
2647   "map": {"at": 46092, "to": "mm"},
2648   "name": "SPI_SHADER_USER_DATA_ADDR_HI_HS"
2649  },
2650  {
2651   "chips": ["gfx10"],
2652   "map": {"at": 46096, "to": "mm"},
2653   "name": "SPI_SHADER_PGM_LO_LS_HS"
2654  },
2655  {
2656   "chips": ["gfx10"],
2657   "map": {"at": 46100, "to": "mm"},
2658   "name": "SPI_SHADER_PGM_HI_LS_HS",
2659   "type_ref": "SPI_SHADER_PGM_HI_PS"
2660  },
2661  {
2662   "chips": ["gfx10"],
2663   "map": {"at": 46108, "to": "mm"},
2664   "name": "SPI_SHADER_PGM_RSRC3_HS",
2665   "type_ref": "SPI_SHADER_PGM_RSRC3_HS"
2666  },
2667  {
2668   "chips": ["gfx10"],
2669   "map": {"at": 46112, "to": "mm"},
2670   "name": "SPI_SHADER_PGM_LO_HS"
2671  },
2672  {
2673   "chips": ["gfx10"],
2674   "map": {"at": 46116, "to": "mm"},
2675   "name": "SPI_SHADER_PGM_HI_HS",
2676   "type_ref": "SPI_SHADER_PGM_HI_PS"
2677  },
2678  {
2679   "chips": ["gfx10"],
2680   "map": {"at": 46120, "to": "mm"},
2681   "name": "SPI_SHADER_PGM_RSRC1_HS",
2682   "type_ref": "SPI_SHADER_PGM_RSRC1_HS"
2683  },
2684  {
2685   "chips": ["gfx10"],
2686   "map": {"at": 46124, "to": "mm"},
2687   "name": "SPI_SHADER_PGM_RSRC2_HS",
2688   "type_ref": "SPI_SHADER_PGM_RSRC2_HS"
2689  },
2690  {
2691   "chips": ["gfx10"],
2692   "map": {"at": 46128, "to": "mm"},
2693   "name": "SPI_SHADER_USER_DATA_HS_0"
2694  },
2695  {
2696   "chips": ["gfx10"],
2697   "map": {"at": 46132, "to": "mm"},
2698   "name": "SPI_SHADER_USER_DATA_HS_1"
2699  },
2700  {
2701   "chips": ["gfx10"],
2702   "map": {"at": 46136, "to": "mm"},
2703   "name": "SPI_SHADER_USER_DATA_HS_2"
2704  },
2705  {
2706   "chips": ["gfx10"],
2707   "map": {"at": 46140, "to": "mm"},
2708   "name": "SPI_SHADER_USER_DATA_HS_3"
2709  },
2710  {
2711   "chips": ["gfx10"],
2712   "map": {"at": 46144, "to": "mm"},
2713   "name": "SPI_SHADER_USER_DATA_HS_4"
2714  },
2715  {
2716   "chips": ["gfx10"],
2717   "map": {"at": 46148, "to": "mm"},
2718   "name": "SPI_SHADER_USER_DATA_HS_5"
2719  },
2720  {
2721   "chips": ["gfx10"],
2722   "map": {"at": 46152, "to": "mm"},
2723   "name": "SPI_SHADER_USER_DATA_HS_6"
2724  },
2725  {
2726   "chips": ["gfx10"],
2727   "map": {"at": 46156, "to": "mm"},
2728   "name": "SPI_SHADER_USER_DATA_HS_7"
2729  },
2730  {
2731   "chips": ["gfx10"],
2732   "map": {"at": 46160, "to": "mm"},
2733   "name": "SPI_SHADER_USER_DATA_HS_8"
2734  },
2735  {
2736   "chips": ["gfx10"],
2737   "map": {"at": 46164, "to": "mm"},
2738   "name": "SPI_SHADER_USER_DATA_HS_9"
2739  },
2740  {
2741   "chips": ["gfx10"],
2742   "map": {"at": 46168, "to": "mm"},
2743   "name": "SPI_SHADER_USER_DATA_HS_10"
2744  },
2745  {
2746   "chips": ["gfx10"],
2747   "map": {"at": 46172, "to": "mm"},
2748   "name": "SPI_SHADER_USER_DATA_HS_11"
2749  },
2750  {
2751   "chips": ["gfx10"],
2752   "map": {"at": 46176, "to": "mm"},
2753   "name": "SPI_SHADER_USER_DATA_HS_12"
2754  },
2755  {
2756   "chips": ["gfx10"],
2757   "map": {"at": 46180, "to": "mm"},
2758   "name": "SPI_SHADER_USER_DATA_HS_13"
2759  },
2760  {
2761   "chips": ["gfx10"],
2762   "map": {"at": 46184, "to": "mm"},
2763   "name": "SPI_SHADER_USER_DATA_HS_14"
2764  },
2765  {
2766   "chips": ["gfx10"],
2767   "map": {"at": 46188, "to": "mm"},
2768   "name": "SPI_SHADER_USER_DATA_HS_15"
2769  },
2770  {
2771   "chips": ["gfx10"],
2772   "map": {"at": 46192, "to": "mm"},
2773   "name": "SPI_SHADER_USER_DATA_HS_16"
2774  },
2775  {
2776   "chips": ["gfx10"],
2777   "map": {"at": 46196, "to": "mm"},
2778   "name": "SPI_SHADER_USER_DATA_HS_17"
2779  },
2780  {
2781   "chips": ["gfx10"],
2782   "map": {"at": 46200, "to": "mm"},
2783   "name": "SPI_SHADER_USER_DATA_HS_18"
2784  },
2785  {
2786   "chips": ["gfx10"],
2787   "map": {"at": 46204, "to": "mm"},
2788   "name": "SPI_SHADER_USER_DATA_HS_19"
2789  },
2790  {
2791   "chips": ["gfx10"],
2792   "map": {"at": 46208, "to": "mm"},
2793   "name": "SPI_SHADER_USER_DATA_HS_20"
2794  },
2795  {
2796   "chips": ["gfx10"],
2797   "map": {"at": 46212, "to": "mm"},
2798   "name": "SPI_SHADER_USER_DATA_HS_21"
2799  },
2800  {
2801   "chips": ["gfx10"],
2802   "map": {"at": 46216, "to": "mm"},
2803   "name": "SPI_SHADER_USER_DATA_HS_22"
2804  },
2805  {
2806   "chips": ["gfx10"],
2807   "map": {"at": 46220, "to": "mm"},
2808   "name": "SPI_SHADER_USER_DATA_HS_23"
2809  },
2810  {
2811   "chips": ["gfx10"],
2812   "map": {"at": 46224, "to": "mm"},
2813   "name": "SPI_SHADER_USER_DATA_HS_24"
2814  },
2815  {
2816   "chips": ["gfx10"],
2817   "map": {"at": 46228, "to": "mm"},
2818   "name": "SPI_SHADER_USER_DATA_HS_25"
2819  },
2820  {
2821   "chips": ["gfx10"],
2822   "map": {"at": 46232, "to": "mm"},
2823   "name": "SPI_SHADER_USER_DATA_HS_26"
2824  },
2825  {
2826   "chips": ["gfx10"],
2827   "map": {"at": 46236, "to": "mm"},
2828   "name": "SPI_SHADER_USER_DATA_HS_27"
2829  },
2830  {
2831   "chips": ["gfx10"],
2832   "map": {"at": 46240, "to": "mm"},
2833   "name": "SPI_SHADER_USER_DATA_HS_28"
2834  },
2835  {
2836   "chips": ["gfx10"],
2837   "map": {"at": 46244, "to": "mm"},
2838   "name": "SPI_SHADER_USER_DATA_HS_29"
2839  },
2840  {
2841   "chips": ["gfx10"],
2842   "map": {"at": 46248, "to": "mm"},
2843   "name": "SPI_SHADER_USER_DATA_HS_30"
2844  },
2845  {
2846   "chips": ["gfx10"],
2847   "map": {"at": 46252, "to": "mm"},
2848   "name": "SPI_SHADER_USER_DATA_HS_31"
2849  },
2850  {
2851   "chips": ["gfx10"],
2852   "map": {"at": 46272, "to": "mm"},
2853   "name": "SPI_SHADER_REQ_CTRL_LSHS",
2854   "type_ref": "SPI_SHADER_REQ_CTRL_PS"
2855  },
2856  {
2857   "chips": ["gfx10"],
2858   "map": {"at": 46276, "to": "mm"},
2859   "name": "SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS",
2860   "type_ref": "SPI_SHADER_PREF_PRI_CNTR_CTRL_PS"
2861  },
2862  {
2863   "chips": ["gfx10"],
2864   "map": {"at": 46280, "to": "mm"},
2865   "name": "SPI_SHADER_USER_ACCUM_LSHS_0",
2866   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2867  },
2868  {
2869   "chips": ["gfx10"],
2870   "map": {"at": 46284, "to": "mm"},
2871   "name": "SPI_SHADER_USER_ACCUM_LSHS_1",
2872   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2873  },
2874  {
2875   "chips": ["gfx10"],
2876   "map": {"at": 46288, "to": "mm"},
2877   "name": "SPI_SHADER_USER_ACCUM_LSHS_2",
2878   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2879  },
2880  {
2881   "chips": ["gfx10"],
2882   "map": {"at": 46292, "to": "mm"},
2883   "name": "SPI_SHADER_USER_ACCUM_LSHS_3",
2884   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2885  },
2886  {
2887   "chips": ["gfx10"],
2888   "map": {"at": 46324, "to": "mm"},
2889   "name": "SPI_SHADER_PGM_RSRC2_LS_HS",
2890   "type_ref": "SPI_SHADER_PGM_RSRC2_LS_VS"
2891  },
2892  {
2893   "chips": ["gfx10"],
2894   "map": {"at": 46364, "to": "mm"},
2895   "name": "SPI_SHADER_PGM_RSRC3_LS",
2896   "type_ref": "SPI_SHADER_PGM_RSRC3_GS"
2897  },
2898  {
2899   "chips": ["gfx10"],
2900   "map": {"at": 46368, "to": "mm"},
2901   "name": "SPI_SHADER_PGM_LO_LS"
2902  },
2903  {
2904   "chips": ["gfx10"],
2905   "map": {"at": 46372, "to": "mm"},
2906   "name": "SPI_SHADER_PGM_HI_LS",
2907   "type_ref": "SPI_SHADER_PGM_HI_PS"
2908  },
2909  {
2910   "chips": ["gfx10"],
2911   "map": {"at": 46376, "to": "mm"},
2912   "name": "SPI_SHADER_PGM_RSRC1_LS",
2913   "type_ref": "SPI_SHADER_PGM_RSRC1_LS"
2914  },
2915  {
2916   "chips": ["gfx10"],
2917   "map": {"at": 46380, "to": "mm"},
2918   "name": "SPI_SHADER_PGM_RSRC2_LS",
2919   "type_ref": "SPI_SHADER_PGM_RSRC2_LS_VS"
2920  },
2921  {
2922   "chips": ["gfx10"],
2923   "map": {"at": 46384, "to": "mm"},
2924   "name": "SPI_SHADER_USER_DATA_LS_0"
2925  },
2926  {
2927   "chips": ["gfx10"],
2928   "map": {"at": 46388, "to": "mm"},
2929   "name": "SPI_SHADER_USER_DATA_LS_1"
2930  },
2931  {
2932   "chips": ["gfx10"],
2933   "map": {"at": 46392, "to": "mm"},
2934   "name": "SPI_SHADER_USER_DATA_LS_2"
2935  },
2936  {
2937   "chips": ["gfx10"],
2938   "map": {"at": 46396, "to": "mm"},
2939   "name": "SPI_SHADER_USER_DATA_LS_3"
2940  },
2941  {
2942   "chips": ["gfx10"],
2943   "map": {"at": 46400, "to": "mm"},
2944   "name": "SPI_SHADER_USER_DATA_LS_4"
2945  },
2946  {
2947   "chips": ["gfx10"],
2948   "map": {"at": 46404, "to": "mm"},
2949   "name": "SPI_SHADER_USER_DATA_LS_5"
2950  },
2951  {
2952   "chips": ["gfx10"],
2953   "map": {"at": 46408, "to": "mm"},
2954   "name": "SPI_SHADER_USER_DATA_LS_6"
2955  },
2956  {
2957   "chips": ["gfx10"],
2958   "map": {"at": 46412, "to": "mm"},
2959   "name": "SPI_SHADER_USER_DATA_LS_7"
2960  },
2961  {
2962   "chips": ["gfx10"],
2963   "map": {"at": 46416, "to": "mm"},
2964   "name": "SPI_SHADER_USER_DATA_LS_8"
2965  },
2966  {
2967   "chips": ["gfx10"],
2968   "map": {"at": 46420, "to": "mm"},
2969   "name": "SPI_SHADER_USER_DATA_LS_9"
2970  },
2971  {
2972   "chips": ["gfx10"],
2973   "map": {"at": 46424, "to": "mm"},
2974   "name": "SPI_SHADER_USER_DATA_LS_10"
2975  },
2976  {
2977   "chips": ["gfx10"],
2978   "map": {"at": 46428, "to": "mm"},
2979   "name": "SPI_SHADER_USER_DATA_LS_11"
2980  },
2981  {
2982   "chips": ["gfx10"],
2983   "map": {"at": 46432, "to": "mm"},
2984   "name": "SPI_SHADER_USER_DATA_LS_12"
2985  },
2986  {
2987   "chips": ["gfx10"],
2988   "map": {"at": 46436, "to": "mm"},
2989   "name": "SPI_SHADER_USER_DATA_LS_13"
2990  },
2991  {
2992   "chips": ["gfx10"],
2993   "map": {"at": 46440, "to": "mm"},
2994   "name": "SPI_SHADER_USER_DATA_LS_14"
2995  },
2996  {
2997   "chips": ["gfx10"],
2998   "map": {"at": 46444, "to": "mm"},
2999   "name": "SPI_SHADER_USER_DATA_LS_15"
3000  },
3001  {
3002   "chips": ["gfx10"],
3003   "map": {"at": 47104, "to": "mm"},
3004   "name": "COMPUTE_DISPATCH_INITIATOR",
3005   "type_ref": "COMPUTE_DISPATCH_INITIATOR"
3006  },
3007  {
3008   "chips": ["gfx10"],
3009   "map": {"at": 47108, "to": "mm"},
3010   "name": "COMPUTE_DIM_X"
3011  },
3012  {
3013   "chips": ["gfx10"],
3014   "map": {"at": 47112, "to": "mm"},
3015   "name": "COMPUTE_DIM_Y"
3016  },
3017  {
3018   "chips": ["gfx10"],
3019   "map": {"at": 47116, "to": "mm"},
3020   "name": "COMPUTE_DIM_Z"
3021  },
3022  {
3023   "chips": ["gfx10"],
3024   "map": {"at": 47120, "to": "mm"},
3025   "name": "COMPUTE_START_X"
3026  },
3027  {
3028   "chips": ["gfx10"],
3029   "map": {"at": 47124, "to": "mm"},
3030   "name": "COMPUTE_START_Y"
3031  },
3032  {
3033   "chips": ["gfx10"],
3034   "map": {"at": 47128, "to": "mm"},
3035   "name": "COMPUTE_START_Z"
3036  },
3037  {
3038   "chips": ["gfx10"],
3039   "map": {"at": 47132, "to": "mm"},
3040   "name": "COMPUTE_NUM_THREAD_X",
3041   "type_ref": "COMPUTE_NUM_THREAD_X"
3042  },
3043  {
3044   "chips": ["gfx10"],
3045   "map": {"at": 47136, "to": "mm"},
3046   "name": "COMPUTE_NUM_THREAD_Y",
3047   "type_ref": "COMPUTE_NUM_THREAD_X"
3048  },
3049  {
3050   "chips": ["gfx10"],
3051   "map": {"at": 47140, "to": "mm"},
3052   "name": "COMPUTE_NUM_THREAD_Z",
3053   "type_ref": "COMPUTE_NUM_THREAD_X"
3054  },
3055  {
3056   "chips": ["gfx10"],
3057   "map": {"at": 47144, "to": "mm"},
3058   "name": "COMPUTE_PIPELINESTAT_ENABLE",
3059   "type_ref": "COMPUTE_PIPELINESTAT_ENABLE"
3060  },
3061  {
3062   "chips": ["gfx10"],
3063   "map": {"at": 47148, "to": "mm"},
3064   "name": "COMPUTE_PERFCOUNT_ENABLE",
3065   "type_ref": "COMPUTE_PERFCOUNT_ENABLE"
3066  },
3067  {
3068   "chips": ["gfx10"],
3069   "map": {"at": 47152, "to": "mm"},
3070   "name": "COMPUTE_PGM_LO"
3071  },
3072  {
3073   "chips": ["gfx10"],
3074   "map": {"at": 47156, "to": "mm"},
3075   "name": "COMPUTE_PGM_HI",
3076   "type_ref": "COMPUTE_PGM_HI"
3077  },
3078  {
3079   "chips": ["gfx10"],
3080   "map": {"at": 47160, "to": "mm"},
3081   "name": "COMPUTE_DISPATCH_PKT_ADDR_LO"
3082  },
3083  {
3084   "chips": ["gfx10"],
3085   "map": {"at": 47164, "to": "mm"},
3086   "name": "COMPUTE_DISPATCH_PKT_ADDR_HI",
3087   "type_ref": "COMPUTE_PGM_HI"
3088  },
3089  {
3090   "chips": ["gfx10"],
3091   "map": {"at": 47168, "to": "mm"},
3092   "name": "COMPUTE_DISPATCH_SCRATCH_BASE_LO"
3093  },
3094  {
3095   "chips": ["gfx10"],
3096   "map": {"at": 47172, "to": "mm"},
3097   "name": "COMPUTE_DISPATCH_SCRATCH_BASE_HI",
3098   "type_ref": "COMPUTE_PGM_HI"
3099  },
3100  {
3101   "chips": ["gfx10"],
3102   "map": {"at": 47176, "to": "mm"},
3103   "name": "COMPUTE_PGM_RSRC1",
3104   "type_ref": "COMPUTE_PGM_RSRC1"
3105  },
3106  {
3107   "chips": ["gfx10"],
3108   "map": {"at": 47180, "to": "mm"},
3109   "name": "COMPUTE_PGM_RSRC2",
3110   "type_ref": "COMPUTE_PGM_RSRC2"
3111  },
3112  {
3113   "chips": ["gfx10"],
3114   "map": {"at": 47184, "to": "mm"},
3115   "name": "COMPUTE_VMID",
3116   "type_ref": "COMPUTE_VMID"
3117  },
3118  {
3119   "chips": ["gfx10"],
3120   "map": {"at": 47188, "to": "mm"},
3121   "name": "COMPUTE_RESOURCE_LIMITS",
3122   "type_ref": "COMPUTE_RESOURCE_LIMITS"
3123  },
3124  {
3125   "chips": ["gfx10"],
3126   "map": {"at": 47192, "to": "mm"},
3127   "name": "COMPUTE_DESTINATION_EN_SE0"
3128  },
3129  {
3130   "chips": ["gfx10"],
3131   "map": {"at": 47196, "to": "mm"},
3132   "name": "COMPUTE_DESTINATION_EN_SE1"
3133  },
3134  {
3135   "chips": ["gfx10"],
3136   "map": {"at": 47200, "to": "mm"},
3137   "name": "COMPUTE_TMPRING_SIZE",
3138   "type_ref": "COMPUTE_TMPRING_SIZE"
3139  },
3140  {
3141   "chips": ["gfx10"],
3142   "map": {"at": 47204, "to": "mm"},
3143   "name": "COMPUTE_DESTINATION_EN_SE2"
3144  },
3145  {
3146   "chips": ["gfx10"],
3147   "map": {"at": 47208, "to": "mm"},
3148   "name": "COMPUTE_DESTINATION_EN_SE3"
3149  },
3150  {
3151   "chips": ["gfx10"],
3152   "map": {"at": 47212, "to": "mm"},
3153   "name": "COMPUTE_RESTART_X"
3154  },
3155  {
3156   "chips": ["gfx10"],
3157   "map": {"at": 47216, "to": "mm"},
3158   "name": "COMPUTE_RESTART_Y"
3159  },
3160  {
3161   "chips": ["gfx10"],
3162   "map": {"at": 47220, "to": "mm"},
3163   "name": "COMPUTE_RESTART_Z"
3164  },
3165  {
3166   "chips": ["gfx10"],
3167   "map": {"at": 47224, "to": "mm"},
3168   "name": "COMPUTE_THREAD_TRACE_ENABLE",
3169   "type_ref": "COMPUTE_THREAD_TRACE_ENABLE"
3170  },
3171  {
3172   "chips": ["gfx10"],
3173   "map": {"at": 47228, "to": "mm"},
3174   "name": "COMPUTE_MISC_RESERVED",
3175   "type_ref": "COMPUTE_MISC_RESERVED"
3176  },
3177  {
3178   "chips": ["gfx10"],
3179   "map": {"at": 47232, "to": "mm"},
3180   "name": "COMPUTE_DISPATCH_ID"
3181  },
3182  {
3183   "chips": ["gfx10"],
3184   "map": {"at": 47236, "to": "mm"},
3185   "name": "COMPUTE_THREADGROUP_ID"
3186  },
3187  {
3188   "chips": ["gfx10"],
3189   "map": {"at": 47240, "to": "mm"},
3190   "name": "COMPUTE_REQ_CTRL",
3191   "type_ref": "COMPUTE_REQ_CTRL"
3192  },
3193  {
3194   "chips": ["gfx10"],
3195   "map": {"at": 47248, "to": "mm"},
3196   "name": "COMPUTE_USER_ACCUM_0",
3197   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
3198  },
3199  {
3200   "chips": ["gfx10"],
3201   "map": {"at": 47252, "to": "mm"},
3202   "name": "COMPUTE_USER_ACCUM_1",
3203   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
3204  },
3205  {
3206   "chips": ["gfx10"],
3207   "map": {"at": 47256, "to": "mm"},
3208   "name": "COMPUTE_USER_ACCUM_2",
3209   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
3210  },
3211  {
3212   "chips": ["gfx10"],
3213   "map": {"at": 47260, "to": "mm"},
3214   "name": "COMPUTE_USER_ACCUM_3",
3215   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
3216  },
3217  {
3218   "chips": ["gfx10"],
3219   "map": {"at": 47264, "to": "mm"},
3220   "name": "COMPUTE_PGM_RSRC3",
3221   "type_ref": "COMPUTE_PGM_RSRC3"
3222  },
3223  {
3224   "chips": ["gfx10"],
3225   "map": {"at": 47268, "to": "mm"},
3226   "name": "COMPUTE_DDID_INDEX",
3227   "type_ref": "COMPUTE_DDID_INDEX"
3228  },
3229  {
3230   "chips": ["gfx10"],
3231   "map": {"at": 47272, "to": "mm"},
3232   "name": "COMPUTE_SHADER_CHKSUM"
3233  },
3234  {
3235   "chips": ["gfx10"],
3236   "map": {"at": 47276, "to": "mm"},
3237   "name": "COMPUTE_RELAUNCH",
3238   "type_ref": "COMPUTE_RELAUNCH"
3239  },
3240  {
3241   "chips": ["gfx10"],
3242   "map": {"at": 47280, "to": "mm"},
3243   "name": "COMPUTE_WAVE_RESTORE_ADDR_LO"
3244  },
3245  {
3246   "chips": ["gfx10"],
3247   "map": {"at": 47284, "to": "mm"},
3248   "name": "COMPUTE_WAVE_RESTORE_ADDR_HI",
3249   "type_ref": "COMPUTE_WAVE_RESTORE_ADDR_HI"
3250  },
3251  {
3252   "chips": ["gfx10"],
3253   "map": {"at": 47288, "to": "mm"},
3254   "name": "COMPUTE_RELAUNCH2",
3255   "type_ref": "COMPUTE_RELAUNCH"
3256  },
3257  {
3258   "chips": ["gfx10"],
3259   "map": {"at": 47360, "to": "mm"},
3260   "name": "COMPUTE_USER_DATA_0"
3261  },
3262  {
3263   "chips": ["gfx10"],
3264   "map": {"at": 47364, "to": "mm"},
3265   "name": "COMPUTE_USER_DATA_1"
3266  },
3267  {
3268   "chips": ["gfx10"],
3269   "map": {"at": 47368, "to": "mm"},
3270   "name": "COMPUTE_USER_DATA_2"
3271  },
3272  {
3273   "chips": ["gfx10"],
3274   "map": {"at": 47372, "to": "mm"},
3275   "name": "COMPUTE_USER_DATA_3"
3276  },
3277  {
3278   "chips": ["gfx10"],
3279   "map": {"at": 47376, "to": "mm"},
3280   "name": "COMPUTE_USER_DATA_4"
3281  },
3282  {
3283   "chips": ["gfx10"],
3284   "map": {"at": 47380, "to": "mm"},
3285   "name": "COMPUTE_USER_DATA_5"
3286  },
3287  {
3288   "chips": ["gfx10"],
3289   "map": {"at": 47384, "to": "mm"},
3290   "name": "COMPUTE_USER_DATA_6"
3291  },
3292  {
3293   "chips": ["gfx10"],
3294   "map": {"at": 47388, "to": "mm"},
3295   "name": "COMPUTE_USER_DATA_7"
3296  },
3297  {
3298   "chips": ["gfx10"],
3299   "map": {"at": 47392, "to": "mm"},
3300   "name": "COMPUTE_USER_DATA_8"
3301  },
3302  {
3303   "chips": ["gfx10"],
3304   "map": {"at": 47396, "to": "mm"},
3305   "name": "COMPUTE_USER_DATA_9"
3306  },
3307  {
3308   "chips": ["gfx10"],
3309   "map": {"at": 47400, "to": "mm"},
3310   "name": "COMPUTE_USER_DATA_10"
3311  },
3312  {
3313   "chips": ["gfx10"],
3314   "map": {"at": 47404, "to": "mm"},
3315   "name": "COMPUTE_USER_DATA_11"
3316  },
3317  {
3318   "chips": ["gfx10"],
3319   "map": {"at": 47408, "to": "mm"},
3320   "name": "COMPUTE_USER_DATA_12"
3321  },
3322  {
3323   "chips": ["gfx10"],
3324   "map": {"at": 47412, "to": "mm"},
3325   "name": "COMPUTE_USER_DATA_13"
3326  },
3327  {
3328   "chips": ["gfx10"],
3329   "map": {"at": 47416, "to": "mm"},
3330   "name": "COMPUTE_USER_DATA_14"
3331  },
3332  {
3333   "chips": ["gfx10"],
3334   "map": {"at": 47420, "to": "mm"},
3335   "name": "COMPUTE_USER_DATA_15"
3336  },
3337  {
3338   "chips": ["gfx10"],
3339   "map": {"at": 47604, "to": "mm"},
3340   "name": "COMPUTE_DISPATCH_TUNNEL",
3341   "type_ref": "COMPUTE_DISPATCH_TUNNEL"
3342  },
3343  {
3344   "chips": ["gfx10"],
3345   "map": {"at": 47608, "to": "mm"},
3346   "name": "COMPUTE_DISPATCH_END"
3347  },
3348  {
3349   "chips": ["gfx10"],
3350   "map": {"at": 47612, "to": "mm"},
3351   "name": "COMPUTE_NOWHERE"
3352  },
3353  {
3354   "chips": ["gfx10"],
3355   "map": {"at": 163840, "to": "mm"},
3356   "name": "DB_RENDER_CONTROL",
3357   "type_ref": "DB_RENDER_CONTROL"
3358  },
3359  {
3360   "chips": ["gfx10"],
3361   "map": {"at": 163844, "to": "mm"},
3362   "name": "DB_COUNT_CONTROL",
3363   "type_ref": "DB_COUNT_CONTROL"
3364  },
3365  {
3366   "chips": ["gfx10"],
3367   "map": {"at": 163848, "to": "mm"},
3368   "name": "DB_DEPTH_VIEW",
3369   "type_ref": "DB_DEPTH_VIEW"
3370  },
3371  {
3372   "chips": ["gfx10"],
3373   "map": {"at": 163852, "to": "mm"},
3374   "name": "DB_RENDER_OVERRIDE",
3375   "type_ref": "DB_RENDER_OVERRIDE"
3376  },
3377  {
3378   "chips": ["gfx10"],
3379   "map": {"at": 163856, "to": "mm"},
3380   "name": "DB_RENDER_OVERRIDE2",
3381   "type_ref": "DB_RENDER_OVERRIDE2"
3382  },
3383  {
3384   "chips": ["gfx10"],
3385   "map": {"at": 163860, "to": "mm"},
3386   "name": "DB_HTILE_DATA_BASE"
3387  },
3388  {
3389   "chips": ["gfx10"],
3390   "map": {"at": 163868, "to": "mm"},
3391   "name": "DB_DEPTH_SIZE_XY",
3392   "type_ref": "DB_DEPTH_SIZE_XY"
3393  },
3394  {
3395   "chips": ["gfx10"],
3396   "map": {"at": 163872, "to": "mm"},
3397   "name": "DB_DEPTH_BOUNDS_MIN"
3398  },
3399  {
3400   "chips": ["gfx10"],
3401   "map": {"at": 163876, "to": "mm"},
3402   "name": "DB_DEPTH_BOUNDS_MAX"
3403  },
3404  {
3405   "chips": ["gfx10"],
3406   "map": {"at": 163880, "to": "mm"},
3407   "name": "DB_STENCIL_CLEAR",
3408   "type_ref": "DB_STENCIL_CLEAR"
3409  },
3410  {
3411   "chips": ["gfx10"],
3412   "map": {"at": 163884, "to": "mm"},
3413   "name": "DB_DEPTH_CLEAR"
3414  },
3415  {
3416   "chips": ["gfx10"],
3417   "map": {"at": 163888, "to": "mm"},
3418   "name": "PA_SC_SCREEN_SCISSOR_TL",
3419   "type_ref": "PA_SC_SCREEN_SCISSOR_TL"
3420  },
3421  {
3422   "chips": ["gfx10"],
3423   "map": {"at": 163892, "to": "mm"},
3424   "name": "PA_SC_SCREEN_SCISSOR_BR",
3425   "type_ref": "PA_SC_SCREEN_SCISSOR_BR"
3426  },
3427  {
3428   "chips": ["gfx10"],
3429   "map": {"at": 163896, "to": "mm"},
3430   "name": "DB_DFSM_CONTROL",
3431   "type_ref": "DB_DFSM_CONTROL"
3432  },
3433  {
3434   "chips": ["gfx10"],
3435   "map": {"at": 163900, "to": "mm"},
3436   "name": "DB_RESERVED_REG_2",
3437   "type_ref": "DB_RESERVED_REG_2"
3438  },
3439  {
3440   "chips": ["gfx10"],
3441   "map": {"at": 163904, "to": "mm"},
3442   "name": "DB_Z_INFO",
3443   "type_ref": "DB_Z_INFO"
3444  },
3445  {
3446   "chips": ["gfx10"],
3447   "map": {"at": 163908, "to": "mm"},
3448   "name": "DB_STENCIL_INFO",
3449   "type_ref": "DB_STENCIL_INFO"
3450  },
3451  {
3452   "chips": ["gfx10"],
3453   "map": {"at": 163912, "to": "mm"},
3454   "name": "DB_Z_READ_BASE"
3455  },
3456  {
3457   "chips": ["gfx10"],
3458   "map": {"at": 163916, "to": "mm"},
3459   "name": "DB_STENCIL_READ_BASE"
3460  },
3461  {
3462   "chips": ["gfx10"],
3463   "map": {"at": 163920, "to": "mm"},
3464   "name": "DB_Z_WRITE_BASE"
3465  },
3466  {
3467   "chips": ["gfx10"],
3468   "map": {"at": 163924, "to": "mm"},
3469   "name": "DB_STENCIL_WRITE_BASE"
3470  },
3471  {
3472   "chips": ["gfx10"],
3473   "map": {"at": 163928, "to": "mm"},
3474   "name": "DB_RESERVED_REG_1",
3475   "type_ref": "DB_RESERVED_REG_1"
3476  },
3477  {
3478   "chips": ["gfx10"],
3479   "map": {"at": 163932, "to": "mm"},
3480   "name": "DB_RESERVED_REG_3",
3481   "type_ref": "DB_RESERVED_REG_3"
3482  },
3483  {
3484   "chips": ["gfx10"],
3485   "map": {"at": 163944, "to": "mm"},
3486   "name": "DB_Z_READ_BASE_HI",
3487   "type_ref": "DB_Z_READ_BASE_HI"
3488  },
3489  {
3490   "chips": ["gfx10"],
3491   "map": {"at": 163948, "to": "mm"},
3492   "name": "DB_STENCIL_READ_BASE_HI",
3493   "type_ref": "DB_Z_READ_BASE_HI"
3494  },
3495  {
3496   "chips": ["gfx10"],
3497   "map": {"at": 163952, "to": "mm"},
3498   "name": "DB_Z_WRITE_BASE_HI",
3499   "type_ref": "DB_Z_READ_BASE_HI"
3500  },
3501  {
3502   "chips": ["gfx10"],
3503   "map": {"at": 163956, "to": "mm"},
3504   "name": "DB_STENCIL_WRITE_BASE_HI",
3505   "type_ref": "DB_Z_READ_BASE_HI"
3506  },
3507  {
3508   "chips": ["gfx10"],
3509   "map": {"at": 163960, "to": "mm"},
3510   "name": "DB_HTILE_DATA_BASE_HI",
3511   "type_ref": "DB_Z_READ_BASE_HI"
3512  },
3513  {
3514   "chips": ["gfx10"],
3515   "map": {"at": 163964, "to": "mm"},
3516   "name": "DB_RMI_L2_CACHE_CONTROL",
3517   "type_ref": "DB_RMI_L2_CACHE_CONTROL"
3518  },
3519  {
3520   "chips": ["gfx10"],
3521   "map": {"at": 163968, "to": "mm"},
3522   "name": "TA_BC_BASE_ADDR"
3523  },
3524  {
3525   "chips": ["gfx10"],
3526   "map": {"at": 163972, "to": "mm"},
3527   "name": "TA_BC_BASE_ADDR_HI",
3528   "type_ref": "TA_BC_BASE_ADDR_HI"
3529  },
3530  {
3531   "chips": ["gfx10"],
3532   "map": {"at": 164328, "to": "mm"},
3533   "name": "COHER_DEST_BASE_HI_0",
3534   "type_ref": "COHER_DEST_BASE_HI_0"
3535  },
3536  {
3537   "chips": ["gfx10"],
3538   "map": {"at": 164332, "to": "mm"},
3539   "name": "COHER_DEST_BASE_HI_1",
3540   "type_ref": "COHER_DEST_BASE_HI_0"
3541  },
3542  {
3543   "chips": ["gfx10"],
3544   "map": {"at": 164336, "to": "mm"},
3545   "name": "COHER_DEST_BASE_HI_2",
3546   "type_ref": "COHER_DEST_BASE_HI_0"
3547  },
3548  {
3549   "chips": ["gfx10"],
3550   "map": {"at": 164340, "to": "mm"},
3551   "name": "COHER_DEST_BASE_HI_3",
3552   "type_ref": "COHER_DEST_BASE_HI_0"
3553  },
3554  {
3555   "chips": ["gfx10"],
3556   "map": {"at": 164344, "to": "mm"},
3557   "name": "COHER_DEST_BASE_2"
3558  },
3559  {
3560   "chips": ["gfx10"],
3561   "map": {"at": 164348, "to": "mm"},
3562   "name": "COHER_DEST_BASE_3"
3563  },
3564  {
3565   "chips": ["gfx10"],
3566   "map": {"at": 164352, "to": "mm"},
3567   "name": "PA_SC_WINDOW_OFFSET",
3568   "type_ref": "PA_SC_WINDOW_OFFSET"
3569  },
3570  {
3571   "chips": ["gfx10"],
3572   "map": {"at": 164356, "to": "mm"},
3573   "name": "PA_SC_WINDOW_SCISSOR_TL",
3574   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3575  },
3576  {
3577   "chips": ["gfx10"],
3578   "map": {"at": 164360, "to": "mm"},
3579   "name": "PA_SC_WINDOW_SCISSOR_BR",
3580   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3581  },
3582  {
3583   "chips": ["gfx10"],
3584   "map": {"at": 164364, "to": "mm"},
3585   "name": "PA_SC_CLIPRECT_RULE",
3586   "type_ref": "PA_SC_CLIPRECT_RULE"
3587  },
3588  {
3589   "chips": ["gfx10"],
3590   "map": {"at": 164368, "to": "mm"},
3591   "name": "PA_SC_CLIPRECT_0_TL",
3592   "type_ref": "PA_SC_CLIPRECT_0_TL"
3593  },
3594  {
3595   "chips": ["gfx10"],
3596   "map": {"at": 164372, "to": "mm"},
3597   "name": "PA_SC_CLIPRECT_0_BR",
3598   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3599  },
3600  {
3601   "chips": ["gfx10"],
3602   "map": {"at": 164376, "to": "mm"},
3603   "name": "PA_SC_CLIPRECT_1_TL",
3604   "type_ref": "PA_SC_CLIPRECT_0_TL"
3605  },
3606  {
3607   "chips": ["gfx10"],
3608   "map": {"at": 164380, "to": "mm"},
3609   "name": "PA_SC_CLIPRECT_1_BR",
3610   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3611  },
3612  {
3613   "chips": ["gfx10"],
3614   "map": {"at": 164384, "to": "mm"},
3615   "name": "PA_SC_CLIPRECT_2_TL",
3616   "type_ref": "PA_SC_CLIPRECT_0_TL"
3617  },
3618  {
3619   "chips": ["gfx10"],
3620   "map": {"at": 164388, "to": "mm"},
3621   "name": "PA_SC_CLIPRECT_2_BR",
3622   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3623  },
3624  {
3625   "chips": ["gfx10"],
3626   "map": {"at": 164392, "to": "mm"},
3627   "name": "PA_SC_CLIPRECT_3_TL",
3628   "type_ref": "PA_SC_CLIPRECT_0_TL"
3629  },
3630  {
3631   "chips": ["gfx10"],
3632   "map": {"at": 164396, "to": "mm"},
3633   "name": "PA_SC_CLIPRECT_3_BR",
3634   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3635  },
3636  {
3637   "chips": ["gfx10"],
3638   "map": {"at": 164400, "to": "mm"},
3639   "name": "PA_SC_EDGERULE",
3640   "type_ref": "PA_SC_EDGERULE"
3641  },
3642  {
3643   "chips": ["gfx10"],
3644   "map": {"at": 164404, "to": "mm"},
3645   "name": "PA_SU_HARDWARE_SCREEN_OFFSET",
3646   "type_ref": "PA_SU_HARDWARE_SCREEN_OFFSET"
3647  },
3648  {
3649   "chips": ["gfx10"],
3650   "map": {"at": 164408, "to": "mm"},
3651   "name": "CB_TARGET_MASK",
3652   "type_ref": "CB_TARGET_MASK"
3653  },
3654  {
3655   "chips": ["gfx10"],
3656   "map": {"at": 164412, "to": "mm"},
3657   "name": "CB_SHADER_MASK",
3658   "type_ref": "CB_SHADER_MASK"
3659  },
3660  {
3661   "chips": ["gfx10"],
3662   "map": {"at": 164416, "to": "mm"},
3663   "name": "PA_SC_GENERIC_SCISSOR_TL",
3664   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3665  },
3666  {
3667   "chips": ["gfx10"],
3668   "map": {"at": 164420, "to": "mm"},
3669   "name": "PA_SC_GENERIC_SCISSOR_BR",
3670   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3671  },
3672  {
3673   "chips": ["gfx10"],
3674   "map": {"at": 164424, "to": "mm"},
3675   "name": "COHER_DEST_BASE_0"
3676  },
3677  {
3678   "chips": ["gfx10"],
3679   "map": {"at": 164428, "to": "mm"},
3680   "name": "COHER_DEST_BASE_1"
3681  },
3682  {
3683   "chips": ["gfx10"],
3684   "map": {"at": 164432, "to": "mm"},
3685   "name": "PA_SC_VPORT_SCISSOR_0_TL",
3686   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3687  },
3688  {
3689   "chips": ["gfx10"],
3690   "map": {"at": 164436, "to": "mm"},
3691   "name": "PA_SC_VPORT_SCISSOR_0_BR",
3692   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3693  },
3694  {
3695   "chips": ["gfx10"],
3696   "map": {"at": 164440, "to": "mm"},
3697   "name": "PA_SC_VPORT_SCISSOR_1_TL",
3698   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3699  },
3700  {
3701   "chips": ["gfx10"],
3702   "map": {"at": 164444, "to": "mm"},
3703   "name": "PA_SC_VPORT_SCISSOR_1_BR",
3704   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3705  },
3706  {
3707   "chips": ["gfx10"],
3708   "map": {"at": 164448, "to": "mm"},
3709   "name": "PA_SC_VPORT_SCISSOR_2_TL",
3710   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3711  },
3712  {
3713   "chips": ["gfx10"],
3714   "map": {"at": 164452, "to": "mm"},
3715   "name": "PA_SC_VPORT_SCISSOR_2_BR",
3716   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3717  },
3718  {
3719   "chips": ["gfx10"],
3720   "map": {"at": 164456, "to": "mm"},
3721   "name": "PA_SC_VPORT_SCISSOR_3_TL",
3722   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3723  },
3724  {
3725   "chips": ["gfx10"],
3726   "map": {"at": 164460, "to": "mm"},
3727   "name": "PA_SC_VPORT_SCISSOR_3_BR",
3728   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3729  },
3730  {
3731   "chips": ["gfx10"],
3732   "map": {"at": 164464, "to": "mm"},
3733   "name": "PA_SC_VPORT_SCISSOR_4_TL",
3734   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3735  },
3736  {
3737   "chips": ["gfx10"],
3738   "map": {"at": 164468, "to": "mm"},
3739   "name": "PA_SC_VPORT_SCISSOR_4_BR",
3740   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3741  },
3742  {
3743   "chips": ["gfx10"],
3744   "map": {"at": 164472, "to": "mm"},
3745   "name": "PA_SC_VPORT_SCISSOR_5_TL",
3746   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3747  },
3748  {
3749   "chips": ["gfx10"],
3750   "map": {"at": 164476, "to": "mm"},
3751   "name": "PA_SC_VPORT_SCISSOR_5_BR",
3752   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3753  },
3754  {
3755   "chips": ["gfx10"],
3756   "map": {"at": 164480, "to": "mm"},
3757   "name": "PA_SC_VPORT_SCISSOR_6_TL",
3758   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3759  },
3760  {
3761   "chips": ["gfx10"],
3762   "map": {"at": 164484, "to": "mm"},
3763   "name": "PA_SC_VPORT_SCISSOR_6_BR",
3764   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3765  },
3766  {
3767   "chips": ["gfx10"],
3768   "map": {"at": 164488, "to": "mm"},
3769   "name": "PA_SC_VPORT_SCISSOR_7_TL",
3770   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3771  },
3772  {
3773   "chips": ["gfx10"],
3774   "map": {"at": 164492, "to": "mm"},
3775   "name": "PA_SC_VPORT_SCISSOR_7_BR",
3776   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3777  },
3778  {
3779   "chips": ["gfx10"],
3780   "map": {"at": 164496, "to": "mm"},
3781   "name": "PA_SC_VPORT_SCISSOR_8_TL",
3782   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3783  },
3784  {
3785   "chips": ["gfx10"],
3786   "map": {"at": 164500, "to": "mm"},
3787   "name": "PA_SC_VPORT_SCISSOR_8_BR",
3788   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3789  },
3790  {
3791   "chips": ["gfx10"],
3792   "map": {"at": 164504, "to": "mm"},
3793   "name": "PA_SC_VPORT_SCISSOR_9_TL",
3794   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3795  },
3796  {
3797   "chips": ["gfx10"],
3798   "map": {"at": 164508, "to": "mm"},
3799   "name": "PA_SC_VPORT_SCISSOR_9_BR",
3800   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3801  },
3802  {
3803   "chips": ["gfx10"],
3804   "map": {"at": 164512, "to": "mm"},
3805   "name": "PA_SC_VPORT_SCISSOR_10_TL",
3806   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3807  },
3808  {
3809   "chips": ["gfx10"],
3810   "map": {"at": 164516, "to": "mm"},
3811   "name": "PA_SC_VPORT_SCISSOR_10_BR",
3812   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3813  },
3814  {
3815   "chips": ["gfx10"],
3816   "map": {"at": 164520, "to": "mm"},
3817   "name": "PA_SC_VPORT_SCISSOR_11_TL",
3818   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3819  },
3820  {
3821   "chips": ["gfx10"],
3822   "map": {"at": 164524, "to": "mm"},
3823   "name": "PA_SC_VPORT_SCISSOR_11_BR",
3824   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3825  },
3826  {
3827   "chips": ["gfx10"],
3828   "map": {"at": 164528, "to": "mm"},
3829   "name": "PA_SC_VPORT_SCISSOR_12_TL",
3830   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3831  },
3832  {
3833   "chips": ["gfx10"],
3834   "map": {"at": 164532, "to": "mm"},
3835   "name": "PA_SC_VPORT_SCISSOR_12_BR",
3836   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3837  },
3838  {
3839   "chips": ["gfx10"],
3840   "map": {"at": 164536, "to": "mm"},
3841   "name": "PA_SC_VPORT_SCISSOR_13_TL",
3842   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3843  },
3844  {
3845   "chips": ["gfx10"],
3846   "map": {"at": 164540, "to": "mm"},
3847   "name": "PA_SC_VPORT_SCISSOR_13_BR",
3848   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3849  },
3850  {
3851   "chips": ["gfx10"],
3852   "map": {"at": 164544, "to": "mm"},
3853   "name": "PA_SC_VPORT_SCISSOR_14_TL",
3854   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3855  },
3856  {
3857   "chips": ["gfx10"],
3858   "map": {"at": 164548, "to": "mm"},
3859   "name": "PA_SC_VPORT_SCISSOR_14_BR",
3860   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3861  },
3862  {
3863   "chips": ["gfx10"],
3864   "map": {"at": 164552, "to": "mm"},
3865   "name": "PA_SC_VPORT_SCISSOR_15_TL",
3866   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3867  },
3868  {
3869   "chips": ["gfx10"],
3870   "map": {"at": 164556, "to": "mm"},
3871   "name": "PA_SC_VPORT_SCISSOR_15_BR",
3872   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3873  },
3874  {
3875   "chips": ["gfx10"],
3876   "map": {"at": 164560, "to": "mm"},
3877   "name": "PA_SC_VPORT_ZMIN_0"
3878  },
3879  {
3880   "chips": ["gfx10"],
3881   "map": {"at": 164564, "to": "mm"},
3882   "name": "PA_SC_VPORT_ZMAX_0"
3883  },
3884  {
3885   "chips": ["gfx10"],
3886   "map": {"at": 164568, "to": "mm"},
3887   "name": "PA_SC_VPORT_ZMIN_1"
3888  },
3889  {
3890   "chips": ["gfx10"],
3891   "map": {"at": 164572, "to": "mm"},
3892   "name": "PA_SC_VPORT_ZMAX_1"
3893  },
3894  {
3895   "chips": ["gfx10"],
3896   "map": {"at": 164576, "to": "mm"},
3897   "name": "PA_SC_VPORT_ZMIN_2"
3898  },
3899  {
3900   "chips": ["gfx10"],
3901   "map": {"at": 164580, "to": "mm"},
3902   "name": "PA_SC_VPORT_ZMAX_2"
3903  },
3904  {
3905   "chips": ["gfx10"],
3906   "map": {"at": 164584, "to": "mm"},
3907   "name": "PA_SC_VPORT_ZMIN_3"
3908  },
3909  {
3910   "chips": ["gfx10"],
3911   "map": {"at": 164588, "to": "mm"},
3912   "name": "PA_SC_VPORT_ZMAX_3"
3913  },
3914  {
3915   "chips": ["gfx10"],
3916   "map": {"at": 164592, "to": "mm"},
3917   "name": "PA_SC_VPORT_ZMIN_4"
3918  },
3919  {
3920   "chips": ["gfx10"],
3921   "map": {"at": 164596, "to": "mm"},
3922   "name": "PA_SC_VPORT_ZMAX_4"
3923  },
3924  {
3925   "chips": ["gfx10"],
3926   "map": {"at": 164600, "to": "mm"},
3927   "name": "PA_SC_VPORT_ZMIN_5"
3928  },
3929  {
3930   "chips": ["gfx10"],
3931   "map": {"at": 164604, "to": "mm"},
3932   "name": "PA_SC_VPORT_ZMAX_5"
3933  },
3934  {
3935   "chips": ["gfx10"],
3936   "map": {"at": 164608, "to": "mm"},
3937   "name": "PA_SC_VPORT_ZMIN_6"
3938  },
3939  {
3940   "chips": ["gfx10"],
3941   "map": {"at": 164612, "to": "mm"},
3942   "name": "PA_SC_VPORT_ZMAX_6"
3943  },
3944  {
3945   "chips": ["gfx10"],
3946   "map": {"at": 164616, "to": "mm"},
3947   "name": "PA_SC_VPORT_ZMIN_7"
3948  },
3949  {
3950   "chips": ["gfx10"],
3951   "map": {"at": 164620, "to": "mm"},
3952   "name": "PA_SC_VPORT_ZMAX_7"
3953  },
3954  {
3955   "chips": ["gfx10"],
3956   "map": {"at": 164624, "to": "mm"},
3957   "name": "PA_SC_VPORT_ZMIN_8"
3958  },
3959  {
3960   "chips": ["gfx10"],
3961   "map": {"at": 164628, "to": "mm"},
3962   "name": "PA_SC_VPORT_ZMAX_8"
3963  },
3964  {
3965   "chips": ["gfx10"],
3966   "map": {"at": 164632, "to": "mm"},
3967   "name": "PA_SC_VPORT_ZMIN_9"
3968  },
3969  {
3970   "chips": ["gfx10"],
3971   "map": {"at": 164636, "to": "mm"},
3972   "name": "PA_SC_VPORT_ZMAX_9"
3973  },
3974  {
3975   "chips": ["gfx10"],
3976   "map": {"at": 164640, "to": "mm"},
3977   "name": "PA_SC_VPORT_ZMIN_10"
3978  },
3979  {
3980   "chips": ["gfx10"],
3981   "map": {"at": 164644, "to": "mm"},
3982   "name": "PA_SC_VPORT_ZMAX_10"
3983  },
3984  {
3985   "chips": ["gfx10"],
3986   "map": {"at": 164648, "to": "mm"},
3987   "name": "PA_SC_VPORT_ZMIN_11"
3988  },
3989  {
3990   "chips": ["gfx10"],
3991   "map": {"at": 164652, "to": "mm"},
3992   "name": "PA_SC_VPORT_ZMAX_11"
3993  },
3994  {
3995   "chips": ["gfx10"],
3996   "map": {"at": 164656, "to": "mm"},
3997   "name": "PA_SC_VPORT_ZMIN_12"
3998  },
3999  {
4000   "chips": ["gfx10"],
4001   "map": {"at": 164660, "to": "mm"},
4002   "name": "PA_SC_VPORT_ZMAX_12"
4003  },
4004  {
4005   "chips": ["gfx10"],
4006   "map": {"at": 164664, "to": "mm"},
4007   "name": "PA_SC_VPORT_ZMIN_13"
4008  },
4009  {
4010   "chips": ["gfx10"],
4011   "map": {"at": 164668, "to": "mm"},
4012   "name": "PA_SC_VPORT_ZMAX_13"
4013  },
4014  {
4015   "chips": ["gfx10"],
4016   "map": {"at": 164672, "to": "mm"},
4017   "name": "PA_SC_VPORT_ZMIN_14"
4018  },
4019  {
4020   "chips": ["gfx10"],
4021   "map": {"at": 164676, "to": "mm"},
4022   "name": "PA_SC_VPORT_ZMAX_14"
4023  },
4024  {
4025   "chips": ["gfx10"],
4026   "map": {"at": 164680, "to": "mm"},
4027   "name": "PA_SC_VPORT_ZMIN_15"
4028  },
4029  {
4030   "chips": ["gfx10"],
4031   "map": {"at": 164684, "to": "mm"},
4032   "name": "PA_SC_VPORT_ZMAX_15"
4033  },
4034  {
4035   "chips": ["gfx10"],
4036   "map": {"at": 164688, "to": "mm"},
4037   "name": "PA_SC_RASTER_CONFIG",
4038   "type_ref": "PA_SC_RASTER_CONFIG"
4039  },
4040  {
4041   "chips": ["gfx10"],
4042   "map": {"at": 164692, "to": "mm"},
4043   "name": "PA_SC_RASTER_CONFIG_1",
4044   "type_ref": "PA_SC_RASTER_CONFIG_1"
4045  },
4046  {
4047   "chips": ["gfx10"],
4048   "map": {"at": 164696, "to": "mm"},
4049   "name": "PA_SC_SCREEN_EXTENT_CONTROL",
4050   "type_ref": "PA_SC_SCREEN_EXTENT_CONTROL"
4051  },
4052  {
4053   "chips": ["gfx10"],
4054   "map": {"at": 164700, "to": "mm"},
4055   "name": "PA_SC_TILE_STEERING_OVERRIDE",
4056   "type_ref": "PA_SC_TILE_STEERING_OVERRIDE"
4057  },
4058  {
4059   "chips": ["gfx10"],
4060   "map": {"at": 164704, "to": "mm"},
4061   "name": "CP_PERFMON_CNTX_CNTL",
4062   "type_ref": "CP_PERFMON_CNTX_CNTL"
4063  },
4064  {
4065   "chips": ["gfx10"],
4066   "map": {"at": 164708, "to": "mm"},
4067   "name": "CP_PIPEID",
4068   "type_ref": "CP_PIPEID"
4069  },
4070  {
4071   "chips": ["gfx10"],
4072   "map": {"at": 164712, "to": "mm"},
4073   "name": "CP_VMID",
4074   "type_ref": "CP_VMID"
4075  },
4076  {
4077   "chips": ["gfx10"],
4078   "map": {"at": 164768, "to": "mm"},
4079   "name": "PA_SC_RIGHT_VERT_GRID",
4080   "type_ref": "PA_SC_RIGHT_VERT_GRID"
4081  },
4082  {
4083   "chips": ["gfx10"],
4084   "map": {"at": 164772, "to": "mm"},
4085   "name": "PA_SC_LEFT_VERT_GRID",
4086   "type_ref": "PA_SC_RIGHT_VERT_GRID"
4087  },
4088  {
4089   "chips": ["gfx10"],
4090   "map": {"at": 164776, "to": "mm"},
4091   "name": "PA_SC_HORIZ_GRID",
4092   "type_ref": "PA_SC_HORIZ_GRID"
4093  },
4094  {
4095   "chips": ["gfx10"],
4096   "map": {"at": 164864, "to": "mm"},
4097   "name": "VGT_MAX_VTX_INDX"
4098  },
4099  {
4100   "chips": ["gfx10"],
4101   "map": {"at": 164868, "to": "mm"},
4102   "name": "VGT_MIN_VTX_INDX"
4103  },
4104  {
4105   "chips": ["gfx10"],
4106   "map": {"at": 164872, "to": "mm"},
4107   "name": "VGT_INDX_OFFSET"
4108  },
4109  {
4110   "chips": ["gfx10"],
4111   "map": {"at": 164876, "to": "mm"},
4112   "name": "VGT_MULTI_PRIM_IB_RESET_INDX"
4113  },
4114  {
4115   "chips": ["gfx10"],
4116   "map": {"at": 164880, "to": "mm"},
4117   "name": "CB_RMI_GL2_CACHE_CONTROL",
4118   "type_ref": "CB_RMI_GL2_CACHE_CONTROL"
4119  },
4120  {
4121   "chips": ["gfx10"],
4122   "map": {"at": 164884, "to": "mm"},
4123   "name": "CB_BLEND_RED"
4124  },
4125  {
4126   "chips": ["gfx10"],
4127   "map": {"at": 164888, "to": "mm"},
4128   "name": "CB_BLEND_GREEN"
4129  },
4130  {
4131   "chips": ["gfx10"],
4132   "map": {"at": 164892, "to": "mm"},
4133   "name": "CB_BLEND_BLUE"
4134  },
4135  {
4136   "chips": ["gfx10"],
4137   "map": {"at": 164896, "to": "mm"},
4138   "name": "CB_BLEND_ALPHA"
4139  },
4140  {
4141   "chips": ["gfx10"],
4142   "map": {"at": 164900, "to": "mm"},
4143   "name": "CB_DCC_CONTROL",
4144   "type_ref": "CB_DCC_CONTROL"
4145  },
4146  {
4147   "chips": ["gfx10"],
4148   "map": {"at": 164904, "to": "mm"},
4149   "name": "CB_COVERAGE_OUT_CONTROL",
4150   "type_ref": "CB_COVERAGE_OUT_CONTROL"
4151  },
4152  {
4153   "chips": ["gfx10"],
4154   "map": {"at": 164908, "to": "mm"},
4155   "name": "DB_STENCIL_CONTROL",
4156   "type_ref": "DB_STENCIL_CONTROL"
4157  },
4158  {
4159   "chips": ["gfx10"],
4160   "map": {"at": 164912, "to": "mm"},
4161   "name": "DB_STENCILREFMASK",
4162   "type_ref": "DB_STENCILREFMASK"
4163  },
4164  {
4165   "chips": ["gfx10"],
4166   "map": {"at": 164916, "to": "mm"},
4167   "name": "DB_STENCILREFMASK_BF",
4168   "type_ref": "DB_STENCILREFMASK_BF"
4169  },
4170  {
4171   "chips": ["gfx10"],
4172   "map": {"at": 164924, "to": "mm"},
4173   "name": "PA_CL_VPORT_XSCALE"
4174  },
4175  {
4176   "chips": ["gfx10"],
4177   "map": {"at": 164928, "to": "mm"},
4178   "name": "PA_CL_VPORT_XOFFSET"
4179  },
4180  {
4181   "chips": ["gfx10"],
4182   "map": {"at": 164932, "to": "mm"},
4183   "name": "PA_CL_VPORT_YSCALE"
4184  },
4185  {
4186   "chips": ["gfx10"],
4187   "map": {"at": 164936, "to": "mm"},
4188   "name": "PA_CL_VPORT_YOFFSET"
4189  },
4190  {
4191   "chips": ["gfx10"],
4192   "map": {"at": 164940, "to": "mm"},
4193   "name": "PA_CL_VPORT_ZSCALE"
4194  },
4195  {
4196   "chips": ["gfx10"],
4197   "map": {"at": 164944, "to": "mm"},
4198   "name": "PA_CL_VPORT_ZOFFSET"
4199  },
4200  {
4201   "chips": ["gfx10"],
4202   "map": {"at": 164948, "to": "mm"},
4203   "name": "PA_CL_VPORT_XSCALE_1"
4204  },
4205  {
4206   "chips": ["gfx10"],
4207   "map": {"at": 164952, "to": "mm"},
4208   "name": "PA_CL_VPORT_XOFFSET_1"
4209  },
4210  {
4211   "chips": ["gfx10"],
4212   "map": {"at": 164956, "to": "mm"},
4213   "name": "PA_CL_VPORT_YSCALE_1"
4214  },
4215  {
4216   "chips": ["gfx10"],
4217   "map": {"at": 164960, "to": "mm"},
4218   "name": "PA_CL_VPORT_YOFFSET_1"
4219  },
4220  {
4221   "chips": ["gfx10"],
4222   "map": {"at": 164964, "to": "mm"},
4223   "name": "PA_CL_VPORT_ZSCALE_1"
4224  },
4225  {
4226   "chips": ["gfx10"],
4227   "map": {"at": 164968, "to": "mm"},
4228   "name": "PA_CL_VPORT_ZOFFSET_1"
4229  },
4230  {
4231   "chips": ["gfx10"],
4232   "map": {"at": 164972, "to": "mm"},
4233   "name": "PA_CL_VPORT_XSCALE_2"
4234  },
4235  {
4236   "chips": ["gfx10"],
4237   "map": {"at": 164976, "to": "mm"},
4238   "name": "PA_CL_VPORT_XOFFSET_2"
4239  },
4240  {
4241   "chips": ["gfx10"],
4242   "map": {"at": 164980, "to": "mm"},
4243   "name": "PA_CL_VPORT_YSCALE_2"
4244  },
4245  {
4246   "chips": ["gfx10"],
4247   "map": {"at": 164984, "to": "mm"},
4248   "name": "PA_CL_VPORT_YOFFSET_2"
4249  },
4250  {
4251   "chips": ["gfx10"],
4252   "map": {"at": 164988, "to": "mm"},
4253   "name": "PA_CL_VPORT_ZSCALE_2"
4254  },
4255  {
4256   "chips": ["gfx10"],
4257   "map": {"at": 164992, "to": "mm"},
4258   "name": "PA_CL_VPORT_ZOFFSET_2"
4259  },
4260  {
4261   "chips": ["gfx10"],
4262   "map": {"at": 164996, "to": "mm"},
4263   "name": "PA_CL_VPORT_XSCALE_3"
4264  },
4265  {
4266   "chips": ["gfx10"],
4267   "map": {"at": 165000, "to": "mm"},
4268   "name": "PA_CL_VPORT_XOFFSET_3"
4269  },
4270  {
4271   "chips": ["gfx10"],
4272   "map": {"at": 165004, "to": "mm"},
4273   "name": "PA_CL_VPORT_YSCALE_3"
4274  },
4275  {
4276   "chips": ["gfx10"],
4277   "map": {"at": 165008, "to": "mm"},
4278   "name": "PA_CL_VPORT_YOFFSET_3"
4279  },
4280  {
4281   "chips": ["gfx10"],
4282   "map": {"at": 165012, "to": "mm"},
4283   "name": "PA_CL_VPORT_ZSCALE_3"
4284  },
4285  {
4286   "chips": ["gfx10"],
4287   "map": {"at": 165016, "to": "mm"},
4288   "name": "PA_CL_VPORT_ZOFFSET_3"
4289  },
4290  {
4291   "chips": ["gfx10"],
4292   "map": {"at": 165020, "to": "mm"},
4293   "name": "PA_CL_VPORT_XSCALE_4"
4294  },
4295  {
4296   "chips": ["gfx10"],
4297   "map": {"at": 165024, "to": "mm"},
4298   "name": "PA_CL_VPORT_XOFFSET_4"
4299  },
4300  {
4301   "chips": ["gfx10"],
4302   "map": {"at": 165028, "to": "mm"},
4303   "name": "PA_CL_VPORT_YSCALE_4"
4304  },
4305  {
4306   "chips": ["gfx10"],
4307   "map": {"at": 165032, "to": "mm"},
4308   "name": "PA_CL_VPORT_YOFFSET_4"
4309  },
4310  {
4311   "chips": ["gfx10"],
4312   "map": {"at": 165036, "to": "mm"},
4313   "name": "PA_CL_VPORT_ZSCALE_4"
4314  },
4315  {
4316   "chips": ["gfx10"],
4317   "map": {"at": 165040, "to": "mm"},
4318   "name": "PA_CL_VPORT_ZOFFSET_4"
4319  },
4320  {
4321   "chips": ["gfx10"],
4322   "map": {"at": 165044, "to": "mm"},
4323   "name": "PA_CL_VPORT_XSCALE_5"
4324  },
4325  {
4326   "chips": ["gfx10"],
4327   "map": {"at": 165048, "to": "mm"},
4328   "name": "PA_CL_VPORT_XOFFSET_5"
4329  },
4330  {
4331   "chips": ["gfx10"],
4332   "map": {"at": 165052, "to": "mm"},
4333   "name": "PA_CL_VPORT_YSCALE_5"
4334  },
4335  {
4336   "chips": ["gfx10"],
4337   "map": {"at": 165056, "to": "mm"},
4338   "name": "PA_CL_VPORT_YOFFSET_5"
4339  },
4340  {
4341   "chips": ["gfx10"],
4342   "map": {"at": 165060, "to": "mm"},
4343   "name": "PA_CL_VPORT_ZSCALE_5"
4344  },
4345  {
4346   "chips": ["gfx10"],
4347   "map": {"at": 165064, "to": "mm"},
4348   "name": "PA_CL_VPORT_ZOFFSET_5"
4349  },
4350  {
4351   "chips": ["gfx10"],
4352   "map": {"at": 165068, "to": "mm"},
4353   "name": "PA_CL_VPORT_XSCALE_6"
4354  },
4355  {
4356   "chips": ["gfx10"],
4357   "map": {"at": 165072, "to": "mm"},
4358   "name": "PA_CL_VPORT_XOFFSET_6"
4359  },
4360  {
4361   "chips": ["gfx10"],
4362   "map": {"at": 165076, "to": "mm"},
4363   "name": "PA_CL_VPORT_YSCALE_6"
4364  },
4365  {
4366   "chips": ["gfx10"],
4367   "map": {"at": 165080, "to": "mm"},
4368   "name": "PA_CL_VPORT_YOFFSET_6"
4369  },
4370  {
4371   "chips": ["gfx10"],
4372   "map": {"at": 165084, "to": "mm"},
4373   "name": "PA_CL_VPORT_ZSCALE_6"
4374  },
4375  {
4376   "chips": ["gfx10"],
4377   "map": {"at": 165088, "to": "mm"},
4378   "name": "PA_CL_VPORT_ZOFFSET_6"
4379  },
4380  {
4381   "chips": ["gfx10"],
4382   "map": {"at": 165092, "to": "mm"},
4383   "name": "PA_CL_VPORT_XSCALE_7"
4384  },
4385  {
4386   "chips": ["gfx10"],
4387   "map": {"at": 165096, "to": "mm"},
4388   "name": "PA_CL_VPORT_XOFFSET_7"
4389  },
4390  {
4391   "chips": ["gfx10"],
4392   "map": {"at": 165100, "to": "mm"},
4393   "name": "PA_CL_VPORT_YSCALE_7"
4394  },
4395  {
4396   "chips": ["gfx10"],
4397   "map": {"at": 165104, "to": "mm"},
4398   "name": "PA_CL_VPORT_YOFFSET_7"
4399  },
4400  {
4401   "chips": ["gfx10"],
4402   "map": {"at": 165108, "to": "mm"},
4403   "name": "PA_CL_VPORT_ZSCALE_7"
4404  },
4405  {
4406   "chips": ["gfx10"],
4407   "map": {"at": 165112, "to": "mm"},
4408   "name": "PA_CL_VPORT_ZOFFSET_7"
4409  },
4410  {
4411   "chips": ["gfx10"],
4412   "map": {"at": 165116, "to": "mm"},
4413   "name": "PA_CL_VPORT_XSCALE_8"
4414  },
4415  {
4416   "chips": ["gfx10"],
4417   "map": {"at": 165120, "to": "mm"},
4418   "name": "PA_CL_VPORT_XOFFSET_8"
4419  },
4420  {
4421   "chips": ["gfx10"],
4422   "map": {"at": 165124, "to": "mm"},
4423   "name": "PA_CL_VPORT_YSCALE_8"
4424  },
4425  {
4426   "chips": ["gfx10"],
4427   "map": {"at": 165128, "to": "mm"},
4428   "name": "PA_CL_VPORT_YOFFSET_8"
4429  },
4430  {
4431   "chips": ["gfx10"],
4432   "map": {"at": 165132, "to": "mm"},
4433   "name": "PA_CL_VPORT_ZSCALE_8"
4434  },
4435  {
4436   "chips": ["gfx10"],
4437   "map": {"at": 165136, "to": "mm"},
4438   "name": "PA_CL_VPORT_ZOFFSET_8"
4439  },
4440  {
4441   "chips": ["gfx10"],
4442   "map": {"at": 165140, "to": "mm"},
4443   "name": "PA_CL_VPORT_XSCALE_9"
4444  },
4445  {
4446   "chips": ["gfx10"],
4447   "map": {"at": 165144, "to": "mm"},
4448   "name": "PA_CL_VPORT_XOFFSET_9"
4449  },
4450  {
4451   "chips": ["gfx10"],
4452   "map": {"at": 165148, "to": "mm"},
4453   "name": "PA_CL_VPORT_YSCALE_9"
4454  },
4455  {
4456   "chips": ["gfx10"],
4457   "map": {"at": 165152, "to": "mm"},
4458   "name": "PA_CL_VPORT_YOFFSET_9"
4459  },
4460  {
4461   "chips": ["gfx10"],
4462   "map": {"at": 165156, "to": "mm"},
4463   "name": "PA_CL_VPORT_ZSCALE_9"
4464  },
4465  {
4466   "chips": ["gfx10"],
4467   "map": {"at": 165160, "to": "mm"},
4468   "name": "PA_CL_VPORT_ZOFFSET_9"
4469  },
4470  {
4471   "chips": ["gfx10"],
4472   "map": {"at": 165164, "to": "mm"},
4473   "name": "PA_CL_VPORT_XSCALE_10"
4474  },
4475  {
4476   "chips": ["gfx10"],
4477   "map": {"at": 165168, "to": "mm"},
4478   "name": "PA_CL_VPORT_XOFFSET_10"
4479  },
4480  {
4481   "chips": ["gfx10"],
4482   "map": {"at": 165172, "to": "mm"},
4483   "name": "PA_CL_VPORT_YSCALE_10"
4484  },
4485  {
4486   "chips": ["gfx10"],
4487   "map": {"at": 165176, "to": "mm"},
4488   "name": "PA_CL_VPORT_YOFFSET_10"
4489  },
4490  {
4491   "chips": ["gfx10"],
4492   "map": {"at": 165180, "to": "mm"},
4493   "name": "PA_CL_VPORT_ZSCALE_10"
4494  },
4495  {
4496   "chips": ["gfx10"],
4497   "map": {"at": 165184, "to": "mm"},
4498   "name": "PA_CL_VPORT_ZOFFSET_10"
4499  },
4500  {
4501   "chips": ["gfx10"],
4502   "map": {"at": 165188, "to": "mm"},
4503   "name": "PA_CL_VPORT_XSCALE_11"
4504  },
4505  {
4506   "chips": ["gfx10"],
4507   "map": {"at": 165192, "to": "mm"},
4508   "name": "PA_CL_VPORT_XOFFSET_11"
4509  },
4510  {
4511   "chips": ["gfx10"],
4512   "map": {"at": 165196, "to": "mm"},
4513   "name": "PA_CL_VPORT_YSCALE_11"
4514  },
4515  {
4516   "chips": ["gfx10"],
4517   "map": {"at": 165200, "to": "mm"},
4518   "name": "PA_CL_VPORT_YOFFSET_11"
4519  },
4520  {
4521   "chips": ["gfx10"],
4522   "map": {"at": 165204, "to": "mm"},
4523   "name": "PA_CL_VPORT_ZSCALE_11"
4524  },
4525  {
4526   "chips": ["gfx10"],
4527   "map": {"at": 165208, "to": "mm"},
4528   "name": "PA_CL_VPORT_ZOFFSET_11"
4529  },
4530  {
4531   "chips": ["gfx10"],
4532   "map": {"at": 165212, "to": "mm"},
4533   "name": "PA_CL_VPORT_XSCALE_12"
4534  },
4535  {
4536   "chips": ["gfx10"],
4537   "map": {"at": 165216, "to": "mm"},
4538   "name": "PA_CL_VPORT_XOFFSET_12"
4539  },
4540  {
4541   "chips": ["gfx10"],
4542   "map": {"at": 165220, "to": "mm"},
4543   "name": "PA_CL_VPORT_YSCALE_12"
4544  },
4545  {
4546   "chips": ["gfx10"],
4547   "map": {"at": 165224, "to": "mm"},
4548   "name": "PA_CL_VPORT_YOFFSET_12"
4549  },
4550  {
4551   "chips": ["gfx10"],
4552   "map": {"at": 165228, "to": "mm"},
4553   "name": "PA_CL_VPORT_ZSCALE_12"
4554  },
4555  {
4556   "chips": ["gfx10"],
4557   "map": {"at": 165232, "to": "mm"},
4558   "name": "PA_CL_VPORT_ZOFFSET_12"
4559  },
4560  {
4561   "chips": ["gfx10"],
4562   "map": {"at": 165236, "to": "mm"},
4563   "name": "PA_CL_VPORT_XSCALE_13"
4564  },
4565  {
4566   "chips": ["gfx10"],
4567   "map": {"at": 165240, "to": "mm"},
4568   "name": "PA_CL_VPORT_XOFFSET_13"
4569  },
4570  {
4571   "chips": ["gfx10"],
4572   "map": {"at": 165244, "to": "mm"},
4573   "name": "PA_CL_VPORT_YSCALE_13"
4574  },
4575  {
4576   "chips": ["gfx10"],
4577   "map": {"at": 165248, "to": "mm"},
4578   "name": "PA_CL_VPORT_YOFFSET_13"
4579  },
4580  {
4581   "chips": ["gfx10"],
4582   "map": {"at": 165252, "to": "mm"},
4583   "name": "PA_CL_VPORT_ZSCALE_13"
4584  },
4585  {
4586   "chips": ["gfx10"],
4587   "map": {"at": 165256, "to": "mm"},
4588   "name": "PA_CL_VPORT_ZOFFSET_13"
4589  },
4590  {
4591   "chips": ["gfx10"],
4592   "map": {"at": 165260, "to": "mm"},
4593   "name": "PA_CL_VPORT_XSCALE_14"
4594  },
4595  {
4596   "chips": ["gfx10"],
4597   "map": {"at": 165264, "to": "mm"},
4598   "name": "PA_CL_VPORT_XOFFSET_14"
4599  },
4600  {
4601   "chips": ["gfx10"],
4602   "map": {"at": 165268, "to": "mm"},
4603   "name": "PA_CL_VPORT_YSCALE_14"
4604  },
4605  {
4606   "chips": ["gfx10"],
4607   "map": {"at": 165272, "to": "mm"},
4608   "name": "PA_CL_VPORT_YOFFSET_14"
4609  },
4610  {
4611   "chips": ["gfx10"],
4612   "map": {"at": 165276, "to": "mm"},
4613   "name": "PA_CL_VPORT_ZSCALE_14"
4614  },
4615  {
4616   "chips": ["gfx10"],
4617   "map": {"at": 165280, "to": "mm"},
4618   "name": "PA_CL_VPORT_ZOFFSET_14"
4619  },
4620  {
4621   "chips": ["gfx10"],
4622   "map": {"at": 165284, "to": "mm"},
4623   "name": "PA_CL_VPORT_XSCALE_15"
4624  },
4625  {
4626   "chips": ["gfx10"],
4627   "map": {"at": 165288, "to": "mm"},
4628   "name": "PA_CL_VPORT_XOFFSET_15"
4629  },
4630  {
4631   "chips": ["gfx10"],
4632   "map": {"at": 165292, "to": "mm"},
4633   "name": "PA_CL_VPORT_YSCALE_15"
4634  },
4635  {
4636   "chips": ["gfx10"],
4637   "map": {"at": 165296, "to": "mm"},
4638   "name": "PA_CL_VPORT_YOFFSET_15"
4639  },
4640  {
4641   "chips": ["gfx10"],
4642   "map": {"at": 165300, "to": "mm"},
4643   "name": "PA_CL_VPORT_ZSCALE_15"
4644  },
4645  {
4646   "chips": ["gfx10"],
4647   "map": {"at": 165304, "to": "mm"},
4648   "name": "PA_CL_VPORT_ZOFFSET_15"
4649  },
4650  {
4651   "chips": ["gfx10"],
4652   "map": {"at": 165308, "to": "mm"},
4653   "name": "PA_CL_UCP_0_X"
4654  },
4655  {
4656   "chips": ["gfx10"],
4657   "map": {"at": 165312, "to": "mm"},
4658   "name": "PA_CL_UCP_0_Y"
4659  },
4660  {
4661   "chips": ["gfx10"],
4662   "map": {"at": 165316, "to": "mm"},
4663   "name": "PA_CL_UCP_0_Z"
4664  },
4665  {
4666   "chips": ["gfx10"],
4667   "map": {"at": 165320, "to": "mm"},
4668   "name": "PA_CL_UCP_0_W"
4669  },
4670  {
4671   "chips": ["gfx10"],
4672   "map": {"at": 165324, "to": "mm"},
4673   "name": "PA_CL_UCP_1_X"
4674  },
4675  {
4676   "chips": ["gfx10"],
4677   "map": {"at": 165328, "to": "mm"},
4678   "name": "PA_CL_UCP_1_Y"
4679  },
4680  {
4681   "chips": ["gfx10"],
4682   "map": {"at": 165332, "to": "mm"},
4683   "name": "PA_CL_UCP_1_Z"
4684  },
4685  {
4686   "chips": ["gfx10"],
4687   "map": {"at": 165336, "to": "mm"},
4688   "name": "PA_CL_UCP_1_W"
4689  },
4690  {
4691   "chips": ["gfx10"],
4692   "map": {"at": 165340, "to": "mm"},
4693   "name": "PA_CL_UCP_2_X"
4694  },
4695  {
4696   "chips": ["gfx10"],
4697   "map": {"at": 165344, "to": "mm"},
4698   "name": "PA_CL_UCP_2_Y"
4699  },
4700  {
4701   "chips": ["gfx10"],
4702   "map": {"at": 165348, "to": "mm"},
4703   "name": "PA_CL_UCP_2_Z"
4704  },
4705  {
4706   "chips": ["gfx10"],
4707   "map": {"at": 165352, "to": "mm"},
4708   "name": "PA_CL_UCP_2_W"
4709  },
4710  {
4711   "chips": ["gfx10"],
4712   "map": {"at": 165356, "to": "mm"},
4713   "name": "PA_CL_UCP_3_X"
4714  },
4715  {
4716   "chips": ["gfx10"],
4717   "map": {"at": 165360, "to": "mm"},
4718   "name": "PA_CL_UCP_3_Y"
4719  },
4720  {
4721   "chips": ["gfx10"],
4722   "map": {"at": 165364, "to": "mm"},
4723   "name": "PA_CL_UCP_3_Z"
4724  },
4725  {
4726   "chips": ["gfx10"],
4727   "map": {"at": 165368, "to": "mm"},
4728   "name": "PA_CL_UCP_3_W"
4729  },
4730  {
4731   "chips": ["gfx10"],
4732   "map": {"at": 165372, "to": "mm"},
4733   "name": "PA_CL_UCP_4_X"
4734  },
4735  {
4736   "chips": ["gfx10"],
4737   "map": {"at": 165376, "to": "mm"},
4738   "name": "PA_CL_UCP_4_Y"
4739  },
4740  {
4741   "chips": ["gfx10"],
4742   "map": {"at": 165380, "to": "mm"},
4743   "name": "PA_CL_UCP_4_Z"
4744  },
4745  {
4746   "chips": ["gfx10"],
4747   "map": {"at": 165384, "to": "mm"},
4748   "name": "PA_CL_UCP_4_W"
4749  },
4750  {
4751   "chips": ["gfx10"],
4752   "map": {"at": 165388, "to": "mm"},
4753   "name": "PA_CL_UCP_5_X"
4754  },
4755  {
4756   "chips": ["gfx10"],
4757   "map": {"at": 165392, "to": "mm"},
4758   "name": "PA_CL_UCP_5_Y"
4759  },
4760  {
4761   "chips": ["gfx10"],
4762   "map": {"at": 165396, "to": "mm"},
4763   "name": "PA_CL_UCP_5_Z"
4764  },
4765  {
4766   "chips": ["gfx10"],
4767   "map": {"at": 165400, "to": "mm"},
4768   "name": "PA_CL_UCP_5_W"
4769  },
4770  {
4771   "chips": ["gfx10"],
4772   "map": {"at": 165404, "to": "mm"},
4773   "name": "PA_CL_PROG_NEAR_CLIP_Z"
4774  },
4775  {
4776   "chips": ["gfx10"],
4777   "map": {"at": 165444, "to": "mm"},
4778   "name": "SPI_PS_INPUT_CNTL_0",
4779   "type_ref": "SPI_PS_INPUT_CNTL_0"
4780  },
4781  {
4782   "chips": ["gfx10"],
4783   "map": {"at": 165448, "to": "mm"},
4784   "name": "SPI_PS_INPUT_CNTL_1",
4785   "type_ref": "SPI_PS_INPUT_CNTL_0"
4786  },
4787  {
4788   "chips": ["gfx10"],
4789   "map": {"at": 165452, "to": "mm"},
4790   "name": "SPI_PS_INPUT_CNTL_2",
4791   "type_ref": "SPI_PS_INPUT_CNTL_0"
4792  },
4793  {
4794   "chips": ["gfx10"],
4795   "map": {"at": 165456, "to": "mm"},
4796   "name": "SPI_PS_INPUT_CNTL_3",
4797   "type_ref": "SPI_PS_INPUT_CNTL_0"
4798  },
4799  {
4800   "chips": ["gfx10"],
4801   "map": {"at": 165460, "to": "mm"},
4802   "name": "SPI_PS_INPUT_CNTL_4",
4803   "type_ref": "SPI_PS_INPUT_CNTL_0"
4804  },
4805  {
4806   "chips": ["gfx10"],
4807   "map": {"at": 165464, "to": "mm"},
4808   "name": "SPI_PS_INPUT_CNTL_5",
4809   "type_ref": "SPI_PS_INPUT_CNTL_0"
4810  },
4811  {
4812   "chips": ["gfx10"],
4813   "map": {"at": 165468, "to": "mm"},
4814   "name": "SPI_PS_INPUT_CNTL_6",
4815   "type_ref": "SPI_PS_INPUT_CNTL_0"
4816  },
4817  {
4818   "chips": ["gfx10"],
4819   "map": {"at": 165472, "to": "mm"},
4820   "name": "SPI_PS_INPUT_CNTL_7",
4821   "type_ref": "SPI_PS_INPUT_CNTL_0"
4822  },
4823  {
4824   "chips": ["gfx10"],
4825   "map": {"at": 165476, "to": "mm"},
4826   "name": "SPI_PS_INPUT_CNTL_8",
4827   "type_ref": "SPI_PS_INPUT_CNTL_0"
4828  },
4829  {
4830   "chips": ["gfx10"],
4831   "map": {"at": 165480, "to": "mm"},
4832   "name": "SPI_PS_INPUT_CNTL_9",
4833   "type_ref": "SPI_PS_INPUT_CNTL_0"
4834  },
4835  {
4836   "chips": ["gfx10"],
4837   "map": {"at": 165484, "to": "mm"},
4838   "name": "SPI_PS_INPUT_CNTL_10",
4839   "type_ref": "SPI_PS_INPUT_CNTL_0"
4840  },
4841  {
4842   "chips": ["gfx10"],
4843   "map": {"at": 165488, "to": "mm"},
4844   "name": "SPI_PS_INPUT_CNTL_11",
4845   "type_ref": "SPI_PS_INPUT_CNTL_0"
4846  },
4847  {
4848   "chips": ["gfx10"],
4849   "map": {"at": 165492, "to": "mm"},
4850   "name": "SPI_PS_INPUT_CNTL_12",
4851   "type_ref": "SPI_PS_INPUT_CNTL_0"
4852  },
4853  {
4854   "chips": ["gfx10"],
4855   "map": {"at": 165496, "to": "mm"},
4856   "name": "SPI_PS_INPUT_CNTL_13",
4857   "type_ref": "SPI_PS_INPUT_CNTL_0"
4858  },
4859  {
4860   "chips": ["gfx10"],
4861   "map": {"at": 165500, "to": "mm"},
4862   "name": "SPI_PS_INPUT_CNTL_14",
4863   "type_ref": "SPI_PS_INPUT_CNTL_0"
4864  },
4865  {
4866   "chips": ["gfx10"],
4867   "map": {"at": 165504, "to": "mm"},
4868   "name": "SPI_PS_INPUT_CNTL_15",
4869   "type_ref": "SPI_PS_INPUT_CNTL_0"
4870  },
4871  {
4872   "chips": ["gfx10"],
4873   "map": {"at": 165508, "to": "mm"},
4874   "name": "SPI_PS_INPUT_CNTL_16",
4875   "type_ref": "SPI_PS_INPUT_CNTL_0"
4876  },
4877  {
4878   "chips": ["gfx10"],
4879   "map": {"at": 165512, "to": "mm"},
4880   "name": "SPI_PS_INPUT_CNTL_17",
4881   "type_ref": "SPI_PS_INPUT_CNTL_0"
4882  },
4883  {
4884   "chips": ["gfx10"],
4885   "map": {"at": 165516, "to": "mm"},
4886   "name": "SPI_PS_INPUT_CNTL_18",
4887   "type_ref": "SPI_PS_INPUT_CNTL_0"
4888  },
4889  {
4890   "chips": ["gfx10"],
4891   "map": {"at": 165520, "to": "mm"},
4892   "name": "SPI_PS_INPUT_CNTL_19",
4893   "type_ref": "SPI_PS_INPUT_CNTL_0"
4894  },
4895  {
4896   "chips": ["gfx10"],
4897   "map": {"at": 165524, "to": "mm"},
4898   "name": "SPI_PS_INPUT_CNTL_20",
4899   "type_ref": "SPI_PS_INPUT_CNTL_20"
4900  },
4901  {
4902   "chips": ["gfx10"],
4903   "map": {"at": 165528, "to": "mm"},
4904   "name": "SPI_PS_INPUT_CNTL_21",
4905   "type_ref": "SPI_PS_INPUT_CNTL_20"
4906  },
4907  {
4908   "chips": ["gfx10"],
4909   "map": {"at": 165532, "to": "mm"},
4910   "name": "SPI_PS_INPUT_CNTL_22",
4911   "type_ref": "SPI_PS_INPUT_CNTL_20"
4912  },
4913  {
4914   "chips": ["gfx10"],
4915   "map": {"at": 165536, "to": "mm"},
4916   "name": "SPI_PS_INPUT_CNTL_23",
4917   "type_ref": "SPI_PS_INPUT_CNTL_20"
4918  },
4919  {
4920   "chips": ["gfx10"],
4921   "map": {"at": 165540, "to": "mm"},
4922   "name": "SPI_PS_INPUT_CNTL_24",
4923   "type_ref": "SPI_PS_INPUT_CNTL_20"
4924  },
4925  {
4926   "chips": ["gfx10"],
4927   "map": {"at": 165544, "to": "mm"},
4928   "name": "SPI_PS_INPUT_CNTL_25",
4929   "type_ref": "SPI_PS_INPUT_CNTL_20"
4930  },
4931  {
4932   "chips": ["gfx10"],
4933   "map": {"at": 165548, "to": "mm"},
4934   "name": "SPI_PS_INPUT_CNTL_26",
4935   "type_ref": "SPI_PS_INPUT_CNTL_20"
4936  },
4937  {
4938   "chips": ["gfx10"],
4939   "map": {"at": 165552, "to": "mm"},
4940   "name": "SPI_PS_INPUT_CNTL_27",
4941   "type_ref": "SPI_PS_INPUT_CNTL_20"
4942  },
4943  {
4944   "chips": ["gfx10"],
4945   "map": {"at": 165556, "to": "mm"},
4946   "name": "SPI_PS_INPUT_CNTL_28",
4947   "type_ref": "SPI_PS_INPUT_CNTL_20"
4948  },
4949  {
4950   "chips": ["gfx10"],
4951   "map": {"at": 165560, "to": "mm"},
4952   "name": "SPI_PS_INPUT_CNTL_29",
4953   "type_ref": "SPI_PS_INPUT_CNTL_20"
4954  },
4955  {
4956   "chips": ["gfx10"],
4957   "map": {"at": 165564, "to": "mm"},
4958   "name": "SPI_PS_INPUT_CNTL_30",
4959   "type_ref": "SPI_PS_INPUT_CNTL_20"
4960  },
4961  {
4962   "chips": ["gfx10"],
4963   "map": {"at": 165568, "to": "mm"},
4964   "name": "SPI_PS_INPUT_CNTL_31",
4965   "type_ref": "SPI_PS_INPUT_CNTL_20"
4966  },
4967  {
4968   "chips": ["gfx10"],
4969   "map": {"at": 165572, "to": "mm"},
4970   "name": "SPI_VS_OUT_CONFIG",
4971   "type_ref": "SPI_VS_OUT_CONFIG"
4972  },
4973  {
4974   "chips": ["gfx10"],
4975   "map": {"at": 165580, "to": "mm"},
4976   "name": "SPI_PS_INPUT_ENA",
4977   "type_ref": "SPI_PS_INPUT_ENA"
4978  },
4979  {
4980   "chips": ["gfx10"],
4981   "map": {"at": 165584, "to": "mm"},
4982   "name": "SPI_PS_INPUT_ADDR",
4983   "type_ref": "SPI_PS_INPUT_ENA"
4984  },
4985  {
4986   "chips": ["gfx10"],
4987   "map": {"at": 165588, "to": "mm"},
4988   "name": "SPI_INTERP_CONTROL_0",
4989   "type_ref": "SPI_INTERP_CONTROL_0"
4990  },
4991  {
4992   "chips": ["gfx10"],
4993   "map": {"at": 165592, "to": "mm"},
4994   "name": "SPI_PS_IN_CONTROL",
4995   "type_ref": "SPI_PS_IN_CONTROL"
4996  },
4997  {
4998   "chips": ["gfx10"],
4999   "map": {"at": 165600, "to": "mm"},
5000   "name": "SPI_BARYC_CNTL",
5001   "type_ref": "SPI_BARYC_CNTL"
5002  },
5003  {
5004   "chips": ["gfx10"],
5005   "map": {"at": 165608, "to": "mm"},
5006   "name": "SPI_TMPRING_SIZE",
5007   "type_ref": "COMPUTE_TMPRING_SIZE"
5008  },
5009  {
5010   "chips": ["gfx10"],
5011   "map": {"at": 165640, "to": "mm"},
5012   "name": "SPI_SHADER_IDX_FORMAT",
5013   "type_ref": "SPI_SHADER_IDX_FORMAT"
5014  },
5015  {
5016   "chips": ["gfx10"],
5017   "map": {"at": 165644, "to": "mm"},
5018   "name": "SPI_SHADER_POS_FORMAT",
5019   "type_ref": "SPI_SHADER_POS_FORMAT"
5020  },
5021  {
5022   "chips": ["gfx10"],
5023   "map": {"at": 165648, "to": "mm"},
5024   "name": "SPI_SHADER_Z_FORMAT",
5025   "type_ref": "SPI_SHADER_Z_FORMAT"
5026  },
5027  {
5028   "chips": ["gfx10"],
5029   "map": {"at": 165652, "to": "mm"},
5030   "name": "SPI_SHADER_COL_FORMAT",
5031   "type_ref": "SPI_SHADER_COL_FORMAT"
5032  },
5033  {
5034   "chips": ["gfx10"],
5035   "map": {"at": 165716, "to": "mm"},
5036   "name": "SX_PS_DOWNCONVERT",
5037   "type_ref": "SX_PS_DOWNCONVERT"
5038  },
5039  {
5040   "chips": ["gfx10"],
5041   "map": {"at": 165720, "to": "mm"},
5042   "name": "SX_BLEND_OPT_EPSILON",
5043   "type_ref": "SX_BLEND_OPT_EPSILON"
5044  },
5045  {
5046   "chips": ["gfx10"],
5047   "map": {"at": 165724, "to": "mm"},
5048   "name": "SX_BLEND_OPT_CONTROL",
5049   "type_ref": "SX_BLEND_OPT_CONTROL"
5050  },
5051  {
5052   "chips": ["gfx10"],
5053   "map": {"at": 165728, "to": "mm"},
5054   "name": "SX_MRT0_BLEND_OPT",
5055   "type_ref": "SX_MRT0_BLEND_OPT"
5056  },
5057  {
5058   "chips": ["gfx10"],
5059   "map": {"at": 165732, "to": "mm"},
5060   "name": "SX_MRT1_BLEND_OPT",
5061   "type_ref": "SX_MRT0_BLEND_OPT"
5062  },
5063  {
5064   "chips": ["gfx10"],
5065   "map": {"at": 165736, "to": "mm"},
5066   "name": "SX_MRT2_BLEND_OPT",
5067   "type_ref": "SX_MRT0_BLEND_OPT"
5068  },
5069  {
5070   "chips": ["gfx10"],
5071   "map": {"at": 165740, "to": "mm"},
5072   "name": "SX_MRT3_BLEND_OPT",
5073   "type_ref": "SX_MRT0_BLEND_OPT"
5074  },
5075  {
5076   "chips": ["gfx10"],
5077   "map": {"at": 165744, "to": "mm"},
5078   "name": "SX_MRT4_BLEND_OPT",
5079   "type_ref": "SX_MRT0_BLEND_OPT"
5080  },
5081  {
5082   "chips": ["gfx10"],
5083   "map": {"at": 165748, "to": "mm"},
5084   "name": "SX_MRT5_BLEND_OPT",
5085   "type_ref": "SX_MRT0_BLEND_OPT"
5086  },
5087  {
5088   "chips": ["gfx10"],
5089   "map": {"at": 165752, "to": "mm"},
5090   "name": "SX_MRT6_BLEND_OPT",
5091   "type_ref": "SX_MRT0_BLEND_OPT"
5092  },
5093  {
5094   "chips": ["gfx10"],
5095   "map": {"at": 165756, "to": "mm"},
5096   "name": "SX_MRT7_BLEND_OPT",
5097   "type_ref": "SX_MRT0_BLEND_OPT"
5098  },
5099  {
5100   "chips": ["gfx10"],
5101   "map": {"at": 165760, "to": "mm"},
5102   "name": "CB_BLEND0_CONTROL",
5103   "type_ref": "CB_BLEND0_CONTROL"
5104  },
5105  {
5106   "chips": ["gfx10"],
5107   "map": {"at": 165764, "to": "mm"},
5108   "name": "CB_BLEND1_CONTROL",
5109   "type_ref": "CB_BLEND0_CONTROL"
5110  },
5111  {
5112   "chips": ["gfx10"],
5113   "map": {"at": 165768, "to": "mm"},
5114   "name": "CB_BLEND2_CONTROL",
5115   "type_ref": "CB_BLEND0_CONTROL"
5116  },
5117  {
5118   "chips": ["gfx10"],
5119   "map": {"at": 165772, "to": "mm"},
5120   "name": "CB_BLEND3_CONTROL",
5121   "type_ref": "CB_BLEND0_CONTROL"
5122  },
5123  {
5124   "chips": ["gfx10"],
5125   "map": {"at": 165776, "to": "mm"},
5126   "name": "CB_BLEND4_CONTROL",
5127   "type_ref": "CB_BLEND0_CONTROL"
5128  },
5129  {
5130   "chips": ["gfx10"],
5131   "map": {"at": 165780, "to": "mm"},
5132   "name": "CB_BLEND5_CONTROL",
5133   "type_ref": "CB_BLEND0_CONTROL"
5134  },
5135  {
5136   "chips": ["gfx10"],
5137   "map": {"at": 165784, "to": "mm"},
5138   "name": "CB_BLEND6_CONTROL",
5139   "type_ref": "CB_BLEND0_CONTROL"
5140  },
5141  {
5142   "chips": ["gfx10"],
5143   "map": {"at": 165788, "to": "mm"},
5144   "name": "CB_BLEND7_CONTROL",
5145   "type_ref": "CB_BLEND0_CONTROL"
5146  },
5147  {
5148   "chips": ["gfx10"],
5149   "map": {"at": 165836, "to": "mm"},
5150   "name": "CS_COPY_STATE",
5151   "type_ref": "CS_COPY_STATE"
5152  },
5153  {
5154   "chips": ["gfx10"],
5155   "map": {"at": 165840, "to": "mm"},
5156   "name": "GFX_COPY_STATE",
5157   "type_ref": "CS_COPY_STATE"
5158  },
5159  {
5160   "chips": ["gfx10"],
5161   "map": {"at": 165844, "to": "mm"},
5162   "name": "PA_CL_POINT_X_RAD"
5163  },
5164  {
5165   "chips": ["gfx10"],
5166   "map": {"at": 165848, "to": "mm"},
5167   "name": "PA_CL_POINT_Y_RAD"
5168  },
5169  {
5170   "chips": ["gfx10"],
5171   "map": {"at": 165852, "to": "mm"},
5172   "name": "PA_CL_POINT_SIZE"
5173  },
5174  {
5175   "chips": ["gfx10"],
5176   "map": {"at": 165856, "to": "mm"},
5177   "name": "PA_CL_POINT_CULL_RAD"
5178  },
5179  {
5180   "chips": ["gfx10"],
5181   "map": {"at": 165860, "to": "mm"},
5182   "name": "VGT_DMA_BASE_HI",
5183   "type_ref": "VGT_DMA_BASE_HI"
5184  },
5185  {
5186   "chips": ["gfx10"],
5187   "map": {"at": 165864, "to": "mm"},
5188   "name": "VGT_DMA_BASE"
5189  },
5190  {
5191   "chips": ["gfx10"],
5192   "map": {"at": 165872, "to": "mm"},
5193   "name": "VGT_DRAW_INITIATOR",
5194   "type_ref": "VGT_DRAW_INITIATOR"
5195  },
5196  {
5197   "chips": ["gfx10"],
5198   "map": {"at": 165876, "to": "mm"},
5199   "name": "VGT_IMMED_DATA"
5200  },
5201  {
5202   "chips": ["gfx10"],
5203   "map": {"at": 165880, "to": "mm"},
5204   "name": "VGT_EVENT_ADDRESS_REG",
5205   "type_ref": "VGT_EVENT_ADDRESS_REG"
5206  },
5207  {
5208   "chips": ["gfx10"],
5209   "map": {"at": 165884, "to": "mm"},
5210   "name": "GE_MAX_OUTPUT_PER_SUBGROUP",
5211   "type_ref": "GE_MAX_OUTPUT_PER_SUBGROUP"
5212  },
5213  {
5214   "chips": ["gfx10"],
5215   "map": {"at": 165888, "to": "mm"},
5216   "name": "DB_DEPTH_CONTROL",
5217   "type_ref": "DB_DEPTH_CONTROL"
5218  },
5219  {
5220   "chips": ["gfx10"],
5221   "map": {"at": 165892, "to": "mm"},
5222   "name": "DB_EQAA",
5223   "type_ref": "DB_EQAA"
5224  },
5225  {
5226   "chips": ["gfx10"],
5227   "map": {"at": 165896, "to": "mm"},
5228   "name": "CB_COLOR_CONTROL",
5229   "type_ref": "CB_COLOR_CONTROL"
5230  },
5231  {
5232   "chips": ["gfx10"],
5233   "map": {"at": 165900, "to": "mm"},
5234   "name": "DB_SHADER_CONTROL",
5235   "type_ref": "DB_SHADER_CONTROL"
5236  },
5237  {
5238   "chips": ["gfx10"],
5239   "map": {"at": 165904, "to": "mm"},
5240   "name": "PA_CL_CLIP_CNTL",
5241   "type_ref": "PA_CL_CLIP_CNTL"
5242  },
5243  {
5244   "chips": ["gfx10"],
5245   "map": {"at": 165908, "to": "mm"},
5246   "name": "PA_SU_SC_MODE_CNTL",
5247   "type_ref": "PA_SU_SC_MODE_CNTL"
5248  },
5249  {
5250   "chips": ["gfx10"],
5251   "map": {"at": 165912, "to": "mm"},
5252   "name": "PA_CL_VTE_CNTL",
5253   "type_ref": "PA_CL_VTE_CNTL"
5254  },
5255  {
5256   "chips": ["gfx10"],
5257   "map": {"at": 165916, "to": "mm"},
5258   "name": "PA_CL_VS_OUT_CNTL",
5259   "type_ref": "PA_CL_VS_OUT_CNTL"
5260  },
5261  {
5262   "chips": ["gfx10"],
5263   "map": {"at": 165920, "to": "mm"},
5264   "name": "PA_CL_NANINF_CNTL",
5265   "type_ref": "PA_CL_NANINF_CNTL"
5266  },
5267  {
5268   "chips": ["gfx10"],
5269   "map": {"at": 165924, "to": "mm"},
5270   "name": "PA_SU_LINE_STIPPLE_CNTL",
5271   "type_ref": "PA_SU_LINE_STIPPLE_CNTL"
5272  },
5273  {
5274   "chips": ["gfx10"],
5275   "map": {"at": 165928, "to": "mm"},
5276   "name": "PA_SU_LINE_STIPPLE_SCALE"
5277  },
5278  {
5279   "chips": ["gfx10"],
5280   "map": {"at": 165932, "to": "mm"},
5281   "name": "PA_SU_PRIM_FILTER_CNTL",
5282   "type_ref": "PA_SU_PRIM_FILTER_CNTL"
5283  },
5284  {
5285   "chips": ["gfx10"],
5286   "map": {"at": 165936, "to": "mm"},
5287   "name": "PA_SU_SMALL_PRIM_FILTER_CNTL",
5288   "type_ref": "PA_SU_SMALL_PRIM_FILTER_CNTL"
5289  },
5290  {
5291   "chips": ["gfx10"],
5292   "map": {"at": 165940, "to": "mm"},
5293   "name": "PA_CL_OBJPRIM_ID_CNTL",
5294   "type_ref": "PA_CL_OBJPRIM_ID_CNTL"
5295  },
5296  {
5297   "chips": ["gfx10"],
5298   "map": {"at": 165944, "to": "mm"},
5299   "name": "PA_CL_NGG_CNTL",
5300   "type_ref": "PA_CL_NGG_CNTL"
5301  },
5302  {
5303   "chips": ["gfx10"],
5304   "map": {"at": 165948, "to": "mm"},
5305   "name": "PA_SU_OVER_RASTERIZATION_CNTL",
5306   "type_ref": "PA_SU_OVER_RASTERIZATION_CNTL"
5307  },
5308  {
5309   "chips": ["gfx10"],
5310   "map": {"at": 165952, "to": "mm"},
5311   "name": "PA_STEREO_CNTL",
5312   "type_ref": "PA_STEREO_CNTL"
5313  },
5314  {
5315   "chips": ["gfx10"],
5316   "map": {"at": 165956, "to": "mm"},
5317   "name": "PA_STATE_STEREO_X"
5318  },
5319  {
5320   "chips": ["gfx10"],
5321   "map": {"at": 166400, "to": "mm"},
5322   "name": "PA_SU_POINT_SIZE",
5323   "type_ref": "PA_SU_POINT_SIZE"
5324  },
5325  {
5326   "chips": ["gfx10"],
5327   "map": {"at": 166404, "to": "mm"},
5328   "name": "PA_SU_POINT_MINMAX",
5329   "type_ref": "PA_SU_POINT_MINMAX"
5330  },
5331  {
5332   "chips": ["gfx10"],
5333   "map": {"at": 166408, "to": "mm"},
5334   "name": "PA_SU_LINE_CNTL",
5335   "type_ref": "PA_SU_LINE_CNTL"
5336  },
5337  {
5338   "chips": ["gfx10"],
5339   "map": {"at": 166412, "to": "mm"},
5340   "name": "PA_SC_LINE_STIPPLE",
5341   "type_ref": "PA_SC_LINE_STIPPLE"
5342  },
5343  {
5344   "chips": ["gfx10"],
5345   "map": {"at": 166416, "to": "mm"},
5346   "name": "VGT_OUTPUT_PATH_CNTL",
5347   "type_ref": "VGT_OUTPUT_PATH_CNTL"
5348  },
5349  {
5350   "chips": ["gfx10"],
5351   "map": {"at": 166420, "to": "mm"},
5352   "name": "VGT_HOS_CNTL",
5353   "type_ref": "VGT_HOS_CNTL"
5354  },
5355  {
5356   "chips": ["gfx10"],
5357   "map": {"at": 166424, "to": "mm"},
5358   "name": "VGT_HOS_MAX_TESS_LEVEL"
5359  },
5360  {
5361   "chips": ["gfx10"],
5362   "map": {"at": 166428, "to": "mm"},
5363   "name": "VGT_HOS_MIN_TESS_LEVEL"
5364  },
5365  {
5366   "chips": ["gfx10"],
5367   "map": {"at": 166432, "to": "mm"},
5368   "name": "VGT_HOS_REUSE_DEPTH",
5369   "type_ref": "VGT_HOS_REUSE_DEPTH"
5370  },
5371  {
5372   "chips": ["gfx10"],
5373   "map": {"at": 166436, "to": "mm"},
5374   "name": "VGT_GROUP_PRIM_TYPE",
5375   "type_ref": "VGT_GROUP_PRIM_TYPE"
5376  },
5377  {
5378   "chips": ["gfx10"],
5379   "map": {"at": 166440, "to": "mm"},
5380   "name": "VGT_GROUP_FIRST_DECR",
5381   "type_ref": "VGT_GROUP_FIRST_DECR"
5382  },
5383  {
5384   "chips": ["gfx10"],
5385   "map": {"at": 166444, "to": "mm"},
5386   "name": "VGT_GROUP_DECR",
5387   "type_ref": "VGT_GROUP_DECR"
5388  },
5389  {
5390   "chips": ["gfx10"],
5391   "map": {"at": 166448, "to": "mm"},
5392   "name": "VGT_GROUP_VECT_0_CNTL",
5393   "type_ref": "VGT_GROUP_VECT_0_CNTL"
5394  },
5395  {
5396   "chips": ["gfx10"],
5397   "map": {"at": 166452, "to": "mm"},
5398   "name": "VGT_GROUP_VECT_1_CNTL",
5399   "type_ref": "VGT_GROUP_VECT_0_CNTL"
5400  },
5401  {
5402   "chips": ["gfx10"],
5403   "map": {"at": 166456, "to": "mm"},
5404   "name": "VGT_GROUP_VECT_0_FMT_CNTL",
5405   "type_ref": "VGT_GROUP_VECT_0_FMT_CNTL"
5406  },
5407  {
5408   "chips": ["gfx10"],
5409   "map": {"at": 166460, "to": "mm"},
5410   "name": "VGT_GROUP_VECT_1_FMT_CNTL",
5411   "type_ref": "VGT_GROUP_VECT_0_FMT_CNTL"
5412  },
5413  {
5414   "chips": ["gfx10"],
5415   "map": {"at": 166464, "to": "mm"},
5416   "name": "VGT_GS_MODE",
5417   "type_ref": "VGT_GS_MODE"
5418  },
5419  {
5420   "chips": ["gfx10"],
5421   "map": {"at": 166468, "to": "mm"},
5422   "name": "VGT_GS_ONCHIP_CNTL",
5423   "type_ref": "VGT_GS_ONCHIP_CNTL"
5424  },
5425  {
5426   "chips": ["gfx10"],
5427   "map": {"at": 166472, "to": "mm"},
5428   "name": "PA_SC_MODE_CNTL_0",
5429   "type_ref": "PA_SC_MODE_CNTL_0"
5430  },
5431  {
5432   "chips": ["gfx10"],
5433   "map": {"at": 166476, "to": "mm"},
5434   "name": "PA_SC_MODE_CNTL_1",
5435   "type_ref": "PA_SC_MODE_CNTL_1"
5436  },
5437  {
5438   "chips": ["gfx10"],
5439   "map": {"at": 166480, "to": "mm"},
5440   "name": "VGT_ENHANCE"
5441  },
5442  {
5443   "chips": ["gfx10"],
5444   "map": {"at": 166484, "to": "mm"},
5445   "name": "VGT_GS_PER_ES",
5446   "type_ref": "VGT_GS_PER_ES"
5447  },
5448  {
5449   "chips": ["gfx10"],
5450   "map": {"at": 166488, "to": "mm"},
5451   "name": "VGT_ES_PER_GS",
5452   "type_ref": "VGT_ES_PER_GS"
5453  },
5454  {
5455   "chips": ["gfx10"],
5456   "map": {"at": 166492, "to": "mm"},
5457   "name": "VGT_GS_PER_VS",
5458   "type_ref": "VGT_GS_PER_VS"
5459  },
5460  {
5461   "chips": ["gfx10"],
5462   "map": {"at": 166496, "to": "mm"},
5463   "name": "VGT_GSVS_RING_OFFSET_1",
5464   "type_ref": "VGT_GSVS_RING_OFFSET_1"
5465  },
5466  {
5467   "chips": ["gfx10"],
5468   "map": {"at": 166500, "to": "mm"},
5469   "name": "VGT_GSVS_RING_OFFSET_2",
5470   "type_ref": "VGT_GSVS_RING_OFFSET_1"
5471  },
5472  {
5473   "chips": ["gfx10"],
5474   "map": {"at": 166504, "to": "mm"},
5475   "name": "VGT_GSVS_RING_OFFSET_3",
5476   "type_ref": "VGT_GSVS_RING_OFFSET_1"
5477  },
5478  {
5479   "chips": ["gfx10"],
5480   "map": {"at": 166508, "to": "mm"},
5481   "name": "VGT_GS_OUT_PRIM_TYPE",
5482   "type_ref": "VGT_GS_OUT_PRIM_TYPE"
5483  },
5484  {
5485   "chips": ["gfx10"],
5486   "map": {"at": 166512, "to": "mm"},
5487   "name": "IA_ENHANCE"
5488  },
5489  {
5490   "chips": ["gfx10"],
5491   "map": {"at": 166516, "to": "mm"},
5492   "name": "VGT_DMA_SIZE"
5493  },
5494  {
5495   "chips": ["gfx10"],
5496   "map": {"at": 166520, "to": "mm"},
5497   "name": "VGT_DMA_MAX_SIZE"
5498  },
5499  {
5500   "chips": ["gfx10"],
5501   "map": {"at": 166524, "to": "mm"},
5502   "name": "VGT_DMA_INDEX_TYPE",
5503   "type_ref": "VGT_DMA_INDEX_TYPE"
5504  },
5505  {
5506   "chips": ["gfx10"],
5507   "map": {"at": 166528, "to": "mm"},
5508   "name": "WD_ENHANCE"
5509  },
5510  {
5511   "chips": ["gfx10"],
5512   "map": {"at": 166532, "to": "mm"},
5513   "name": "VGT_PRIMITIVEID_EN",
5514   "type_ref": "VGT_PRIMITIVEID_EN"
5515  },
5516  {
5517   "chips": ["gfx10"],
5518   "map": {"at": 166536, "to": "mm"},
5519   "name": "VGT_DMA_NUM_INSTANCES"
5520  },
5521  {
5522   "chips": ["gfx10"],
5523   "map": {"at": 166540, "to": "mm"},
5524   "name": "VGT_PRIMITIVEID_RESET"
5525  },
5526  {
5527   "chips": ["gfx10"],
5528   "map": {"at": 166544, "to": "mm"},
5529   "name": "VGT_EVENT_INITIATOR",
5530   "type_ref": "VGT_EVENT_INITIATOR"
5531  },
5532  {
5533   "chips": ["gfx10"],
5534   "map": {"at": 166548, "to": "mm"},
5535   "name": "VGT_MULTI_PRIM_IB_RESET_EN",
5536   "type_ref": "VGT_MULTI_PRIM_IB_RESET_EN"
5537  },
5538  {
5539   "chips": ["gfx10"],
5540   "map": {"at": 166552, "to": "mm"},
5541   "name": "VGT_DRAW_PAYLOAD_CNTL",
5542   "type_ref": "VGT_DRAW_PAYLOAD_CNTL"
5543  },
5544  {
5545   "chips": ["gfx10"],
5546   "map": {"at": 166560, "to": "mm"},
5547   "name": "VGT_INSTANCE_STEP_RATE_0"
5548  },
5549  {
5550   "chips": ["gfx10"],
5551   "map": {"at": 166564, "to": "mm"},
5552   "name": "VGT_INSTANCE_STEP_RATE_1"
5553  },
5554  {
5555   "chips": ["gfx10"],
5556   "map": {"at": 166568, "to": "mm"},
5557   "name": "IA_MULTI_VGT_PARAM",
5558   "type_ref": "IA_MULTI_VGT_PARAM"
5559  },
5560  {
5561   "chips": ["gfx10"],
5562   "map": {"at": 166572, "to": "mm"},
5563   "name": "VGT_ESGS_RING_ITEMSIZE",
5564   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5565  },
5566  {
5567   "chips": ["gfx10"],
5568   "map": {"at": 166576, "to": "mm"},
5569   "name": "VGT_GSVS_RING_ITEMSIZE",
5570   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5571  },
5572  {
5573   "chips": ["gfx10"],
5574   "map": {"at": 166580, "to": "mm"},
5575   "name": "VGT_REUSE_OFF",
5576   "type_ref": "VGT_REUSE_OFF"
5577  },
5578  {
5579   "chips": ["gfx10"],
5580   "map": {"at": 166584, "to": "mm"},
5581   "name": "VGT_VTX_CNT_EN",
5582   "type_ref": "VGT_VTX_CNT_EN"
5583  },
5584  {
5585   "chips": ["gfx10"],
5586   "map": {"at": 166588, "to": "mm"},
5587   "name": "DB_HTILE_SURFACE",
5588   "type_ref": "DB_HTILE_SURFACE"
5589  },
5590  {
5591   "chips": ["gfx10"],
5592   "map": {"at": 166592, "to": "mm"},
5593   "name": "DB_SRESULTS_COMPARE_STATE0",
5594   "type_ref": "DB_SRESULTS_COMPARE_STATE0"
5595  },
5596  {
5597   "chips": ["gfx10"],
5598   "map": {"at": 166596, "to": "mm"},
5599   "name": "DB_SRESULTS_COMPARE_STATE1",
5600   "type_ref": "DB_SRESULTS_COMPARE_STATE1"
5601  },
5602  {
5603   "chips": ["gfx10"],
5604   "map": {"at": 166600, "to": "mm"},
5605   "name": "DB_PRELOAD_CONTROL",
5606   "type_ref": "DB_PRELOAD_CONTROL"
5607  },
5608  {
5609   "chips": ["gfx10"],
5610   "map": {"at": 166608, "to": "mm"},
5611   "name": "VGT_STRMOUT_BUFFER_SIZE_0"
5612  },
5613  {
5614   "chips": ["gfx10"],
5615   "map": {"at": 166612, "to": "mm"},
5616   "name": "VGT_STRMOUT_VTX_STRIDE_0",
5617   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
5618  },
5619  {
5620   "chips": ["gfx10"],
5621   "map": {"at": 166620, "to": "mm"},
5622   "name": "VGT_STRMOUT_BUFFER_OFFSET_0"
5623  },
5624  {
5625   "chips": ["gfx10"],
5626   "map": {"at": 166624, "to": "mm"},
5627   "name": "VGT_STRMOUT_BUFFER_SIZE_1"
5628  },
5629  {
5630   "chips": ["gfx10"],
5631   "map": {"at": 166628, "to": "mm"},
5632   "name": "VGT_STRMOUT_VTX_STRIDE_1",
5633   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
5634  },
5635  {
5636   "chips": ["gfx10"],
5637   "map": {"at": 166636, "to": "mm"},
5638   "name": "VGT_STRMOUT_BUFFER_OFFSET_1"
5639  },
5640  {
5641   "chips": ["gfx10"],
5642   "map": {"at": 166640, "to": "mm"},
5643   "name": "VGT_STRMOUT_BUFFER_SIZE_2"
5644  },
5645  {
5646   "chips": ["gfx10"],
5647   "map": {"at": 166644, "to": "mm"},
5648   "name": "VGT_STRMOUT_VTX_STRIDE_2",
5649   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
5650  },
5651  {
5652   "chips": ["gfx10"],
5653   "map": {"at": 166652, "to": "mm"},
5654   "name": "VGT_STRMOUT_BUFFER_OFFSET_2"
5655  },
5656  {
5657   "chips": ["gfx10"],
5658   "map": {"at": 166656, "to": "mm"},
5659   "name": "VGT_STRMOUT_BUFFER_SIZE_3"
5660  },
5661  {
5662   "chips": ["gfx10"],
5663   "map": {"at": 166660, "to": "mm"},
5664   "name": "VGT_STRMOUT_VTX_STRIDE_3",
5665   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
5666  },
5667  {
5668   "chips": ["gfx10"],
5669   "map": {"at": 166668, "to": "mm"},
5670   "name": "VGT_STRMOUT_BUFFER_OFFSET_3"
5671  },
5672  {
5673   "chips": ["gfx10"],
5674   "map": {"at": 166696, "to": "mm"},
5675   "name": "VGT_STRMOUT_DRAW_OPAQUE_OFFSET"
5676  },
5677  {
5678   "chips": ["gfx10"],
5679   "map": {"at": 166700, "to": "mm"},
5680   "name": "VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE"
5681  },
5682  {
5683   "chips": ["gfx10"],
5684   "map": {"at": 166704, "to": "mm"},
5685   "name": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE",
5686   "type_ref": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE"
5687  },
5688  {
5689   "chips": ["gfx10"],
5690   "map": {"at": 166712, "to": "mm"},
5691   "name": "VGT_GS_MAX_VERT_OUT",
5692   "type_ref": "VGT_GS_MAX_VERT_OUT"
5693  },
5694  {
5695   "chips": ["gfx10"],
5696   "map": {"at": 166732, "to": "mm"},
5697   "name": "GE_NGG_SUBGRP_CNTL",
5698   "type_ref": "GE_NGG_SUBGRP_CNTL"
5699  },
5700  {
5701   "chips": ["gfx10"],
5702   "map": {"at": 166736, "to": "mm"},
5703   "name": "VGT_TESS_DISTRIBUTION",
5704   "type_ref": "VGT_TESS_DISTRIBUTION"
5705  },
5706  {
5707   "chips": ["gfx10"],
5708   "map": {"at": 166740, "to": "mm"},
5709   "name": "VGT_SHADER_STAGES_EN",
5710   "type_ref": "VGT_SHADER_STAGES_EN"
5711  },
5712  {
5713   "chips": ["gfx10"],
5714   "map": {"at": 166744, "to": "mm"},
5715   "name": "VGT_LS_HS_CONFIG",
5716   "type_ref": "VGT_LS_HS_CONFIG"
5717  },
5718  {
5719   "chips": ["gfx10"],
5720   "map": {"at": 166748, "to": "mm"},
5721   "name": "VGT_GS_VERT_ITEMSIZE",
5722   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5723  },
5724  {
5725   "chips": ["gfx10"],
5726   "map": {"at": 166752, "to": "mm"},
5727   "name": "VGT_GS_VERT_ITEMSIZE_1",
5728   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5729  },
5730  {
5731   "chips": ["gfx10"],
5732   "map": {"at": 166756, "to": "mm"},
5733   "name": "VGT_GS_VERT_ITEMSIZE_2",
5734   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5735  },
5736  {
5737   "chips": ["gfx10"],
5738   "map": {"at": 166760, "to": "mm"},
5739   "name": "VGT_GS_VERT_ITEMSIZE_3",
5740   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5741  },
5742  {
5743   "chips": ["gfx10"],
5744   "map": {"at": 166764, "to": "mm"},
5745   "name": "VGT_TF_PARAM",
5746   "type_ref": "VGT_TF_PARAM"
5747  },
5748  {
5749   "chips": ["gfx10"],
5750   "map": {"at": 166768, "to": "mm"},
5751   "name": "DB_ALPHA_TO_MASK",
5752   "type_ref": "DB_ALPHA_TO_MASK"
5753  },
5754  {
5755   "chips": ["gfx10"],
5756   "map": {"at": 166772, "to": "mm"},
5757   "name": "VGT_DISPATCH_DRAW_INDEX"
5758  },
5759  {
5760   "chips": ["gfx10"],
5761   "map": {"at": 166776, "to": "mm"},
5762   "name": "PA_SU_POLY_OFFSET_DB_FMT_CNTL",
5763   "type_ref": "PA_SU_POLY_OFFSET_DB_FMT_CNTL"
5764  },
5765  {
5766   "chips": ["gfx10"],
5767   "map": {"at": 166780, "to": "mm"},
5768   "name": "PA_SU_POLY_OFFSET_CLAMP"
5769  },
5770  {
5771   "chips": ["gfx10"],
5772   "map": {"at": 166784, "to": "mm"},
5773   "name": "PA_SU_POLY_OFFSET_FRONT_SCALE"
5774  },
5775  {
5776   "chips": ["gfx10"],
5777   "map": {"at": 166788, "to": "mm"},
5778   "name": "PA_SU_POLY_OFFSET_FRONT_OFFSET"
5779  },
5780  {
5781   "chips": ["gfx10"],
5782   "map": {"at": 166792, "to": "mm"},
5783   "name": "PA_SU_POLY_OFFSET_BACK_SCALE"
5784  },
5785  {
5786   "chips": ["gfx10"],
5787   "map": {"at": 166796, "to": "mm"},
5788   "name": "PA_SU_POLY_OFFSET_BACK_OFFSET"
5789  },
5790  {
5791   "chips": ["gfx10"],
5792   "map": {"at": 166800, "to": "mm"},
5793   "name": "VGT_GS_INSTANCE_CNT",
5794   "type_ref": "VGT_GS_INSTANCE_CNT"
5795  },
5796  {
5797   "chips": ["gfx10"],
5798   "map": {"at": 166804, "to": "mm"},
5799   "name": "VGT_STRMOUT_CONFIG",
5800   "type_ref": "VGT_STRMOUT_CONFIG"
5801  },
5802  {
5803   "chips": ["gfx10"],
5804   "map": {"at": 166808, "to": "mm"},
5805   "name": "VGT_STRMOUT_BUFFER_CONFIG",
5806   "type_ref": "VGT_STRMOUT_BUFFER_CONFIG"
5807  },
5808  {
5809   "chips": ["gfx10"],
5810   "map": {"at": 166812, "to": "mm"},
5811   "name": "VGT_DMA_EVENT_INITIATOR",
5812   "type_ref": "VGT_EVENT_INITIATOR"
5813  },
5814  {
5815   "chips": ["gfx10"],
5816   "map": {"at": 166868, "to": "mm"},
5817   "name": "PA_SC_CENTROID_PRIORITY_0",
5818   "type_ref": "PA_SC_CENTROID_PRIORITY_0"
5819  },
5820  {
5821   "chips": ["gfx10"],
5822   "map": {"at": 166872, "to": "mm"},
5823   "name": "PA_SC_CENTROID_PRIORITY_1",
5824   "type_ref": "PA_SC_CENTROID_PRIORITY_1"
5825  },
5826  {
5827   "chips": ["gfx10"],
5828   "map": {"at": 166876, "to": "mm"},
5829   "name": "PA_SC_LINE_CNTL",
5830   "type_ref": "PA_SC_LINE_CNTL"
5831  },
5832  {
5833   "chips": ["gfx10"],
5834   "map": {"at": 166880, "to": "mm"},
5835   "name": "PA_SC_AA_CONFIG",
5836   "type_ref": "PA_SC_AA_CONFIG"
5837  },
5838  {
5839   "chips": ["gfx10"],
5840   "map": {"at": 166884, "to": "mm"},
5841   "name": "PA_SU_VTX_CNTL",
5842   "type_ref": "PA_SU_VTX_CNTL"
5843  },
5844  {
5845   "chips": ["gfx10"],
5846   "map": {"at": 166888, "to": "mm"},
5847   "name": "PA_CL_GB_VERT_CLIP_ADJ"
5848  },
5849  {
5850   "chips": ["gfx10"],
5851   "map": {"at": 166892, "to": "mm"},
5852   "name": "PA_CL_GB_VERT_DISC_ADJ"
5853  },
5854  {
5855   "chips": ["gfx10"],
5856   "map": {"at": 166896, "to": "mm"},
5857   "name": "PA_CL_GB_HORZ_CLIP_ADJ"
5858  },
5859  {
5860   "chips": ["gfx10"],
5861   "map": {"at": 166900, "to": "mm"},
5862   "name": "PA_CL_GB_HORZ_DISC_ADJ"
5863  },
5864  {
5865   "chips": ["gfx10"],
5866   "map": {"at": 166904, "to": "mm"},
5867   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0",
5868   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
5869  },
5870  {
5871   "chips": ["gfx10"],
5872   "map": {"at": 166908, "to": "mm"},
5873   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1",
5874   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
5875  },
5876  {
5877   "chips": ["gfx10"],
5878   "map": {"at": 166912, "to": "mm"},
5879   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2",
5880   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
5881  },
5882  {
5883   "chips": ["gfx10"],
5884   "map": {"at": 166916, "to": "mm"},
5885   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3",
5886   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
5887  },
5888  {
5889   "chips": ["gfx10"],
5890   "map": {"at": 166920, "to": "mm"},
5891   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0",
5892   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
5893  },
5894  {
5895   "chips": ["gfx10"],
5896   "map": {"at": 166924, "to": "mm"},
5897   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1",
5898   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
5899  },
5900  {
5901   "chips": ["gfx10"],
5902   "map": {"at": 166928, "to": "mm"},
5903   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2",
5904   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
5905  },
5906  {
5907   "chips": ["gfx10"],
5908   "map": {"at": 166932, "to": "mm"},
5909   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3",
5910   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
5911  },
5912  {
5913   "chips": ["gfx10"],
5914   "map": {"at": 166936, "to": "mm"},
5915   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0",
5916   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
5917  },
5918  {
5919   "chips": ["gfx10"],
5920   "map": {"at": 166940, "to": "mm"},
5921   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1",
5922   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
5923  },
5924  {
5925   "chips": ["gfx10"],
5926   "map": {"at": 166944, "to": "mm"},
5927   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2",
5928   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
5929  },
5930  {
5931   "chips": ["gfx10"],
5932   "map": {"at": 166948, "to": "mm"},
5933   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3",
5934   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
5935  },
5936  {
5937   "chips": ["gfx10"],
5938   "map": {"at": 166952, "to": "mm"},
5939   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0",
5940   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
5941  },
5942  {
5943   "chips": ["gfx10"],
5944   "map": {"at": 166956, "to": "mm"},
5945   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1",
5946   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
5947  },
5948  {
5949   "chips": ["gfx10"],
5950   "map": {"at": 166960, "to": "mm"},
5951   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2",
5952   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
5953  },
5954  {
5955   "chips": ["gfx10"],
5956   "map": {"at": 166964, "to": "mm"},
5957   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3",
5958   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
5959  },
5960  {
5961   "chips": ["gfx10"],
5962   "map": {"at": 166968, "to": "mm"},
5963   "name": "PA_SC_AA_MASK_X0Y0_X1Y0",
5964   "type_ref": "PA_SC_AA_MASK_X0Y0_X1Y0"
5965  },
5966  {
5967   "chips": ["gfx10"],
5968   "map": {"at": 166972, "to": "mm"},
5969   "name": "PA_SC_AA_MASK_X0Y1_X1Y1",
5970   "type_ref": "PA_SC_AA_MASK_X0Y1_X1Y1"
5971  },
5972  {
5973   "chips": ["gfx10"],
5974   "map": {"at": 166976, "to": "mm"},
5975   "name": "PA_SC_SHADER_CONTROL",
5976   "type_ref": "PA_SC_SHADER_CONTROL"
5977  },
5978  {
5979   "chips": ["gfx10"],
5980   "map": {"at": 166980, "to": "mm"},
5981   "name": "PA_SC_BINNER_CNTL_0",
5982   "type_ref": "PA_SC_BINNER_CNTL_0"
5983  },
5984  {
5985   "chips": ["gfx10"],
5986   "map": {"at": 166984, "to": "mm"},
5987   "name": "PA_SC_BINNER_CNTL_1",
5988   "type_ref": "PA_SC_BINNER_CNTL_1"
5989  },
5990  {
5991   "chips": ["gfx10"],
5992   "map": {"at": 166988, "to": "mm"},
5993   "name": "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL",
5994   "type_ref": "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL"
5995  },
5996  {
5997   "chips": ["gfx10"],
5998   "map": {"at": 166992, "to": "mm"},
5999   "name": "PA_SC_NGG_MODE_CNTL",
6000   "type_ref": "PA_SC_NGG_MODE_CNTL"
6001  },
6002  {
6003   "chips": ["gfx10"],
6004   "map": {"at": 167000, "to": "mm"},
6005   "name": "VGT_VERTEX_REUSE_BLOCK_CNTL",
6006   "type_ref": "VGT_VERTEX_REUSE_BLOCK_CNTL"
6007  },
6008  {
6009   "chips": ["gfx10"],
6010   "map": {"at": 167004, "to": "mm"},
6011   "name": "VGT_OUT_DEALLOC_CNTL",
6012   "type_ref": "VGT_OUT_DEALLOC_CNTL"
6013  },
6014  {
6015   "chips": ["gfx10"],
6016   "map": {"at": 167008, "to": "mm"},
6017   "name": "CB_COLOR0_BASE"
6018  },
6019  {
6020   "chips": ["gfx10"],
6021   "map": {"at": 167012, "to": "mm"},
6022   "name": "CB_COLOR0_PITCH",
6023   "type_ref": "CB_COLOR0_PITCH"
6024  },
6025  {
6026   "chips": ["gfx10"],
6027   "map": {"at": 167016, "to": "mm"},
6028   "name": "CB_COLOR0_SLICE",
6029   "type_ref": "CB_COLOR0_SLICE"
6030  },
6031  {
6032   "chips": ["gfx10"],
6033   "map": {"at": 167020, "to": "mm"},
6034   "name": "CB_COLOR0_VIEW",
6035   "type_ref": "CB_COLOR0_VIEW"
6036  },
6037  {
6038   "chips": ["gfx10"],
6039   "map": {"at": 167024, "to": "mm"},
6040   "name": "CB_COLOR0_INFO",
6041   "type_ref": "CB_COLOR0_INFO"
6042  },
6043  {
6044   "chips": ["gfx10"],
6045   "map": {"at": 167028, "to": "mm"},
6046   "name": "CB_COLOR0_ATTRIB",
6047   "type_ref": "CB_COLOR0_ATTRIB"
6048  },
6049  {
6050   "chips": ["gfx10"],
6051   "map": {"at": 167032, "to": "mm"},
6052   "name": "CB_COLOR0_DCC_CONTROL",
6053   "type_ref": "CB_COLOR0_DCC_CONTROL"
6054  },
6055  {
6056   "chips": ["gfx10"],
6057   "map": {"at": 167036, "to": "mm"},
6058   "name": "CB_COLOR0_CMASK"
6059  },
6060  {
6061   "chips": ["gfx10"],
6062   "map": {"at": 167040, "to": "mm"},
6063   "name": "CB_COLOR0_CMASK_SLICE",
6064   "type_ref": "CB_COLOR0_CMASK_SLICE"
6065  },
6066  {
6067   "chips": ["gfx10"],
6068   "map": {"at": 167044, "to": "mm"},
6069   "name": "CB_COLOR0_FMASK"
6070  },
6071  {
6072   "chips": ["gfx10"],
6073   "map": {"at": 167048, "to": "mm"},
6074   "name": "CB_COLOR0_FMASK_SLICE",
6075   "type_ref": "CB_COLOR0_SLICE"
6076  },
6077  {
6078   "chips": ["gfx10"],
6079   "map": {"at": 167052, "to": "mm"},
6080   "name": "CB_COLOR0_CLEAR_WORD0"
6081  },
6082  {
6083   "chips": ["gfx10"],
6084   "map": {"at": 167056, "to": "mm"},
6085   "name": "CB_COLOR0_CLEAR_WORD1"
6086  },
6087  {
6088   "chips": ["gfx10"],
6089   "map": {"at": 167060, "to": "mm"},
6090   "name": "CB_COLOR0_DCC_BASE"
6091  },
6092  {
6093   "chips": ["gfx10"],
6094   "map": {"at": 167068, "to": "mm"},
6095   "name": "CB_COLOR1_BASE"
6096  },
6097  {
6098   "chips": ["gfx10"],
6099   "map": {"at": 167072, "to": "mm"},
6100   "name": "CB_COLOR1_PITCH",
6101   "type_ref": "CB_COLOR0_PITCH"
6102  },
6103  {
6104   "chips": ["gfx10"],
6105   "map": {"at": 167076, "to": "mm"},
6106   "name": "CB_COLOR1_SLICE",
6107   "type_ref": "CB_COLOR0_SLICE"
6108  },
6109  {
6110   "chips": ["gfx10"],
6111   "map": {"at": 167080, "to": "mm"},
6112   "name": "CB_COLOR1_VIEW",
6113   "type_ref": "CB_COLOR0_VIEW"
6114  },
6115  {
6116   "chips": ["gfx10"],
6117   "map": {"at": 167084, "to": "mm"},
6118   "name": "CB_COLOR1_INFO",
6119   "type_ref": "CB_COLOR0_INFO"
6120  },
6121  {
6122   "chips": ["gfx10"],
6123   "map": {"at": 167088, "to": "mm"},
6124   "name": "CB_COLOR1_ATTRIB",
6125   "type_ref": "CB_COLOR0_ATTRIB"
6126  },
6127  {
6128   "chips": ["gfx10"],
6129   "map": {"at": 167092, "to": "mm"},
6130   "name": "CB_COLOR1_DCC_CONTROL",
6131   "type_ref": "CB_COLOR0_DCC_CONTROL"
6132  },
6133  {
6134   "chips": ["gfx10"],
6135   "map": {"at": 167096, "to": "mm"},
6136   "name": "CB_COLOR1_CMASK"
6137  },
6138  {
6139   "chips": ["gfx10"],
6140   "map": {"at": 167100, "to": "mm"},
6141   "name": "CB_COLOR1_CMASK_SLICE",
6142   "type_ref": "CB_COLOR0_CMASK_SLICE"
6143  },
6144  {
6145   "chips": ["gfx10"],
6146   "map": {"at": 167104, "to": "mm"},
6147   "name": "CB_COLOR1_FMASK"
6148  },
6149  {
6150   "chips": ["gfx10"],
6151   "map": {"at": 167108, "to": "mm"},
6152   "name": "CB_COLOR1_FMASK_SLICE",
6153   "type_ref": "CB_COLOR0_SLICE"
6154  },
6155  {
6156   "chips": ["gfx10"],
6157   "map": {"at": 167112, "to": "mm"},
6158   "name": "CB_COLOR1_CLEAR_WORD0"
6159  },
6160  {
6161   "chips": ["gfx10"],
6162   "map": {"at": 167116, "to": "mm"},
6163   "name": "CB_COLOR1_CLEAR_WORD1"
6164  },
6165  {
6166   "chips": ["gfx10"],
6167   "map": {"at": 167120, "to": "mm"},
6168   "name": "CB_COLOR1_DCC_BASE"
6169  },
6170  {
6171   "chips": ["gfx10"],
6172   "map": {"at": 167128, "to": "mm"},
6173   "name": "CB_COLOR2_BASE"
6174  },
6175  {
6176   "chips": ["gfx10"],
6177   "map": {"at": 167132, "to": "mm"},
6178   "name": "CB_COLOR2_PITCH",
6179   "type_ref": "CB_COLOR0_PITCH"
6180  },
6181  {
6182   "chips": ["gfx10"],
6183   "map": {"at": 167136, "to": "mm"},
6184   "name": "CB_COLOR2_SLICE",
6185   "type_ref": "CB_COLOR0_SLICE"
6186  },
6187  {
6188   "chips": ["gfx10"],
6189   "map": {"at": 167140, "to": "mm"},
6190   "name": "CB_COLOR2_VIEW",
6191   "type_ref": "CB_COLOR0_VIEW"
6192  },
6193  {
6194   "chips": ["gfx10"],
6195   "map": {"at": 167144, "to": "mm"},
6196   "name": "CB_COLOR2_INFO",
6197   "type_ref": "CB_COLOR0_INFO"
6198  },
6199  {
6200   "chips": ["gfx10"],
6201   "map": {"at": 167148, "to": "mm"},
6202   "name": "CB_COLOR2_ATTRIB",
6203   "type_ref": "CB_COLOR0_ATTRIB"
6204  },
6205  {
6206   "chips": ["gfx10"],
6207   "map": {"at": 167152, "to": "mm"},
6208   "name": "CB_COLOR2_DCC_CONTROL",
6209   "type_ref": "CB_COLOR0_DCC_CONTROL"
6210  },
6211  {
6212   "chips": ["gfx10"],
6213   "map": {"at": 167156, "to": "mm"},
6214   "name": "CB_COLOR2_CMASK"
6215  },
6216  {
6217   "chips": ["gfx10"],
6218   "map": {"at": 167160, "to": "mm"},
6219   "name": "CB_COLOR2_CMASK_SLICE",
6220   "type_ref": "CB_COLOR0_CMASK_SLICE"
6221  },
6222  {
6223   "chips": ["gfx10"],
6224   "map": {"at": 167164, "to": "mm"},
6225   "name": "CB_COLOR2_FMASK"
6226  },
6227  {
6228   "chips": ["gfx10"],
6229   "map": {"at": 167168, "to": "mm"},
6230   "name": "CB_COLOR2_FMASK_SLICE",
6231   "type_ref": "CB_COLOR0_SLICE"
6232  },
6233  {
6234   "chips": ["gfx10"],
6235   "map": {"at": 167172, "to": "mm"},
6236   "name": "CB_COLOR2_CLEAR_WORD0"
6237  },
6238  {
6239   "chips": ["gfx10"],
6240   "map": {"at": 167176, "to": "mm"},
6241   "name": "CB_COLOR2_CLEAR_WORD1"
6242  },
6243  {
6244   "chips": ["gfx10"],
6245   "map": {"at": 167180, "to": "mm"},
6246   "name": "CB_COLOR2_DCC_BASE"
6247  },
6248  {
6249   "chips": ["gfx10"],
6250   "map": {"at": 167188, "to": "mm"},
6251   "name": "CB_COLOR3_BASE"
6252  },
6253  {
6254   "chips": ["gfx10"],
6255   "map": {"at": 167192, "to": "mm"},
6256   "name": "CB_COLOR3_PITCH",
6257   "type_ref": "CB_COLOR0_PITCH"
6258  },
6259  {
6260   "chips": ["gfx10"],
6261   "map": {"at": 167196, "to": "mm"},
6262   "name": "CB_COLOR3_SLICE",
6263   "type_ref": "CB_COLOR0_SLICE"
6264  },
6265  {
6266   "chips": ["gfx10"],
6267   "map": {"at": 167200, "to": "mm"},
6268   "name": "CB_COLOR3_VIEW",
6269   "type_ref": "CB_COLOR0_VIEW"
6270  },
6271  {
6272   "chips": ["gfx10"],
6273   "map": {"at": 167204, "to": "mm"},
6274   "name": "CB_COLOR3_INFO",
6275   "type_ref": "CB_COLOR0_INFO"
6276  },
6277  {
6278   "chips": ["gfx10"],
6279   "map": {"at": 167208, "to": "mm"},
6280   "name": "CB_COLOR3_ATTRIB",
6281   "type_ref": "CB_COLOR0_ATTRIB"
6282  },
6283  {
6284   "chips": ["gfx10"],
6285   "map": {"at": 167212, "to": "mm"},
6286   "name": "CB_COLOR3_DCC_CONTROL",
6287   "type_ref": "CB_COLOR0_DCC_CONTROL"
6288  },
6289  {
6290   "chips": ["gfx10"],
6291   "map": {"at": 167216, "to": "mm"},
6292   "name": "CB_COLOR3_CMASK"
6293  },
6294  {
6295   "chips": ["gfx10"],
6296   "map": {"at": 167220, "to": "mm"},
6297   "name": "CB_COLOR3_CMASK_SLICE",
6298   "type_ref": "CB_COLOR0_CMASK_SLICE"
6299  },
6300  {
6301   "chips": ["gfx10"],
6302   "map": {"at": 167224, "to": "mm"},
6303   "name": "CB_COLOR3_FMASK"
6304  },
6305  {
6306   "chips": ["gfx10"],
6307   "map": {"at": 167228, "to": "mm"},
6308   "name": "CB_COLOR3_FMASK_SLICE",
6309   "type_ref": "CB_COLOR0_SLICE"
6310  },
6311  {
6312   "chips": ["gfx10"],
6313   "map": {"at": 167232, "to": "mm"},
6314   "name": "CB_COLOR3_CLEAR_WORD0"
6315  },
6316  {
6317   "chips": ["gfx10"],
6318   "map": {"at": 167236, "to": "mm"},
6319   "name": "CB_COLOR3_CLEAR_WORD1"
6320  },
6321  {
6322   "chips": ["gfx10"],
6323   "map": {"at": 167240, "to": "mm"},
6324   "name": "CB_COLOR3_DCC_BASE"
6325  },
6326  {
6327   "chips": ["gfx10"],
6328   "map": {"at": 167248, "to": "mm"},
6329   "name": "CB_COLOR4_BASE"
6330  },
6331  {
6332   "chips": ["gfx10"],
6333   "map": {"at": 167252, "to": "mm"},
6334   "name": "CB_COLOR4_PITCH",
6335   "type_ref": "CB_COLOR0_PITCH"
6336  },
6337  {
6338   "chips": ["gfx10"],
6339   "map": {"at": 167256, "to": "mm"},
6340   "name": "CB_COLOR4_SLICE",
6341   "type_ref": "CB_COLOR0_SLICE"
6342  },
6343  {
6344   "chips": ["gfx10"],
6345   "map": {"at": 167260, "to": "mm"},
6346   "name": "CB_COLOR4_VIEW",
6347   "type_ref": "CB_COLOR0_VIEW"
6348  },
6349  {
6350   "chips": ["gfx10"],
6351   "map": {"at": 167264, "to": "mm"},
6352   "name": "CB_COLOR4_INFO",
6353   "type_ref": "CB_COLOR0_INFO"
6354  },
6355  {
6356   "chips": ["gfx10"],
6357   "map": {"at": 167268, "to": "mm"},
6358   "name": "CB_COLOR4_ATTRIB",
6359   "type_ref": "CB_COLOR0_ATTRIB"
6360  },
6361  {
6362   "chips": ["gfx10"],
6363   "map": {"at": 167272, "to": "mm"},
6364   "name": "CB_COLOR4_DCC_CONTROL",
6365   "type_ref": "CB_COLOR0_DCC_CONTROL"
6366  },
6367  {
6368   "chips": ["gfx10"],
6369   "map": {"at": 167276, "to": "mm"},
6370   "name": "CB_COLOR4_CMASK"
6371  },
6372  {
6373   "chips": ["gfx10"],
6374   "map": {"at": 167280, "to": "mm"},
6375   "name": "CB_COLOR4_CMASK_SLICE",
6376   "type_ref": "CB_COLOR0_CMASK_SLICE"
6377  },
6378  {
6379   "chips": ["gfx10"],
6380   "map": {"at": 167284, "to": "mm"},
6381   "name": "CB_COLOR4_FMASK"
6382  },
6383  {
6384   "chips": ["gfx10"],
6385   "map": {"at": 167288, "to": "mm"},
6386   "name": "CB_COLOR4_FMASK_SLICE",
6387   "type_ref": "CB_COLOR0_SLICE"
6388  },
6389  {
6390   "chips": ["gfx10"],
6391   "map": {"at": 167292, "to": "mm"},
6392   "name": "CB_COLOR4_CLEAR_WORD0"
6393  },
6394  {
6395   "chips": ["gfx10"],
6396   "map": {"at": 167296, "to": "mm"},
6397   "name": "CB_COLOR4_CLEAR_WORD1"
6398  },
6399  {
6400   "chips": ["gfx10"],
6401   "map": {"at": 167300, "to": "mm"},
6402   "name": "CB_COLOR4_DCC_BASE"
6403  },
6404  {
6405   "chips": ["gfx10"],
6406   "map": {"at": 167308, "to": "mm"},
6407   "name": "CB_COLOR5_BASE"
6408  },
6409  {
6410   "chips": ["gfx10"],
6411   "map": {"at": 167312, "to": "mm"},
6412   "name": "CB_COLOR5_PITCH",
6413   "type_ref": "CB_COLOR0_PITCH"
6414  },
6415  {
6416   "chips": ["gfx10"],
6417   "map": {"at": 167316, "to": "mm"},
6418   "name": "CB_COLOR5_SLICE",
6419   "type_ref": "CB_COLOR0_SLICE"
6420  },
6421  {
6422   "chips": ["gfx10"],
6423   "map": {"at": 167320, "to": "mm"},
6424   "name": "CB_COLOR5_VIEW",
6425   "type_ref": "CB_COLOR0_VIEW"
6426  },
6427  {
6428   "chips": ["gfx10"],
6429   "map": {"at": 167324, "to": "mm"},
6430   "name": "CB_COLOR5_INFO",
6431   "type_ref": "CB_COLOR0_INFO"
6432  },
6433  {
6434   "chips": ["gfx10"],
6435   "map": {"at": 167328, "to": "mm"},
6436   "name": "CB_COLOR5_ATTRIB",
6437   "type_ref": "CB_COLOR0_ATTRIB"
6438  },
6439  {
6440   "chips": ["gfx10"],
6441   "map": {"at": 167332, "to": "mm"},
6442   "name": "CB_COLOR5_DCC_CONTROL",
6443   "type_ref": "CB_COLOR0_DCC_CONTROL"
6444  },
6445  {
6446   "chips": ["gfx10"],
6447   "map": {"at": 167336, "to": "mm"},
6448   "name": "CB_COLOR5_CMASK"
6449  },
6450  {
6451   "chips": ["gfx10"],
6452   "map": {"at": 167340, "to": "mm"},
6453   "name": "CB_COLOR5_CMASK_SLICE",
6454   "type_ref": "CB_COLOR0_CMASK_SLICE"
6455  },
6456  {
6457   "chips": ["gfx10"],
6458   "map": {"at": 167344, "to": "mm"},
6459   "name": "CB_COLOR5_FMASK"
6460  },
6461  {
6462   "chips": ["gfx10"],
6463   "map": {"at": 167348, "to": "mm"},
6464   "name": "CB_COLOR5_FMASK_SLICE",
6465   "type_ref": "CB_COLOR0_SLICE"
6466  },
6467  {
6468   "chips": ["gfx10"],
6469   "map": {"at": 167352, "to": "mm"},
6470   "name": "CB_COLOR5_CLEAR_WORD0"
6471  },
6472  {
6473   "chips": ["gfx10"],
6474   "map": {"at": 167356, "to": "mm"},
6475   "name": "CB_COLOR5_CLEAR_WORD1"
6476  },
6477  {
6478   "chips": ["gfx10"],
6479   "map": {"at": 167360, "to": "mm"},
6480   "name": "CB_COLOR5_DCC_BASE"
6481  },
6482  {
6483   "chips": ["gfx10"],
6484   "map": {"at": 167368, "to": "mm"},
6485   "name": "CB_COLOR6_BASE"
6486  },
6487  {
6488   "chips": ["gfx10"],
6489   "map": {"at": 167372, "to": "mm"},
6490   "name": "CB_COLOR6_PITCH",
6491   "type_ref": "CB_COLOR0_PITCH"
6492  },
6493  {
6494   "chips": ["gfx10"],
6495   "map": {"at": 167376, "to": "mm"},
6496   "name": "CB_COLOR6_SLICE",
6497   "type_ref": "CB_COLOR0_SLICE"
6498  },
6499  {
6500   "chips": ["gfx10"],
6501   "map": {"at": 167380, "to": "mm"},
6502   "name": "CB_COLOR6_VIEW",
6503   "type_ref": "CB_COLOR0_VIEW"
6504  },
6505  {
6506   "chips": ["gfx10"],
6507   "map": {"at": 167384, "to": "mm"},
6508   "name": "CB_COLOR6_INFO",
6509   "type_ref": "CB_COLOR0_INFO"
6510  },
6511  {
6512   "chips": ["gfx10"],
6513   "map": {"at": 167388, "to": "mm"},
6514   "name": "CB_COLOR6_ATTRIB",
6515   "type_ref": "CB_COLOR0_ATTRIB"
6516  },
6517  {
6518   "chips": ["gfx10"],
6519   "map": {"at": 167392, "to": "mm"},
6520   "name": "CB_COLOR6_DCC_CONTROL",
6521   "type_ref": "CB_COLOR0_DCC_CONTROL"
6522  },
6523  {
6524   "chips": ["gfx10"],
6525   "map": {"at": 167396, "to": "mm"},
6526   "name": "CB_COLOR6_CMASK"
6527  },
6528  {
6529   "chips": ["gfx10"],
6530   "map": {"at": 167400, "to": "mm"},
6531   "name": "CB_COLOR6_CMASK_SLICE",
6532   "type_ref": "CB_COLOR0_CMASK_SLICE"
6533  },
6534  {
6535   "chips": ["gfx10"],
6536   "map": {"at": 167404, "to": "mm"},
6537   "name": "CB_COLOR6_FMASK"
6538  },
6539  {
6540   "chips": ["gfx10"],
6541   "map": {"at": 167408, "to": "mm"},
6542   "name": "CB_COLOR6_FMASK_SLICE",
6543   "type_ref": "CB_COLOR0_SLICE"
6544  },
6545  {
6546   "chips": ["gfx10"],
6547   "map": {"at": 167412, "to": "mm"},
6548   "name": "CB_COLOR6_CLEAR_WORD0"
6549  },
6550  {
6551   "chips": ["gfx10"],
6552   "map": {"at": 167416, "to": "mm"},
6553   "name": "CB_COLOR6_CLEAR_WORD1"
6554  },
6555  {
6556   "chips": ["gfx10"],
6557   "map": {"at": 167420, "to": "mm"},
6558   "name": "CB_COLOR6_DCC_BASE"
6559  },
6560  {
6561   "chips": ["gfx10"],
6562   "map": {"at": 167428, "to": "mm"},
6563   "name": "CB_COLOR7_BASE"
6564  },
6565  {
6566   "chips": ["gfx10"],
6567   "map": {"at": 167432, "to": "mm"},
6568   "name": "CB_COLOR7_PITCH",
6569   "type_ref": "CB_COLOR0_PITCH"
6570  },
6571  {
6572   "chips": ["gfx10"],
6573   "map": {"at": 167436, "to": "mm"},
6574   "name": "CB_COLOR7_SLICE",
6575   "type_ref": "CB_COLOR0_SLICE"
6576  },
6577  {
6578   "chips": ["gfx10"],
6579   "map": {"at": 167440, "to": "mm"},
6580   "name": "CB_COLOR7_VIEW",
6581   "type_ref": "CB_COLOR0_VIEW"
6582  },
6583  {
6584   "chips": ["gfx10"],
6585   "map": {"at": 167444, "to": "mm"},
6586   "name": "CB_COLOR7_INFO",
6587   "type_ref": "CB_COLOR0_INFO"
6588  },
6589  {
6590   "chips": ["gfx10"],
6591   "map": {"at": 167448, "to": "mm"},
6592   "name": "CB_COLOR7_ATTRIB",
6593   "type_ref": "CB_COLOR0_ATTRIB"
6594  },
6595  {
6596   "chips": ["gfx10"],
6597   "map": {"at": 167452, "to": "mm"},
6598   "name": "CB_COLOR7_DCC_CONTROL",
6599   "type_ref": "CB_COLOR0_DCC_CONTROL"
6600  },
6601  {
6602   "chips": ["gfx10"],
6603   "map": {"at": 167456, "to": "mm"},
6604   "name": "CB_COLOR7_CMASK"
6605  },
6606  {
6607   "chips": ["gfx10"],
6608   "map": {"at": 167460, "to": "mm"},
6609   "name": "CB_COLOR7_CMASK_SLICE",
6610   "type_ref": "CB_COLOR0_CMASK_SLICE"
6611  },
6612  {
6613   "chips": ["gfx10"],
6614   "map": {"at": 167464, "to": "mm"},
6615   "name": "CB_COLOR7_FMASK"
6616  },
6617  {
6618   "chips": ["gfx10"],
6619   "map": {"at": 167468, "to": "mm"},
6620   "name": "CB_COLOR7_FMASK_SLICE",
6621   "type_ref": "CB_COLOR0_SLICE"
6622  },
6623  {
6624   "chips": ["gfx10"],
6625   "map": {"at": 167472, "to": "mm"},
6626   "name": "CB_COLOR7_CLEAR_WORD0"
6627  },
6628  {
6629   "chips": ["gfx10"],
6630   "map": {"at": 167476, "to": "mm"},
6631   "name": "CB_COLOR7_CLEAR_WORD1"
6632  },
6633  {
6634   "chips": ["gfx10"],
6635   "map": {"at": 167480, "to": "mm"},
6636   "name": "CB_COLOR7_DCC_BASE"
6637  },
6638  {
6639   "chips": ["gfx10"],
6640   "map": {"at": 167488, "to": "mm"},
6641   "name": "CB_COLOR0_BASE_EXT",
6642   "type_ref": "CB_COLOR0_BASE_EXT"
6643  },
6644  {
6645   "chips": ["gfx10"],
6646   "map": {"at": 167492, "to": "mm"},
6647   "name": "CB_COLOR1_BASE_EXT",
6648   "type_ref": "CB_COLOR0_BASE_EXT"
6649  },
6650  {
6651   "chips": ["gfx10"],
6652   "map": {"at": 167496, "to": "mm"},
6653   "name": "CB_COLOR2_BASE_EXT",
6654   "type_ref": "CB_COLOR0_BASE_EXT"
6655  },
6656  {
6657   "chips": ["gfx10"],
6658   "map": {"at": 167500, "to": "mm"},
6659   "name": "CB_COLOR3_BASE_EXT",
6660   "type_ref": "CB_COLOR0_BASE_EXT"
6661  },
6662  {
6663   "chips": ["gfx10"],
6664   "map": {"at": 167504, "to": "mm"},
6665   "name": "CB_COLOR4_BASE_EXT",
6666   "type_ref": "CB_COLOR0_BASE_EXT"
6667  },
6668  {
6669   "chips": ["gfx10"],
6670   "map": {"at": 167508, "to": "mm"},
6671   "name": "CB_COLOR5_BASE_EXT",
6672   "type_ref": "CB_COLOR0_BASE_EXT"
6673  },
6674  {
6675   "chips": ["gfx10"],
6676   "map": {"at": 167512, "to": "mm"},
6677   "name": "CB_COLOR6_BASE_EXT",
6678   "type_ref": "CB_COLOR0_BASE_EXT"
6679  },
6680  {
6681   "chips": ["gfx10"],
6682   "map": {"at": 167516, "to": "mm"},
6683   "name": "CB_COLOR7_BASE_EXT",
6684   "type_ref": "CB_COLOR0_BASE_EXT"
6685  },
6686  {
6687   "chips": ["gfx10"],
6688   "map": {"at": 167520, "to": "mm"},
6689   "name": "CB_COLOR0_CMASK_BASE_EXT",
6690   "type_ref": "CB_COLOR0_BASE_EXT"
6691  },
6692  {
6693   "chips": ["gfx10"],
6694   "map": {"at": 167524, "to": "mm"},
6695   "name": "CB_COLOR1_CMASK_BASE_EXT",
6696   "type_ref": "CB_COLOR0_BASE_EXT"
6697  },
6698  {
6699   "chips": ["gfx10"],
6700   "map": {"at": 167528, "to": "mm"},
6701   "name": "CB_COLOR2_CMASK_BASE_EXT",
6702   "type_ref": "CB_COLOR0_BASE_EXT"
6703  },
6704  {
6705   "chips": ["gfx10"],
6706   "map": {"at": 167532, "to": "mm"},
6707   "name": "CB_COLOR3_CMASK_BASE_EXT",
6708   "type_ref": "CB_COLOR0_BASE_EXT"
6709  },
6710  {
6711   "chips": ["gfx10"],
6712   "map": {"at": 167536, "to": "mm"},
6713   "name": "CB_COLOR4_CMASK_BASE_EXT",
6714   "type_ref": "CB_COLOR0_BASE_EXT"
6715  },
6716  {
6717   "chips": ["gfx10"],
6718   "map": {"at": 167540, "to": "mm"},
6719   "name": "CB_COLOR5_CMASK_BASE_EXT",
6720   "type_ref": "CB_COLOR0_BASE_EXT"
6721  },
6722  {
6723   "chips": ["gfx10"],
6724   "map": {"at": 167544, "to": "mm"},
6725   "name": "CB_COLOR6_CMASK_BASE_EXT",
6726   "type_ref": "CB_COLOR0_BASE_EXT"
6727  },
6728  {
6729   "chips": ["gfx10"],
6730   "map": {"at": 167548, "to": "mm"},
6731   "name": "CB_COLOR7_CMASK_BASE_EXT",
6732   "type_ref": "CB_COLOR0_BASE_EXT"
6733  },
6734  {
6735   "chips": ["gfx10"],
6736   "map": {"at": 167552, "to": "mm"},
6737   "name": "CB_COLOR0_FMASK_BASE_EXT",
6738   "type_ref": "CB_COLOR0_BASE_EXT"
6739  },
6740  {
6741   "chips": ["gfx10"],
6742   "map": {"at": 167556, "to": "mm"},
6743   "name": "CB_COLOR1_FMASK_BASE_EXT",
6744   "type_ref": "CB_COLOR0_BASE_EXT"
6745  },
6746  {
6747   "chips": ["gfx10"],
6748   "map": {"at": 167560, "to": "mm"},
6749   "name": "CB_COLOR2_FMASK_BASE_EXT",
6750   "type_ref": "CB_COLOR0_BASE_EXT"
6751  },
6752  {
6753   "chips": ["gfx10"],
6754   "map": {"at": 167564, "to": "mm"},
6755   "name": "CB_COLOR3_FMASK_BASE_EXT",
6756   "type_ref": "CB_COLOR0_BASE_EXT"
6757  },
6758  {
6759   "chips": ["gfx10"],
6760   "map": {"at": 167568, "to": "mm"},
6761   "name": "CB_COLOR4_FMASK_BASE_EXT",
6762   "type_ref": "CB_COLOR0_BASE_EXT"
6763  },
6764  {
6765   "chips": ["gfx10"],
6766   "map": {"at": 167572, "to": "mm"},
6767   "name": "CB_COLOR5_FMASK_BASE_EXT",
6768   "type_ref": "CB_COLOR0_BASE_EXT"
6769  },
6770  {
6771   "chips": ["gfx10"],
6772   "map": {"at": 167576, "to": "mm"},
6773   "name": "CB_COLOR6_FMASK_BASE_EXT",
6774   "type_ref": "CB_COLOR0_BASE_EXT"
6775  },
6776  {
6777   "chips": ["gfx10"],
6778   "map": {"at": 167580, "to": "mm"},
6779   "name": "CB_COLOR7_FMASK_BASE_EXT",
6780   "type_ref": "CB_COLOR0_BASE_EXT"
6781  },
6782  {
6783   "chips": ["gfx10"],
6784   "map": {"at": 167584, "to": "mm"},
6785   "name": "CB_COLOR0_DCC_BASE_EXT",
6786   "type_ref": "CB_COLOR0_BASE_EXT"
6787  },
6788  {
6789   "chips": ["gfx10"],
6790   "map": {"at": 167588, "to": "mm"},
6791   "name": "CB_COLOR1_DCC_BASE_EXT",
6792   "type_ref": "CB_COLOR0_BASE_EXT"
6793  },
6794  {
6795   "chips": ["gfx10"],
6796   "map": {"at": 167592, "to": "mm"},
6797   "name": "CB_COLOR2_DCC_BASE_EXT",
6798   "type_ref": "CB_COLOR0_BASE_EXT"
6799  },
6800  {
6801   "chips": ["gfx10"],
6802   "map": {"at": 167596, "to": "mm"},
6803   "name": "CB_COLOR3_DCC_BASE_EXT",
6804   "type_ref": "CB_COLOR0_BASE_EXT"
6805  },
6806  {
6807   "chips": ["gfx10"],
6808   "map": {"at": 167600, "to": "mm"},
6809   "name": "CB_COLOR4_DCC_BASE_EXT",
6810   "type_ref": "CB_COLOR0_BASE_EXT"
6811  },
6812  {
6813   "chips": ["gfx10"],
6814   "map": {"at": 167604, "to": "mm"},
6815   "name": "CB_COLOR5_DCC_BASE_EXT",
6816   "type_ref": "CB_COLOR0_BASE_EXT"
6817  },
6818  {
6819   "chips": ["gfx10"],
6820   "map": {"at": 167608, "to": "mm"},
6821   "name": "CB_COLOR6_DCC_BASE_EXT",
6822   "type_ref": "CB_COLOR0_BASE_EXT"
6823  },
6824  {
6825   "chips": ["gfx10"],
6826   "map": {"at": 167612, "to": "mm"},
6827   "name": "CB_COLOR7_DCC_BASE_EXT",
6828   "type_ref": "CB_COLOR0_BASE_EXT"
6829  },
6830  {
6831   "chips": ["gfx10"],
6832   "map": {"at": 167616, "to": "mm"},
6833   "name": "CB_COLOR0_ATTRIB2",
6834   "type_ref": "CB_COLOR0_ATTRIB2"
6835  },
6836  {
6837   "chips": ["gfx10"],
6838   "map": {"at": 167620, "to": "mm"},
6839   "name": "CB_COLOR1_ATTRIB2",
6840   "type_ref": "CB_COLOR0_ATTRIB2"
6841  },
6842  {
6843   "chips": ["gfx10"],
6844   "map": {"at": 167624, "to": "mm"},
6845   "name": "CB_COLOR2_ATTRIB2",
6846   "type_ref": "CB_COLOR0_ATTRIB2"
6847  },
6848  {
6849   "chips": ["gfx10"],
6850   "map": {"at": 167628, "to": "mm"},
6851   "name": "CB_COLOR3_ATTRIB2",
6852   "type_ref": "CB_COLOR0_ATTRIB2"
6853  },
6854  {
6855   "chips": ["gfx10"],
6856   "map": {"at": 167632, "to": "mm"},
6857   "name": "CB_COLOR4_ATTRIB2",
6858   "type_ref": "CB_COLOR0_ATTRIB2"
6859  },
6860  {
6861   "chips": ["gfx10"],
6862   "map": {"at": 167636, "to": "mm"},
6863   "name": "CB_COLOR5_ATTRIB2",
6864   "type_ref": "CB_COLOR0_ATTRIB2"
6865  },
6866  {
6867   "chips": ["gfx10"],
6868   "map": {"at": 167640, "to": "mm"},
6869   "name": "CB_COLOR6_ATTRIB2",
6870   "type_ref": "CB_COLOR0_ATTRIB2"
6871  },
6872  {
6873   "chips": ["gfx10"],
6874   "map": {"at": 167644, "to": "mm"},
6875   "name": "CB_COLOR7_ATTRIB2",
6876   "type_ref": "CB_COLOR0_ATTRIB2"
6877  },
6878  {
6879   "chips": ["gfx10"],
6880   "map": {"at": 167648, "to": "mm"},
6881   "name": "CB_COLOR0_ATTRIB3",
6882   "type_ref": "CB_COLOR0_ATTRIB3"
6883  },
6884  {
6885   "chips": ["gfx10"],
6886   "map": {"at": 167652, "to": "mm"},
6887   "name": "CB_COLOR1_ATTRIB3",
6888   "type_ref": "CB_COLOR0_ATTRIB3"
6889  },
6890  {
6891   "chips": ["gfx10"],
6892   "map": {"at": 167656, "to": "mm"},
6893   "name": "CB_COLOR2_ATTRIB3",
6894   "type_ref": "CB_COLOR0_ATTRIB3"
6895  },
6896  {
6897   "chips": ["gfx10"],
6898   "map": {"at": 167660, "to": "mm"},
6899   "name": "CB_COLOR3_ATTRIB3",
6900   "type_ref": "CB_COLOR0_ATTRIB3"
6901  },
6902  {
6903   "chips": ["gfx10"],
6904   "map": {"at": 167664, "to": "mm"},
6905   "name": "CB_COLOR4_ATTRIB3",
6906   "type_ref": "CB_COLOR0_ATTRIB3"
6907  },
6908  {
6909   "chips": ["gfx10"],
6910   "map": {"at": 167668, "to": "mm"},
6911   "name": "CB_COLOR5_ATTRIB3",
6912   "type_ref": "CB_COLOR0_ATTRIB3"
6913  },
6914  {
6915   "chips": ["gfx10"],
6916   "map": {"at": 167672, "to": "mm"},
6917   "name": "CB_COLOR6_ATTRIB3",
6918   "type_ref": "CB_COLOR0_ATTRIB3"
6919  },
6920  {
6921   "chips": ["gfx10"],
6922   "map": {"at": 167676, "to": "mm"},
6923   "name": "CB_COLOR7_ATTRIB3",
6924   "type_ref": "CB_COLOR0_ATTRIB3"
6925  },
6926  {
6927   "chips": ["gfx10"],
6928   "map": {"at": 196608, "to": "mm"},
6929   "name": "CP_EOP_DONE_ADDR_LO",
6930   "type_ref": "CP_EOP_DONE_ADDR_LO"
6931  },
6932  {
6933   "chips": ["gfx10"],
6934   "map": {"at": 196612, "to": "mm"},
6935   "name": "CP_EOP_DONE_ADDR_HI",
6936   "type_ref": "CP_EOP_DONE_ADDR_HI"
6937  },
6938  {
6939   "chips": ["gfx10"],
6940   "map": {"at": 196616, "to": "mm"},
6941   "name": "CP_EOP_DONE_DATA_LO"
6942  },
6943  {
6944   "chips": ["gfx10"],
6945   "map": {"at": 196620, "to": "mm"},
6946   "name": "CP_EOP_DONE_DATA_HI"
6947  },
6948  {
6949   "chips": ["gfx10"],
6950   "map": {"at": 196624, "to": "mm"},
6951   "name": "CP_EOP_LAST_FENCE_LO"
6952  },
6953  {
6954   "chips": ["gfx10"],
6955   "map": {"at": 196628, "to": "mm"},
6956   "name": "CP_EOP_LAST_FENCE_HI"
6957  },
6958  {
6959   "chips": ["gfx10"],
6960   "map": {"at": 196632, "to": "mm"},
6961   "name": "CP_STREAM_OUT_ADDR_LO",
6962   "type_ref": "CP_STREAM_OUT_ADDR_LO"
6963  },
6964  {
6965   "chips": ["gfx10"],
6966   "map": {"at": 196636, "to": "mm"},
6967   "name": "CP_STREAM_OUT_ADDR_HI",
6968   "type_ref": "CP_STREAM_OUT_ADDR_HI"
6969  },
6970  {
6971   "chips": ["gfx10"],
6972   "map": {"at": 196640, "to": "mm"},
6973   "name": "CP_NUM_PRIM_WRITTEN_COUNT0_LO"
6974  },
6975  {
6976   "chips": ["gfx10"],
6977   "map": {"at": 196644, "to": "mm"},
6978   "name": "CP_NUM_PRIM_WRITTEN_COUNT0_HI"
6979  },
6980  {
6981   "chips": ["gfx10"],
6982   "map": {"at": 196648, "to": "mm"},
6983   "name": "CP_NUM_PRIM_NEEDED_COUNT0_LO"
6984  },
6985  {
6986   "chips": ["gfx10"],
6987   "map": {"at": 196652, "to": "mm"},
6988   "name": "CP_NUM_PRIM_NEEDED_COUNT0_HI"
6989  },
6990  {
6991   "chips": ["gfx10"],
6992   "map": {"at": 196656, "to": "mm"},
6993   "name": "CP_NUM_PRIM_WRITTEN_COUNT1_LO"
6994  },
6995  {
6996   "chips": ["gfx10"],
6997   "map": {"at": 196660, "to": "mm"},
6998   "name": "CP_NUM_PRIM_WRITTEN_COUNT1_HI"
6999  },
7000  {
7001   "chips": ["gfx10"],
7002   "map": {"at": 196664, "to": "mm"},
7003   "name": "CP_NUM_PRIM_NEEDED_COUNT1_LO"
7004  },
7005  {
7006   "chips": ["gfx10"],
7007   "map": {"at": 196668, "to": "mm"},
7008   "name": "CP_NUM_PRIM_NEEDED_COUNT1_HI"
7009  },
7010  {
7011   "chips": ["gfx10"],
7012   "map": {"at": 196672, "to": "mm"},
7013   "name": "CP_NUM_PRIM_WRITTEN_COUNT2_LO"
7014  },
7015  {
7016   "chips": ["gfx10"],
7017   "map": {"at": 196676, "to": "mm"},
7018   "name": "CP_NUM_PRIM_WRITTEN_COUNT2_HI"
7019  },
7020  {
7021   "chips": ["gfx10"],
7022   "map": {"at": 196680, "to": "mm"},
7023   "name": "CP_NUM_PRIM_NEEDED_COUNT2_LO"
7024  },
7025  {
7026   "chips": ["gfx10"],
7027   "map": {"at": 196684, "to": "mm"},
7028   "name": "CP_NUM_PRIM_NEEDED_COUNT2_HI"
7029  },
7030  {
7031   "chips": ["gfx10"],
7032   "map": {"at": 196688, "to": "mm"},
7033   "name": "CP_NUM_PRIM_WRITTEN_COUNT3_LO"
7034  },
7035  {
7036   "chips": ["gfx10"],
7037   "map": {"at": 196692, "to": "mm"},
7038   "name": "CP_NUM_PRIM_WRITTEN_COUNT3_HI"
7039  },
7040  {
7041   "chips": ["gfx10"],
7042   "map": {"at": 196696, "to": "mm"},
7043   "name": "CP_NUM_PRIM_NEEDED_COUNT3_LO"
7044  },
7045  {
7046   "chips": ["gfx10"],
7047   "map": {"at": 196700, "to": "mm"},
7048   "name": "CP_NUM_PRIM_NEEDED_COUNT3_HI"
7049  },
7050  {
7051   "chips": ["gfx10"],
7052   "map": {"at": 196704, "to": "mm"},
7053   "name": "CP_PIPE_STATS_ADDR_LO",
7054   "type_ref": "CP_PIPE_STATS_ADDR_LO"
7055  },
7056  {
7057   "chips": ["gfx10"],
7058   "map": {"at": 196708, "to": "mm"},
7059   "name": "CP_PIPE_STATS_ADDR_HI",
7060   "type_ref": "CP_PIPE_STATS_ADDR_HI"
7061  },
7062  {
7063   "chips": ["gfx10"],
7064   "map": {"at": 196712, "to": "mm"},
7065   "name": "CP_VGT_IAVERT_COUNT_LO"
7066  },
7067  {
7068   "chips": ["gfx10"],
7069   "map": {"at": 196716, "to": "mm"},
7070   "name": "CP_VGT_IAVERT_COUNT_HI"
7071  },
7072  {
7073   "chips": ["gfx10"],
7074   "map": {"at": 196720, "to": "mm"},
7075   "name": "CP_VGT_IAPRIM_COUNT_LO"
7076  },
7077  {
7078   "chips": ["gfx10"],
7079   "map": {"at": 196724, "to": "mm"},
7080   "name": "CP_VGT_IAPRIM_COUNT_HI"
7081  },
7082  {
7083   "chips": ["gfx10"],
7084   "map": {"at": 196728, "to": "mm"},
7085   "name": "CP_VGT_GSPRIM_COUNT_LO"
7086  },
7087  {
7088   "chips": ["gfx10"],
7089   "map": {"at": 196732, "to": "mm"},
7090   "name": "CP_VGT_GSPRIM_COUNT_HI"
7091  },
7092  {
7093   "chips": ["gfx10"],
7094   "map": {"at": 196736, "to": "mm"},
7095   "name": "CP_VGT_VSINVOC_COUNT_LO"
7096  },
7097  {
7098   "chips": ["gfx10"],
7099   "map": {"at": 196740, "to": "mm"},
7100   "name": "CP_VGT_VSINVOC_COUNT_HI"
7101  },
7102  {
7103   "chips": ["gfx10"],
7104   "map": {"at": 196744, "to": "mm"},
7105   "name": "CP_VGT_GSINVOC_COUNT_LO"
7106  },
7107  {
7108   "chips": ["gfx10"],
7109   "map": {"at": 196748, "to": "mm"},
7110   "name": "CP_VGT_GSINVOC_COUNT_HI"
7111  },
7112  {
7113   "chips": ["gfx10"],
7114   "map": {"at": 196752, "to": "mm"},
7115   "name": "CP_VGT_HSINVOC_COUNT_LO"
7116  },
7117  {
7118   "chips": ["gfx10"],
7119   "map": {"at": 196756, "to": "mm"},
7120   "name": "CP_VGT_HSINVOC_COUNT_HI"
7121  },
7122  {
7123   "chips": ["gfx10"],
7124   "map": {"at": 196760, "to": "mm"},
7125   "name": "CP_VGT_DSINVOC_COUNT_LO"
7126  },
7127  {
7128   "chips": ["gfx10"],
7129   "map": {"at": 196764, "to": "mm"},
7130   "name": "CP_VGT_DSINVOC_COUNT_HI"
7131  },
7132  {
7133   "chips": ["gfx10"],
7134   "map": {"at": 196768, "to": "mm"},
7135   "name": "CP_PA_CINVOC_COUNT_LO"
7136  },
7137  {
7138   "chips": ["gfx10"],
7139   "map": {"at": 196772, "to": "mm"},
7140   "name": "CP_PA_CINVOC_COUNT_HI"
7141  },
7142  {
7143   "chips": ["gfx10"],
7144   "map": {"at": 196776, "to": "mm"},
7145   "name": "CP_PA_CPRIM_COUNT_LO"
7146  },
7147  {
7148   "chips": ["gfx10"],
7149   "map": {"at": 196780, "to": "mm"},
7150   "name": "CP_PA_CPRIM_COUNT_HI"
7151  },
7152  {
7153   "chips": ["gfx10"],
7154   "map": {"at": 196784, "to": "mm"},
7155   "name": "CP_SC_PSINVOC_COUNT0_LO"
7156  },
7157  {
7158   "chips": ["gfx10"],
7159   "map": {"at": 196788, "to": "mm"},
7160   "name": "CP_SC_PSINVOC_COUNT0_HI"
7161  },
7162  {
7163   "chips": ["gfx10"],
7164   "map": {"at": 196792, "to": "mm"},
7165   "name": "CP_SC_PSINVOC_COUNT1_LO"
7166  },
7167  {
7168   "chips": ["gfx10"],
7169   "map": {"at": 196796, "to": "mm"},
7170   "name": "CP_SC_PSINVOC_COUNT1_HI"
7171  },
7172  {
7173   "chips": ["gfx10"],
7174   "map": {"at": 196800, "to": "mm"},
7175   "name": "CP_VGT_CSINVOC_COUNT_LO"
7176  },
7177  {
7178   "chips": ["gfx10"],
7179   "map": {"at": 196804, "to": "mm"},
7180   "name": "CP_VGT_CSINVOC_COUNT_HI"
7181  },
7182  {
7183   "chips": ["gfx10"],
7184   "map": {"at": 196808, "to": "mm"},
7185   "name": "CP_EOP_DONE_DOORBELL",
7186   "type_ref": "CP_EOP_DONE_DOORBELL"
7187  },
7188  {
7189   "chips": ["gfx10"],
7190   "map": {"at": 196812, "to": "mm"},
7191   "name": "CP_STREAM_OUT_DOORBELL",
7192   "type_ref": "CP_EOP_DONE_DOORBELL"
7193  },
7194  {
7195   "chips": ["gfx10"],
7196   "map": {"at": 196816, "to": "mm"},
7197   "name": "CP_SEM_DOORBELL",
7198   "type_ref": "CP_EOP_DONE_DOORBELL"
7199  },
7200  {
7201   "chips": ["gfx10"],
7202   "map": {"at": 196852, "to": "mm"},
7203   "name": "CP_PIPE_STATS_CONTROL",
7204   "type_ref": "CP_PIPE_STATS_CONTROL"
7205  },
7206  {
7207   "chips": ["gfx10"],
7208   "map": {"at": 196856, "to": "mm"},
7209   "name": "CP_STREAM_OUT_CONTROL",
7210   "type_ref": "CP_PIPE_STATS_CONTROL"
7211  },
7212  {
7213   "chips": ["gfx10"],
7214   "map": {"at": 196860, "to": "mm"},
7215   "name": "CP_STRMOUT_CNTL",
7216   "type_ref": "CP_STRMOUT_CNTL"
7217  },
7218  {
7219   "chips": ["gfx10"],
7220   "map": {"at": 196864, "to": "mm"},
7221   "name": "SCRATCH_REG0"
7222  },
7223  {
7224   "chips": ["gfx10"],
7225   "map": {"at": 196868, "to": "mm"},
7226   "name": "SCRATCH_REG1"
7227  },
7228  {
7229   "chips": ["gfx10"],
7230   "map": {"at": 196872, "to": "mm"},
7231   "name": "SCRATCH_REG2"
7232  },
7233  {
7234   "chips": ["gfx10"],
7235   "map": {"at": 196876, "to": "mm"},
7236   "name": "SCRATCH_REG3"
7237  },
7238  {
7239   "chips": ["gfx10"],
7240   "map": {"at": 196880, "to": "mm"},
7241   "name": "SCRATCH_REG4"
7242  },
7243  {
7244   "chips": ["gfx10"],
7245   "map": {"at": 196884, "to": "mm"},
7246   "name": "SCRATCH_REG5"
7247  },
7248  {
7249   "chips": ["gfx10"],
7250   "map": {"at": 196888, "to": "mm"},
7251   "name": "SCRATCH_REG6"
7252  },
7253  {
7254   "chips": ["gfx10"],
7255   "map": {"at": 196892, "to": "mm"},
7256   "name": "SCRATCH_REG7"
7257  },
7258  {
7259   "chips": ["gfx10"],
7260   "map": {"at": 196896, "to": "mm"},
7261   "name": "CP_PIPE_STATS_DOORBELL",
7262   "type_ref": "CP_EOP_DONE_DOORBELL"
7263  },
7264  {
7265   "chips": ["gfx10"],
7266   "map": {"at": 196908, "to": "mm"},
7267   "name": "CP_APPEND_DDID_CNT",
7268   "type_ref": "COMPUTE_PGM_HI"
7269  },
7270  {
7271   "chips": ["gfx10"],
7272   "map": {"at": 196912, "to": "mm"},
7273   "name": "CP_APPEND_DATA_HI"
7274  },
7275  {
7276   "chips": ["gfx10"],
7277   "map": {"at": 196916, "to": "mm"},
7278   "name": "CP_APPEND_LAST_CS_FENCE_HI"
7279  },
7280  {
7281   "chips": ["gfx10"],
7282   "map": {"at": 196920, "to": "mm"},
7283   "name": "CP_APPEND_LAST_PS_FENCE_HI"
7284  },
7285  {
7286   "chips": ["gfx10"],
7287   "map": {"at": 196928, "to": "mm"},
7288   "name": "SCRATCH_UMSK",
7289   "type_ref": "SCRATCH_UMSK"
7290  },
7291  {
7292   "chips": ["gfx10"],
7293   "map": {"at": 196932, "to": "mm"},
7294   "name": "SCRATCH_ADDR"
7295  },
7296  {
7297   "chips": ["gfx10"],
7298   "map": {"at": 196936, "to": "mm"},
7299   "name": "CP_PFP_ATOMIC_PREOP_LO"
7300  },
7301  {
7302   "chips": ["gfx10"],
7303   "map": {"at": 196940, "to": "mm"},
7304   "name": "CP_PFP_ATOMIC_PREOP_HI"
7305  },
7306  {
7307   "chips": ["gfx10"],
7308   "map": {"at": 196944, "to": "mm"},
7309   "name": "CP_PFP_GDS_ATOMIC0_PREOP_LO"
7310  },
7311  {
7312   "chips": ["gfx10"],
7313   "map": {"at": 196948, "to": "mm"},
7314   "name": "CP_PFP_GDS_ATOMIC0_PREOP_HI"
7315  },
7316  {
7317   "chips": ["gfx10"],
7318   "map": {"at": 196952, "to": "mm"},
7319   "name": "CP_PFP_GDS_ATOMIC1_PREOP_LO"
7320  },
7321  {
7322   "chips": ["gfx10"],
7323   "map": {"at": 196956, "to": "mm"},
7324   "name": "CP_PFP_GDS_ATOMIC1_PREOP_HI"
7325  },
7326  {
7327   "chips": ["gfx10"],
7328   "map": {"at": 196960, "to": "mm"},
7329   "name": "CP_APPEND_ADDR_LO",
7330   "type_ref": "CP_APPEND_ADDR_LO"
7331  },
7332  {
7333   "chips": ["gfx10"],
7334   "map": {"at": 196964, "to": "mm"},
7335   "name": "CP_APPEND_ADDR_HI",
7336   "type_ref": "CP_APPEND_ADDR_HI"
7337  },
7338  {
7339   "chips": ["gfx10"],
7340   "map": {"at": 196968, "to": "mm"},
7341   "name": "CP_APPEND_DATA"
7342  },
7343  {
7344   "chips": ["gfx10"],
7345   "map": {"at": 196972, "to": "mm"},
7346   "name": "CP_APPEND_LAST_CS_FENCE"
7347  },
7348  {
7349   "chips": ["gfx10"],
7350   "map": {"at": 196976, "to": "mm"},
7351   "name": "CP_APPEND_LAST_PS_FENCE"
7352  },
7353  {
7354   "chips": ["gfx10"],
7355   "map": {"at": 196980, "to": "mm"},
7356   "name": "CP_ATOMIC_PREOP_LO"
7357  },
7358  {
7359   "chips": ["gfx10"],
7360   "map": {"at": 196984, "to": "mm"},
7361   "name": "CP_ATOMIC_PREOP_HI"
7362  },
7363  {
7364   "chips": ["gfx10"],
7365   "map": {"at": 196988, "to": "mm"},
7366   "name": "CP_GDS_ATOMIC0_PREOP_LO"
7367  },
7368  {
7369   "chips": ["gfx10"],
7370   "map": {"at": 196992, "to": "mm"},
7371   "name": "CP_GDS_ATOMIC0_PREOP_HI"
7372  },
7373  {
7374   "chips": ["gfx10"],
7375   "map": {"at": 196996, "to": "mm"},
7376   "name": "CP_GDS_ATOMIC1_PREOP_LO"
7377  },
7378  {
7379   "chips": ["gfx10"],
7380   "map": {"at": 197000, "to": "mm"},
7381   "name": "CP_GDS_ATOMIC1_PREOP_HI"
7382  },
7383  {
7384   "chips": ["gfx10"],
7385   "map": {"at": 197028, "to": "mm"},
7386   "name": "CP_ME_MC_WADDR_LO",
7387   "type_ref": "CP_ME_MC_WADDR_LO"
7388  },
7389  {
7390   "chips": ["gfx10"],
7391   "map": {"at": 197032, "to": "mm"},
7392   "name": "CP_ME_MC_WADDR_HI",
7393   "type_ref": "CP_ME_MC_WADDR_HI"
7394  },
7395  {
7396   "chips": ["gfx10"],
7397   "map": {"at": 197036, "to": "mm"},
7398   "name": "CP_ME_MC_WDATA_LO"
7399  },
7400  {
7401   "chips": ["gfx10"],
7402   "map": {"at": 197040, "to": "mm"},
7403   "name": "CP_ME_MC_WDATA_HI"
7404  },
7405  {
7406   "chips": ["gfx10"],
7407   "map": {"at": 197044, "to": "mm"},
7408   "name": "CP_ME_MC_RADDR_LO",
7409   "type_ref": "CP_ME_MC_RADDR_LO"
7410  },
7411  {
7412   "chips": ["gfx10"],
7413   "map": {"at": 197048, "to": "mm"},
7414   "name": "CP_ME_MC_RADDR_HI",
7415   "type_ref": "CP_ME_MC_RADDR_HI"
7416  },
7417  {
7418   "chips": ["gfx10"],
7419   "map": {"at": 197052, "to": "mm"},
7420   "name": "CP_SEM_WAIT_TIMER"
7421  },
7422  {
7423   "chips": ["gfx10"],
7424   "map": {"at": 197056, "to": "mm"},
7425   "name": "CP_SIG_SEM_ADDR_LO",
7426   "type_ref": "CP_SIG_SEM_ADDR_LO"
7427  },
7428  {
7429   "chips": ["gfx10"],
7430   "map": {"at": 197060, "to": "mm"},
7431   "name": "CP_SIG_SEM_ADDR_HI",
7432   "type_ref": "CP_SIG_SEM_ADDR_HI"
7433  },
7434  {
7435   "chips": ["gfx10"],
7436   "map": {"at": 197072, "to": "mm"},
7437   "name": "CP_WAIT_REG_MEM_TIMEOUT"
7438  },
7439  {
7440   "chips": ["gfx10"],
7441   "map": {"at": 197076, "to": "mm"},
7442   "name": "CP_WAIT_SEM_ADDR_LO",
7443   "type_ref": "CP_SIG_SEM_ADDR_LO"
7444  },
7445  {
7446   "chips": ["gfx10"],
7447   "map": {"at": 197080, "to": "mm"},
7448   "name": "CP_WAIT_SEM_ADDR_HI",
7449   "type_ref": "CP_SIG_SEM_ADDR_HI"
7450  },
7451  {
7452   "chips": ["gfx10"],
7453   "map": {"at": 197084, "to": "mm"},
7454   "name": "CP_DMA_PFP_CONTROL",
7455   "type_ref": "CP_DMA_PFP_CONTROL"
7456  },
7457  {
7458   "chips": ["gfx10"],
7459   "map": {"at": 197088, "to": "mm"},
7460   "name": "CP_DMA_ME_CONTROL",
7461   "type_ref": "CP_DMA_PFP_CONTROL"
7462  },
7463  {
7464   "chips": ["gfx10"],
7465   "map": {"at": 197092, "to": "mm"},
7466   "name": "CP_COHER_BASE_HI",
7467   "type_ref": "CP_COHER_BASE_HI"
7468  },
7469  {
7470   "chips": ["gfx10"],
7471   "map": {"at": 197100, "to": "mm"},
7472   "name": "CP_COHER_START_DELAY",
7473   "type_ref": "CP_COHER_START_DELAY"
7474  },
7475  {
7476   "chips": ["gfx10"],
7477   "map": {"at": 197104, "to": "mm"},
7478   "name": "CP_COHER_CNTL",
7479   "type_ref": "CP_COHER_CNTL"
7480  },
7481  {
7482   "chips": ["gfx10"],
7483   "map": {"at": 197108, "to": "mm"},
7484   "name": "CP_COHER_SIZE"
7485  },
7486  {
7487   "chips": ["gfx10"],
7488   "map": {"at": 197112, "to": "mm"},
7489   "name": "CP_COHER_BASE"
7490  },
7491  {
7492   "chips": ["gfx10"],
7493   "map": {"at": 197116, "to": "mm"},
7494   "name": "CP_COHER_STATUS",
7495   "type_ref": "CP_COHER_STATUS"
7496  },
7497  {
7498   "chips": ["gfx10"],
7499   "map": {"at": 197120, "to": "mm"},
7500   "name": "CP_DMA_ME_SRC_ADDR"
7501  },
7502  {
7503   "chips": ["gfx10"],
7504   "map": {"at": 197124, "to": "mm"},
7505   "name": "CP_DMA_ME_SRC_ADDR_HI",
7506   "type_ref": "CP_DMA_ME_SRC_ADDR_HI"
7507  },
7508  {
7509   "chips": ["gfx10"],
7510   "map": {"at": 197128, "to": "mm"},
7511   "name": "CP_DMA_ME_DST_ADDR"
7512  },
7513  {
7514   "chips": ["gfx10"],
7515   "map": {"at": 197132, "to": "mm"},
7516   "name": "CP_DMA_ME_DST_ADDR_HI",
7517   "type_ref": "CP_DMA_ME_DST_ADDR_HI"
7518  },
7519  {
7520   "chips": ["gfx10"],
7521   "map": {"at": 197136, "to": "mm"},
7522   "name": "CP_DMA_ME_COMMAND",
7523   "type_ref": "CP_DMA_ME_COMMAND"
7524  },
7525  {
7526   "chips": ["gfx10"],
7527   "map": {"at": 197140, "to": "mm"},
7528   "name": "CP_DMA_PFP_SRC_ADDR"
7529  },
7530  {
7531   "chips": ["gfx10"],
7532   "map": {"at": 197144, "to": "mm"},
7533   "name": "CP_DMA_PFP_SRC_ADDR_HI",
7534   "type_ref": "CP_DMA_ME_SRC_ADDR_HI"
7535  },
7536  {
7537   "chips": ["gfx10"],
7538   "map": {"at": 197148, "to": "mm"},
7539   "name": "CP_DMA_PFP_DST_ADDR"
7540  },
7541  {
7542   "chips": ["gfx10"],
7543   "map": {"at": 197152, "to": "mm"},
7544   "name": "CP_DMA_PFP_DST_ADDR_HI",
7545   "type_ref": "CP_DMA_ME_DST_ADDR_HI"
7546  },
7547  {
7548   "chips": ["gfx10"],
7549   "map": {"at": 197156, "to": "mm"},
7550   "name": "CP_DMA_PFP_COMMAND",
7551   "type_ref": "CP_DMA_ME_COMMAND"
7552  },
7553  {
7554   "chips": ["gfx10"],
7555   "map": {"at": 197160, "to": "mm"},
7556   "name": "CP_DMA_CNTL",
7557   "type_ref": "CP_DMA_CNTL"
7558  },
7559  {
7560   "chips": ["gfx10"],
7561   "map": {"at": 197164, "to": "mm"},
7562   "name": "CP_DMA_READ_TAGS",
7563   "type_ref": "CP_DMA_READ_TAGS"
7564  },
7565  {
7566   "chips": ["gfx10"],
7567   "map": {"at": 197168, "to": "mm"},
7568   "name": "CP_COHER_SIZE_HI",
7569   "type_ref": "CP_COHER_SIZE_HI"
7570  },
7571  {
7572   "chips": ["gfx10"],
7573   "map": {"at": 197172, "to": "mm"},
7574   "name": "CP_PFP_IB_CONTROL",
7575   "type_ref": "CP_PFP_IB_CONTROL"
7576  },
7577  {
7578   "chips": ["gfx10"],
7579   "map": {"at": 197176, "to": "mm"},
7580   "name": "CP_PFP_LOAD_CONTROL",
7581   "type_ref": "CP_PFP_LOAD_CONTROL"
7582  },
7583  {
7584   "chips": ["gfx10"],
7585   "map": {"at": 197180, "to": "mm"},
7586   "name": "CP_SCRATCH_INDEX",
7587   "type_ref": "CP_SCRATCH_INDEX"
7588  },
7589  {
7590   "chips": ["gfx10"],
7591   "map": {"at": 197184, "to": "mm"},
7592   "name": "CP_SCRATCH_DATA"
7593  },
7594  {
7595   "chips": ["gfx10"],
7596   "map": {"at": 197188, "to": "mm"},
7597   "name": "CP_RB_OFFSET",
7598   "type_ref": "CP_RB_OFFSET"
7599  },
7600  {
7601   "chips": ["gfx10"],
7602   "map": {"at": 197192, "to": "mm"},
7603   "name": "CP_IB1_OFFSET",
7604   "type_ref": "CP_IB1_OFFSET"
7605  },
7606  {
7607   "chips": ["gfx10"],
7608   "map": {"at": 197196, "to": "mm"},
7609   "name": "CP_IB2_OFFSET",
7610   "type_ref": "CP_IB2_OFFSET"
7611  },
7612  {
7613   "chips": ["gfx10"],
7614   "map": {"at": 197200, "to": "mm"},
7615   "name": "CP_IB1_PREAMBLE_BEGIN",
7616   "type_ref": "CP_IB1_PREAMBLE_BEGIN"
7617  },
7618  {
7619   "chips": ["gfx10"],
7620   "map": {"at": 197204, "to": "mm"},
7621   "name": "CP_IB1_PREAMBLE_END",
7622   "type_ref": "CP_IB1_PREAMBLE_END"
7623  },
7624  {
7625   "chips": ["gfx10"],
7626   "map": {"at": 197208, "to": "mm"},
7627   "name": "CP_IB2_PREAMBLE_BEGIN",
7628   "type_ref": "CP_IB2_PREAMBLE_BEGIN"
7629  },
7630  {
7631   "chips": ["gfx10"],
7632   "map": {"at": 197212, "to": "mm"},
7633   "name": "CP_IB2_PREAMBLE_END",
7634   "type_ref": "CP_IB2_PREAMBLE_END"
7635  },
7636  {
7637   "chips": ["gfx10"],
7638   "map": {"at": 197216, "to": "mm"},
7639   "name": "CP_CE_IB1_OFFSET",
7640   "type_ref": "CP_IB1_OFFSET"
7641  },
7642  {
7643   "chips": ["gfx10"],
7644   "map": {"at": 197220, "to": "mm"},
7645   "name": "CP_CE_IB2_OFFSET",
7646   "type_ref": "CP_IB2_OFFSET"
7647  },
7648  {
7649   "chips": ["gfx10"],
7650   "map": {"at": 197224, "to": "mm"},
7651   "name": "CP_CE_COUNTER"
7652  },
7653  {
7654   "chips": ["gfx10"],
7655   "map": {"at": 197232, "to": "mm"},
7656   "name": "CP_DMA_ME_CMD_ADDR_LO",
7657   "type_ref": "CP_DMA_ME_CMD_ADDR_LO"
7658  },
7659  {
7660   "chips": ["gfx10"],
7661   "map": {"at": 197236, "to": "mm"},
7662   "name": "CP_DMA_ME_CMD_ADDR_HI",
7663   "type_ref": "CP_DMA_ME_CMD_ADDR_HI"
7664  },
7665  {
7666   "chips": ["gfx10"],
7667   "map": {"at": 197240, "to": "mm"},
7668   "name": "CP_DMA_PFP_CMD_ADDR_LO",
7669   "type_ref": "CP_DMA_ME_CMD_ADDR_LO"
7670  },
7671  {
7672   "chips": ["gfx10"],
7673   "map": {"at": 197244, "to": "mm"},
7674   "name": "CP_DMA_PFP_CMD_ADDR_HI",
7675   "type_ref": "CP_DMA_ME_CMD_ADDR_HI"
7676  },
7677  {
7678   "chips": ["gfx10"],
7679   "map": {"at": 197248, "to": "mm"},
7680   "name": "CP_APPEND_CMD_ADDR_LO",
7681   "type_ref": "CP_DMA_ME_CMD_ADDR_LO"
7682  },
7683  {
7684   "chips": ["gfx10"],
7685   "map": {"at": 197252, "to": "mm"},
7686   "name": "CP_APPEND_CMD_ADDR_HI",
7687   "type_ref": "CP_DMA_ME_CMD_ADDR_HI"
7688  },
7689  {
7690   "chips": ["gfx10"],
7691   "map": {"at": 197364, "to": "mm"},
7692   "name": "CP_CE_INIT_CMD_BUFSZ",
7693   "type_ref": "CP_CE_INIT_CMD_BUFSZ"
7694  },
7695  {
7696   "chips": ["gfx10"],
7697   "map": {"at": 197368, "to": "mm"},
7698   "name": "CP_CE_IB1_CMD_BUFSZ",
7699   "type_ref": "CP_CE_IB1_CMD_BUFSZ"
7700  },
7701  {
7702   "chips": ["gfx10"],
7703   "map": {"at": 197372, "to": "mm"},
7704   "name": "CP_CE_IB2_CMD_BUFSZ",
7705   "type_ref": "CP_CE_IB2_CMD_BUFSZ"
7706  },
7707  {
7708   "chips": ["gfx10"],
7709   "map": {"at": 197376, "to": "mm"},
7710   "name": "CP_IB1_CMD_BUFSZ",
7711   "type_ref": "CP_CE_IB1_CMD_BUFSZ"
7712  },
7713  {
7714   "chips": ["gfx10"],
7715   "map": {"at": 197380, "to": "mm"},
7716   "name": "CP_IB2_CMD_BUFSZ",
7717   "type_ref": "CP_CE_IB2_CMD_BUFSZ"
7718  },
7719  {
7720   "chips": ["gfx10"],
7721   "map": {"at": 197384, "to": "mm"},
7722   "name": "CP_ST_CMD_BUFSZ",
7723   "type_ref": "CP_ST_CMD_BUFSZ"
7724  },
7725  {
7726   "chips": ["gfx10"],
7727   "map": {"at": 197388, "to": "mm"},
7728   "name": "CP_CE_INIT_BASE_LO",
7729   "type_ref": "CP_CE_INIT_BASE_LO"
7730  },
7731  {
7732   "chips": ["gfx10"],
7733   "map": {"at": 197392, "to": "mm"},
7734   "name": "CP_CE_INIT_BASE_HI",
7735   "type_ref": "CP_CE_INIT_BASE_HI"
7736  },
7737  {
7738   "chips": ["gfx10"],
7739   "map": {"at": 197396, "to": "mm"},
7740   "name": "CP_CE_INIT_BUFSZ",
7741   "type_ref": "CP_CE_INIT_BUFSZ"
7742  },
7743  {
7744   "chips": ["gfx10"],
7745   "map": {"at": 197400, "to": "mm"},
7746   "name": "CP_CE_IB1_BASE_LO",
7747   "type_ref": "CP_CE_IB1_BASE_LO"
7748  },
7749  {
7750   "chips": ["gfx10"],
7751   "map": {"at": 197404, "to": "mm"},
7752   "name": "CP_CE_IB1_BASE_HI",
7753   "type_ref": "CP_CE_IB1_BASE_HI"
7754  },
7755  {
7756   "chips": ["gfx10"],
7757   "map": {"at": 197408, "to": "mm"},
7758   "name": "CP_CE_IB1_BUFSZ",
7759   "type_ref": "CP_CE_IB1_BUFSZ"
7760  },
7761  {
7762   "chips": ["gfx10"],
7763   "map": {"at": 197412, "to": "mm"},
7764   "name": "CP_CE_IB2_BASE_LO",
7765   "type_ref": "CP_CE_IB2_BASE_LO"
7766  },
7767  {
7768   "chips": ["gfx10"],
7769   "map": {"at": 197416, "to": "mm"},
7770   "name": "CP_CE_IB2_BASE_HI",
7771   "type_ref": "CP_CE_IB2_BASE_HI"
7772  },
7773  {
7774   "chips": ["gfx10"],
7775   "map": {"at": 197420, "to": "mm"},
7776   "name": "CP_CE_IB2_BUFSZ",
7777   "type_ref": "CP_CE_IB2_BUFSZ"
7778  },
7779  {
7780   "chips": ["gfx10"],
7781   "map": {"at": 197424, "to": "mm"},
7782   "name": "CP_IB1_BASE_LO",
7783   "type_ref": "CP_CE_IB1_BASE_LO"
7784  },
7785  {
7786   "chips": ["gfx10"],
7787   "map": {"at": 197428, "to": "mm"},
7788   "name": "CP_IB1_BASE_HI",
7789   "type_ref": "CP_CE_IB1_BASE_HI"
7790  },
7791  {
7792   "chips": ["gfx10"],
7793   "map": {"at": 197432, "to": "mm"},
7794   "name": "CP_IB1_BUFSZ",
7795   "type_ref": "CP_CE_IB1_BUFSZ"
7796  },
7797  {
7798   "chips": ["gfx10"],
7799   "map": {"at": 197436, "to": "mm"},
7800   "name": "CP_IB2_BASE_LO",
7801   "type_ref": "CP_CE_IB2_BASE_LO"
7802  },
7803  {
7804   "chips": ["gfx10"],
7805   "map": {"at": 197440, "to": "mm"},
7806   "name": "CP_IB2_BASE_HI",
7807   "type_ref": "CP_CE_IB2_BASE_HI"
7808  },
7809  {
7810   "chips": ["gfx10"],
7811   "map": {"at": 197444, "to": "mm"},
7812   "name": "CP_IB2_BUFSZ",
7813   "type_ref": "CP_CE_IB2_BUFSZ"
7814  },
7815  {
7816   "chips": ["gfx10"],
7817   "map": {"at": 197448, "to": "mm"},
7818   "name": "CP_ST_BASE_LO",
7819   "type_ref": "CP_ST_BASE_LO"
7820  },
7821  {
7822   "chips": ["gfx10"],
7823   "map": {"at": 197452, "to": "mm"},
7824   "name": "CP_ST_BASE_HI",
7825   "type_ref": "CP_ST_BASE_HI"
7826  },
7827  {
7828   "chips": ["gfx10"],
7829   "map": {"at": 197456, "to": "mm"},
7830   "name": "CP_ST_BUFSZ",
7831   "type_ref": "CP_ST_BUFSZ"
7832  },
7833  {
7834   "chips": ["gfx10"],
7835   "map": {"at": 197460, "to": "mm"},
7836   "name": "CP_EOP_DONE_EVENT_CNTL",
7837   "type_ref": "CP_EOP_DONE_EVENT_CNTL"
7838  },
7839  {
7840   "chips": ["gfx10"],
7841   "map": {"at": 197464, "to": "mm"},
7842   "name": "CP_EOP_DONE_DATA_CNTL",
7843   "type_ref": "CP_EOP_DONE_DATA_CNTL"
7844  },
7845  {
7846   "chips": ["gfx10"],
7847   "map": {"at": 197468, "to": "mm"},
7848   "name": "CP_EOP_DONE_CNTX_ID"
7849  },
7850  {
7851   "chips": ["gfx10"],
7852   "map": {"at": 197472, "to": "mm"},
7853   "name": "CP_DB_BASE_LO",
7854   "type_ref": "CP_DB_BASE_LO"
7855  },
7856  {
7857   "chips": ["gfx10"],
7858   "map": {"at": 197476, "to": "mm"},
7859   "name": "CP_DB_BASE_HI",
7860   "type_ref": "CP_DB_BASE_HI"
7861  },
7862  {
7863   "chips": ["gfx10"],
7864   "map": {"at": 197480, "to": "mm"},
7865   "name": "CP_DB_BUFSZ",
7866   "type_ref": "CP_DB_BUFSZ"
7867  },
7868  {
7869   "chips": ["gfx10"],
7870   "map": {"at": 197484, "to": "mm"},
7871   "name": "CP_DB_CMD_BUFSZ",
7872   "type_ref": "CP_DB_CMD_BUFSZ"
7873  },
7874  {
7875   "chips": ["gfx10"],
7876   "map": {"at": 197488, "to": "mm"},
7877   "name": "CP_CE_DB_BASE_LO",
7878   "type_ref": "CP_DB_BASE_LO"
7879  },
7880  {
7881   "chips": ["gfx10"],
7882   "map": {"at": 197492, "to": "mm"},
7883   "name": "CP_CE_DB_BASE_HI",
7884   "type_ref": "CP_DB_BASE_HI"
7885  },
7886  {
7887   "chips": ["gfx10"],
7888   "map": {"at": 197496, "to": "mm"},
7889   "name": "CP_CE_DB_BUFSZ",
7890   "type_ref": "CP_DB_BUFSZ"
7891  },
7892  {
7893   "chips": ["gfx10"],
7894   "map": {"at": 197500, "to": "mm"},
7895   "name": "CP_CE_DB_CMD_BUFSZ",
7896   "type_ref": "CP_DB_CMD_BUFSZ"
7897  },
7898  {
7899   "chips": ["gfx10"],
7900   "map": {"at": 197552, "to": "mm"},
7901   "name": "CP_PFP_COMPLETION_STATUS",
7902   "type_ref": "CP_PFP_COMPLETION_STATUS"
7903  },
7904  {
7905   "chips": ["gfx10"],
7906   "map": {"at": 197556, "to": "mm"},
7907   "name": "CP_CE_COMPLETION_STATUS",
7908   "type_ref": "CP_PFP_COMPLETION_STATUS"
7909  },
7910  {
7911   "chips": ["gfx10"],
7912   "map": {"at": 197560, "to": "mm"},
7913   "name": "CP_PRED_NOT_VISIBLE",
7914   "type_ref": "CP_PRED_NOT_VISIBLE"
7915  },
7916  {
7917   "chips": ["gfx10"],
7918   "map": {"at": 197568, "to": "mm"},
7919   "name": "CP_PFP_METADATA_BASE_ADDR"
7920  },
7921  {
7922   "chips": ["gfx10"],
7923   "map": {"at": 197572, "to": "mm"},
7924   "name": "CP_PFP_METADATA_BASE_ADDR_HI",
7925   "type_ref": "CP_EOP_DONE_ADDR_HI"
7926  },
7927  {
7928   "chips": ["gfx10"],
7929   "map": {"at": 197576, "to": "mm"},
7930   "name": "CP_CE_METADATA_BASE_ADDR"
7931  },
7932  {
7933   "chips": ["gfx10"],
7934   "map": {"at": 197580, "to": "mm"},
7935   "name": "CP_CE_METADATA_BASE_ADDR_HI",
7936   "type_ref": "CP_EOP_DONE_ADDR_HI"
7937  },
7938  {
7939   "chips": ["gfx10"],
7940   "map": {"at": 197584, "to": "mm"},
7941   "name": "CP_DRAW_INDX_INDR_ADDR"
7942  },
7943  {
7944   "chips": ["gfx10"],
7945   "map": {"at": 197588, "to": "mm"},
7946   "name": "CP_DRAW_INDX_INDR_ADDR_HI",
7947   "type_ref": "CP_EOP_DONE_ADDR_HI"
7948  },
7949  {
7950   "chips": ["gfx10"],
7951   "map": {"at": 197592, "to": "mm"},
7952   "name": "CP_DISPATCH_INDR_ADDR"
7953  },
7954  {
7955   "chips": ["gfx10"],
7956   "map": {"at": 197596, "to": "mm"},
7957   "name": "CP_DISPATCH_INDR_ADDR_HI",
7958   "type_ref": "CP_EOP_DONE_ADDR_HI"
7959  },
7960  {
7961   "chips": ["gfx10"],
7962   "map": {"at": 197600, "to": "mm"},
7963   "name": "CP_INDEX_BASE_ADDR"
7964  },
7965  {
7966   "chips": ["gfx10"],
7967   "map": {"at": 197604, "to": "mm"},
7968   "name": "CP_INDEX_BASE_ADDR_HI",
7969   "type_ref": "CP_EOP_DONE_ADDR_HI"
7970  },
7971  {
7972   "chips": ["gfx10"],
7973   "map": {"at": 197608, "to": "mm"},
7974   "name": "CP_INDEX_TYPE",
7975   "type_ref": "CP_INDEX_TYPE"
7976  },
7977  {
7978   "chips": ["gfx10"],
7979   "map": {"at": 197612, "to": "mm"},
7980   "name": "CP_GDS_BKUP_ADDR"
7981  },
7982  {
7983   "chips": ["gfx10"],
7984   "map": {"at": 197616, "to": "mm"},
7985   "name": "CP_GDS_BKUP_ADDR_HI",
7986   "type_ref": "CP_EOP_DONE_ADDR_HI"
7987  },
7988  {
7989   "chips": ["gfx10"],
7990   "map": {"at": 197620, "to": "mm"},
7991   "name": "CP_SAMPLE_STATUS",
7992   "type_ref": "CP_SAMPLE_STATUS"
7993  },
7994  {
7995   "chips": ["gfx10"],
7996   "map": {"at": 197624, "to": "mm"},
7997   "name": "CP_ME_COHER_CNTL",
7998   "type_ref": "CP_ME_COHER_CNTL"
7999  },
8000  {
8001   "chips": ["gfx10"],
8002   "map": {"at": 197628, "to": "mm"},
8003   "name": "CP_ME_COHER_SIZE"
8004  },
8005  {
8006   "chips": ["gfx10"],
8007   "map": {"at": 197632, "to": "mm"},
8008   "name": "CP_ME_COHER_SIZE_HI",
8009   "type_ref": "CP_COHER_SIZE_HI"
8010  },
8011  {
8012   "chips": ["gfx10"],
8013   "map": {"at": 197636, "to": "mm"},
8014   "name": "CP_ME_COHER_BASE"
8015  },
8016  {
8017   "chips": ["gfx10"],
8018   "map": {"at": 197640, "to": "mm"},
8019   "name": "CP_ME_COHER_BASE_HI",
8020   "type_ref": "CP_COHER_BASE_HI"
8021  },
8022  {
8023   "chips": ["gfx10"],
8024   "map": {"at": 197644, "to": "mm"},
8025   "name": "CP_ME_COHER_STATUS",
8026   "type_ref": "CP_ME_COHER_STATUS"
8027  },
8028  {
8029   "chips": ["gfx10"],
8030   "map": {"at": 197888, "to": "mm"},
8031   "name": "RLC_GPM_PERF_COUNT_0",
8032   "type_ref": "RLC_GPM_PERF_COUNT_0"
8033  },
8034  {
8035   "chips": ["gfx10"],
8036   "map": {"at": 197892, "to": "mm"},
8037   "name": "RLC_GPM_PERF_COUNT_1",
8038   "type_ref": "RLC_GPM_PERF_COUNT_0"
8039  },
8040  {
8041   "chips": ["gfx10"],
8042   "map": {"at": 198656, "to": "mm"},
8043   "name": "GRBM_GFX_INDEX",
8044   "type_ref": "GRBM_GFX_INDEX"
8045  },
8046  {
8047   "chips": ["gfx10"],
8048   "map": {"at": 198912, "to": "mm"},
8049   "name": "VGT_ESGS_RING_SIZE"
8050  },
8051  {
8052   "chips": ["gfx10"],
8053   "map": {"at": 198916, "to": "mm"},
8054   "name": "VGT_GSVS_RING_SIZE"
8055  },
8056  {
8057   "chips": ["gfx10"],
8058   "map": {"at": 198920, "to": "mm"},
8059   "name": "VGT_PRIMITIVE_TYPE",
8060   "type_ref": "VGT_PRIMITIVE_TYPE"
8061  },
8062  {
8063   "chips": ["gfx10"],
8064   "map": {"at": 198924, "to": "mm"},
8065   "name": "VGT_INDEX_TYPE",
8066   "type_ref": "CP_INDEX_TYPE"
8067  },
8068  {
8069   "chips": ["gfx10"],
8070   "map": {"at": 198928, "to": "mm"},
8071   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_0"
8072  },
8073  {
8074   "chips": ["gfx10"],
8075   "map": {"at": 198932, "to": "mm"},
8076   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_1"
8077  },
8078  {
8079   "chips": ["gfx10"],
8080   "map": {"at": 198936, "to": "mm"},
8081   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_2"
8082  },
8083  {
8084   "chips": ["gfx10"],
8085   "map": {"at": 198940, "to": "mm"},
8086   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_3"
8087  },
8088  {
8089   "chips": ["gfx10"],
8090   "map": {"at": 198948, "to": "mm"},
8091   "name": "GE_MIN_VTX_INDX"
8092  },
8093  {
8094   "chips": ["gfx10"],
8095   "map": {"at": 198952, "to": "mm"},
8096   "name": "GE_INDX_OFFSET"
8097  },
8098  {
8099   "chips": ["gfx10"],
8100   "map": {"at": 198956, "to": "mm"},
8101   "name": "GE_MULTI_PRIM_IB_RESET_EN",
8102   "type_ref": "VGT_MULTI_PRIM_IB_RESET_EN"
8103  },
8104  {
8105   "chips": ["gfx10"],
8106   "map": {"at": 198960, "to": "mm"},
8107   "name": "VGT_NUM_INDICES"
8108  },
8109  {
8110   "chips": ["gfx10"],
8111   "map": {"at": 198964, "to": "mm"},
8112   "name": "VGT_NUM_INSTANCES"
8113  },
8114  {
8115   "chips": ["gfx10"],
8116   "map": {"at": 198968, "to": "mm"},
8117   "name": "VGT_TF_RING_SIZE",
8118   "type_ref": "VGT_TF_RING_SIZE"
8119  },
8120  {
8121   "chips": ["gfx10"],
8122   "map": {"at": 198972, "to": "mm"},
8123   "name": "VGT_HS_OFFCHIP_PARAM",
8124   "type_ref": "VGT_HS_OFFCHIP_PARAM"
8125  },
8126  {
8127   "chips": ["gfx10"],
8128   "map": {"at": 198976, "to": "mm"},
8129   "name": "VGT_TF_MEMORY_BASE"
8130  },
8131  {
8132   "chips": ["gfx10"],
8133   "map": {"at": 198980, "to": "mm"},
8134   "name": "GE_DMA_FIRST_INDEX"
8135  },
8136  {
8137   "chips": ["gfx10"],
8138   "map": {"at": 198984, "to": "mm"},
8139   "name": "WD_POS_BUF_BASE"
8140  },
8141  {
8142   "chips": ["gfx10"],
8143   "map": {"at": 198988, "to": "mm"},
8144   "name": "WD_POS_BUF_BASE_HI",
8145   "type_ref": "DB_Z_READ_BASE_HI"
8146  },
8147  {
8148   "chips": ["gfx10"],
8149   "map": {"at": 198992, "to": "mm"},
8150   "name": "WD_CNTL_SB_BUF_BASE"
8151  },
8152  {
8153   "chips": ["gfx10"],
8154   "map": {"at": 198996, "to": "mm"},
8155   "name": "WD_CNTL_SB_BUF_BASE_HI",
8156   "type_ref": "DB_Z_READ_BASE_HI"
8157  },
8158  {
8159   "chips": ["gfx10"],
8160   "map": {"at": 199000, "to": "mm"},
8161   "name": "WD_INDEX_BUF_BASE"
8162  },
8163  {
8164   "chips": ["gfx10"],
8165   "map": {"at": 199004, "to": "mm"},
8166   "name": "WD_INDEX_BUF_BASE_HI",
8167   "type_ref": "DB_Z_READ_BASE_HI"
8168  },
8169  {
8170   "chips": ["gfx10"],
8171   "map": {"at": 199008, "to": "mm"},
8172   "name": "IA_MULTI_VGT_PARAM_PIPED",
8173   "type_ref": "IA_MULTI_VGT_PARAM_PIPED"
8174  },
8175  {
8176   "chips": ["gfx10"],
8177   "map": {"at": 199012, "to": "mm"},
8178   "name": "GE_MAX_VTX_INDX"
8179  },
8180  {
8181   "chips": ["gfx10"],
8182   "map": {"at": 199016, "to": "mm"},
8183   "name": "VGT_INSTANCE_BASE_ID"
8184  },
8185  {
8186   "chips": ["gfx10"],
8187   "map": {"at": 199020, "to": "mm"},
8188   "name": "GE_CNTL",
8189   "type_ref": "GE_CNTL"
8190  },
8191  {
8192   "chips": ["gfx10"],
8193   "map": {"at": 199024, "to": "mm"},
8194   "name": "GE_USER_VGPR1"
8195  },
8196  {
8197   "chips": ["gfx10"],
8198   "map": {"at": 199028, "to": "mm"},
8199   "name": "GE_USER_VGPR2"
8200  },
8201  {
8202   "chips": ["gfx10"],
8203   "map": {"at": 199032, "to": "mm"},
8204   "name": "GE_USER_VGPR3"
8205  },
8206  {
8207   "chips": ["gfx10"],
8208   "map": {"at": 199036, "to": "mm"},
8209   "name": "GE_STEREO_CNTL",
8210   "type_ref": "GE_STEREO_CNTL"
8211  },
8212  {
8213   "chips": ["gfx10"],
8214   "map": {"at": 199040, "to": "mm"},
8215   "name": "GE_PC_ALLOC",
8216   "type_ref": "GE_PC_ALLOC"
8217  },
8218  {
8219   "chips": ["gfx10"],
8220   "map": {"at": 199044, "to": "mm"},
8221   "name": "VGT_TF_MEMORY_BASE_HI",
8222   "type_ref": "DB_Z_READ_BASE_HI"
8223  },
8224  {
8225   "chips": ["gfx10"],
8226   "map": {"at": 199048, "to": "mm"},
8227   "name": "GE_USER_VGPR_EN",
8228   "type_ref": "GE_USER_VGPR_EN"
8229  },
8230  {
8231   "chips": ["gfx10"],
8232   "map": {"at": 199168, "to": "mm"},
8233   "name": "PA_SU_LINE_STIPPLE_VALUE",
8234   "type_ref": "PA_SU_LINE_STIPPLE_VALUE"
8235  },
8236  {
8237   "chips": ["gfx10"],
8238   "map": {"at": 199172, "to": "mm"},
8239   "name": "PA_SC_LINE_STIPPLE_STATE",
8240   "type_ref": "PA_SC_LINE_STIPPLE_STATE"
8241  },
8242  {
8243   "chips": ["gfx10"],
8244   "map": {"at": 199184, "to": "mm"},
8245   "name": "PA_SC_SCREEN_EXTENT_MIN_0",
8246   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
8247  },
8248  {
8249   "chips": ["gfx10"],
8250   "map": {"at": 199188, "to": "mm"},
8251   "name": "PA_SC_SCREEN_EXTENT_MAX_0",
8252   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
8253  },
8254  {
8255   "chips": ["gfx10"],
8256   "map": {"at": 199192, "to": "mm"},
8257   "name": "PA_SC_SCREEN_EXTENT_MIN_1",
8258   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
8259  },
8260  {
8261   "chips": ["gfx10"],
8262   "map": {"at": 199212, "to": "mm"},
8263   "name": "PA_SC_SCREEN_EXTENT_MAX_1",
8264   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
8265  },
8266  {
8267   "chips": ["gfx10"],
8268   "map": {"at": 199296, "to": "mm"},
8269   "name": "PA_SC_P3D_TRAP_SCREEN_HV_EN",
8270   "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN"
8271  },
8272  {
8273   "chips": ["gfx10"],
8274   "map": {"at": 199300, "to": "mm"},
8275   "name": "PA_SC_P3D_TRAP_SCREEN_H",
8276   "type_ref": "PA_SC_P3D_TRAP_SCREEN_H"
8277  },
8278  {
8279   "chips": ["gfx10"],
8280   "map": {"at": 199304, "to": "mm"},
8281   "name": "PA_SC_P3D_TRAP_SCREEN_V",
8282   "type_ref": "PA_SC_P3D_TRAP_SCREEN_V"
8283  },
8284  {
8285   "chips": ["gfx10"],
8286   "map": {"at": 199308, "to": "mm"},
8287   "name": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE",
8288   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
8289  },
8290  {
8291   "chips": ["gfx10"],
8292   "map": {"at": 199312, "to": "mm"},
8293   "name": "PA_SC_P3D_TRAP_SCREEN_COUNT",
8294   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
8295  },
8296  {
8297   "chips": ["gfx10"],
8298   "map": {"at": 199328, "to": "mm"},
8299   "name": "PA_SC_HP3D_TRAP_SCREEN_HV_EN",
8300   "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN"
8301  },
8302  {
8303   "chips": ["gfx10"],
8304   "map": {"at": 199332, "to": "mm"},
8305   "name": "PA_SC_HP3D_TRAP_SCREEN_H",
8306   "type_ref": "PA_SC_P3D_TRAP_SCREEN_H"
8307  },
8308  {
8309   "chips": ["gfx10"],
8310   "map": {"at": 199336, "to": "mm"},
8311   "name": "PA_SC_HP3D_TRAP_SCREEN_V",
8312   "type_ref": "PA_SC_P3D_TRAP_SCREEN_V"
8313  },
8314  {
8315   "chips": ["gfx10"],
8316   "map": {"at": 199340, "to": "mm"},
8317   "name": "PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE",
8318   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
8319  },
8320  {
8321   "chips": ["gfx10"],
8322   "map": {"at": 199344, "to": "mm"},
8323   "name": "PA_SC_HP3D_TRAP_SCREEN_COUNT",
8324   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
8325  },
8326  {
8327   "chips": ["gfx10"],
8328   "map": {"at": 199360, "to": "mm"},
8329   "name": "PA_SC_TRAP_SCREEN_HV_EN",
8330   "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN"
8331  },
8332  {
8333   "chips": ["gfx10"],
8334   "map": {"at": 199364, "to": "mm"},
8335   "name": "PA_SC_TRAP_SCREEN_H",
8336   "type_ref": "PA_SC_P3D_TRAP_SCREEN_H"
8337  },
8338  {
8339   "chips": ["gfx10"],
8340   "map": {"at": 199368, "to": "mm"},
8341   "name": "PA_SC_TRAP_SCREEN_V",
8342   "type_ref": "PA_SC_P3D_TRAP_SCREEN_V"
8343  },
8344  {
8345   "chips": ["gfx10"],
8346   "map": {"at": 199372, "to": "mm"},
8347   "name": "PA_SC_TRAP_SCREEN_OCCURRENCE",
8348   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
8349  },
8350  {
8351   "chips": ["gfx10"],
8352   "map": {"at": 199376, "to": "mm"},
8353   "name": "PA_SC_TRAP_SCREEN_COUNT",
8354   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
8355  },
8356  {
8357   "chips": ["gfx10"],
8358   "map": {"at": 199936, "to": "mm"},
8359   "name": "SQ_THREAD_TRACE_USERDATA_0"
8360  },
8361  {
8362   "chips": ["gfx10"],
8363   "map": {"at": 199940, "to": "mm"},
8364   "name": "SQ_THREAD_TRACE_USERDATA_1"
8365  },
8366  {
8367   "chips": ["gfx10"],
8368   "map": {"at": 199944, "to": "mm"},
8369   "name": "SQ_THREAD_TRACE_USERDATA_2"
8370  },
8371  {
8372   "chips": ["gfx10"],
8373   "map": {"at": 199948, "to": "mm"},
8374   "name": "SQ_THREAD_TRACE_USERDATA_3"
8375  },
8376  {
8377   "chips": ["gfx10"],
8378   "map": {"at": 199952, "to": "mm"},
8379   "name": "SQ_THREAD_TRACE_USERDATA_4"
8380  },
8381  {
8382   "chips": ["gfx10"],
8383   "map": {"at": 199956, "to": "mm"},
8384   "name": "SQ_THREAD_TRACE_USERDATA_5"
8385  },
8386  {
8387   "chips": ["gfx10"],
8388   "map": {"at": 199960, "to": "mm"},
8389   "name": "SQ_THREAD_TRACE_USERDATA_6"
8390  },
8391  {
8392   "chips": ["gfx10"],
8393   "map": {"at": 199964, "to": "mm"},
8394   "name": "SQ_THREAD_TRACE_USERDATA_7"
8395  },
8396  {
8397   "chips": ["gfx10"],
8398   "map": {"at": 199968, "to": "mm"},
8399   "name": "SQC_CACHES",
8400   "type_ref": "SQC_CACHES"
8401  },
8402  {
8403   "chips": ["gfx10"],
8404   "map": {"at": 199972, "to": "mm"},
8405   "name": "SQC_WRITEBACK",
8406   "type_ref": "SQC_WRITEBACK"
8407  },
8408  {
8409   "chips": ["gfx10"],
8410   "map": {"at": 200192, "to": "mm"},
8411   "name": "TA_CS_BC_BASE_ADDR"
8412  },
8413  {
8414   "chips": ["gfx10"],
8415   "map": {"at": 200196, "to": "mm"},
8416   "name": "TA_CS_BC_BASE_ADDR_HI",
8417   "type_ref": "TA_BC_BASE_ADDR_HI"
8418  },
8419  {
8420   "chips": ["gfx10"],
8421   "map": {"at": 200448, "to": "mm"},
8422   "name": "DB_OCCLUSION_COUNT0_LOW"
8423  },
8424  {
8425   "chips": ["gfx10"],
8426   "map": {"at": 200452, "to": "mm"},
8427   "name": "DB_OCCLUSION_COUNT0_HI",
8428   "type_ref": "DB_OCCLUSION_COUNT0_HI"
8429  },
8430  {
8431   "chips": ["gfx10"],
8432   "map": {"at": 200456, "to": "mm"},
8433   "name": "DB_OCCLUSION_COUNT1_LOW"
8434  },
8435  {
8436   "chips": ["gfx10"],
8437   "map": {"at": 200460, "to": "mm"},
8438   "name": "DB_OCCLUSION_COUNT1_HI",
8439   "type_ref": "DB_OCCLUSION_COUNT0_HI"
8440  },
8441  {
8442   "chips": ["gfx10"],
8443   "map": {"at": 200464, "to": "mm"},
8444   "name": "DB_OCCLUSION_COUNT2_LOW"
8445  },
8446  {
8447   "chips": ["gfx10"],
8448   "map": {"at": 200468, "to": "mm"},
8449   "name": "DB_OCCLUSION_COUNT2_HI",
8450   "type_ref": "DB_OCCLUSION_COUNT0_HI"
8451  },
8452  {
8453   "chips": ["gfx10"],
8454   "map": {"at": 200472, "to": "mm"},
8455   "name": "DB_OCCLUSION_COUNT3_LOW"
8456  },
8457  {
8458   "chips": ["gfx10"],
8459   "map": {"at": 200476, "to": "mm"},
8460   "name": "DB_OCCLUSION_COUNT3_HI",
8461   "type_ref": "DB_OCCLUSION_COUNT0_HI"
8462  },
8463  {
8464   "chips": ["gfx10"],
8465   "map": {"at": 200696, "to": "mm"},
8466   "name": "DB_ZPASS_COUNT_LOW"
8467  },
8468  {
8469   "chips": ["gfx10"],
8470   "map": {"at": 200700, "to": "mm"},
8471   "name": "DB_ZPASS_COUNT_HI",
8472   "type_ref": "DB_OCCLUSION_COUNT0_HI"
8473  },
8474  {
8475   "chips": ["gfx10"],
8476   "map": {"at": 200704, "to": "mm"},
8477   "name": "GDS_RD_ADDR"
8478  },
8479  {
8480   "chips": ["gfx10"],
8481   "map": {"at": 200708, "to": "mm"},
8482   "name": "GDS_RD_DATA"
8483  },
8484  {
8485   "chips": ["gfx10"],
8486   "map": {"at": 200712, "to": "mm"},
8487   "name": "GDS_RD_BURST_ADDR"
8488  },
8489  {
8490   "chips": ["gfx10"],
8491   "map": {"at": 200716, "to": "mm"},
8492   "name": "GDS_RD_BURST_COUNT"
8493  },
8494  {
8495   "chips": ["gfx10"],
8496   "map": {"at": 200720, "to": "mm"},
8497   "name": "GDS_RD_BURST_DATA"
8498  },
8499  {
8500   "chips": ["gfx10"],
8501   "map": {"at": 200724, "to": "mm"},
8502   "name": "GDS_WR_ADDR"
8503  },
8504  {
8505   "chips": ["gfx10"],
8506   "map": {"at": 200728, "to": "mm"},
8507   "name": "GDS_WR_DATA"
8508  },
8509  {
8510   "chips": ["gfx10"],
8511   "map": {"at": 200732, "to": "mm"},
8512   "name": "GDS_WR_BURST_ADDR"
8513  },
8514  {
8515   "chips": ["gfx10"],
8516   "map": {"at": 200736, "to": "mm"},
8517   "name": "GDS_WR_BURST_DATA"
8518  },
8519  {
8520   "chips": ["gfx10"],
8521   "map": {"at": 200740, "to": "mm"},
8522   "name": "GDS_WRITE_COMPLETE"
8523  },
8524  {
8525   "chips": ["gfx10"],
8526   "map": {"at": 200744, "to": "mm"},
8527   "name": "GDS_ATOM_CNTL",
8528   "type_ref": "GDS_ATOM_CNTL"
8529  },
8530  {
8531   "chips": ["gfx10"],
8532   "map": {"at": 200748, "to": "mm"},
8533   "name": "GDS_ATOM_COMPLETE",
8534   "type_ref": "GDS_ATOM_COMPLETE"
8535  },
8536  {
8537   "chips": ["gfx10"],
8538   "map": {"at": 200752, "to": "mm"},
8539   "name": "GDS_ATOM_BASE",
8540   "type_ref": "GDS_ATOM_BASE"
8541  },
8542  {
8543   "chips": ["gfx10"],
8544   "map": {"at": 200756, "to": "mm"},
8545   "name": "GDS_ATOM_SIZE",
8546   "type_ref": "GDS_ATOM_SIZE"
8547  },
8548  {
8549   "chips": ["gfx10"],
8550   "map": {"at": 200760, "to": "mm"},
8551   "name": "GDS_ATOM_OFFSET0",
8552   "type_ref": "GDS_ATOM_OFFSET0"
8553  },
8554  {
8555   "chips": ["gfx10"],
8556   "map": {"at": 200764, "to": "mm"},
8557   "name": "GDS_ATOM_OFFSET1",
8558   "type_ref": "GDS_ATOM_OFFSET1"
8559  },
8560  {
8561   "chips": ["gfx10"],
8562   "map": {"at": 200768, "to": "mm"},
8563   "name": "GDS_ATOM_DST"
8564  },
8565  {
8566   "chips": ["gfx10"],
8567   "map": {"at": 200772, "to": "mm"},
8568   "name": "GDS_ATOM_OP",
8569   "type_ref": "GDS_ATOM_OP"
8570  },
8571  {
8572   "chips": ["gfx10"],
8573   "map": {"at": 200776, "to": "mm"},
8574   "name": "GDS_ATOM_SRC0"
8575  },
8576  {
8577   "chips": ["gfx10"],
8578   "map": {"at": 200780, "to": "mm"},
8579   "name": "GDS_ATOM_SRC0_U"
8580  },
8581  {
8582   "chips": ["gfx10"],
8583   "map": {"at": 200784, "to": "mm"},
8584   "name": "GDS_ATOM_SRC1"
8585  },
8586  {
8587   "chips": ["gfx10"],
8588   "map": {"at": 200788, "to": "mm"},
8589   "name": "GDS_ATOM_SRC1_U"
8590  },
8591  {
8592   "chips": ["gfx10"],
8593   "map": {"at": 200792, "to": "mm"},
8594   "name": "GDS_ATOM_READ0"
8595  },
8596  {
8597   "chips": ["gfx10"],
8598   "map": {"at": 200796, "to": "mm"},
8599   "name": "GDS_ATOM_READ0_U"
8600  },
8601  {
8602   "chips": ["gfx10"],
8603   "map": {"at": 200800, "to": "mm"},
8604   "name": "GDS_ATOM_READ1"
8605  },
8606  {
8607   "chips": ["gfx10"],
8608   "map": {"at": 200804, "to": "mm"},
8609   "name": "GDS_ATOM_READ1_U"
8610  },
8611  {
8612   "chips": ["gfx10"],
8613   "map": {"at": 200808, "to": "mm"},
8614   "name": "GDS_GWS_RESOURCE_CNTL",
8615   "type_ref": "GDS_GWS_RESOURCE_CNTL"
8616  },
8617  {
8618   "chips": ["gfx10"],
8619   "map": {"at": 200812, "to": "mm"},
8620   "name": "GDS_GWS_RESOURCE",
8621   "type_ref": "GDS_GWS_RESOURCE"
8622  },
8623  {
8624   "chips": ["gfx10"],
8625   "map": {"at": 200816, "to": "mm"},
8626   "name": "GDS_GWS_RESOURCE_CNT",
8627   "type_ref": "GDS_GWS_RESOURCE_CNT"
8628  },
8629  {
8630   "chips": ["gfx10"],
8631   "map": {"at": 200820, "to": "mm"},
8632   "name": "GDS_OA_CNTL",
8633   "type_ref": "GDS_OA_CNTL"
8634  },
8635  {
8636   "chips": ["gfx10"],
8637   "map": {"at": 200824, "to": "mm"},
8638   "name": "GDS_OA_COUNTER"
8639  },
8640  {
8641   "chips": ["gfx10"],
8642   "map": {"at": 200828, "to": "mm"},
8643   "name": "GDS_OA_ADDRESS",
8644   "type_ref": "GDS_OA_ADDRESS"
8645  },
8646  {
8647   "chips": ["gfx10"],
8648   "map": {"at": 200832, "to": "mm"},
8649   "name": "GDS_OA_INCDEC",
8650   "type_ref": "GDS_OA_INCDEC"
8651  },
8652  {
8653   "chips": ["gfx10"],
8654   "map": {"at": 200836, "to": "mm"},
8655   "name": "GDS_OA_RING_SIZE"
8656  },
8657  {
8658   "chips": ["gfx10"],
8659   "map": {"at": 200960, "to": "mm"},
8660   "name": "SPI_CONFIG_CNTL_REMAP"
8661  },
8662  {
8663   "chips": ["gfx10"],
8664   "map": {"at": 200964, "to": "mm"},
8665   "name": "SPI_CONFIG_CNTL_1_REMAP"
8666  },
8667  {
8668   "chips": ["gfx10"],
8669   "map": {"at": 200968, "to": "mm"},
8670   "name": "SPI_CONFIG_CNTL_2_REMAP"
8671  },
8672  {
8673   "chips": ["gfx10"],
8674   "map": {"at": 200972, "to": "mm"},
8675   "name": "SPI_WAVE_LIMIT_CNTL_REMAP"
8676  },
8677  {
8678   "chips": ["gfx10"],
8679   "map": {"at": 212992, "to": "mm"},
8680   "name": "CPG_PERFCOUNTER1_LO"
8681  },
8682  {
8683   "chips": ["gfx10"],
8684   "map": {"at": 212996, "to": "mm"},
8685   "name": "CPG_PERFCOUNTER1_HI"
8686  },
8687  {
8688   "chips": ["gfx10"],
8689   "map": {"at": 213000, "to": "mm"},
8690   "name": "CPG_PERFCOUNTER0_LO"
8691  },
8692  {
8693   "chips": ["gfx10"],
8694   "map": {"at": 213004, "to": "mm"},
8695   "name": "CPG_PERFCOUNTER0_HI"
8696  },
8697  {
8698   "chips": ["gfx10"],
8699   "map": {"at": 213008, "to": "mm"},
8700   "name": "CPC_PERFCOUNTER1_LO"
8701  },
8702  {
8703   "chips": ["gfx10"],
8704   "map": {"at": 213012, "to": "mm"},
8705   "name": "CPC_PERFCOUNTER1_HI"
8706  },
8707  {
8708   "chips": ["gfx10"],
8709   "map": {"at": 213016, "to": "mm"},
8710   "name": "CPC_PERFCOUNTER0_LO"
8711  },
8712  {
8713   "chips": ["gfx10"],
8714   "map": {"at": 213020, "to": "mm"},
8715   "name": "CPC_PERFCOUNTER0_HI"
8716  },
8717  {
8718   "chips": ["gfx10"],
8719   "map": {"at": 213024, "to": "mm"},
8720   "name": "CPF_PERFCOUNTER1_LO"
8721  },
8722  {
8723   "chips": ["gfx10"],
8724   "map": {"at": 213028, "to": "mm"},
8725   "name": "CPF_PERFCOUNTER1_HI"
8726  },
8727  {
8728   "chips": ["gfx10"],
8729   "map": {"at": 213032, "to": "mm"},
8730   "name": "CPF_PERFCOUNTER0_LO"
8731  },
8732  {
8733   "chips": ["gfx10"],
8734   "map": {"at": 213036, "to": "mm"},
8735   "name": "CPF_PERFCOUNTER0_HI"
8736  },
8737  {
8738   "chips": ["gfx10"],
8739   "map": {"at": 213040, "to": "mm"},
8740   "name": "CPF_LATENCY_STATS_DATA"
8741  },
8742  {
8743   "chips": ["gfx10"],
8744   "map": {"at": 213044, "to": "mm"},
8745   "name": "CPG_LATENCY_STATS_DATA"
8746  },
8747  {
8748   "chips": ["gfx10"],
8749   "map": {"at": 213048, "to": "mm"},
8750   "name": "CPC_LATENCY_STATS_DATA"
8751  },
8752  {
8753   "chips": ["gfx10"],
8754   "map": {"at": 213248, "to": "mm"},
8755   "name": "GRBM_PERFCOUNTER0_LO"
8756  },
8757  {
8758   "chips": ["gfx10"],
8759   "map": {"at": 213252, "to": "mm"},
8760   "name": "GRBM_PERFCOUNTER0_HI"
8761  },
8762  {
8763   "chips": ["gfx10"],
8764   "map": {"at": 213260, "to": "mm"},
8765   "name": "GRBM_PERFCOUNTER1_LO"
8766  },
8767  {
8768   "chips": ["gfx10"],
8769   "map": {"at": 213264, "to": "mm"},
8770   "name": "GRBM_PERFCOUNTER1_HI"
8771  },
8772  {
8773   "chips": ["gfx10"],
8774   "map": {"at": 213268, "to": "mm"},
8775   "name": "GRBM_SE0_PERFCOUNTER_LO"
8776  },
8777  {
8778   "chips": ["gfx10"],
8779   "map": {"at": 213272, "to": "mm"},
8780   "name": "GRBM_SE0_PERFCOUNTER_HI"
8781  },
8782  {
8783   "chips": ["gfx10"],
8784   "map": {"at": 213276, "to": "mm"},
8785   "name": "GRBM_SE1_PERFCOUNTER_LO"
8786  },
8787  {
8788   "chips": ["gfx10"],
8789   "map": {"at": 213280, "to": "mm"},
8790   "name": "GRBM_SE1_PERFCOUNTER_HI"
8791  },
8792  {
8793   "chips": ["gfx10"],
8794   "map": {"at": 213284, "to": "mm"},
8795   "name": "GRBM_SE2_PERFCOUNTER_LO"
8796  },
8797  {
8798   "chips": ["gfx10"],
8799   "map": {"at": 213288, "to": "mm"},
8800   "name": "GRBM_SE2_PERFCOUNTER_HI"
8801  },
8802  {
8803   "chips": ["gfx10"],
8804   "map": {"at": 213292, "to": "mm"},
8805   "name": "GRBM_SE3_PERFCOUNTER_LO"
8806  },
8807  {
8808   "chips": ["gfx10"],
8809   "map": {"at": 213296, "to": "mm"},
8810   "name": "GRBM_SE3_PERFCOUNTER_HI"
8811  },
8812  {
8813   "chips": ["gfx10"],
8814   "map": {"at": 213504, "to": "mm"},
8815   "name": "GE_PERFCOUNTER0_LO"
8816  },
8817  {
8818   "chips": ["gfx10"],
8819   "map": {"at": 213508, "to": "mm"},
8820   "name": "GE_PERFCOUNTER0_HI"
8821  },
8822  {
8823   "chips": ["gfx10"],
8824   "map": {"at": 213512, "to": "mm"},
8825   "name": "GE_PERFCOUNTER1_LO"
8826  },
8827  {
8828   "chips": ["gfx10"],
8829   "map": {"at": 213516, "to": "mm"},
8830   "name": "GE_PERFCOUNTER1_HI"
8831  },
8832  {
8833   "chips": ["gfx10"],
8834   "map": {"at": 213520, "to": "mm"},
8835   "name": "GE_PERFCOUNTER2_LO"
8836  },
8837  {
8838   "chips": ["gfx10"],
8839   "map": {"at": 213524, "to": "mm"},
8840   "name": "GE_PERFCOUNTER2_HI"
8841  },
8842  {
8843   "chips": ["gfx10"],
8844   "map": {"at": 213528, "to": "mm"},
8845   "name": "GE_PERFCOUNTER3_LO"
8846  },
8847  {
8848   "chips": ["gfx10"],
8849   "map": {"at": 213532, "to": "mm"},
8850   "name": "GE_PERFCOUNTER3_HI"
8851  },
8852  {
8853   "chips": ["gfx10"],
8854   "map": {"at": 213536, "to": "mm"},
8855   "name": "GE_PERFCOUNTER4_LO"
8856  },
8857  {
8858   "chips": ["gfx10"],
8859   "map": {"at": 213540, "to": "mm"},
8860   "name": "GE_PERFCOUNTER4_HI"
8861  },
8862  {
8863   "chips": ["gfx10"],
8864   "map": {"at": 213544, "to": "mm"},
8865   "name": "GE_PERFCOUNTER5_LO"
8866  },
8867  {
8868   "chips": ["gfx10"],
8869   "map": {"at": 213548, "to": "mm"},
8870   "name": "GE_PERFCOUNTER5_HI"
8871  },
8872  {
8873   "chips": ["gfx10"],
8874   "map": {"at": 213552, "to": "mm"},
8875   "name": "GE_PERFCOUNTER6_LO"
8876  },
8877  {
8878   "chips": ["gfx10"],
8879   "map": {"at": 213556, "to": "mm"},
8880   "name": "GE_PERFCOUNTER6_HI"
8881  },
8882  {
8883   "chips": ["gfx10"],
8884   "map": {"at": 213560, "to": "mm"},
8885   "name": "GE_PERFCOUNTER7_LO"
8886  },
8887  {
8888   "chips": ["gfx10"],
8889   "map": {"at": 213564, "to": "mm"},
8890   "name": "GE_PERFCOUNTER7_HI"
8891  },
8892  {
8893   "chips": ["gfx10"],
8894   "map": {"at": 213568, "to": "mm"},
8895   "name": "GE_PERFCOUNTER8_LO"
8896  },
8897  {
8898   "chips": ["gfx10"],
8899   "map": {"at": 213572, "to": "mm"},
8900   "name": "GE_PERFCOUNTER8_HI"
8901  },
8902  {
8903   "chips": ["gfx10"],
8904   "map": {"at": 213576, "to": "mm"},
8905   "name": "GE_PERFCOUNTER9_LO"
8906  },
8907  {
8908   "chips": ["gfx10"],
8909   "map": {"at": 213580, "to": "mm"},
8910   "name": "GE_PERFCOUNTER9_HI"
8911  },
8912  {
8913   "chips": ["gfx10"],
8914   "map": {"at": 213584, "to": "mm"},
8915   "name": "GE_PERFCOUNTER10_LO"
8916  },
8917  {
8918   "chips": ["gfx10"],
8919   "map": {"at": 213588, "to": "mm"},
8920   "name": "GE_PERFCOUNTER10_HI"
8921  },
8922  {
8923   "chips": ["gfx10"],
8924   "map": {"at": 213592, "to": "mm"},
8925   "name": "GE_PERFCOUNTER11_LO"
8926  },
8927  {
8928   "chips": ["gfx10"],
8929   "map": {"at": 213596, "to": "mm"},
8930   "name": "GE_PERFCOUNTER11_HI"
8931  },
8932  {
8933   "chips": ["gfx10"],
8934   "map": {"at": 214016, "to": "mm"},
8935   "name": "PA_SU_PERFCOUNTER0_LO"
8936  },
8937  {
8938   "chips": ["gfx10"],
8939   "map": {"at": 214020, "to": "mm"},
8940   "name": "PA_SU_PERFCOUNTER0_HI",
8941   "type_ref": "PA_SU_PERFCOUNTER0_HI"
8942  },
8943  {
8944   "chips": ["gfx10"],
8945   "map": {"at": 214024, "to": "mm"},
8946   "name": "PA_SU_PERFCOUNTER1_LO"
8947  },
8948  {
8949   "chips": ["gfx10"],
8950   "map": {"at": 214028, "to": "mm"},
8951   "name": "PA_SU_PERFCOUNTER1_HI",
8952   "type_ref": "PA_SU_PERFCOUNTER0_HI"
8953  },
8954  {
8955   "chips": ["gfx10"],
8956   "map": {"at": 214032, "to": "mm"},
8957   "name": "PA_SU_PERFCOUNTER2_LO"
8958  },
8959  {
8960   "chips": ["gfx10"],
8961   "map": {"at": 214036, "to": "mm"},
8962   "name": "PA_SU_PERFCOUNTER2_HI",
8963   "type_ref": "PA_SU_PERFCOUNTER0_HI"
8964  },
8965  {
8966   "chips": ["gfx10"],
8967   "map": {"at": 214040, "to": "mm"},
8968   "name": "PA_SU_PERFCOUNTER3_LO"
8969  },
8970  {
8971   "chips": ["gfx10"],
8972   "map": {"at": 214044, "to": "mm"},
8973   "name": "PA_SU_PERFCOUNTER3_HI",
8974   "type_ref": "PA_SU_PERFCOUNTER0_HI"
8975  },
8976  {
8977   "chips": ["gfx10"],
8978   "map": {"at": 214272, "to": "mm"},
8979   "name": "PA_SC_PERFCOUNTER0_LO"
8980  },
8981  {
8982   "chips": ["gfx10"],
8983   "map": {"at": 214276, "to": "mm"},
8984   "name": "PA_SC_PERFCOUNTER0_HI"
8985  },
8986  {
8987   "chips": ["gfx10"],
8988   "map": {"at": 214280, "to": "mm"},
8989   "name": "PA_SC_PERFCOUNTER1_LO"
8990  },
8991  {
8992   "chips": ["gfx10"],
8993   "map": {"at": 214284, "to": "mm"},
8994   "name": "PA_SC_PERFCOUNTER1_HI"
8995  },
8996  {
8997   "chips": ["gfx10"],
8998   "map": {"at": 214288, "to": "mm"},
8999   "name": "PA_SC_PERFCOUNTER2_LO"
9000  },
9001  {
9002   "chips": ["gfx10"],
9003   "map": {"at": 214292, "to": "mm"},
9004   "name": "PA_SC_PERFCOUNTER2_HI"
9005  },
9006  {
9007   "chips": ["gfx10"],
9008   "map": {"at": 214296, "to": "mm"},
9009   "name": "PA_SC_PERFCOUNTER3_LO"
9010  },
9011  {
9012   "chips": ["gfx10"],
9013   "map": {"at": 214300, "to": "mm"},
9014   "name": "PA_SC_PERFCOUNTER3_HI"
9015  },
9016  {
9017   "chips": ["gfx10"],
9018   "map": {"at": 214304, "to": "mm"},
9019   "name": "PA_SC_PERFCOUNTER4_LO"
9020  },
9021  {
9022   "chips": ["gfx10"],
9023   "map": {"at": 214308, "to": "mm"},
9024   "name": "PA_SC_PERFCOUNTER4_HI"
9025  },
9026  {
9027   "chips": ["gfx10"],
9028   "map": {"at": 214312, "to": "mm"},
9029   "name": "PA_SC_PERFCOUNTER5_LO"
9030  },
9031  {
9032   "chips": ["gfx10"],
9033   "map": {"at": 214316, "to": "mm"},
9034   "name": "PA_SC_PERFCOUNTER5_HI"
9035  },
9036  {
9037   "chips": ["gfx10"],
9038   "map": {"at": 214320, "to": "mm"},
9039   "name": "PA_SC_PERFCOUNTER6_LO"
9040  },
9041  {
9042   "chips": ["gfx10"],
9043   "map": {"at": 214324, "to": "mm"},
9044   "name": "PA_SC_PERFCOUNTER6_HI"
9045  },
9046  {
9047   "chips": ["gfx10"],
9048   "map": {"at": 214328, "to": "mm"},
9049   "name": "PA_SC_PERFCOUNTER7_LO"
9050  },
9051  {
9052   "chips": ["gfx10"],
9053   "map": {"at": 214332, "to": "mm"},
9054   "name": "PA_SC_PERFCOUNTER7_HI"
9055  },
9056  {
9057   "chips": ["gfx10"],
9058   "map": {"at": 214528, "to": "mm"},
9059   "name": "SPI_PERFCOUNTER0_HI"
9060  },
9061  {
9062   "chips": ["gfx10"],
9063   "map": {"at": 214532, "to": "mm"},
9064   "name": "SPI_PERFCOUNTER0_LO"
9065  },
9066  {
9067   "chips": ["gfx10"],
9068   "map": {"at": 214536, "to": "mm"},
9069   "name": "SPI_PERFCOUNTER1_HI"
9070  },
9071  {
9072   "chips": ["gfx10"],
9073   "map": {"at": 214540, "to": "mm"},
9074   "name": "SPI_PERFCOUNTER1_LO"
9075  },
9076  {
9077   "chips": ["gfx10"],
9078   "map": {"at": 214544, "to": "mm"},
9079   "name": "SPI_PERFCOUNTER2_HI"
9080  },
9081  {
9082   "chips": ["gfx10"],
9083   "map": {"at": 214548, "to": "mm"},
9084   "name": "SPI_PERFCOUNTER2_LO"
9085  },
9086  {
9087   "chips": ["gfx10"],
9088   "map": {"at": 214552, "to": "mm"},
9089   "name": "SPI_PERFCOUNTER3_HI"
9090  },
9091  {
9092   "chips": ["gfx10"],
9093   "map": {"at": 214556, "to": "mm"},
9094   "name": "SPI_PERFCOUNTER3_LO"
9095  },
9096  {
9097   "chips": ["gfx10"],
9098   "map": {"at": 214560, "to": "mm"},
9099   "name": "SPI_PERFCOUNTER4_HI"
9100  },
9101  {
9102   "chips": ["gfx10"],
9103   "map": {"at": 214564, "to": "mm"},
9104   "name": "SPI_PERFCOUNTER4_LO"
9105  },
9106  {
9107   "chips": ["gfx10"],
9108   "map": {"at": 214568, "to": "mm"},
9109   "name": "SPI_PERFCOUNTER5_HI"
9110  },
9111  {
9112   "chips": ["gfx10"],
9113   "map": {"at": 214572, "to": "mm"},
9114   "name": "SPI_PERFCOUNTER5_LO"
9115  },
9116  {
9117   "chips": ["gfx10"],
9118   "map": {"at": 214784, "to": "mm"},
9119   "name": "SQ_PERFCOUNTER0_LO"
9120  },
9121  {
9122   "chips": ["gfx10"],
9123   "map": {"at": 214788, "to": "mm"},
9124   "name": "SQ_PERFCOUNTER0_HI"
9125  },
9126  {
9127   "chips": ["gfx10"],
9128   "map": {"at": 214792, "to": "mm"},
9129   "name": "SQ_PERFCOUNTER1_LO"
9130  },
9131  {
9132   "chips": ["gfx10"],
9133   "map": {"at": 214796, "to": "mm"},
9134   "name": "SQ_PERFCOUNTER1_HI"
9135  },
9136  {
9137   "chips": ["gfx10"],
9138   "map": {"at": 214800, "to": "mm"},
9139   "name": "SQ_PERFCOUNTER2_LO"
9140  },
9141  {
9142   "chips": ["gfx10"],
9143   "map": {"at": 214804, "to": "mm"},
9144   "name": "SQ_PERFCOUNTER2_HI"
9145  },
9146  {
9147   "chips": ["gfx10"],
9148   "map": {"at": 214808, "to": "mm"},
9149   "name": "SQ_PERFCOUNTER3_LO"
9150  },
9151  {
9152   "chips": ["gfx10"],
9153   "map": {"at": 214812, "to": "mm"},
9154   "name": "SQ_PERFCOUNTER3_HI"
9155  },
9156  {
9157   "chips": ["gfx10"],
9158   "map": {"at": 214816, "to": "mm"},
9159   "name": "SQ_PERFCOUNTER4_LO"
9160  },
9161  {
9162   "chips": ["gfx10"],
9163   "map": {"at": 214820, "to": "mm"},
9164   "name": "SQ_PERFCOUNTER4_HI"
9165  },
9166  {
9167   "chips": ["gfx10"],
9168   "map": {"at": 214824, "to": "mm"},
9169   "name": "SQ_PERFCOUNTER5_LO"
9170  },
9171  {
9172   "chips": ["gfx10"],
9173   "map": {"at": 214828, "to": "mm"},
9174   "name": "SQ_PERFCOUNTER5_HI"
9175  },
9176  {
9177   "chips": ["gfx10"],
9178   "map": {"at": 214832, "to": "mm"},
9179   "name": "SQ_PERFCOUNTER6_LO"
9180  },
9181  {
9182   "chips": ["gfx10"],
9183   "map": {"at": 214836, "to": "mm"},
9184   "name": "SQ_PERFCOUNTER6_HI"
9185  },
9186  {
9187   "chips": ["gfx10"],
9188   "map": {"at": 214840, "to": "mm"},
9189   "name": "SQ_PERFCOUNTER7_LO"
9190  },
9191  {
9192   "chips": ["gfx10"],
9193   "map": {"at": 214844, "to": "mm"},
9194   "name": "SQ_PERFCOUNTER7_HI"
9195  },
9196  {
9197   "chips": ["gfx10"],
9198   "map": {"at": 214848, "to": "mm"},
9199   "name": "SQ_PERFCOUNTER8_LO"
9200  },
9201  {
9202   "chips": ["gfx10"],
9203   "map": {"at": 214852, "to": "mm"},
9204   "name": "SQ_PERFCOUNTER8_HI"
9205  },
9206  {
9207   "chips": ["gfx10"],
9208   "map": {"at": 214856, "to": "mm"},
9209   "name": "SQ_PERFCOUNTER9_LO"
9210  },
9211  {
9212   "chips": ["gfx10"],
9213   "map": {"at": 214860, "to": "mm"},
9214   "name": "SQ_PERFCOUNTER9_HI"
9215  },
9216  {
9217   "chips": ["gfx10"],
9218   "map": {"at": 214864, "to": "mm"},
9219   "name": "SQ_PERFCOUNTER10_LO"
9220  },
9221  {
9222   "chips": ["gfx10"],
9223   "map": {"at": 214868, "to": "mm"},
9224   "name": "SQ_PERFCOUNTER10_HI"
9225  },
9226  {
9227   "chips": ["gfx10"],
9228   "map": {"at": 214872, "to": "mm"},
9229   "name": "SQ_PERFCOUNTER11_LO"
9230  },
9231  {
9232   "chips": ["gfx10"],
9233   "map": {"at": 214876, "to": "mm"},
9234   "name": "SQ_PERFCOUNTER11_HI"
9235  },
9236  {
9237   "chips": ["gfx10"],
9238   "map": {"at": 214880, "to": "mm"},
9239   "name": "SQ_PERFCOUNTER12_LO"
9240  },
9241  {
9242   "chips": ["gfx10"],
9243   "map": {"at": 214884, "to": "mm"},
9244   "name": "SQ_PERFCOUNTER12_HI"
9245  },
9246  {
9247   "chips": ["gfx10"],
9248   "map": {"at": 214888, "to": "mm"},
9249   "name": "SQ_PERFCOUNTER13_LO"
9250  },
9251  {
9252   "chips": ["gfx10"],
9253   "map": {"at": 214892, "to": "mm"},
9254   "name": "SQ_PERFCOUNTER13_HI"
9255  },
9256  {
9257   "chips": ["gfx10"],
9258   "map": {"at": 214896, "to": "mm"},
9259   "name": "SQ_PERFCOUNTER14_LO"
9260  },
9261  {
9262   "chips": ["gfx10"],
9263   "map": {"at": 214900, "to": "mm"},
9264   "name": "SQ_PERFCOUNTER14_HI"
9265  },
9266  {
9267   "chips": ["gfx10"],
9268   "map": {"at": 214904, "to": "mm"},
9269   "name": "SQ_PERFCOUNTER15_LO"
9270  },
9271  {
9272   "chips": ["gfx10"],
9273   "map": {"at": 214908, "to": "mm"},
9274   "name": "SQ_PERFCOUNTER15_HI"
9275  },
9276  {
9277   "chips": ["gfx10"],
9278   "map": {"at": 215296, "to": "mm"},
9279   "name": "SX_PERFCOUNTER0_LO"
9280  },
9281  {
9282   "chips": ["gfx10"],
9283   "map": {"at": 215300, "to": "mm"},
9284   "name": "SX_PERFCOUNTER0_HI"
9285  },
9286  {
9287   "chips": ["gfx10"],
9288   "map": {"at": 215304, "to": "mm"},
9289   "name": "SX_PERFCOUNTER1_LO"
9290  },
9291  {
9292   "chips": ["gfx10"],
9293   "map": {"at": 215308, "to": "mm"},
9294   "name": "SX_PERFCOUNTER1_HI"
9295  },
9296  {
9297   "chips": ["gfx10"],
9298   "map": {"at": 215312, "to": "mm"},
9299   "name": "SX_PERFCOUNTER2_LO"
9300  },
9301  {
9302   "chips": ["gfx10"],
9303   "map": {"at": 215316, "to": "mm"},
9304   "name": "SX_PERFCOUNTER2_HI"
9305  },
9306  {
9307   "chips": ["gfx10"],
9308   "map": {"at": 215320, "to": "mm"},
9309   "name": "SX_PERFCOUNTER3_LO"
9310  },
9311  {
9312   "chips": ["gfx10"],
9313   "map": {"at": 215324, "to": "mm"},
9314   "name": "SX_PERFCOUNTER3_HI"
9315  },
9316  {
9317   "chips": ["gfx10"],
9318   "map": {"at": 215424, "to": "mm"},
9319   "name": "GCEA_PERFCOUNTER2_LO"
9320  },
9321  {
9322   "chips": ["gfx10"],
9323   "map": {"at": 215428, "to": "mm"},
9324   "name": "GCEA_PERFCOUNTER2_HI"
9325  },
9326  {
9327   "chips": ["gfx10"],
9328   "map": {"at": 215552, "to": "mm"},
9329   "name": "GDS_PERFCOUNTER0_LO"
9330  },
9331  {
9332   "chips": ["gfx10"],
9333   "map": {"at": 215556, "to": "mm"},
9334   "name": "GDS_PERFCOUNTER0_HI"
9335  },
9336  {
9337   "chips": ["gfx10"],
9338   "map": {"at": 215560, "to": "mm"},
9339   "name": "GDS_PERFCOUNTER1_LO"
9340  },
9341  {
9342   "chips": ["gfx10"],
9343   "map": {"at": 215564, "to": "mm"},
9344   "name": "GDS_PERFCOUNTER1_HI"
9345  },
9346  {
9347   "chips": ["gfx10"],
9348   "map": {"at": 215568, "to": "mm"},
9349   "name": "GDS_PERFCOUNTER2_LO"
9350  },
9351  {
9352   "chips": ["gfx10"],
9353   "map": {"at": 215572, "to": "mm"},
9354   "name": "GDS_PERFCOUNTER2_HI"
9355  },
9356  {
9357   "chips": ["gfx10"],
9358   "map": {"at": 215576, "to": "mm"},
9359   "name": "GDS_PERFCOUNTER3_LO"
9360  },
9361  {
9362   "chips": ["gfx10"],
9363   "map": {"at": 215580, "to": "mm"},
9364   "name": "GDS_PERFCOUNTER3_HI"
9365  },
9366  {
9367   "chips": ["gfx10"],
9368   "map": {"at": 215808, "to": "mm"},
9369   "name": "TA_PERFCOUNTER0_LO"
9370  },
9371  {
9372   "chips": ["gfx10"],
9373   "map": {"at": 215812, "to": "mm"},
9374   "name": "TA_PERFCOUNTER0_HI"
9375  },
9376  {
9377   "chips": ["gfx10"],
9378   "map": {"at": 215816, "to": "mm"},
9379   "name": "TA_PERFCOUNTER1_LO"
9380  },
9381  {
9382   "chips": ["gfx10"],
9383   "map": {"at": 215820, "to": "mm"},
9384   "name": "TA_PERFCOUNTER1_HI"
9385  },
9386  {
9387   "chips": ["gfx10"],
9388   "map": {"at": 216064, "to": "mm"},
9389   "name": "TD_PERFCOUNTER0_LO"
9390  },
9391  {
9392   "chips": ["gfx10"],
9393   "map": {"at": 216068, "to": "mm"},
9394   "name": "TD_PERFCOUNTER0_HI"
9395  },
9396  {
9397   "chips": ["gfx10"],
9398   "map": {"at": 216072, "to": "mm"},
9399   "name": "TD_PERFCOUNTER1_LO"
9400  },
9401  {
9402   "chips": ["gfx10"],
9403   "map": {"at": 216076, "to": "mm"},
9404   "name": "TD_PERFCOUNTER1_HI"
9405  },
9406  {
9407   "chips": ["gfx10"],
9408   "map": {"at": 216320, "to": "mm"},
9409   "name": "TCP_PERFCOUNTER0_LO"
9410  },
9411  {
9412   "chips": ["gfx10"],
9413   "map": {"at": 216324, "to": "mm"},
9414   "name": "TCP_PERFCOUNTER0_HI"
9415  },
9416  {
9417   "chips": ["gfx10"],
9418   "map": {"at": 216328, "to": "mm"},
9419   "name": "TCP_PERFCOUNTER1_LO"
9420  },
9421  {
9422   "chips": ["gfx10"],
9423   "map": {"at": 216332, "to": "mm"},
9424   "name": "TCP_PERFCOUNTER1_HI"
9425  },
9426  {
9427   "chips": ["gfx10"],
9428   "map": {"at": 216336, "to": "mm"},
9429   "name": "TCP_PERFCOUNTER2_LO"
9430  },
9431  {
9432   "chips": ["gfx10"],
9433   "map": {"at": 216340, "to": "mm"},
9434   "name": "TCP_PERFCOUNTER2_HI"
9435  },
9436  {
9437   "chips": ["gfx10"],
9438   "map": {"at": 216344, "to": "mm"},
9439   "name": "TCP_PERFCOUNTER3_LO"
9440  },
9441  {
9442   "chips": ["gfx10"],
9443   "map": {"at": 216348, "to": "mm"},
9444   "name": "TCP_PERFCOUNTER3_HI"
9445  },
9446  {
9447   "chips": ["gfx10"],
9448   "map": {"at": 216576, "to": "mm"},
9449   "name": "GL2C_PERFCOUNTER0_LO"
9450  },
9451  {
9452   "chips": ["gfx10"],
9453   "map": {"at": 216580, "to": "mm"},
9454   "name": "GL2C_PERFCOUNTER0_HI"
9455  },
9456  {
9457   "chips": ["gfx10"],
9458   "map": {"at": 216584, "to": "mm"},
9459   "name": "GL2C_PERFCOUNTER1_LO"
9460  },
9461  {
9462   "chips": ["gfx10"],
9463   "map": {"at": 216588, "to": "mm"},
9464   "name": "GL2C_PERFCOUNTER1_HI"
9465  },
9466  {
9467   "chips": ["gfx10"],
9468   "map": {"at": 216592, "to": "mm"},
9469   "name": "GL2C_PERFCOUNTER2_LO"
9470  },
9471  {
9472   "chips": ["gfx10"],
9473   "map": {"at": 216596, "to": "mm"},
9474   "name": "GL2C_PERFCOUNTER2_HI"
9475  },
9476  {
9477   "chips": ["gfx10"],
9478   "map": {"at": 216600, "to": "mm"},
9479   "name": "GL2C_PERFCOUNTER3_LO"
9480  },
9481  {
9482   "chips": ["gfx10"],
9483   "map": {"at": 216604, "to": "mm"},
9484   "name": "GL2C_PERFCOUNTER3_HI"
9485  },
9486  {
9487   "chips": ["gfx10"],
9488   "map": {"at": 216640, "to": "mm"},
9489   "name": "GL2A_PERFCOUNTER0_LO"
9490  },
9491  {
9492   "chips": ["gfx10"],
9493   "map": {"at": 216644, "to": "mm"},
9494   "name": "GL2A_PERFCOUNTER0_HI"
9495  },
9496  {
9497   "chips": ["gfx10"],
9498   "map": {"at": 216648, "to": "mm"},
9499   "name": "GL2A_PERFCOUNTER1_LO"
9500  },
9501  {
9502   "chips": ["gfx10"],
9503   "map": {"at": 216652, "to": "mm"},
9504   "name": "GL2A_PERFCOUNTER1_HI"
9505  },
9506  {
9507   "chips": ["gfx10"],
9508   "map": {"at": 216656, "to": "mm"},
9509   "name": "GL2A_PERFCOUNTER2_LO"
9510  },
9511  {
9512   "chips": ["gfx10"],
9513   "map": {"at": 216660, "to": "mm"},
9514   "name": "GL2A_PERFCOUNTER2_HI"
9515  },
9516  {
9517   "chips": ["gfx10"],
9518   "map": {"at": 216664, "to": "mm"},
9519   "name": "GL2A_PERFCOUNTER3_LO"
9520  },
9521  {
9522   "chips": ["gfx10"],
9523   "map": {"at": 216668, "to": "mm"},
9524   "name": "GL2A_PERFCOUNTER3_HI"
9525  },
9526  {
9527   "chips": ["gfx10"],
9528   "map": {"at": 216704, "to": "mm"},
9529   "name": "GL1C_PERFCOUNTER0_LO"
9530  },
9531  {
9532   "chips": ["gfx10"],
9533   "map": {"at": 216708, "to": "mm"},
9534   "name": "GL1C_PERFCOUNTER0_HI"
9535  },
9536  {
9537   "chips": ["gfx10"],
9538   "map": {"at": 216712, "to": "mm"},
9539   "name": "GL1C_PERFCOUNTER1_LO"
9540  },
9541  {
9542   "chips": ["gfx10"],
9543   "map": {"at": 216716, "to": "mm"},
9544   "name": "GL1C_PERFCOUNTER1_HI"
9545  },
9546  {
9547   "chips": ["gfx10"],
9548   "map": {"at": 216720, "to": "mm"},
9549   "name": "GL1C_PERFCOUNTER2_LO"
9550  },
9551  {
9552   "chips": ["gfx10"],
9553   "map": {"at": 216724, "to": "mm"},
9554   "name": "GL1C_PERFCOUNTER2_HI"
9555  },
9556  {
9557   "chips": ["gfx10"],
9558   "map": {"at": 216728, "to": "mm"},
9559   "name": "GL1C_PERFCOUNTER3_LO"
9560  },
9561  {
9562   "chips": ["gfx10"],
9563   "map": {"at": 216732, "to": "mm"},
9564   "name": "GL1C_PERFCOUNTER3_HI"
9565  },
9566  {
9567   "chips": ["gfx10"],
9568   "map": {"at": 216832, "to": "mm"},
9569   "name": "CHC_PERFCOUNTER0_LO"
9570  },
9571  {
9572   "chips": ["gfx10"],
9573   "map": {"at": 216836, "to": "mm"},
9574   "name": "CHC_PERFCOUNTER0_HI"
9575  },
9576  {
9577   "chips": ["gfx10"],
9578   "map": {"at": 216840, "to": "mm"},
9579   "name": "CHC_PERFCOUNTER1_LO"
9580  },
9581  {
9582   "chips": ["gfx10"],
9583   "map": {"at": 216844, "to": "mm"},
9584   "name": "CHC_PERFCOUNTER1_HI"
9585  },
9586  {
9587   "chips": ["gfx10"],
9588   "map": {"at": 216848, "to": "mm"},
9589   "name": "CHC_PERFCOUNTER2_LO"
9590  },
9591  {
9592   "chips": ["gfx10"],
9593   "map": {"at": 216852, "to": "mm"},
9594   "name": "CHC_PERFCOUNTER2_HI"
9595  },
9596  {
9597   "chips": ["gfx10"],
9598   "map": {"at": 216856, "to": "mm"},
9599   "name": "CHC_PERFCOUNTER3_LO"
9600  },
9601  {
9602   "chips": ["gfx10"],
9603   "map": {"at": 216860, "to": "mm"},
9604   "name": "CHC_PERFCOUNTER3_HI"
9605  },
9606  {
9607   "chips": ["gfx10"],
9608   "map": {"at": 216864, "to": "mm"},
9609   "name": "CHCG_PERFCOUNTER0_LO"
9610  },
9611  {
9612   "chips": ["gfx10"],
9613   "map": {"at": 216868, "to": "mm"},
9614   "name": "CHCG_PERFCOUNTER0_HI"
9615  },
9616  {
9617   "chips": ["gfx10"],
9618   "map": {"at": 216872, "to": "mm"},
9619   "name": "CHCG_PERFCOUNTER1_LO"
9620  },
9621  {
9622   "chips": ["gfx10"],
9623   "map": {"at": 216876, "to": "mm"},
9624   "name": "CHCG_PERFCOUNTER1_HI"
9625  },
9626  {
9627   "chips": ["gfx10"],
9628   "map": {"at": 216880, "to": "mm"},
9629   "name": "CHCG_PERFCOUNTER2_LO"
9630  },
9631  {
9632   "chips": ["gfx10"],
9633   "map": {"at": 216884, "to": "mm"},
9634   "name": "CHCG_PERFCOUNTER2_HI"
9635  },
9636  {
9637   "chips": ["gfx10"],
9638   "map": {"at": 216888, "to": "mm"},
9639   "name": "CHCG_PERFCOUNTER3_LO"
9640  },
9641  {
9642   "chips": ["gfx10"],
9643   "map": {"at": 216892, "to": "mm"},
9644   "name": "CHCG_PERFCOUNTER3_HI"
9645  },
9646  {
9647   "chips": ["gfx10"],
9648   "map": {"at": 217112, "to": "mm"},
9649   "name": "CB_PERFCOUNTER0_LO"
9650  },
9651  {
9652   "chips": ["gfx10"],
9653   "map": {"at": 217116, "to": "mm"},
9654   "name": "CB_PERFCOUNTER0_HI"
9655  },
9656  {
9657   "chips": ["gfx10"],
9658   "map": {"at": 217120, "to": "mm"},
9659   "name": "CB_PERFCOUNTER1_LO"
9660  },
9661  {
9662   "chips": ["gfx10"],
9663   "map": {"at": 217124, "to": "mm"},
9664   "name": "CB_PERFCOUNTER1_HI"
9665  },
9666  {
9667   "chips": ["gfx10"],
9668   "map": {"at": 217128, "to": "mm"},
9669   "name": "CB_PERFCOUNTER2_LO"
9670  },
9671  {
9672   "chips": ["gfx10"],
9673   "map": {"at": 217132, "to": "mm"},
9674   "name": "CB_PERFCOUNTER2_HI"
9675  },
9676  {
9677   "chips": ["gfx10"],
9678   "map": {"at": 217136, "to": "mm"},
9679   "name": "CB_PERFCOUNTER3_LO"
9680  },
9681  {
9682   "chips": ["gfx10"],
9683   "map": {"at": 217140, "to": "mm"},
9684   "name": "CB_PERFCOUNTER3_HI"
9685  },
9686  {
9687   "chips": ["gfx10"],
9688   "map": {"at": 217344, "to": "mm"},
9689   "name": "DB_PERFCOUNTER0_LO"
9690  },
9691  {
9692   "chips": ["gfx10"],
9693   "map": {"at": 217348, "to": "mm"},
9694   "name": "DB_PERFCOUNTER0_HI"
9695  },
9696  {
9697   "chips": ["gfx10"],
9698   "map": {"at": 217352, "to": "mm"},
9699   "name": "DB_PERFCOUNTER1_LO"
9700  },
9701  {
9702   "chips": ["gfx10"],
9703   "map": {"at": 217356, "to": "mm"},
9704   "name": "DB_PERFCOUNTER1_HI"
9705  },
9706  {
9707   "chips": ["gfx10"],
9708   "map": {"at": 217360, "to": "mm"},
9709   "name": "DB_PERFCOUNTER2_LO"
9710  },
9711  {
9712   "chips": ["gfx10"],
9713   "map": {"at": 217364, "to": "mm"},
9714   "name": "DB_PERFCOUNTER2_HI"
9715  },
9716  {
9717   "chips": ["gfx10"],
9718   "map": {"at": 217368, "to": "mm"},
9719   "name": "DB_PERFCOUNTER3_LO"
9720  },
9721  {
9722   "chips": ["gfx10"],
9723   "map": {"at": 217372, "to": "mm"},
9724   "name": "DB_PERFCOUNTER3_HI"
9725  },
9726  {
9727   "chips": ["gfx10"],
9728   "map": {"at": 217600, "to": "mm"},
9729   "name": "RLC_PERFCOUNTER0_LO"
9730  },
9731  {
9732   "chips": ["gfx10"],
9733   "map": {"at": 217604, "to": "mm"},
9734   "name": "RLC_PERFCOUNTER0_HI"
9735  },
9736  {
9737   "chips": ["gfx10"],
9738   "map": {"at": 217608, "to": "mm"},
9739   "name": "RLC_PERFCOUNTER1_LO"
9740  },
9741  {
9742   "chips": ["gfx10"],
9743   "map": {"at": 217612, "to": "mm"},
9744   "name": "RLC_PERFCOUNTER1_HI"
9745  },
9746  {
9747   "chips": ["gfx10"],
9748   "map": {"at": 217856, "to": "mm"},
9749   "name": "RMI_PERFCOUNTER0_LO"
9750  },
9751  {
9752   "chips": ["gfx10"],
9753   "map": {"at": 217860, "to": "mm"},
9754   "name": "RMI_PERFCOUNTER0_HI"
9755  },
9756  {
9757   "chips": ["gfx10"],
9758   "map": {"at": 217864, "to": "mm"},
9759   "name": "RMI_PERFCOUNTER1_LO"
9760  },
9761  {
9762   "chips": ["gfx10"],
9763   "map": {"at": 217868, "to": "mm"},
9764   "name": "RMI_PERFCOUNTER1_HI"
9765  },
9766  {
9767   "chips": ["gfx10"],
9768   "map": {"at": 217872, "to": "mm"},
9769   "name": "RMI_PERFCOUNTER2_LO"
9770  },
9771  {
9772   "chips": ["gfx10"],
9773   "map": {"at": 217876, "to": "mm"},
9774   "name": "RMI_PERFCOUNTER2_HI"
9775  },
9776  {
9777   "chips": ["gfx10"],
9778   "map": {"at": 217880, "to": "mm"},
9779   "name": "RMI_PERFCOUNTER3_LO"
9780  },
9781  {
9782   "chips": ["gfx10"],
9783   "map": {"at": 217884, "to": "mm"},
9784   "name": "RMI_PERFCOUNTER3_HI"
9785  },
9786  {
9787   "chips": ["gfx10"],
9788   "map": {"at": 217984, "to": "mm"},
9789   "name": "GC_ATC_L2_PERFCOUNTER_LO"
9790  },
9791  {
9792   "chips": ["gfx10"],
9793   "map": {"at": 217988, "to": "mm"},
9794   "name": "GC_ATC_L2_PERFCOUNTER_HI",
9795   "type_ref": "GC_ATC_L2_PERFCOUNTER_HI"
9796  },
9797  {
9798   "chips": ["gfx10"],
9799   "map": {"at": 218016, "to": "mm"},
9800   "name": "GCMC_VM_L2_PERFCOUNTER_LO"
9801  },
9802  {
9803   "chips": ["gfx10"],
9804   "map": {"at": 218020, "to": "mm"},
9805   "name": "GCMC_VM_L2_PERFCOUNTER_HI",
9806   "type_ref": "GC_ATC_L2_PERFCOUNTER_HI"
9807  },
9808  {
9809   "chips": ["gfx10"],
9810   "map": {"at": 218080, "to": "mm"},
9811   "name": "GCVML2_PERFCOUNTER2_0_LO"
9812  },
9813  {
9814   "chips": ["gfx10"],
9815   "map": {"at": 218084, "to": "mm"},
9816   "name": "GCVML2_PERFCOUNTER2_1_LO"
9817  },
9818  {
9819   "chips": ["gfx10"],
9820   "map": {"at": 218088, "to": "mm"},
9821   "name": "GCVML2_PERFCOUNTER2_0_HI"
9822  },
9823  {
9824   "chips": ["gfx10"],
9825   "map": {"at": 218092, "to": "mm"},
9826   "name": "GCVML2_PERFCOUNTER2_1_HI"
9827  },
9828  {
9829   "chips": ["gfx10"],
9830   "map": {"at": 218096, "to": "mm"},
9831   "name": "GC_ATC_L2_PERFCOUNTER2_LO"
9832  },
9833  {
9834   "chips": ["gfx10"],
9835   "map": {"at": 218100, "to": "mm"},
9836   "name": "GC_ATC_L2_PERFCOUNTER2_HI"
9837  },
9838  {
9839   "chips": ["gfx10"],
9840   "map": {"at": 218224, "to": "mm"},
9841   "name": "UTCL1_PERFCOUNTER0_LO"
9842  },
9843  {
9844   "chips": ["gfx10"],
9845   "map": {"at": 218228, "to": "mm"},
9846   "name": "UTCL1_PERFCOUNTER0_HI"
9847  },
9848  {
9849   "chips": ["gfx10"],
9850   "map": {"at": 218232, "to": "mm"},
9851   "name": "UTCL1_PERFCOUNTER1_LO"
9852  },
9853  {
9854   "chips": ["gfx10"],
9855   "map": {"at": 218236, "to": "mm"},
9856   "name": "UTCL1_PERFCOUNTER1_HI"
9857  },
9858  {
9859   "chips": ["gfx10"],
9860   "map": {"at": 218240, "to": "mm"},
9861   "name": "GCR_PERFCOUNTER0_LO"
9862  },
9863  {
9864   "chips": ["gfx10"],
9865   "map": {"at": 218244, "to": "mm"},
9866   "name": "GCR_PERFCOUNTER0_HI"
9867  },
9868  {
9869   "chips": ["gfx10"],
9870   "map": {"at": 218248, "to": "mm"},
9871   "name": "GCR_PERFCOUNTER1_LO"
9872  },
9873  {
9874   "chips": ["gfx10"],
9875   "map": {"at": 218252, "to": "mm"},
9876   "name": "GCR_PERFCOUNTER1_HI"
9877  },
9878  {
9879   "chips": ["gfx10"],
9880   "map": {"at": 218624, "to": "mm"},
9881   "name": "PA_PH_PERFCOUNTER0_LO"
9882  },
9883  {
9884   "chips": ["gfx10"],
9885   "map": {"at": 218628, "to": "mm"},
9886   "name": "PA_PH_PERFCOUNTER0_HI"
9887  },
9888  {
9889   "chips": ["gfx10"],
9890   "map": {"at": 218632, "to": "mm"},
9891   "name": "PA_PH_PERFCOUNTER1_LO"
9892  },
9893  {
9894   "chips": ["gfx10"],
9895   "map": {"at": 218636, "to": "mm"},
9896   "name": "PA_PH_PERFCOUNTER1_HI"
9897  },
9898  {
9899   "chips": ["gfx10"],
9900   "map": {"at": 218640, "to": "mm"},
9901   "name": "PA_PH_PERFCOUNTER2_LO"
9902  },
9903  {
9904   "chips": ["gfx10"],
9905   "map": {"at": 218644, "to": "mm"},
9906   "name": "PA_PH_PERFCOUNTER2_HI"
9907  },
9908  {
9909   "chips": ["gfx10"],
9910   "map": {"at": 218648, "to": "mm"},
9911   "name": "PA_PH_PERFCOUNTER3_LO"
9912  },
9913  {
9914   "chips": ["gfx10"],
9915   "map": {"at": 218652, "to": "mm"},
9916   "name": "PA_PH_PERFCOUNTER3_HI"
9917  },
9918  {
9919   "chips": ["gfx10"],
9920   "map": {"at": 218656, "to": "mm"},
9921   "name": "PA_PH_PERFCOUNTER4_LO"
9922  },
9923  {
9924   "chips": ["gfx10"],
9925   "map": {"at": 218660, "to": "mm"},
9926   "name": "PA_PH_PERFCOUNTER4_HI"
9927  },
9928  {
9929   "chips": ["gfx10"],
9930   "map": {"at": 218664, "to": "mm"},
9931   "name": "PA_PH_PERFCOUNTER5_LO"
9932  },
9933  {
9934   "chips": ["gfx10"],
9935   "map": {"at": 218668, "to": "mm"},
9936   "name": "PA_PH_PERFCOUNTER5_HI"
9937  },
9938  {
9939   "chips": ["gfx10"],
9940   "map": {"at": 218672, "to": "mm"},
9941   "name": "PA_PH_PERFCOUNTER6_LO"
9942  },
9943  {
9944   "chips": ["gfx10"],
9945   "map": {"at": 218676, "to": "mm"},
9946   "name": "PA_PH_PERFCOUNTER6_HI"
9947  },
9948  {
9949   "chips": ["gfx10"],
9950   "map": {"at": 218680, "to": "mm"},
9951   "name": "PA_PH_PERFCOUNTER7_LO"
9952  },
9953  {
9954   "chips": ["gfx10"],
9955   "map": {"at": 218684, "to": "mm"},
9956   "name": "PA_PH_PERFCOUNTER7_HI"
9957  },
9958  {
9959   "chips": ["gfx10"],
9960   "map": {"at": 218880, "to": "mm"},
9961   "name": "GL1A_PERFCOUNTER0_LO"
9962  },
9963  {
9964   "chips": ["gfx10"],
9965   "map": {"at": 218884, "to": "mm"},
9966   "name": "GL1A_PERFCOUNTER0_HI"
9967  },
9968  {
9969   "chips": ["gfx10"],
9970   "map": {"at": 218888, "to": "mm"},
9971   "name": "GL1A_PERFCOUNTER1_LO"
9972  },
9973  {
9974   "chips": ["gfx10"],
9975   "map": {"at": 218892, "to": "mm"},
9976   "name": "GL1A_PERFCOUNTER1_HI"
9977  },
9978  {
9979   "chips": ["gfx10"],
9980   "map": {"at": 218896, "to": "mm"},
9981   "name": "GL1A_PERFCOUNTER2_LO"
9982  },
9983  {
9984   "chips": ["gfx10"],
9985   "map": {"at": 218900, "to": "mm"},
9986   "name": "GL1A_PERFCOUNTER2_HI"
9987  },
9988  {
9989   "chips": ["gfx10"],
9990   "map": {"at": 218904, "to": "mm"},
9991   "name": "GL1A_PERFCOUNTER3_LO"
9992  },
9993  {
9994   "chips": ["gfx10"],
9995   "map": {"at": 218908, "to": "mm"},
9996   "name": "GL1A_PERFCOUNTER3_HI"
9997  },
9998  {
9999   "chips": ["gfx10"],
10000   "map": {"at": 219136, "to": "mm"},
10001   "name": "CHA_PERFCOUNTER0_LO"
10002  },
10003  {
10004   "chips": ["gfx10"],
10005   "map": {"at": 219140, "to": "mm"},
10006   "name": "CHA_PERFCOUNTER0_HI"
10007  },
10008  {
10009   "chips": ["gfx10"],
10010   "map": {"at": 219144, "to": "mm"},
10011   "name": "CHA_PERFCOUNTER1_LO"
10012  },
10013  {
10014   "chips": ["gfx10"],
10015   "map": {"at": 219148, "to": "mm"},
10016   "name": "CHA_PERFCOUNTER1_HI"
10017  },
10018  {
10019   "chips": ["gfx10"],
10020   "map": {"at": 219152, "to": "mm"},
10021   "name": "CHA_PERFCOUNTER2_LO"
10022  },
10023  {
10024   "chips": ["gfx10"],
10025   "map": {"at": 219156, "to": "mm"},
10026   "name": "CHA_PERFCOUNTER2_HI"
10027  },
10028  {
10029   "chips": ["gfx10"],
10030   "map": {"at": 219160, "to": "mm"},
10031   "name": "CHA_PERFCOUNTER3_LO"
10032  },
10033  {
10034   "chips": ["gfx10"],
10035   "map": {"at": 219164, "to": "mm"},
10036   "name": "CHA_PERFCOUNTER3_HI"
10037  },
10038  {
10039   "chips": ["gfx10"],
10040   "map": {"at": 219392, "to": "mm"},
10041   "name": "GUS_PERFCOUNTER2_LO"
10042  },
10043  {
10044   "chips": ["gfx10"],
10045   "map": {"at": 219396, "to": "mm"},
10046   "name": "GUS_PERFCOUNTER2_HI"
10047  },
10048  {
10049   "chips": ["gfx10"],
10050   "map": {"at": 221184, "to": "mm"},
10051   "name": "CPG_PERFCOUNTER1_SELECT",
10052   "type_ref": "CPG_PERFCOUNTER1_SELECT"
10053  },
10054  {
10055   "chips": ["gfx10"],
10056   "map": {"at": 221188, "to": "mm"},
10057   "name": "CPG_PERFCOUNTER0_SELECT1",
10058   "type_ref": "CPG_PERFCOUNTER0_SELECT1"
10059  },
10060  {
10061   "chips": ["gfx10"],
10062   "map": {"at": 221192, "to": "mm"},
10063   "name": "CPG_PERFCOUNTER0_SELECT",
10064   "type_ref": "CPG_PERFCOUNTER1_SELECT"
10065  },
10066  {
10067   "chips": ["gfx10"],
10068   "map": {"at": 221196, "to": "mm"},
10069   "name": "CPC_PERFCOUNTER1_SELECT",
10070   "type_ref": "CPG_PERFCOUNTER1_SELECT"
10071  },
10072  {
10073   "chips": ["gfx10"],
10074   "map": {"at": 221200, "to": "mm"},
10075   "name": "CPC_PERFCOUNTER0_SELECT1",
10076   "type_ref": "CPG_PERFCOUNTER0_SELECT1"
10077  },
10078  {
10079   "chips": ["gfx10"],
10080   "map": {"at": 221204, "to": "mm"},
10081   "name": "CPF_PERFCOUNTER1_SELECT",
10082   "type_ref": "CPG_PERFCOUNTER1_SELECT"
10083  },
10084  {
10085   "chips": ["gfx10"],
10086   "map": {"at": 221208, "to": "mm"},
10087   "name": "CPF_PERFCOUNTER0_SELECT1",
10088   "type_ref": "CPG_PERFCOUNTER0_SELECT1"
10089  },
10090  {
10091   "chips": ["gfx10"],
10092   "map": {"at": 221212, "to": "mm"},
10093   "name": "CPF_PERFCOUNTER0_SELECT",
10094   "type_ref": "CPG_PERFCOUNTER1_SELECT"
10095  },
10096  {
10097   "chips": ["gfx10"],
10098   "map": {"at": 221216, "to": "mm"},
10099   "name": "CP_PERFMON_CNTL",
10100   "type_ref": "CP_PERFMON_CNTL"
10101  },
10102  {
10103   "chips": ["gfx10"],
10104   "map": {"at": 221220, "to": "mm"},
10105   "name": "CPC_PERFCOUNTER0_SELECT",
10106   "type_ref": "CPG_PERFCOUNTER1_SELECT"
10107  },
10108  {
10109   "chips": ["gfx10"],
10110   "map": {"at": 221224, "to": "mm"},
10111   "name": "CPF_TC_PERF_COUNTER_WINDOW_SELECT",
10112   "type_ref": "CPF_TC_PERF_COUNTER_WINDOW_SELECT"
10113  },
10114  {
10115   "chips": ["gfx10"],
10116   "map": {"at": 221228, "to": "mm"},
10117   "name": "CPG_TC_PERF_COUNTER_WINDOW_SELECT",
10118   "type_ref": "CPG_TC_PERF_COUNTER_WINDOW_SELECT"
10119  },
10120  {
10121   "chips": ["gfx10"],
10122   "map": {"at": 221232, "to": "mm"},
10123   "name": "CPF_LATENCY_STATS_SELECT",
10124   "type_ref": "CPF_LATENCY_STATS_SELECT"
10125  },
10126  {
10127   "chips": ["gfx10"],
10128   "map": {"at": 221236, "to": "mm"},
10129   "name": "CPG_LATENCY_STATS_SELECT",
10130   "type_ref": "CPG_LATENCY_STATS_SELECT"
10131  },
10132  {
10133   "chips": ["gfx10"],
10134   "map": {"at": 221240, "to": "mm"},
10135   "name": "CPC_LATENCY_STATS_SELECT",
10136   "type_ref": "CPF_LATENCY_STATS_SELECT"
10137  },
10138  {
10139   "chips": ["gfx10"],
10140   "map": {"at": 221248, "to": "mm"},
10141   "name": "CP_DRAW_OBJECT"
10142  },
10143  {
10144   "chips": ["gfx10"],
10145   "map": {"at": 221252, "to": "mm"},
10146   "name": "CP_DRAW_OBJECT_COUNTER",
10147   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
10148  },
10149  {
10150   "chips": ["gfx10"],
10151   "map": {"at": 221256, "to": "mm"},
10152   "name": "CP_DRAW_WINDOW_MASK_HI"
10153  },
10154  {
10155   "chips": ["gfx10"],
10156   "map": {"at": 221260, "to": "mm"},
10157   "name": "CP_DRAW_WINDOW_HI"
10158  },
10159  {
10160   "chips": ["gfx10"],
10161   "map": {"at": 221264, "to": "mm"},
10162   "name": "CP_DRAW_WINDOW_LO",
10163   "type_ref": "CP_DRAW_WINDOW_LO"
10164  },
10165  {
10166   "chips": ["gfx10"],
10167   "map": {"at": 221268, "to": "mm"},
10168   "name": "CP_DRAW_WINDOW_CNTL",
10169   "type_ref": "CP_DRAW_WINDOW_CNTL"
10170  },
10171  {
10172   "chips": ["gfx10"],
10173   "map": {"at": 221440, "to": "mm"},
10174   "name": "GRBM_PERFCOUNTER0_SELECT",
10175   "type_ref": "GRBM_PERFCOUNTER0_SELECT"
10176  },
10177  {
10178   "chips": ["gfx10"],
10179   "map": {"at": 221444, "to": "mm"},
10180   "name": "GRBM_PERFCOUNTER1_SELECT",
10181   "type_ref": "GRBM_PERFCOUNTER0_SELECT"
10182  },
10183  {
10184   "chips": ["gfx10"],
10185   "map": {"at": 221448, "to": "mm"},
10186   "name": "GRBM_SE0_PERFCOUNTER_SELECT",
10187   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
10188  },
10189  {
10190   "chips": ["gfx10"],
10191   "map": {"at": 221452, "to": "mm"},
10192   "name": "GRBM_SE1_PERFCOUNTER_SELECT",
10193   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
10194  },
10195  {
10196   "chips": ["gfx10"],
10197   "map": {"at": 221456, "to": "mm"},
10198   "name": "GRBM_SE2_PERFCOUNTER_SELECT",
10199   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
10200  },
10201  {
10202   "chips": ["gfx10"],
10203   "map": {"at": 221460, "to": "mm"},
10204   "name": "GRBM_SE3_PERFCOUNTER_SELECT",
10205   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
10206  },
10207  {
10208   "chips": ["gfx10"],
10209   "map": {"at": 221492, "to": "mm"},
10210   "name": "GRBM_PERFCOUNTER0_SELECT_HI",
10211   "type_ref": "GRBM_PERFCOUNTER0_SELECT_HI"
10212  },
10213  {
10214   "chips": ["gfx10"],
10215   "map": {"at": 221496, "to": "mm"},
10216   "name": "GRBM_PERFCOUNTER1_SELECT_HI",
10217   "type_ref": "GRBM_PERFCOUNTER0_SELECT_HI"
10218  },
10219  {
10220   "chips": ["gfx10"],
10221   "map": {"at": 221696, "to": "mm"},
10222   "name": "GE_PERFCOUNTER0_SELECT",
10223   "type_ref": "GE_PERFCOUNTER0_SELECT"
10224  },
10225  {
10226   "chips": ["gfx10"],
10227   "map": {"at": 221700, "to": "mm"},
10228   "name": "GE_PERFCOUNTER0_SELECT1",
10229   "type_ref": "GE_PERFCOUNTER0_SELECT1"
10230  },
10231  {
10232   "chips": ["gfx10"],
10233   "map": {"at": 221704, "to": "mm"},
10234   "name": "GE_PERFCOUNTER1_SELECT",
10235   "type_ref": "GE_PERFCOUNTER0_SELECT"
10236  },
10237  {
10238   "chips": ["gfx10"],
10239   "map": {"at": 221708, "to": "mm"},
10240   "name": "GE_PERFCOUNTER1_SELECT1",
10241   "type_ref": "GE_PERFCOUNTER0_SELECT1"
10242  },
10243  {
10244   "chips": ["gfx10"],
10245   "map": {"at": 221712, "to": "mm"},
10246   "name": "GE_PERFCOUNTER2_SELECT",
10247   "type_ref": "GE_PERFCOUNTER0_SELECT"
10248  },
10249  {
10250   "chips": ["gfx10"],
10251   "map": {"at": 221716, "to": "mm"},
10252   "name": "GE_PERFCOUNTER2_SELECT1",
10253   "type_ref": "GE_PERFCOUNTER0_SELECT1"
10254  },
10255  {
10256   "chips": ["gfx10"],
10257   "map": {"at": 221720, "to": "mm"},
10258   "name": "GE_PERFCOUNTER3_SELECT",
10259   "type_ref": "GE_PERFCOUNTER0_SELECT"
10260  },
10261  {
10262   "chips": ["gfx10"],
10263   "map": {"at": 221724, "to": "mm"},
10264   "name": "GE_PERFCOUNTER3_SELECT1",
10265   "type_ref": "GE_PERFCOUNTER0_SELECT1"
10266  },
10267  {
10268   "chips": ["gfx10"],
10269   "map": {"at": 221728, "to": "mm"},
10270   "name": "GE_PERFCOUNTER4_SELECT",
10271   "type_ref": "GE_PERFCOUNTER4_SELECT"
10272  },
10273  {
10274   "chips": ["gfx10"],
10275   "map": {"at": 221736, "to": "mm"},
10276   "name": "GE_PERFCOUNTER5_SELECT",
10277   "type_ref": "GE_PERFCOUNTER4_SELECT"
10278  },
10279  {
10280   "chips": ["gfx10"],
10281   "map": {"at": 221744, "to": "mm"},
10282   "name": "GE_PERFCOUNTER6_SELECT",
10283   "type_ref": "GE_PERFCOUNTER4_SELECT"
10284  },
10285  {
10286   "chips": ["gfx10"],
10287   "map": {"at": 221752, "to": "mm"},
10288   "name": "GE_PERFCOUNTER7_SELECT",
10289   "type_ref": "GE_PERFCOUNTER4_SELECT"
10290  },
10291  {
10292   "chips": ["gfx10"],
10293   "map": {"at": 221760, "to": "mm"},
10294   "name": "GE_PERFCOUNTER8_SELECT",
10295   "type_ref": "GE_PERFCOUNTER4_SELECT"
10296  },
10297  {
10298   "chips": ["gfx10"],
10299   "map": {"at": 221768, "to": "mm"},
10300   "name": "GE_PERFCOUNTER9_SELECT",
10301   "type_ref": "GE_PERFCOUNTER4_SELECT"
10302  },
10303  {
10304   "chips": ["gfx10"],
10305   "map": {"at": 221776, "to": "mm"},
10306   "name": "GE_PERFCOUNTER10_SELECT",
10307   "type_ref": "GE_PERFCOUNTER4_SELECT"
10308  },
10309  {
10310   "chips": ["gfx10"],
10311   "map": {"at": 221784, "to": "mm"},
10312   "name": "GE_PERFCOUNTER11_SELECT",
10313   "type_ref": "GE_PERFCOUNTER4_SELECT"
10314  },
10315  {
10316   "chips": ["gfx10"],
10317   "map": {"at": 222208, "to": "mm"},
10318   "name": "PA_SU_PERFCOUNTER0_SELECT",
10319   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10320  },
10321  {
10322   "chips": ["gfx10"],
10323   "map": {"at": 222212, "to": "mm"},
10324   "name": "PA_SU_PERFCOUNTER0_SELECT1",
10325   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10326  },
10327  {
10328   "chips": ["gfx10"],
10329   "map": {"at": 222216, "to": "mm"},
10330   "name": "PA_SU_PERFCOUNTER1_SELECT",
10331   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10332  },
10333  {
10334   "chips": ["gfx10"],
10335   "map": {"at": 222220, "to": "mm"},
10336   "name": "PA_SU_PERFCOUNTER1_SELECT1",
10337   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10338  },
10339  {
10340   "chips": ["gfx10"],
10341   "map": {"at": 222224, "to": "mm"},
10342   "name": "PA_SU_PERFCOUNTER2_SELECT",
10343   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10344  },
10345  {
10346   "chips": ["gfx10"],
10347   "map": {"at": 222228, "to": "mm"},
10348   "name": "PA_SU_PERFCOUNTER2_SELECT1",
10349   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10350  },
10351  {
10352   "chips": ["gfx10"],
10353   "map": {"at": 222232, "to": "mm"},
10354   "name": "PA_SU_PERFCOUNTER3_SELECT",
10355   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10356  },
10357  {
10358   "chips": ["gfx10"],
10359   "map": {"at": 222236, "to": "mm"},
10360   "name": "PA_SU_PERFCOUNTER3_SELECT1",
10361   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10362  },
10363  {
10364   "chips": ["gfx10"],
10365   "map": {"at": 222464, "to": "mm"},
10366   "name": "PA_SC_PERFCOUNTER0_SELECT",
10367   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10368  },
10369  {
10370   "chips": ["gfx10"],
10371   "map": {"at": 222468, "to": "mm"},
10372   "name": "PA_SC_PERFCOUNTER0_SELECT1",
10373   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10374  },
10375  {
10376   "chips": ["gfx10"],
10377   "map": {"at": 222472, "to": "mm"},
10378   "name": "PA_SC_PERFCOUNTER1_SELECT",
10379   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
10380  },
10381  {
10382   "chips": ["gfx10"],
10383   "map": {"at": 222476, "to": "mm"},
10384   "name": "PA_SC_PERFCOUNTER2_SELECT",
10385   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
10386  },
10387  {
10388   "chips": ["gfx10"],
10389   "map": {"at": 222480, "to": "mm"},
10390   "name": "PA_SC_PERFCOUNTER3_SELECT",
10391   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
10392  },
10393  {
10394   "chips": ["gfx10"],
10395   "map": {"at": 222484, "to": "mm"},
10396   "name": "PA_SC_PERFCOUNTER4_SELECT",
10397   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
10398  },
10399  {
10400   "chips": ["gfx10"],
10401   "map": {"at": 222488, "to": "mm"},
10402   "name": "PA_SC_PERFCOUNTER5_SELECT",
10403   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
10404  },
10405  {
10406   "chips": ["gfx10"],
10407   "map": {"at": 222492, "to": "mm"},
10408   "name": "PA_SC_PERFCOUNTER6_SELECT",
10409   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
10410  },
10411  {
10412   "chips": ["gfx10"],
10413   "map": {"at": 222496, "to": "mm"},
10414   "name": "PA_SC_PERFCOUNTER7_SELECT",
10415   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
10416  },
10417  {
10418   "chips": ["gfx10"],
10419   "map": {"at": 222720, "to": "mm"},
10420   "name": "SPI_PERFCOUNTER0_SELECT",
10421   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10422  },
10423  {
10424   "chips": ["gfx10"],
10425   "map": {"at": 222724, "to": "mm"},
10426   "name": "SPI_PERFCOUNTER1_SELECT",
10427   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10428  },
10429  {
10430   "chips": ["gfx10"],
10431   "map": {"at": 222728, "to": "mm"},
10432   "name": "SPI_PERFCOUNTER2_SELECT",
10433   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10434  },
10435  {
10436   "chips": ["gfx10"],
10437   "map": {"at": 222732, "to": "mm"},
10438   "name": "SPI_PERFCOUNTER3_SELECT",
10439   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10440  },
10441  {
10442   "chips": ["gfx10"],
10443   "map": {"at": 222736, "to": "mm"},
10444   "name": "SPI_PERFCOUNTER0_SELECT1",
10445   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10446  },
10447  {
10448   "chips": ["gfx10"],
10449   "map": {"at": 222740, "to": "mm"},
10450   "name": "SPI_PERFCOUNTER1_SELECT1",
10451   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10452  },
10453  {
10454   "chips": ["gfx10"],
10455   "map": {"at": 222744, "to": "mm"},
10456   "name": "SPI_PERFCOUNTER2_SELECT1",
10457   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10458  },
10459  {
10460   "chips": ["gfx10"],
10461   "map": {"at": 222748, "to": "mm"},
10462   "name": "SPI_PERFCOUNTER3_SELECT1",
10463   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10464  },
10465  {
10466   "chips": ["gfx10"],
10467   "map": {"at": 222752, "to": "mm"},
10468   "name": "SPI_PERFCOUNTER4_SELECT",
10469   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
10470  },
10471  {
10472   "chips": ["gfx10"],
10473   "map": {"at": 222756, "to": "mm"},
10474   "name": "SPI_PERFCOUNTER5_SELECT",
10475   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
10476  },
10477  {
10478   "chips": ["gfx10"],
10479   "map": {"at": 222760, "to": "mm"},
10480   "name": "SPI_PERFCOUNTER_BINS",
10481   "type_ref": "SPI_PERFCOUNTER_BINS"
10482  },
10483  {
10484   "chips": ["gfx10"],
10485   "map": {"at": 222976, "to": "mm"},
10486   "name": "SQ_PERFCOUNTER0_SELECT",
10487   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10488  },
10489  {
10490   "chips": ["gfx10"],
10491   "map": {"at": 222980, "to": "mm"},
10492   "name": "SQ_PERFCOUNTER1_SELECT",
10493   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10494  },
10495  {
10496   "chips": ["gfx10"],
10497   "map": {"at": 222984, "to": "mm"},
10498   "name": "SQ_PERFCOUNTER2_SELECT",
10499   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10500  },
10501  {
10502   "chips": ["gfx10"],
10503   "map": {"at": 222988, "to": "mm"},
10504   "name": "SQ_PERFCOUNTER3_SELECT",
10505   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10506  },
10507  {
10508   "chips": ["gfx10"],
10509   "map": {"at": 222992, "to": "mm"},
10510   "name": "SQ_PERFCOUNTER4_SELECT",
10511   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10512  },
10513  {
10514   "chips": ["gfx10"],
10515   "map": {"at": 222996, "to": "mm"},
10516   "name": "SQ_PERFCOUNTER5_SELECT",
10517   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10518  },
10519  {
10520   "chips": ["gfx10"],
10521   "map": {"at": 223000, "to": "mm"},
10522   "name": "SQ_PERFCOUNTER6_SELECT",
10523   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10524  },
10525  {
10526   "chips": ["gfx10"],
10527   "map": {"at": 223004, "to": "mm"},
10528   "name": "SQ_PERFCOUNTER7_SELECT",
10529   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10530  },
10531  {
10532   "chips": ["gfx10"],
10533   "map": {"at": 223008, "to": "mm"},
10534   "name": "SQ_PERFCOUNTER8_SELECT",
10535   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10536  },
10537  {
10538   "chips": ["gfx10"],
10539   "map": {"at": 223012, "to": "mm"},
10540   "name": "SQ_PERFCOUNTER9_SELECT",
10541   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10542  },
10543  {
10544   "chips": ["gfx10"],
10545   "map": {"at": 223016, "to": "mm"},
10546   "name": "SQ_PERFCOUNTER10_SELECT",
10547   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10548  },
10549  {
10550   "chips": ["gfx10"],
10551   "map": {"at": 223020, "to": "mm"},
10552   "name": "SQ_PERFCOUNTER11_SELECT",
10553   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10554  },
10555  {
10556   "chips": ["gfx10"],
10557   "map": {"at": 223024, "to": "mm"},
10558   "name": "SQ_PERFCOUNTER12_SELECT",
10559   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10560  },
10561  {
10562   "chips": ["gfx10"],
10563   "map": {"at": 223028, "to": "mm"},
10564   "name": "SQ_PERFCOUNTER13_SELECT",
10565   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10566  },
10567  {
10568   "chips": ["gfx10"],
10569   "map": {"at": 223032, "to": "mm"},
10570   "name": "SQ_PERFCOUNTER14_SELECT",
10571   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10572  },
10573  {
10574   "chips": ["gfx10"],
10575   "map": {"at": 223036, "to": "mm"},
10576   "name": "SQ_PERFCOUNTER15_SELECT",
10577   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10578  },
10579  {
10580   "chips": ["gfx10"],
10581   "map": {"at": 223104, "to": "mm"},
10582   "name": "SQ_PERFCOUNTER_CTRL",
10583   "type_ref": "SQ_PERFCOUNTER_CTRL"
10584  },
10585  {
10586   "chips": ["gfx10"],
10587   "map": {"at": 223112, "to": "mm"},
10588   "name": "SQ_PERFCOUNTER_CTRL2",
10589   "type_ref": "SQ_PERFCOUNTER_CTRL2"
10590  },
10591  {
10592   "chips": ["gfx10"],
10593   "map": {"at": 223232, "to": "mm"},
10594   "name": "GCEA_PERFCOUNTER2_SELECT",
10595   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10596  },
10597  {
10598   "chips": ["gfx10"],
10599   "map": {"at": 223236, "to": "mm"},
10600   "name": "GCEA_PERFCOUNTER2_SELECT1",
10601   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10602  },
10603  {
10604   "chips": ["gfx10"],
10605   "map": {"at": 223240, "to": "mm"},
10606   "name": "GCEA_PERFCOUNTER2_MODE",
10607   "type_ref": "GCEA_PERFCOUNTER2_MODE"
10608  },
10609  {
10610   "chips": ["gfx10"],
10611   "map": {"at": 223488, "to": "mm"},
10612   "name": "SX_PERFCOUNTER0_SELECT",
10613   "type_ref": "SX_PERFCOUNTER0_SELECT"
10614  },
10615  {
10616   "chips": ["gfx10"],
10617   "map": {"at": 223492, "to": "mm"},
10618   "name": "SX_PERFCOUNTER1_SELECT",
10619   "type_ref": "SX_PERFCOUNTER0_SELECT"
10620  },
10621  {
10622   "chips": ["gfx10"],
10623   "map": {"at": 223496, "to": "mm"},
10624   "name": "SX_PERFCOUNTER2_SELECT",
10625   "type_ref": "SX_PERFCOUNTER0_SELECT"
10626  },
10627  {
10628   "chips": ["gfx10"],
10629   "map": {"at": 223500, "to": "mm"},
10630   "name": "SX_PERFCOUNTER3_SELECT",
10631   "type_ref": "SX_PERFCOUNTER0_SELECT"
10632  },
10633  {
10634   "chips": ["gfx10"],
10635   "map": {"at": 223504, "to": "mm"},
10636   "name": "SX_PERFCOUNTER0_SELECT1",
10637   "type_ref": "SX_PERFCOUNTER0_SELECT1"
10638  },
10639  {
10640   "chips": ["gfx10"],
10641   "map": {"at": 223508, "to": "mm"},
10642   "name": "SX_PERFCOUNTER1_SELECT1",
10643   "type_ref": "SX_PERFCOUNTER0_SELECT1"
10644  },
10645  {
10646   "chips": ["gfx10"],
10647   "map": {"at": 223744, "to": "mm"},
10648   "name": "GDS_PERFCOUNTER0_SELECT",
10649   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10650  },
10651  {
10652   "chips": ["gfx10"],
10653   "map": {"at": 223748, "to": "mm"},
10654   "name": "GDS_PERFCOUNTER1_SELECT",
10655   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10656  },
10657  {
10658   "chips": ["gfx10"],
10659   "map": {"at": 223752, "to": "mm"},
10660   "name": "GDS_PERFCOUNTER2_SELECT",
10661   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10662  },
10663  {
10664   "chips": ["gfx10"],
10665   "map": {"at": 223756, "to": "mm"},
10666   "name": "GDS_PERFCOUNTER3_SELECT",
10667   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10668  },
10669  {
10670   "chips": ["gfx10"],
10671   "map": {"at": 223760, "to": "mm"},
10672   "name": "GDS_PERFCOUNTER0_SELECT1",
10673   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10674  },
10675  {
10676   "chips": ["gfx10"],
10677   "map": {"at": 224000, "to": "mm"},
10678   "name": "TA_PERFCOUNTER0_SELECT",
10679   "type_ref": "TA_PERFCOUNTER0_SELECT"
10680  },
10681  {
10682   "chips": ["gfx10"],
10683   "map": {"at": 224004, "to": "mm"},
10684   "name": "TA_PERFCOUNTER0_SELECT1",
10685   "type_ref": "TA_PERFCOUNTER0_SELECT1"
10686  },
10687  {
10688   "chips": ["gfx10"],
10689   "map": {"at": 224008, "to": "mm"},
10690   "name": "TA_PERFCOUNTER1_SELECT",
10691   "type_ref": "TA_PERFCOUNTER1_SELECT"
10692  },
10693  {
10694   "chips": ["gfx10"],
10695   "map": {"at": 224256, "to": "mm"},
10696   "name": "TD_PERFCOUNTER0_SELECT",
10697   "type_ref": "TA_PERFCOUNTER0_SELECT"
10698  },
10699  {
10700   "chips": ["gfx10"],
10701   "map": {"at": 224260, "to": "mm"},
10702   "name": "TD_PERFCOUNTER0_SELECT1",
10703   "type_ref": "TA_PERFCOUNTER0_SELECT1"
10704  },
10705  {
10706   "chips": ["gfx10"],
10707   "map": {"at": 224264, "to": "mm"},
10708   "name": "TD_PERFCOUNTER1_SELECT",
10709   "type_ref": "TA_PERFCOUNTER1_SELECT"
10710  },
10711  {
10712   "chips": ["gfx10"],
10713   "map": {"at": 224512, "to": "mm"},
10714   "name": "TCP_PERFCOUNTER0_SELECT",
10715   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10716  },
10717  {
10718   "chips": ["gfx10"],
10719   "map": {"at": 224516, "to": "mm"},
10720   "name": "TCP_PERFCOUNTER0_SELECT1",
10721   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10722  },
10723  {
10724   "chips": ["gfx10"],
10725   "map": {"at": 224520, "to": "mm"},
10726   "name": "TCP_PERFCOUNTER1_SELECT",
10727   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10728  },
10729  {
10730   "chips": ["gfx10"],
10731   "map": {"at": 224524, "to": "mm"},
10732   "name": "TCP_PERFCOUNTER1_SELECT1",
10733   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10734  },
10735  {
10736   "chips": ["gfx10"],
10737   "map": {"at": 224528, "to": "mm"},
10738   "name": "TCP_PERFCOUNTER2_SELECT",
10739   "type_ref": "TCP_PERFCOUNTER2_SELECT"
10740  },
10741  {
10742   "chips": ["gfx10"],
10743   "map": {"at": 224532, "to": "mm"},
10744   "name": "TCP_PERFCOUNTER3_SELECT",
10745   "type_ref": "TCP_PERFCOUNTER2_SELECT"
10746  },
10747  {
10748   "chips": ["gfx10"],
10749   "map": {"at": 224768, "to": "mm"},
10750   "name": "GL2C_PERFCOUNTER0_SELECT",
10751   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10752  },
10753  {
10754   "chips": ["gfx10"],
10755   "map": {"at": 224772, "to": "mm"},
10756   "name": "GL2C_PERFCOUNTER0_SELECT1",
10757   "type_ref": "GE_PERFCOUNTER0_SELECT1"
10758  },
10759  {
10760   "chips": ["gfx10"],
10761   "map": {"at": 224776, "to": "mm"},
10762   "name": "GL2C_PERFCOUNTER1_SELECT",
10763   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10764  },
10765  {
10766   "chips": ["gfx10"],
10767   "map": {"at": 224780, "to": "mm"},
10768   "name": "GL2C_PERFCOUNTER1_SELECT1",
10769   "type_ref": "GE_PERFCOUNTER0_SELECT1"
10770  },
10771  {
10772   "chips": ["gfx10"],
10773   "map": {"at": 224784, "to": "mm"},
10774   "name": "GL2C_PERFCOUNTER2_SELECT",
10775   "type_ref": "TCP_PERFCOUNTER2_SELECT"
10776  },
10777  {
10778   "chips": ["gfx10"],
10779   "map": {"at": 224788, "to": "mm"},
10780   "name": "GL2C_PERFCOUNTER3_SELECT",
10781   "type_ref": "TCP_PERFCOUNTER2_SELECT"
10782  },
10783  {
10784   "chips": ["gfx10"],
10785   "map": {"at": 224832, "to": "mm"},
10786   "name": "GL2A_PERFCOUNTER0_SELECT",
10787   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10788  },
10789  {
10790   "chips": ["gfx10"],
10791   "map": {"at": 224836, "to": "mm"},
10792   "name": "GL2A_PERFCOUNTER0_SELECT1",
10793   "type_ref": "GE_PERFCOUNTER0_SELECT1"
10794  },
10795  {
10796   "chips": ["gfx10"],
10797   "map": {"at": 224840, "to": "mm"},
10798   "name": "GL2A_PERFCOUNTER1_SELECT",
10799   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10800  },
10801  {
10802   "chips": ["gfx10"],
10803   "map": {"at": 224844, "to": "mm"},
10804   "name": "GL2A_PERFCOUNTER1_SELECT1",
10805   "type_ref": "GE_PERFCOUNTER0_SELECT1"
10806  },
10807  {
10808   "chips": ["gfx10"],
10809   "map": {"at": 224848, "to": "mm"},
10810   "name": "GL2A_PERFCOUNTER2_SELECT",
10811   "type_ref": "TCP_PERFCOUNTER2_SELECT"
10812  },
10813  {
10814   "chips": ["gfx10"],
10815   "map": {"at": 224852, "to": "mm"},
10816   "name": "GL2A_PERFCOUNTER3_SELECT",
10817   "type_ref": "TCP_PERFCOUNTER2_SELECT"
10818  },
10819  {
10820   "chips": ["gfx10"],
10821   "map": {"at": 224896, "to": "mm"},
10822   "name": "GL1C_PERFCOUNTER0_SELECT",
10823   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10824  },
10825  {
10826   "chips": ["gfx10"],
10827   "map": {"at": 224900, "to": "mm"},
10828   "name": "GL1C_PERFCOUNTER0_SELECT1",
10829   "type_ref": "GE_PERFCOUNTER0_SELECT1"
10830  },
10831  {
10832   "chips": ["gfx10"],
10833   "map": {"at": 224904, "to": "mm"},
10834   "name": "GL1C_PERFCOUNTER1_SELECT",
10835   "type_ref": "TCP_PERFCOUNTER2_SELECT"
10836  },
10837  {
10838   "chips": ["gfx10"],
10839   "map": {"at": 224908, "to": "mm"},
10840   "name": "GL1C_PERFCOUNTER2_SELECT",
10841   "type_ref": "TCP_PERFCOUNTER2_SELECT"
10842  },
10843  {
10844   "chips": ["gfx10"],
10845   "map": {"at": 224912, "to": "mm"},
10846   "name": "GL1C_PERFCOUNTER3_SELECT",
10847   "type_ref": "TCP_PERFCOUNTER2_SELECT"
10848  },
10849  {
10850   "chips": ["gfx10"],
10851   "map": {"at": 225024, "to": "mm"},
10852   "name": "CHC_PERFCOUNTER0_SELECT",
10853   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10854  },
10855  {
10856   "chips": ["gfx10"],
10857   "map": {"at": 225028, "to": "mm"},
10858   "name": "CHC_PERFCOUNTER0_SELECT1",
10859   "type_ref": "GE_PERFCOUNTER0_SELECT1"
10860  },
10861  {
10862   "chips": ["gfx10"],
10863   "map": {"at": 225032, "to": "mm"},
10864   "name": "CHC_PERFCOUNTER1_SELECT",
10865   "type_ref": "TCP_PERFCOUNTER2_SELECT"
10866  },
10867  {
10868   "chips": ["gfx10"],
10869   "map": {"at": 225036, "to": "mm"},
10870   "name": "CHC_PERFCOUNTER2_SELECT",
10871   "type_ref": "TCP_PERFCOUNTER2_SELECT"
10872  },
10873  {
10874   "chips": ["gfx10"],
10875   "map": {"at": 225040, "to": "mm"},
10876   "name": "CHC_PERFCOUNTER3_SELECT",
10877   "type_ref": "TCP_PERFCOUNTER2_SELECT"
10878  },
10879  {
10880   "chips": ["gfx10"],
10881   "map": {"at": 225048, "to": "mm"},
10882   "name": "CHCG_PERFCOUNTER0_SELECT",
10883   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10884  },
10885  {
10886   "chips": ["gfx10"],
10887   "map": {"at": 225052, "to": "mm"},
10888   "name": "CHCG_PERFCOUNTER0_SELECT1",
10889   "type_ref": "GE_PERFCOUNTER0_SELECT1"
10890  },
10891  {
10892   "chips": ["gfx10"],
10893   "map": {"at": 225056, "to": "mm"},
10894   "name": "CHCG_PERFCOUNTER1_SELECT",
10895   "type_ref": "TCP_PERFCOUNTER2_SELECT"
10896  },
10897  {
10898   "chips": ["gfx10"],
10899   "map": {"at": 225060, "to": "mm"},
10900   "name": "CHCG_PERFCOUNTER2_SELECT",
10901   "type_ref": "TCP_PERFCOUNTER2_SELECT"
10902  },
10903  {
10904   "chips": ["gfx10"],
10905   "map": {"at": 225064, "to": "mm"},
10906   "name": "CHCG_PERFCOUNTER3_SELECT",
10907   "type_ref": "TCP_PERFCOUNTER2_SELECT"
10908  },
10909  {
10910   "chips": ["gfx10"],
10911   "map": {"at": 225280, "to": "mm"},
10912   "name": "CB_PERFCOUNTER_FILTER",
10913   "type_ref": "CB_PERFCOUNTER_FILTER"
10914  },
10915  {
10916   "chips": ["gfx10"],
10917   "map": {"at": 225284, "to": "mm"},
10918   "name": "CB_PERFCOUNTER0_SELECT",
10919   "type_ref": "CB_PERFCOUNTER0_SELECT"
10920  },
10921  {
10922   "chips": ["gfx10"],
10923   "map": {"at": 225288, "to": "mm"},
10924   "name": "CB_PERFCOUNTER0_SELECT1",
10925   "type_ref": "CB_PERFCOUNTER0_SELECT1"
10926  },
10927  {
10928   "chips": ["gfx10"],
10929   "map": {"at": 225292, "to": "mm"},
10930   "name": "CB_PERFCOUNTER1_SELECT",
10931   "type_ref": "CB_PERFCOUNTER1_SELECT"
10932  },
10933  {
10934   "chips": ["gfx10"],
10935   "map": {"at": 225296, "to": "mm"},
10936   "name": "CB_PERFCOUNTER2_SELECT",
10937   "type_ref": "CB_PERFCOUNTER1_SELECT"
10938  },
10939  {
10940   "chips": ["gfx10"],
10941   "map": {"at": 225300, "to": "mm"},
10942   "name": "CB_PERFCOUNTER3_SELECT",
10943   "type_ref": "CB_PERFCOUNTER1_SELECT"
10944  },
10945  {
10946   "chips": ["gfx10"],
10947   "map": {"at": 225536, "to": "mm"},
10948   "name": "DB_PERFCOUNTER0_SELECT",
10949   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10950  },
10951  {
10952   "chips": ["gfx10"],
10953   "map": {"at": 225540, "to": "mm"},
10954   "name": "DB_PERFCOUNTER0_SELECT1",
10955   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10956  },
10957  {
10958   "chips": ["gfx10"],
10959   "map": {"at": 225544, "to": "mm"},
10960   "name": "DB_PERFCOUNTER1_SELECT",
10961   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10962  },
10963  {
10964   "chips": ["gfx10"],
10965   "map": {"at": 225548, "to": "mm"},
10966   "name": "DB_PERFCOUNTER1_SELECT1",
10967   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10968  },
10969  {
10970   "chips": ["gfx10"],
10971   "map": {"at": 225552, "to": "mm"},
10972   "name": "DB_PERFCOUNTER2_SELECT",
10973   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10974  },
10975  {
10976   "chips": ["gfx10"],
10977   "map": {"at": 225560, "to": "mm"},
10978   "name": "DB_PERFCOUNTER3_SELECT",
10979   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10980  },
10981  {
10982   "chips": ["gfx10"],
10983   "map": {"at": 225792, "to": "mm"},
10984   "name": "RLC_SPM_PERFMON_CNTL",
10985   "type_ref": "RLC_SPM_PERFMON_CNTL"
10986  },
10987  {
10988   "chips": ["gfx10"],
10989   "map": {"at": 225796, "to": "mm"},
10990   "name": "RLC_SPM_PERFMON_RING_BASE_LO"
10991  },
10992  {
10993   "chips": ["gfx10"],
10994   "map": {"at": 225800, "to": "mm"},
10995   "name": "RLC_SPM_PERFMON_RING_BASE_HI",
10996   "type_ref": "RLC_SPM_PERFMON_RING_BASE_HI"
10997  },
10998  {
10999   "chips": ["gfx10"],
11000   "map": {"at": 225804, "to": "mm"},
11001   "name": "RLC_SPM_PERFMON_RING_SIZE"
11002  },
11003  {
11004   "chips": ["gfx10"],
11005   "map": {"at": 225808, "to": "mm"},
11006   "name": "RLC_SPM_PERFMON_SEGMENT_SIZE",
11007   "type_ref": "RLC_SPM_PERFMON_SEGMENT_SIZE"
11008  },
11009  {
11010   "chips": ["gfx10"],
11011   "map": {"at": 225812, "to": "mm"},
11012   "name": "RLC_SPM_RING_RDPTR"
11013  },
11014  {
11015   "chips": ["gfx10"],
11016   "map": {"at": 225816, "to": "mm"},
11017   "name": "RLC_SPM_SEGMENT_THRESHOLD",
11018   "type_ref": "RLC_SPM_SEGMENT_THRESHOLD"
11019  },
11020  {
11021   "chips": ["gfx10"],
11022   "map": {"at": 225820, "to": "mm"},
11023   "name": "RLC_SPM_SE_MUXSEL_ADDR",
11024   "type_ref": "RLC_SPM_SE_MUXSEL_ADDR"
11025  },
11026  {
11027   "chips": ["gfx10"],
11028   "map": {"at": 225824, "to": "mm"},
11029   "name": "RLC_SPM_SE_MUXSEL_DATA"
11030  },
11031  {
11032   "chips": ["gfx10"],
11033   "map": {"at": 225828, "to": "mm"},
11034   "name": "RLC_SPM_GLOBAL_MUXSEL_ADDR",
11035   "type_ref": "RLC_SPM_GLOBAL_MUXSEL_ADDR"
11036  },
11037  {
11038   "chips": ["gfx10"],
11039   "map": {"at": 225832, "to": "mm"},
11040   "name": "RLC_SPM_GLOBAL_MUXSEL_DATA"
11041  },
11042  {
11043   "chips": ["gfx10"],
11044   "map": {"at": 225836, "to": "mm"},
11045   "name": "RLC_SPM_DESER_START_SKEW",
11046   "type_ref": "RLC_SPM_DESER_START_SKEW"
11047  },
11048  {
11049   "chips": ["gfx10"],
11050   "map": {"at": 225840, "to": "mm"},
11051   "name": "RLC_SPM_GLOBALS_SAMPLE_SKEW",
11052   "type_ref": "RLC_SPM_GLOBALS_SAMPLE_SKEW"
11053  },
11054  {
11055   "chips": ["gfx10"],
11056   "map": {"at": 225844, "to": "mm"},
11057   "name": "RLC_SPM_GLOBALS_MUXSEL_SKEW",
11058   "type_ref": "RLC_SPM_GLOBALS_MUXSEL_SKEW"
11059  },
11060  {
11061   "chips": ["gfx10"],
11062   "map": {"at": 225848, "to": "mm"},
11063   "name": "RLC_SPM_SE_SAMPLE_SKEW",
11064   "type_ref": "RLC_SPM_SE_SAMPLE_SKEW"
11065  },
11066  {
11067   "chips": ["gfx10"],
11068   "map": {"at": 225852, "to": "mm"},
11069   "name": "RLC_SPM_SE_MUXSEL_SKEW",
11070   "type_ref": "RLC_SPM_SE_MUXSEL_SKEW"
11071  },
11072  {
11073   "chips": ["gfx10"],
11074   "map": {"at": 225856, "to": "mm"},
11075   "name": "RLC_SPM_GLB_SAMPLEDELAY_IND_ADDR"
11076  },
11077  {
11078   "chips": ["gfx10"],
11079   "map": {"at": 225860, "to": "mm"},
11080   "name": "RLC_SPM_GLB_SAMPLEDELAY_IND_DATA",
11081   "type_ref": "RLC_SPM_GLB_SAMPLEDELAY_IND_DATA"
11082  },
11083  {
11084   "chips": ["gfx10"],
11085   "map": {"at": 225864, "to": "mm"},
11086   "name": "RLC_SPM_SE_SAMPLEDELAY_IND_ADDR"
11087  },
11088  {
11089   "chips": ["gfx10"],
11090   "map": {"at": 225868, "to": "mm"},
11091   "name": "RLC_SPM_SE_SAMPLEDELAY_IND_DATA",
11092   "type_ref": "RLC_SPM_GLB_SAMPLEDELAY_IND_DATA"
11093  },
11094  {
11095   "chips": ["gfx10"],
11096   "map": {"at": 225872, "to": "mm"},
11097   "name": "RLC_SPM_RING_WRPTR",
11098   "type_ref": "RLC_SPM_RING_WRPTR"
11099  },
11100  {
11101   "chips": ["gfx10"],
11102   "map": {"at": 225876, "to": "mm"},
11103   "name": "RLC_SPM_ACCUM_DATARAM_ADDR",
11104   "type_ref": "RLC_SPM_ACCUM_DATARAM_ADDR"
11105  },
11106  {
11107   "chips": ["gfx10"],
11108   "map": {"at": 225880, "to": "mm"},
11109   "name": "RLC_SPM_ACCUM_DATARAM_DATA"
11110  },
11111  {
11112   "chips": ["gfx10"],
11113   "map": {"at": 225884, "to": "mm"},
11114   "name": "RLC_SPM_ACCUM_CTRLRAM_ADDR",
11115   "type_ref": "RLC_SPM_ACCUM_CTRLRAM_ADDR"
11116  },
11117  {
11118   "chips": ["gfx10"],
11119   "map": {"at": 225888, "to": "mm"},
11120   "name": "RLC_SPM_ACCUM_CTRLRAM_DATA",
11121   "type_ref": "RLC_SPM_ACCUM_CTRLRAM_DATA"
11122  },
11123  {
11124   "chips": ["gfx10"],
11125   "map": {"at": 225892, "to": "mm"},
11126   "name": "RLC_SPM_ACCUM_STATUS",
11127   "type_ref": "RLC_SPM_ACCUM_STATUS"
11128  },
11129  {
11130   "chips": ["gfx10"],
11131   "map": {"at": 225896, "to": "mm"},
11132   "name": "RLC_SPM_ACCUM_CTRL",
11133   "type_ref": "RLC_SPM_ACCUM_CTRL"
11134  },
11135  {
11136   "chips": ["gfx10"],
11137   "map": {"at": 225900, "to": "mm"},
11138   "name": "RLC_SPM_ACCUM_MODE",
11139   "type_ref": "RLC_SPM_ACCUM_MODE"
11140  },
11141  {
11142   "chips": ["gfx10"],
11143   "map": {"at": 225904, "to": "mm"},
11144   "name": "RLC_SPM_ACCUM_THRESHOLD",
11145   "type_ref": "RLC_SPM_ACCUM_THRESHOLD"
11146  },
11147  {
11148   "chips": ["gfx10"],
11149   "map": {"at": 225908, "to": "mm"},
11150   "name": "RLC_SPM_ACCUM_SAMPLES_REQUESTED",
11151   "type_ref": "RLC_SPM_ACCUM_SAMPLES_REQUESTED"
11152  },
11153  {
11154   "chips": ["gfx10"],
11155   "map": {"at": 225912, "to": "mm"},
11156   "name": "RLC_SPM_ACCUM_DATARAM_WRCOUNT",
11157   "type_ref": "RLC_SPM_ACCUM_DATARAM_WRCOUNT"
11158  },
11159  {
11160   "chips": ["gfx10"],
11161   "map": {"at": 225916, "to": "mm"},
11162   "name": "RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE",
11163   "type_ref": "RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE"
11164  },
11165  {
11166   "chips": ["gfx10"],
11167   "map": {"at": 225920, "to": "mm"},
11168   "name": "RLC_SPM_PERFMON_GLB_SEGMENT_SIZE",
11169   "type_ref": "RLC_SPM_PERFMON_GLB_SEGMENT_SIZE"
11170  },
11171  {
11172   "chips": ["gfx10"],
11173   "map": {"at": 225924, "to": "mm"},
11174   "name": "RLC_SPM_VIRT_CTRL",
11175   "type_ref": "RLC_SPM_VIRT_CTRL"
11176  },
11177  {
11178   "chips": ["gfx10"],
11179   "map": {"at": 225932, "to": "mm"},
11180   "name": "RLC_SPM_VIRT_STATUS",
11181   "type_ref": "RLC_SPM_VIRT_STATUS"
11182  },
11183  {
11184   "chips": ["gfx10"],
11185   "map": {"at": 226048, "to": "mm"},
11186   "name": "RLC_PERFMON_CNTL",
11187   "type_ref": "RLC_PERFMON_CNTL"
11188  },
11189  {
11190   "chips": ["gfx10"],
11191   "map": {"at": 226052, "to": "mm"},
11192   "name": "RLC_PERFCOUNTER0_SELECT",
11193   "type_ref": "RLC_PERFCOUNTER0_SELECT"
11194  },
11195  {
11196   "chips": ["gfx10"],
11197   "map": {"at": 226056, "to": "mm"},
11198   "name": "RLC_PERFCOUNTER1_SELECT",
11199   "type_ref": "RLC_PERFCOUNTER0_SELECT"
11200  },
11201  {
11202   "chips": ["gfx10"],
11203   "map": {"at": 226060, "to": "mm"},
11204   "name": "RLC_GPU_IOV_PERF_CNT_CNTL",
11205   "type_ref": "RLC_GPU_IOV_PERF_CNT_CNTL"
11206  },
11207  {
11208   "chips": ["gfx10"],
11209   "map": {"at": 226064, "to": "mm"},
11210   "name": "RLC_GPU_IOV_PERF_CNT_WR_ADDR",
11211   "type_ref": "RLC_GPU_IOV_PERF_CNT_WR_ADDR"
11212  },
11213  {
11214   "chips": ["gfx10"],
11215   "map": {"at": 226068, "to": "mm"},
11216   "name": "RLC_GPU_IOV_PERF_CNT_WR_DATA"
11217  },
11218  {
11219   "chips": ["gfx10"],
11220   "map": {"at": 226072, "to": "mm"},
11221   "name": "RLC_GPU_IOV_PERF_CNT_RD_ADDR",
11222   "type_ref": "RLC_GPU_IOV_PERF_CNT_WR_ADDR"
11223  },
11224  {
11225   "chips": ["gfx10"],
11226   "map": {"at": 226076, "to": "mm"},
11227   "name": "RLC_GPU_IOV_PERF_CNT_RD_DATA"
11228  },
11229  {
11230   "chips": ["gfx10"],
11231   "map": {"at": 226192, "to": "mm"},
11232   "name": "RLC_PERFMON_CLK_CNTL",
11233   "type_ref": "RLC_PERFMON_CLK_CNTL"
11234  },
11235  {
11236   "chips": ["gfx10"],
11237   "map": {"at": 226196, "to": "mm"},
11238   "name": "RLC_PERFMON_CLK_CNTL_UCODE",
11239   "type_ref": "RLC_PERFMON_CLK_CNTL"
11240  },
11241  {
11242   "chips": ["gfx10"],
11243   "map": {"at": 226304, "to": "mm"},
11244   "name": "RMI_PERFCOUNTER0_SELECT",
11245   "type_ref": "CB_PERFCOUNTER0_SELECT"
11246  },
11247  {
11248   "chips": ["gfx10"],
11249   "map": {"at": 226308, "to": "mm"},
11250   "name": "RMI_PERFCOUNTER0_SELECT1",
11251   "type_ref": "CB_PERFCOUNTER0_SELECT1"
11252  },
11253  {
11254   "chips": ["gfx10"],
11255   "map": {"at": 226312, "to": "mm"},
11256   "name": "RMI_PERFCOUNTER1_SELECT",
11257   "type_ref": "CB_PERFCOUNTER1_SELECT"
11258  },
11259  {
11260   "chips": ["gfx10"],
11261   "map": {"at": 226316, "to": "mm"},
11262   "name": "RMI_PERFCOUNTER2_SELECT",
11263   "type_ref": "CB_PERFCOUNTER0_SELECT"
11264  },
11265  {
11266   "chips": ["gfx10"],
11267   "map": {"at": 226320, "to": "mm"},
11268   "name": "RMI_PERFCOUNTER2_SELECT1",
11269   "type_ref": "CB_PERFCOUNTER0_SELECT1"
11270  },
11271  {
11272   "chips": ["gfx10"],
11273   "map": {"at": 226324, "to": "mm"},
11274   "name": "RMI_PERFCOUNTER3_SELECT",
11275   "type_ref": "CB_PERFCOUNTER1_SELECT"
11276  },
11277  {
11278   "chips": ["gfx10"],
11279   "map": {"at": 226328, "to": "mm"},
11280   "name": "RMI_PERF_COUNTER_CNTL",
11281   "type_ref": "RMI_PERF_COUNTER_CNTL"
11282  },
11283  {
11284   "chips": ["gfx10"],
11285   "map": {"at": 226432, "to": "mm"},
11286   "name": "GC_ATC_L2_PERFCOUNTER0_CFG",
11287   "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG"
11288  },
11289  {
11290   "chips": ["gfx10"],
11291   "map": {"at": 226436, "to": "mm"},
11292   "name": "GC_ATC_L2_PERFCOUNTER1_CFG",
11293   "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG"
11294  },
11295  {
11296   "chips": ["gfx10"],
11297   "map": {"at": 226440, "to": "mm"},
11298   "name": "GC_ATC_L2_PERFCOUNTER_RSLT_CNTL",
11299   "type_ref": "GC_ATC_L2_PERFCOUNTER_RSLT_CNTL"
11300  },
11301  {
11302   "chips": ["gfx10"],
11303   "map": {"at": 226480, "to": "mm"},
11304   "name": "GCMC_VM_L2_PERFCOUNTER0_CFG",
11305   "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG"
11306  },
11307  {
11308   "chips": ["gfx10"],
11309   "map": {"at": 226484, "to": "mm"},
11310   "name": "GCMC_VM_L2_PERFCOUNTER1_CFG",
11311   "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG"
11312  },
11313  {
11314   "chips": ["gfx10"],
11315   "map": {"at": 226488, "to": "mm"},
11316   "name": "GCMC_VM_L2_PERFCOUNTER2_CFG",
11317   "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG"
11318  },
11319  {
11320   "chips": ["gfx10"],
11321   "map": {"at": 226492, "to": "mm"},
11322   "name": "GCMC_VM_L2_PERFCOUNTER3_CFG",
11323   "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG"
11324  },
11325  {
11326   "chips": ["gfx10"],
11327   "map": {"at": 226496, "to": "mm"},
11328   "name": "GCMC_VM_L2_PERFCOUNTER4_CFG",
11329   "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG"
11330  },
11331  {
11332   "chips": ["gfx10"],
11333   "map": {"at": 226500, "to": "mm"},
11334   "name": "GCMC_VM_L2_PERFCOUNTER5_CFG",
11335   "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG"
11336  },
11337  {
11338   "chips": ["gfx10"],
11339   "map": {"at": 226504, "to": "mm"},
11340   "name": "GCMC_VM_L2_PERFCOUNTER6_CFG",
11341   "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG"
11342  },
11343  {
11344   "chips": ["gfx10"],
11345   "map": {"at": 226508, "to": "mm"},
11346   "name": "GCMC_VM_L2_PERFCOUNTER7_CFG",
11347   "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG"
11348  },
11349  {
11350   "chips": ["gfx10"],
11351   "map": {"at": 226512, "to": "mm"},
11352   "name": "GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL",
11353   "type_ref": "GC_ATC_L2_PERFCOUNTER_RSLT_CNTL"
11354  },
11355  {
11356   "chips": ["gfx10"],
11357   "map": {"at": 226544, "to": "mm"},
11358   "name": "GCVML2_PERFCOUNTER2_0_SELECT",
11359   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11360  },
11361  {
11362   "chips": ["gfx10"],
11363   "map": {"at": 226548, "to": "mm"},
11364   "name": "GCVML2_PERFCOUNTER2_1_SELECT",
11365   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11366  },
11367  {
11368   "chips": ["gfx10"],
11369   "map": {"at": 226552, "to": "mm"},
11370   "name": "GCVML2_PERFCOUNTER2_0_SELECT1",
11371   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11372  },
11373  {
11374   "chips": ["gfx10"],
11375   "map": {"at": 226556, "to": "mm"},
11376   "name": "GCVML2_PERFCOUNTER2_1_SELECT1",
11377   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11378  },
11379  {
11380   "chips": ["gfx10"],
11381   "map": {"at": 226560, "to": "mm"},
11382   "name": "GCVML2_PERFCOUNTER2_0_MODE",
11383   "type_ref": "GCEA_PERFCOUNTER2_MODE"
11384  },
11385  {
11386   "chips": ["gfx10"],
11387   "map": {"at": 226564, "to": "mm"},
11388   "name": "GCVML2_PERFCOUNTER2_1_MODE",
11389   "type_ref": "GCEA_PERFCOUNTER2_MODE"
11390  },
11391  {
11392   "chips": ["gfx10"],
11393   "map": {"at": 226608, "to": "mm"},
11394   "name": "GC_ATC_L2_PERFCOUNTER2_SELECT",
11395   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11396  },
11397  {
11398   "chips": ["gfx10"],
11399   "map": {"at": 226612, "to": "mm"},
11400   "name": "GC_ATC_L2_PERFCOUNTER2_SELECT1",
11401   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11402  },
11403  {
11404   "chips": ["gfx10"],
11405   "map": {"at": 226616, "to": "mm"},
11406   "name": "GC_ATC_L2_PERFCOUNTER2_MODE",
11407   "type_ref": "GCEA_PERFCOUNTER2_MODE"
11408  },
11409  {
11410   "chips": ["gfx10"],
11411   "map": {"at": 226688, "to": "mm"},
11412   "name": "GCR_PERFCOUNTER0_SELECT",
11413   "type_ref": "CB_PERFCOUNTER0_SELECT"
11414  },
11415  {
11416   "chips": ["gfx10"],
11417   "map": {"at": 226692, "to": "mm"},
11418   "name": "GCR_PERFCOUNTER0_SELECT1",
11419   "type_ref": "CB_PERFCOUNTER0_SELECT1"
11420  },
11421  {
11422   "chips": ["gfx10"],
11423   "map": {"at": 226696, "to": "mm"},
11424   "name": "GCR_PERFCOUNTER1_SELECT",
11425   "type_ref": "GCR_PERFCOUNTER1_SELECT"
11426  },
11427  {
11428   "chips": ["gfx10"],
11429   "map": {"at": 226700, "to": "mm"},
11430   "name": "UTCL1_PERFCOUNTER0_SELECT",
11431   "type_ref": "UTCL1_PERFCOUNTER0_SELECT"
11432  },
11433  {
11434   "chips": ["gfx10"],
11435   "map": {"at": 226704, "to": "mm"},
11436   "name": "UTCL1_PERFCOUNTER1_SELECT",
11437   "type_ref": "UTCL1_PERFCOUNTER0_SELECT"
11438  },
11439  {
11440   "chips": ["gfx10"],
11441   "map": {"at": 226816, "to": "mm"},
11442   "name": "PA_PH_PERFCOUNTER0_SELECT",
11443   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11444  },
11445  {
11446   "chips": ["gfx10"],
11447   "map": {"at": 226820, "to": "mm"},
11448   "name": "PA_PH_PERFCOUNTER0_SELECT1",
11449   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11450  },
11451  {
11452   "chips": ["gfx10"],
11453   "map": {"at": 226824, "to": "mm"},
11454   "name": "PA_PH_PERFCOUNTER1_SELECT",
11455   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11456  },
11457  {
11458   "chips": ["gfx10"],
11459   "map": {"at": 226828, "to": "mm"},
11460   "name": "PA_PH_PERFCOUNTER2_SELECT",
11461   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11462  },
11463  {
11464   "chips": ["gfx10"],
11465   "map": {"at": 226832, "to": "mm"},
11466   "name": "PA_PH_PERFCOUNTER3_SELECT",
11467   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11468  },
11469  {
11470   "chips": ["gfx10"],
11471   "map": {"at": 226836, "to": "mm"},
11472   "name": "PA_PH_PERFCOUNTER4_SELECT",
11473   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
11474  },
11475  {
11476   "chips": ["gfx10"],
11477   "map": {"at": 226840, "to": "mm"},
11478   "name": "PA_PH_PERFCOUNTER5_SELECT",
11479   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
11480  },
11481  {
11482   "chips": ["gfx10"],
11483   "map": {"at": 226844, "to": "mm"},
11484   "name": "PA_PH_PERFCOUNTER6_SELECT",
11485   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
11486  },
11487  {
11488   "chips": ["gfx10"],
11489   "map": {"at": 226848, "to": "mm"},
11490   "name": "PA_PH_PERFCOUNTER7_SELECT",
11491   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
11492  },
11493  {
11494   "chips": ["gfx10"],
11495   "map": {"at": 226880, "to": "mm"},
11496   "name": "PA_PH_PERFCOUNTER1_SELECT1",
11497   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11498  },
11499  {
11500   "chips": ["gfx10"],
11501   "map": {"at": 226884, "to": "mm"},
11502   "name": "PA_PH_PERFCOUNTER2_SELECT1",
11503   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11504  },
11505  {
11506   "chips": ["gfx10"],
11507   "map": {"at": 226888, "to": "mm"},
11508   "name": "PA_PH_PERFCOUNTER3_SELECT1",
11509   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11510  },
11511  {
11512   "chips": ["gfx10"],
11513   "map": {"at": 227072, "to": "mm"},
11514   "name": "GL1A_PERFCOUNTER0_SELECT",
11515   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11516  },
11517  {
11518   "chips": ["gfx10"],
11519   "map": {"at": 227076, "to": "mm"},
11520   "name": "GL1A_PERFCOUNTER0_SELECT1",
11521   "type_ref": "GE_PERFCOUNTER0_SELECT1"
11522  },
11523  {
11524   "chips": ["gfx10"],
11525   "map": {"at": 227080, "to": "mm"},
11526   "name": "GL1A_PERFCOUNTER1_SELECT",
11527   "type_ref": "TCP_PERFCOUNTER2_SELECT"
11528  },
11529  {
11530   "chips": ["gfx10"],
11531   "map": {"at": 227084, "to": "mm"},
11532   "name": "GL1A_PERFCOUNTER2_SELECT",
11533   "type_ref": "TCP_PERFCOUNTER2_SELECT"
11534  },
11535  {
11536   "chips": ["gfx10"],
11537   "map": {"at": 227088, "to": "mm"},
11538   "name": "GL1A_PERFCOUNTER3_SELECT",
11539   "type_ref": "TCP_PERFCOUNTER2_SELECT"
11540  },
11541  {
11542   "chips": ["gfx10"],
11543   "map": {"at": 227200, "to": "mm"},
11544   "name": "CHA_PERFCOUNTER0_SELECT",
11545   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11546  },
11547  {
11548   "chips": ["gfx10"],
11549   "map": {"at": 227204, "to": "mm"},
11550   "name": "CHA_PERFCOUNTER0_SELECT1",
11551   "type_ref": "GE_PERFCOUNTER0_SELECT1"
11552  },
11553  {
11554   "chips": ["gfx10"],
11555   "map": {"at": 227208, "to": "mm"},
11556   "name": "CHA_PERFCOUNTER1_SELECT",
11557   "type_ref": "TCP_PERFCOUNTER2_SELECT"
11558  },
11559  {
11560   "chips": ["gfx10"],
11561   "map": {"at": 227212, "to": "mm"},
11562   "name": "CHA_PERFCOUNTER2_SELECT",
11563   "type_ref": "TCP_PERFCOUNTER2_SELECT"
11564  },
11565  {
11566   "chips": ["gfx10"],
11567   "map": {"at": 227216, "to": "mm"},
11568   "name": "CHA_PERFCOUNTER3_SELECT",
11569   "type_ref": "TCP_PERFCOUNTER2_SELECT"
11570  },
11571  {
11572   "chips": ["gfx10"],
11573   "map": {"at": 227328, "to": "mm"},
11574   "name": "GUS_PERFCOUNTER2_SELECT",
11575   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11576  },
11577  {
11578   "chips": ["gfx10"],
11579   "map": {"at": 227332, "to": "mm"},
11580   "name": "GUS_PERFCOUNTER2_SELECT1",
11581   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11582  },
11583  {
11584   "chips": ["gfx10"],
11585   "map": {"at": 227336, "to": "mm"},
11586   "name": "GUS_PERFCOUNTER2_MODE",
11587   "type_ref": "GCEA_PERFCOUNTER2_MODE"
11588  }
11589 ],
11590 "register_types": {
11591  "CB_BLEND0_CONTROL": {
11592   "fields": [
11593    {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"},
11594    {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"},
11595    {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"},
11596    {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"},
11597    {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"},
11598    {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"},
11599    {"bits": [29, 29], "name": "SEPARATE_ALPHA_BLEND"},
11600    {"bits": [30, 30], "name": "ENABLE"},
11601    {"bits": [31, 31], "name": "DISABLE_ROP3"}
11602   ]
11603  },
11604  "CB_COLOR0_ATTRIB": {
11605   "fields": [
11606    {"bits": [0, 4], "name": "TILE_MODE_INDEX"},
11607    {"bits": [5, 9], "name": "FMASK_TILE_MODE_INDEX"},
11608    {"bits": [10, 11], "name": "FMASK_BANK_HEIGHT"},
11609    {"bits": [12, 14], "name": "NUM_SAMPLES"},
11610    {"bits": [15, 16], "name": "NUM_FRAGMENTS"},
11611    {"bits": [17, 17], "name": "FORCE_DST_ALPHA_1"},
11612    {"bits": [18, 18], "name": "DISABLE_FMASK_NOFETCH_OPT"},
11613    {"bits": [19, 19], "name": "LIMIT_COLOR_FETCH_TO_256B_MAX"}
11614   ]
11615  },
11616  "CB_COLOR0_ATTRIB2": {
11617   "fields": [
11618    {"bits": [0, 13], "name": "MIP0_HEIGHT"},
11619    {"bits": [14, 27], "name": "MIP0_WIDTH"},
11620    {"bits": [28, 31], "name": "MAX_MIP"}
11621   ]
11622  },
11623  "CB_COLOR0_ATTRIB3": {
11624   "fields": [
11625    {"bits": [0, 12], "name": "MIP0_DEPTH"},
11626    {"bits": [13, 13], "name": "META_LINEAR"},
11627    {"bits": [14, 18], "name": "COLOR_SW_MODE"},
11628    {"bits": [19, 23], "name": "FMASK_SW_MODE"},
11629    {"bits": [24, 25], "name": "RESOURCE_TYPE"},
11630    {"bits": [26, 26], "name": "CMASK_PIPE_ALIGNED"},
11631    {"bits": [27, 29], "name": "RESOURCE_LEVEL"},
11632    {"bits": [30, 30], "name": "DCC_PIPE_ALIGNED"}
11633   ]
11634  },
11635  "CB_COLOR0_BASE_EXT": {
11636   "fields": [
11637    {"bits": [0, 7], "name": "BASE_256B"}
11638   ]
11639  },
11640  "CB_COLOR0_CMASK_SLICE": {
11641   "fields": [
11642    {"bits": [0, 13], "name": "TILE_MAX"}
11643   ]
11644  },
11645  "CB_COLOR0_DCC_CONTROL": {
11646   "fields": [
11647    {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"},
11648    {"bits": [1, 1], "name": "KEY_CLEAR_ENABLE"},
11649    {"bits": [2, 3], "enum_ref": "CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE", "name": "MAX_UNCOMPRESSED_BLOCK_SIZE"},
11650    {"bits": [4, 4], "enum_ref": "CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE", "name": "MIN_COMPRESSED_BLOCK_SIZE"},
11651    {"bits": [5, 6], "name": "MAX_COMPRESSED_BLOCK_SIZE"},
11652    {"bits": [7, 8], "name": "COLOR_TRANSFORM"},
11653    {"bits": [9, 9], "name": "INDEPENDENT_64B_BLOCKS"},
11654    {"bits": [10, 13], "name": "LOSSY_RGB_PRECISION"},
11655    {"bits": [14, 17], "name": "LOSSY_ALPHA_PRECISION"},
11656    {"bits": [18, 18], "name": "DISABLE_CONSTANT_ENCODE_REG"},
11657    {"bits": [19, 19], "name": "ENABLE_CONSTANT_ENCODE_REG_WRITE"},
11658    {"bits": [20, 20], "name": "INDEPENDENT_128B_BLOCKS"}
11659   ]
11660  },
11661  "CB_COLOR0_INFO": {
11662   "fields": [
11663    {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"},
11664    {"bits": [2, 6], "enum_ref": "ColorFormat", "name": "FORMAT"},
11665    {"bits": [7, 7], "name": "LINEAR_GENERAL"},
11666    {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"},
11667    {"bits": [11, 12], "enum_ref": "SurfaceSwap", "name": "COMP_SWAP"},
11668    {"bits": [13, 13], "name": "FAST_CLEAR"},
11669    {"bits": [14, 14], "name": "COMPRESSION"},
11670    {"bits": [15, 15], "name": "BLEND_CLAMP"},
11671    {"bits": [16, 16], "name": "BLEND_BYPASS"},
11672    {"bits": [17, 17], "name": "SIMPLE_FLOAT"},
11673    {"bits": [18, 18], "name": "ROUND_MODE"},
11674    {"bits": [19, 19], "name": "CMASK_IS_LINEAR"},
11675    {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"},
11676    {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"},
11677    {"bits": [26, 26], "name": "FMASK_COMPRESSION_DISABLE"},
11678    {"bits": [27, 27], "name": "FMASK_COMPRESS_1FRAG_ONLY"},
11679    {"bits": [28, 28], "name": "DCC_ENABLE"},
11680    {"bits": [29, 30], "enum_ref": "CmaskAddr", "name": "CMASK_ADDR_TYPE"},
11681    {"bits": [31, 31], "name": "ALT_TILE_MODE"}
11682   ]
11683  },
11684  "CB_COLOR0_PITCH": {
11685   "fields": [
11686    {"bits": [0, 10], "name": "TILE_MAX"},
11687    {"bits": [20, 30], "name": "FMASK_TILE_MAX"}
11688   ]
11689  },
11690  "CB_COLOR0_SLICE": {
11691   "fields": [
11692    {"bits": [0, 21], "name": "TILE_MAX"}
11693   ]
11694  },
11695  "CB_COLOR0_VIEW": {
11696   "fields": [
11697    {"bits": [0, 12], "name": "SLICE_START"},
11698    {"bits": [13, 25], "name": "SLICE_MAX"},
11699    {"bits": [26, 29], "name": "MIP_LEVEL"}
11700   ]
11701  },
11702  "CB_COLOR_CONTROL": {
11703   "fields": [
11704    {"bits": [0, 0], "name": "DISABLE_DUAL_QUAD"},
11705    {"bits": [3, 3], "name": "DEGAMMA_ENABLE"},
11706    {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"},
11707    {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"}
11708   ]
11709  },
11710  "CB_COVERAGE_OUT_CONTROL": {
11711   "fields": [
11712    {"bits": [0, 0], "name": "COVERAGE_OUT_ENABLE"},
11713    {"bits": [1, 3], "name": "COVERAGE_OUT_MRT"},
11714    {"bits": [4, 5], "name": "COVERAGE_OUT_CHANNEL"},
11715    {"bits": [8, 11], "name": "COVERAGE_OUT_SAMPLES"}
11716   ]
11717  },
11718  "CB_DCC_CONTROL": {
11719   "fields": [
11720    {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"},
11721    {"bits": [2, 6], "name": "OVERWRITE_COMBINER_WATERMARK"},
11722    {"bits": [8, 8], "name": "DISABLE_CONSTANT_ENCODE_AC01"},
11723    {"bits": [9, 9], "name": "DISABLE_CONSTANT_ENCODE_SINGLE"},
11724    {"bits": [10, 10], "name": "DISABLE_CONSTANT_ENCODE_REG"},
11725    {"bits": [12, 12], "name": "DISABLE_ELIMFC_SKIP_OF_AC01"},
11726    {"bits": [13, 13], "name": "DISABLE_ELIMFC_SKIP_OF_SINGLE"},
11727    {"bits": [14, 14], "name": "ENABLE_ELIMFC_SKIP_OF_REG"}
11728   ]
11729  },
11730  "CB_PERFCOUNTER0_SELECT": {
11731   "fields": [
11732    {"bits": [0, 8], "name": "PERF_SEL"},
11733    {"bits": [10, 18], "name": "PERF_SEL1"},
11734    {"bits": [20, 23], "name": "CNTR_MODE"},
11735    {"bits": [24, 27], "name": "PERF_MODE1"},
11736    {"bits": [28, 31], "name": "PERF_MODE"}
11737   ]
11738  },
11739  "CB_PERFCOUNTER0_SELECT1": {
11740   "fields": [
11741    {"bits": [0, 8], "name": "PERF_SEL2"},
11742    {"bits": [10, 18], "name": "PERF_SEL3"},
11743    {"bits": [24, 27], "name": "PERF_MODE3"},
11744    {"bits": [28, 31], "name": "PERF_MODE2"}
11745   ]
11746  },
11747  "CB_PERFCOUNTER1_SELECT": {
11748   "fields": [
11749    {"bits": [0, 8], "name": "PERF_SEL"},
11750    {"bits": [28, 31], "name": "PERF_MODE"}
11751   ]
11752  },
11753  "CB_PERFCOUNTER_FILTER": {
11754   "fields": [
11755    {"bits": [0, 0], "name": "OP_FILTER_ENABLE"},
11756    {"bits": [1, 3], "enum_ref": "CBPerfOpFilterSel", "name": "OP_FILTER_SEL"},
11757    {"bits": [4, 4], "name": "FORMAT_FILTER_ENABLE"},
11758    {"bits": [5, 9], "name": "FORMAT_FILTER_SEL"},
11759    {"bits": [10, 10], "name": "CLEAR_FILTER_ENABLE"},
11760    {"bits": [11, 11], "enum_ref": "CBPerfClearFilterSel", "name": "CLEAR_FILTER_SEL"},
11761    {"bits": [12, 12], "name": "MRT_FILTER_ENABLE"},
11762    {"bits": [13, 15], "name": "MRT_FILTER_SEL"},
11763    {"bits": [17, 17], "name": "NUM_SAMPLES_FILTER_ENABLE"},
11764    {"bits": [18, 20], "name": "NUM_SAMPLES_FILTER_SEL"},
11765    {"bits": [21, 21], "name": "NUM_FRAGMENTS_FILTER_ENABLE"},
11766    {"bits": [22, 23], "name": "NUM_FRAGMENTS_FILTER_SEL"}
11767   ]
11768  },
11769  "CB_RMI_GL2_CACHE_CONTROL": {
11770   "fields": [
11771    {"bits": [0, 1], "enum_ref": "WritePolicy", "name": "CMASK_WR_POLICY"},
11772    {"bits": [2, 3], "enum_ref": "WritePolicy", "name": "FMASK_WR_POLICY"},
11773    {"bits": [4, 5], "enum_ref": "WritePolicy", "name": "DCC_WR_POLICY"},
11774    {"bits": [6, 7], "enum_ref": "WritePolicy", "name": "COLOR_WR_POLICY"},
11775    {"bits": [16, 17], "enum_ref": "ReadPolicy", "name": "CMASK_RD_POLICY"},
11776    {"bits": [18, 19], "enum_ref": "ReadPolicy", "name": "FMASK_RD_POLICY"},
11777    {"bits": [20, 21], "enum_ref": "ReadPolicy", "name": "DCC_RD_POLICY"},
11778    {"bits": [22, 23], "enum_ref": "ReadPolicy", "name": "COLOR_RD_POLICY"},
11779    {"bits": [30, 30], "name": "FMASK_BIG_PAGE"},
11780    {"bits": [31, 31], "name": "COLOR_BIG_PAGE"}
11781   ]
11782  },
11783  "CB_SHADER_MASK": {
11784   "fields": [
11785    {"bits": [0, 3], "name": "OUTPUT0_ENABLE"},
11786    {"bits": [4, 7], "name": "OUTPUT1_ENABLE"},
11787    {"bits": [8, 11], "name": "OUTPUT2_ENABLE"},
11788    {"bits": [12, 15], "name": "OUTPUT3_ENABLE"},
11789    {"bits": [16, 19], "name": "OUTPUT4_ENABLE"},
11790    {"bits": [20, 23], "name": "OUTPUT5_ENABLE"},
11791    {"bits": [24, 27], "name": "OUTPUT6_ENABLE"},
11792    {"bits": [28, 31], "name": "OUTPUT7_ENABLE"}
11793   ]
11794  },
11795  "CB_TARGET_MASK": {
11796   "fields": [
11797    {"bits": [0, 3], "name": "TARGET0_ENABLE"},
11798    {"bits": [4, 7], "name": "TARGET1_ENABLE"},
11799    {"bits": [8, 11], "name": "TARGET2_ENABLE"},
11800    {"bits": [12, 15], "name": "TARGET3_ENABLE"},
11801    {"bits": [16, 19], "name": "TARGET4_ENABLE"},
11802    {"bits": [20, 23], "name": "TARGET5_ENABLE"},
11803    {"bits": [24, 27], "name": "TARGET6_ENABLE"},
11804    {"bits": [28, 31], "name": "TARGET7_ENABLE"}
11805   ]
11806  },
11807  "COHER_DEST_BASE_HI_0": {
11808   "fields": [
11809    {"bits": [0, 7], "name": "DEST_BASE_HI_256B"}
11810   ]
11811  },
11812  "COMPUTE_DDID_INDEX": {
11813   "fields": [
11814    {"bits": [0, 10], "name": "INDEX"}
11815   ]
11816  },
11817  "COMPUTE_DISPATCH_INITIATOR": {
11818   "fields": [
11819    {"bits": [0, 0], "name": "COMPUTE_SHADER_EN"},
11820    {"bits": [1, 1], "name": "PARTIAL_TG_EN"},
11821    {"bits": [2, 2], "name": "FORCE_START_AT_000"},
11822    {"bits": [3, 3], "name": "ORDERED_APPEND_ENBL"},
11823    {"bits": [4, 4], "name": "ORDERED_APPEND_MODE"},
11824    {"bits": [5, 5], "name": "USE_THREAD_DIMENSIONS"},
11825    {"bits": [6, 6], "name": "ORDER_MODE"},
11826    {"bits": [10, 10], "name": "SCALAR_L1_INV_VOL"},
11827    {"bits": [11, 11], "name": "VECTOR_L1_INV_VOL"},
11828    {"bits": [12, 12], "name": "RESERVED"},
11829    {"bits": [13, 13], "name": "TUNNEL_ENABLE"},
11830    {"bits": [14, 14], "name": "RESTORE"},
11831    {"bits": [15, 15], "name": "CS_W32_EN"}
11832   ]
11833  },
11834  "COMPUTE_DISPATCH_TUNNEL": {
11835   "fields": [
11836    {"bits": [0, 9], "name": "OFF_DELAY"},
11837    {"bits": [10, 10], "name": "IMMEDIATE"}
11838   ]
11839  },
11840  "COMPUTE_MISC_RESERVED": {
11841   "fields": [
11842    {"bits": [0, 1], "name": "SEND_SEID"},
11843    {"bits": [2, 2], "name": "RESERVED2"},
11844    {"bits": [3, 3], "name": "RESERVED3"},
11845    {"bits": [4, 4], "name": "RESERVED4"},
11846    {"bits": [5, 16], "name": "WAVE_ID_BASE"}
11847   ]
11848  },
11849  "COMPUTE_NUM_THREAD_X": {
11850   "fields": [
11851    {"bits": [0, 15], "name": "NUM_THREAD_FULL"},
11852    {"bits": [16, 31], "name": "NUM_THREAD_PARTIAL"}
11853   ]
11854  },
11855  "COMPUTE_PERFCOUNT_ENABLE": {
11856   "fields": [
11857    {"bits": [0, 0], "name": "PERFCOUNT_ENABLE"}
11858   ]
11859  },
11860  "COMPUTE_PGM_HI": {
11861   "fields": [
11862    {"bits": [0, 7], "name": "DATA"}
11863   ]
11864  },
11865  "COMPUTE_PGM_RSRC1": {
11866   "fields": [
11867    {"bits": [0, 5], "name": "VGPRS"},
11868    {"bits": [6, 9], "name": "SGPRS"},
11869    {"bits": [10, 11], "name": "PRIORITY"},
11870    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
11871    {"bits": [20, 20], "name": "PRIV"},
11872    {"bits": [21, 21], "name": "DX10_CLAMP"},
11873    {"bits": [23, 23], "name": "IEEE_MODE"},
11874    {"bits": [24, 24], "name": "BULKY"},
11875    {"bits": [26, 26], "name": "FP16_OVFL"},
11876    {"bits": [29, 29], "name": "WGP_MODE"},
11877    {"bits": [30, 30], "name": "MEM_ORDERED"},
11878    {"bits": [31, 31], "name": "FWD_PROGRESS"}
11879   ]
11880  },
11881  "COMPUTE_PGM_RSRC2": {
11882   "fields": [
11883    {"bits": [0, 0], "name": "SCRATCH_EN"},
11884    {"bits": [1, 5], "name": "USER_SGPR"},
11885    {"bits": [6, 6], "name": "TRAP_PRESENT"},
11886    {"bits": [7, 7], "name": "TGID_X_EN"},
11887    {"bits": [8, 8], "name": "TGID_Y_EN"},
11888    {"bits": [9, 9], "name": "TGID_Z_EN"},
11889    {"bits": [10, 10], "name": "TG_SIZE_EN"},
11890    {"bits": [11, 12], "name": "TIDIG_COMP_CNT"},
11891    {"bits": [13, 14], "name": "EXCP_EN_MSB"},
11892    {"bits": [15, 23], "name": "LDS_SIZE"},
11893    {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
11894   ]
11895  },
11896  "COMPUTE_PGM_RSRC3": {
11897   "fields": [
11898    {"bits": [0, 3], "name": "SHARED_VGPR_CNT"}
11899   ]
11900  },
11901  "COMPUTE_PIPELINESTAT_ENABLE": {
11902   "fields": [
11903    {"bits": [0, 0], "name": "PIPELINESTAT_ENABLE"}
11904   ]
11905  },
11906  "COMPUTE_RELAUNCH": {
11907   "fields": [
11908    {"bits": [0, 29], "name": "PAYLOAD"},
11909    {"bits": [30, 30], "name": "IS_EVENT"},
11910    {"bits": [31, 31], "name": "IS_STATE"}
11911   ]
11912  },
11913  "COMPUTE_REQ_CTRL": {
11914   "fields": [
11915    {"bits": [0, 0], "name": "SOFT_GROUPING_EN"},
11916    {"bits": [1, 4], "name": "NUMBER_OF_REQUESTS_PER_CU"},
11917    {"bits": [5, 8], "name": "SOFT_GROUPING_ALLOCATION_TIMEOUT"},
11918    {"bits": [9, 9], "name": "HARD_LOCK_HYSTERESIS"},
11919    {"bits": [10, 14], "name": "HARD_LOCK_LOW_THRESHOLD"},
11920    {"bits": [15, 15], "name": "PRODUCER_REQUEST_LOCKOUT"},
11921    {"bits": [16, 16], "name": "GLOBAL_SCANNING_EN"},
11922    {"bits": [17, 19], "name": "ALLOCATION_RATE_THROTTLING_THRESHOLD"},
11923    {"bits": [20, 26], "name": "DEDICATED_PREALLOCATION_BUFFER_LIMIT"}
11924   ]
11925  },
11926  "COMPUTE_RESOURCE_LIMITS": {
11927   "fields": [
11928    {"bits": [0, 9], "name": "WAVES_PER_SH"},
11929    {"bits": [12, 15], "name": "TG_PER_CU"},
11930    {"bits": [16, 21], "name": "LOCK_THRESHOLD"},
11931    {"bits": [22, 22], "name": "SIMD_DEST_CNTL"},
11932    {"bits": [23, 23], "name": "FORCE_SIMD_DIST"},
11933    {"bits": [24, 26], "name": "CU_GROUP_COUNT"}
11934   ]
11935  },
11936  "COMPUTE_THREAD_TRACE_ENABLE": {
11937   "fields": [
11938    {"bits": [0, 0], "name": "THREAD_TRACE_ENABLE"}
11939   ]
11940  },
11941  "COMPUTE_TMPRING_SIZE": {
11942   "fields": [
11943    {"bits": [0, 11], "name": "WAVES"},
11944    {"bits": [12, 24], "name": "WAVESIZE"}
11945   ]
11946  },
11947  "COMPUTE_VMID": {
11948   "fields": [
11949    {"bits": [0, 3], "name": "DATA"}
11950   ]
11951  },
11952  "COMPUTE_WAVE_RESTORE_ADDR_HI": {
11953   "fields": [
11954    {"bits": [0, 15], "name": "ADDR"}
11955   ]
11956  },
11957  "CPF_LATENCY_STATS_SELECT": {
11958   "fields": [
11959    {"bits": [0, 3], "name": "INDEX"},
11960    {"bits": [30, 30], "name": "CLEAR"},
11961    {"bits": [31, 31], "name": "ENABLE"}
11962   ]
11963  },
11964  "CPF_TC_PERF_COUNTER_WINDOW_SELECT": {
11965   "fields": [
11966    {"bits": [0, 2], "name": "INDEX"},
11967    {"bits": [30, 30], "name": "ALWAYS"},
11968    {"bits": [31, 31], "name": "ENABLE"}
11969   ]
11970  },
11971  "CPG_LATENCY_STATS_SELECT": {
11972   "fields": [
11973    {"bits": [0, 4], "name": "INDEX"},
11974    {"bits": [30, 30], "name": "CLEAR"},
11975    {"bits": [31, 31], "name": "ENABLE"}
11976   ]
11977  },
11978  "CPG_PERFCOUNTER0_SELECT1": {
11979   "fields": [
11980    {"bits": [0, 9], "name": "PERF_SEL2"},
11981    {"bits": [10, 19], "name": "PERF_SEL3"},
11982    {"bits": [24, 27], "name": "CNTR_MODE3"},
11983    {"bits": [28, 31], "name": "CNTR_MODE2"}
11984   ]
11985  },
11986  "CPG_PERFCOUNTER1_SELECT": {
11987   "fields": [
11988    {"bits": [0, 9], "name": "PERF_SEL"},
11989    {"bits": [10, 19], "name": "PERF_SEL1"},
11990    {"bits": [20, 23], "name": "SPM_MODE"},
11991    {"bits": [24, 27], "name": "CNTR_MODE1"},
11992    {"bits": [28, 31], "name": "CNTR_MODE0"}
11993   ]
11994  },
11995  "CPG_TC_PERF_COUNTER_WINDOW_SELECT": {
11996   "fields": [
11997    {"bits": [0, 4], "name": "INDEX"},
11998    {"bits": [30, 30], "name": "ALWAYS"},
11999    {"bits": [31, 31], "name": "ENABLE"}
12000   ]
12001  },
12002  "CP_APPEND_ADDR_HI": {
12003   "fields": [
12004    {"bits": [0, 15], "name": "MEM_ADDR_HI"},
12005    {"bits": [16, 16], "name": "CS_PS_SEL"},
12006    {"bits": [25, 26], "name": "CACHE_POLICY"},
12007    {"bits": [29, 31], "name": "COMMAND"}
12008   ]
12009  },
12010  "CP_APPEND_ADDR_LO": {
12011   "fields": [
12012    {"bits": [2, 31], "name": "MEM_ADDR_LO"}
12013   ]
12014  },
12015  "CP_CE_IB1_BASE_HI": {
12016   "fields": [
12017    {"bits": [0, 15], "name": "IB1_BASE_HI"}
12018   ]
12019  },
12020  "CP_CE_IB1_BASE_LO": {
12021   "fields": [
12022    {"bits": [2, 31], "name": "IB1_BASE_LO"}
12023   ]
12024  },
12025  "CP_CE_IB1_BUFSZ": {
12026   "fields": [
12027    {"bits": [0, 19], "name": "IB1_BUFSZ"}
12028   ]
12029  },
12030  "CP_CE_IB1_CMD_BUFSZ": {
12031   "fields": [
12032    {"bits": [0, 19], "name": "IB1_CMD_REQSZ"}
12033   ]
12034  },
12035  "CP_CE_IB2_BASE_HI": {
12036   "fields": [
12037    {"bits": [0, 15], "name": "IB2_BASE_HI"}
12038   ]
12039  },
12040  "CP_CE_IB2_BASE_LO": {
12041   "fields": [
12042    {"bits": [2, 31], "name": "IB2_BASE_LO"}
12043   ]
12044  },
12045  "CP_CE_IB2_BUFSZ": {
12046   "fields": [
12047    {"bits": [0, 19], "name": "IB2_BUFSZ"}
12048   ]
12049  },
12050  "CP_CE_IB2_CMD_BUFSZ": {
12051   "fields": [
12052    {"bits": [0, 19], "name": "IB2_CMD_REQSZ"}
12053   ]
12054  },
12055  "CP_CE_INIT_BASE_HI": {
12056   "fields": [
12057    {"bits": [0, 15], "name": "INIT_BASE_HI"}
12058   ]
12059  },
12060  "CP_CE_INIT_BASE_LO": {
12061   "fields": [
12062    {"bits": [5, 31], "name": "INIT_BASE_LO"}
12063   ]
12064  },
12065  "CP_CE_INIT_BUFSZ": {
12066   "fields": [
12067    {"bits": [0, 11], "name": "INIT_BUFSZ"}
12068   ]
12069  },
12070  "CP_CE_INIT_CMD_BUFSZ": {
12071   "fields": [
12072    {"bits": [0, 11], "name": "INIT_CMD_REQSZ"}
12073   ]
12074  },
12075  "CP_COHER_BASE_HI": {
12076   "fields": [
12077    {"bits": [0, 7], "name": "COHER_BASE_HI_256B"}
12078   ]
12079  },
12080  "CP_COHER_CNTL": {
12081   "fields": [
12082    {"bits": [3, 3], "name": "TC_NC_ACTION_ENA"},
12083    {"bits": [4, 4], "name": "TC_WC_ACTION_ENA"},
12084    {"bits": [5, 5], "name": "TC_INV_METADATA_ACTION_ENA"},
12085    {"bits": [15, 15], "name": "TCL1_VOL_ACTION_ENA"},
12086    {"bits": [18, 18], "name": "TC_WB_ACTION_ENA"},
12087    {"bits": [22, 22], "name": "TCL1_ACTION_ENA"},
12088    {"bits": [23, 23], "name": "TC_ACTION_ENA"},
12089    {"bits": [25, 25], "name": "CB_ACTION_ENA"},
12090    {"bits": [26, 26], "name": "DB_ACTION_ENA"},
12091    {"bits": [27, 27], "name": "SH_KCACHE_ACTION_ENA"},
12092    {"bits": [28, 28], "name": "SH_KCACHE_VOL_ACTION_ENA"},
12093    {"bits": [29, 29], "name": "SH_ICACHE_ACTION_ENA"},
12094    {"bits": [30, 30], "name": "SH_KCACHE_WB_ACTION_ENA"}
12095   ]
12096  },
12097  "CP_COHER_SIZE_HI": {
12098   "fields": [
12099    {"bits": [0, 7], "name": "COHER_SIZE_HI_256B"}
12100   ]
12101  },
12102  "CP_COHER_START_DELAY": {
12103   "fields": [
12104    {"bits": [0, 5], "name": "START_DELAY_COUNT"}
12105   ]
12106  },
12107  "CP_COHER_STATUS": {
12108   "fields": [
12109    {"bits": [24, 25], "name": "MEID"},
12110    {"bits": [31, 31], "name": "STATUS"}
12111   ]
12112  },
12113  "CP_CPC_BUSY_STAT": {
12114   "fields": [
12115    {"bits": [0, 0], "name": "MEC1_LOAD_BUSY"},
12116    {"bits": [1, 1], "name": "MEC1_SEMAPOHRE_BUSY"},
12117    {"bits": [2, 2], "name": "MEC1_MUTEX_BUSY"},
12118    {"bits": [3, 3], "name": "MEC1_MESSAGE_BUSY"},
12119    {"bits": [4, 4], "name": "MEC1_EOP_QUEUE_BUSY"},
12120    {"bits": [5, 5], "name": "MEC1_IQ_QUEUE_BUSY"},
12121    {"bits": [6, 6], "name": "MEC1_IB_QUEUE_BUSY"},
12122    {"bits": [7, 7], "name": "MEC1_TC_BUSY"},
12123    {"bits": [8, 8], "name": "MEC1_DMA_BUSY"},
12124    {"bits": [9, 9], "name": "MEC1_PARTIAL_FLUSH_BUSY"},
12125    {"bits": [10, 10], "name": "MEC1_PIPE0_BUSY"},
12126    {"bits": [11, 11], "name": "MEC1_PIPE1_BUSY"},
12127    {"bits": [12, 12], "name": "MEC1_PIPE2_BUSY"},
12128    {"bits": [13, 13], "name": "MEC1_PIPE3_BUSY"},
12129    {"bits": [16, 16], "name": "MEC2_LOAD_BUSY"},
12130    {"bits": [17, 17], "name": "MEC2_SEMAPOHRE_BUSY"},
12131    {"bits": [18, 18], "name": "MEC2_MUTEX_BUSY"},
12132    {"bits": [19, 19], "name": "MEC2_MESSAGE_BUSY"},
12133    {"bits": [20, 20], "name": "MEC2_EOP_QUEUE_BUSY"},
12134    {"bits": [21, 21], "name": "MEC2_IQ_QUEUE_BUSY"},
12135    {"bits": [22, 22], "name": "MEC2_IB_QUEUE_BUSY"},
12136    {"bits": [23, 23], "name": "MEC2_TC_BUSY"},
12137    {"bits": [24, 24], "name": "MEC2_DMA_BUSY"},
12138    {"bits": [25, 25], "name": "MEC2_PARTIAL_FLUSH_BUSY"},
12139    {"bits": [26, 26], "name": "MEC2_PIPE0_BUSY"},
12140    {"bits": [27, 27], "name": "MEC2_PIPE1_BUSY"},
12141    {"bits": [28, 28], "name": "MEC2_PIPE2_BUSY"},
12142    {"bits": [29, 29], "name": "MEC2_PIPE3_BUSY"}
12143   ]
12144  },
12145  "CP_CPC_BUSY_STAT2": {
12146   "fields": [
12147    {"bits": [0, 0], "name": "MES_LOAD_BUSY"},
12148    {"bits": [2, 2], "name": "MES_MUTEX_BUSY"},
12149    {"bits": [3, 3], "name": "MES_MESSAGE_BUSY"},
12150    {"bits": [7, 7], "name": "MES_TC_BUSY"},
12151    {"bits": [8, 8], "name": "MES_DMA_BUSY"},
12152    {"bits": [10, 10], "name": "MES_PIPE0_BUSY"},
12153    {"bits": [11, 11], "name": "MES_PIPE1_BUSY"},
12154    {"bits": [12, 12], "name": "MES_PIPE2_BUSY"},
12155    {"bits": [13, 13], "name": "MES_PIPE3_BUSY"}
12156   ]
12157  },
12158  "CP_CPC_GRBM_FREE_COUNT": {
12159   "fields": [
12160    {"bits": [0, 5], "name": "FREE_COUNT"}
12161   ]
12162  },
12163  "CP_CPC_HALT_HYST_COUNT": {
12164   "fields": [
12165    {"bits": [0, 3], "name": "COUNT"}
12166   ]
12167  },
12168  "CP_CPC_SCRATCH_INDEX": {
12169   "fields": [
12170    {"bits": [0, 8], "name": "SCRATCH_INDEX"},
12171    {"bits": [31, 31], "name": "SCRATCH_INDEX_64BIT_MODE"}
12172   ]
12173  },
12174  "CP_CPC_STALLED_STAT1": {
12175   "fields": [
12176    {"bits": [3, 3], "name": "RCIU_TX_FREE_STALL"},
12177    {"bits": [4, 4], "name": "RCIU_PRIV_VIOLATION"},
12178    {"bits": [6, 6], "name": "TCIU_TX_FREE_STALL"},
12179    {"bits": [8, 8], "name": "MEC1_DECODING_PACKET"},
12180    {"bits": [9, 9], "name": "MEC1_WAIT_ON_RCIU"},
12181    {"bits": [10, 10], "name": "MEC1_WAIT_ON_RCIU_READ"},
12182    {"bits": [13, 13], "name": "MEC1_WAIT_ON_ROQ_DATA"},
12183    {"bits": [16, 16], "name": "MEC2_DECODING_PACKET"},
12184    {"bits": [17, 17], "name": "MEC2_WAIT_ON_RCIU"},
12185    {"bits": [18, 18], "name": "MEC2_WAIT_ON_RCIU_READ"},
12186    {"bits": [21, 21], "name": "MEC2_WAIT_ON_ROQ_DATA"},
12187    {"bits": [22, 22], "name": "UTCL2IU_WAITING_ON_FREE"},
12188    {"bits": [23, 23], "name": "UTCL2IU_WAITING_ON_TAGS"},
12189    {"bits": [24, 24], "name": "UTCL1_WAITING_ON_TRANS"},
12190    {"bits": [25, 25], "name": "GCRIU_WAITING_ON_FREE"}
12191   ]
12192  },
12193  "CP_CPC_STATUS": {
12194   "fields": [
12195    {"bits": [0, 0], "name": "MEC1_BUSY"},
12196    {"bits": [1, 1], "name": "MEC2_BUSY"},
12197    {"bits": [2, 2], "name": "DC0_BUSY"},
12198    {"bits": [3, 3], "name": "DC1_BUSY"},
12199    {"bits": [4, 4], "name": "RCIU1_BUSY"},
12200    {"bits": [5, 5], "name": "RCIU2_BUSY"},
12201    {"bits": [6, 6], "name": "ROQ1_BUSY"},
12202    {"bits": [7, 7], "name": "ROQ2_BUSY"},
12203    {"bits": [10, 10], "name": "TCIU_BUSY"},
12204    {"bits": [11, 11], "name": "SCRATCH_RAM_BUSY"},
12205    {"bits": [12, 12], "name": "QU_BUSY"},
12206    {"bits": [13, 13], "name": "UTCL2IU_BUSY"},
12207    {"bits": [14, 14], "name": "SAVE_RESTORE_BUSY"},
12208    {"bits": [15, 15], "name": "GCRIU_BUSY"},
12209    {"bits": [16, 16], "name": "MES_BUSY"},
12210    {"bits": [17, 17], "name": "MES_SCRATCH_RAM_BUSY"},
12211    {"bits": [18, 18], "name": "RCIU3_BUSY"},
12212    {"bits": [19, 19], "name": "MES_INSTRUCTION_CACHE_BUSY"},
12213    {"bits": [29, 29], "name": "CPG_CPC_BUSY"},
12214    {"bits": [30, 30], "name": "CPF_CPC_BUSY"},
12215    {"bits": [31, 31], "name": "CPC_BUSY"}
12216   ]
12217  },
12218  "CP_CPF_BUSY_STAT": {
12219   "fields": [
12220    {"bits": [0, 0], "name": "REG_BUS_FIFO_BUSY"},
12221    {"bits": [1, 1], "name": "CSF_RING_BUSY"},
12222    {"bits": [2, 2], "name": "CSF_INDIRECT1_BUSY"},
12223    {"bits": [3, 3], "name": "CSF_INDIRECT2_BUSY"},
12224    {"bits": [4, 4], "name": "CSF_STATE_BUSY"},
12225    {"bits": [5, 5], "name": "CSF_CE_INDR1_BUSY"},
12226    {"bits": [6, 6], "name": "CSF_CE_INDR2_BUSY"},
12227    {"bits": [7, 7], "name": "CSF_ARBITER_BUSY"},
12228    {"bits": [8, 8], "name": "CSF_INPUT_BUSY"},
12229    {"bits": [9, 9], "name": "CSF_DATA_BUSY"},
12230    {"bits": [10, 10], "name": "CSF_CE_DATA_BUSY"},
12231    {"bits": [11, 11], "name": "HPD_PROCESSING_EOP_BUSY"},
12232    {"bits": [12, 12], "name": "HQD_DISPATCH_BUSY"},
12233    {"bits": [13, 13], "name": "HQD_IQ_TIMER_BUSY"},
12234    {"bits": [14, 14], "name": "HQD_DMA_OFFLOAD_BUSY"},
12235    {"bits": [15, 15], "name": "HQD_WAIT_SEMAPHORE_BUSY"},
12236    {"bits": [16, 16], "name": "HQD_SIGNAL_SEMAPHORE_BUSY"},
12237    {"bits": [17, 17], "name": "HQD_MESSAGE_BUSY"},
12238    {"bits": [18, 18], "name": "HQD_PQ_FETCHER_BUSY"},
12239    {"bits": [19, 19], "name": "HQD_IB_FETCHER_BUSY"},
12240    {"bits": [20, 20], "name": "HQD_IQ_FETCHER_BUSY"},
12241    {"bits": [21, 21], "name": "HQD_EOP_FETCHER_BUSY"},
12242    {"bits": [22, 22], "name": "HQD_CONSUMED_RPTR_BUSY"},
12243    {"bits": [23, 23], "name": "HQD_FETCHER_ARB_BUSY"},
12244    {"bits": [24, 24], "name": "HQD_ROQ_ALIGN_BUSY"},
12245    {"bits": [25, 25], "name": "HQD_ROQ_EOP_BUSY"},
12246    {"bits": [26, 26], "name": "HQD_ROQ_IQ_BUSY"},
12247    {"bits": [27, 27], "name": "HQD_ROQ_PQ_BUSY"},
12248    {"bits": [28, 28], "name": "HQD_ROQ_IB_BUSY"},
12249    {"bits": [29, 29], "name": "HQD_WPTR_POLL_BUSY"},
12250    {"bits": [30, 30], "name": "HQD_PQ_BUSY"},
12251    {"bits": [31, 31], "name": "HQD_IB_BUSY"}
12252   ]
12253  },
12254  "CP_CPF_BUSY_STAT2": {
12255   "fields": [
12256    {"bits": [12, 12], "name": "MES_HQD_DISPATCH_BUSY"},
12257    {"bits": [14, 14], "name": "MES_HQD_DMA_OFFLOAD_BUSY"},
12258    {"bits": [17, 17], "name": "MES_HQD_MESSAGE_BUSY"},
12259    {"bits": [18, 18], "name": "MES_HQD_PQ_FETCHER_BUSY"},
12260    {"bits": [22, 22], "name": "MES_HQD_CONSUMED_RPTR_BUSY"},
12261    {"bits": [23, 23], "name": "MES_HQD_FETCHER_ARB_BUSY"},
12262    {"bits": [24, 24], "name": "MES_HQD_ROQ_ALIGN_BUSY"},
12263    {"bits": [27, 27], "name": "MES_HQD_ROQ_PQ_BUSY"},
12264    {"bits": [30, 30], "name": "MES_HQD_PQ_BUSY"}
12265   ]
12266  },
12267  "CP_CPF_GRBM_FREE_COUNT": {
12268   "fields": [
12269    {"bits": [0, 2], "name": "FREE_COUNT"}
12270   ]
12271  },
12272  "CP_CPF_STALLED_STAT1": {
12273   "fields": [
12274    {"bits": [0, 0], "name": "RING_FETCHING_DATA"},
12275    {"bits": [1, 1], "name": "INDR1_FETCHING_DATA"},
12276    {"bits": [2, 2], "name": "INDR2_FETCHING_DATA"},
12277    {"bits": [3, 3], "name": "STATE_FETCHING_DATA"},
12278    {"bits": [5, 5], "name": "TCIU_WAITING_ON_FREE"},
12279    {"bits": [6, 6], "name": "TCIU_WAITING_ON_TAGS"},
12280    {"bits": [7, 7], "name": "UTCL2IU_WAITING_ON_FREE"},
12281    {"bits": [8, 8], "name": "UTCL2IU_WAITING_ON_TAGS"},
12282    {"bits": [9, 9], "name": "GFX_UTCL1_WAITING_ON_TRANS"},
12283    {"bits": [10, 10], "name": "CMP_UTCL1_WAITING_ON_TRANS"},
12284    {"bits": [11, 11], "name": "RCIU_WAITING_ON_FREE"},
12285    {"bits": [12, 12], "name": "DATA_FETCHING_DATA"},
12286    {"bits": [13, 13], "name": "GCRIU_WAIT_ON_FREE"}
12287   ]
12288  },
12289  "CP_CPF_STATUS": {
12290   "fields": [
12291    {"bits": [0, 0], "name": "POST_WPTR_GFX_BUSY"},
12292    {"bits": [1, 1], "name": "CSF_BUSY"},
12293    {"bits": [4, 4], "name": "ROQ_ALIGN_BUSY"},
12294    {"bits": [5, 5], "name": "ROQ_RING_BUSY"},
12295    {"bits": [6, 6], "name": "ROQ_INDIRECT1_BUSY"},
12296    {"bits": [7, 7], "name": "ROQ_INDIRECT2_BUSY"},
12297    {"bits": [8, 8], "name": "ROQ_STATE_BUSY"},
12298    {"bits": [9, 9], "name": "ROQ_CE_RING_BUSY"},
12299    {"bits": [10, 10], "name": "ROQ_CE_INDIRECT1_BUSY"},
12300    {"bits": [11, 11], "name": "ROQ_CE_INDIRECT2_BUSY"},
12301    {"bits": [12, 12], "name": "SEMAPHORE_BUSY"},
12302    {"bits": [13, 13], "name": "INTERRUPT_BUSY"},
12303    {"bits": [14, 14], "name": "TCIU_BUSY"},
12304    {"bits": [15, 15], "name": "HQD_BUSY"},
12305    {"bits": [16, 16], "name": "PRT_BUSY"},
12306    {"bits": [17, 17], "name": "UTCL2IU_BUSY"},
12307    {"bits": [18, 18], "name": "RCIU_BUSY"},
12308    {"bits": [19, 19], "name": "RCIU_GFX_BUSY"},
12309    {"bits": [20, 20], "name": "RCIU_CMP_BUSY"},
12310    {"bits": [21, 21], "name": "ROQ_DATA_BUSY"},
12311    {"bits": [22, 22], "name": "ROQ_CE_DATA_BUSY"},
12312    {"bits": [23, 23], "name": "GCRIU_BUSY"},
12313    {"bits": [24, 24], "name": "MES_HQD_BUSY"},
12314    {"bits": [26, 26], "name": "CPF_GFX_BUSY"},
12315    {"bits": [27, 27], "name": "CPF_CMP_BUSY"},
12316    {"bits": [28, 29], "name": "GRBM_CPF_STAT_BUSY"},
12317    {"bits": [30, 30], "name": "CPC_CPF_BUSY"},
12318    {"bits": [31, 31], "name": "CPF_BUSY"}
12319   ]
12320  },
12321  "CP_DB_BASE_HI": {
12322   "fields": [
12323    {"bits": [0, 15], "name": "DB_BASE_HI"}
12324   ]
12325  },
12326  "CP_DB_BASE_LO": {
12327   "fields": [
12328    {"bits": [2, 31], "name": "DB_BASE_LO"}
12329   ]
12330  },
12331  "CP_DB_BUFSZ": {
12332   "fields": [
12333    {"bits": [0, 19], "name": "DB_BUFSZ"}
12334   ]
12335  },
12336  "CP_DB_CMD_BUFSZ": {
12337   "fields": [
12338    {"bits": [0, 19], "name": "DB_CMD_REQSZ"}
12339   ]
12340  },
12341  "CP_DMA_CNTL": {
12342   "fields": [
12343    {"bits": [0, 0], "name": "UTCL1_FAULT_CONTROL"},
12344    {"bits": [1, 1], "name": "WATCH_CONTROL"},
12345    {"bits": [4, 5], "name": "MIN_AVAILSZ"},
12346    {"bits": [16, 24], "name": "BUFFER_DEPTH"},
12347    {"bits": [28, 28], "name": "PIO_FIFO_EMPTY"},
12348    {"bits": [29, 29], "name": "PIO_FIFO_FULL"},
12349    {"bits": [30, 31], "name": "PIO_COUNT"}
12350   ]
12351  },
12352  "CP_DMA_ME_CMD_ADDR_HI": {
12353   "fields": [
12354    {"bits": [0, 15], "name": "ADDR_HI"},
12355    {"bits": [16, 31], "name": "RSVD"}
12356   ]
12357  },
12358  "CP_DMA_ME_CMD_ADDR_LO": {
12359   "fields": [
12360    {"bits": [0, 1], "name": "RSVD"},
12361    {"bits": [2, 31], "name": "ADDR_LO"}
12362   ]
12363  },
12364  "CP_DMA_ME_COMMAND": {
12365   "fields": [
12366    {"bits": [0, 25], "name": "BYTE_COUNT"},
12367    {"bits": [26, 26], "name": "SAS"},
12368    {"bits": [27, 27], "name": "DAS"},
12369    {"bits": [28, 28], "name": "SAIC"},
12370    {"bits": [29, 29], "name": "DAIC"},
12371    {"bits": [30, 30], "name": "RAW_WAIT"},
12372    {"bits": [31, 31], "name": "DIS_WC"}
12373   ]
12374  },
12375  "CP_DMA_ME_DST_ADDR_HI": {
12376   "fields": [
12377    {"bits": [0, 15], "name": "DST_ADDR_HI"}
12378   ]
12379  },
12380  "CP_DMA_ME_SRC_ADDR_HI": {
12381   "fields": [
12382    {"bits": [0, 15], "name": "SRC_ADDR_HI"}
12383   ]
12384  },
12385  "CP_DMA_PFP_CONTROL": {
12386   "fields": [
12387    {"bits": [10, 10], "name": "MEMLOG_CLEAR"},
12388    {"bits": [13, 14], "name": "SRC_CACHE_POLICY"},
12389    {"bits": [15, 15], "name": "SRC_VOLATLE"},
12390    {"bits": [20, 21], "name": "DST_SELECT"},
12391    {"bits": [25, 26], "name": "DST_CACHE_POLICY"},
12392    {"bits": [27, 27], "name": "DST_VOLATLE"},
12393    {"bits": [29, 30], "name": "SRC_SELECT"}
12394   ]
12395  },
12396  "CP_DMA_READ_TAGS": {
12397   "fields": [
12398    {"bits": [0, 25], "name": "DMA_READ_TAG"},
12399    {"bits": [28, 28], "name": "DMA_READ_TAG_VALID"}
12400   ]
12401  },
12402  "CP_DRAW_WINDOW_CNTL": {
12403   "fields": [
12404    {"bits": [0, 0], "name": "DISABLE_DRAW_WINDOW_LO_MAX"},
12405    {"bits": [1, 1], "name": "DISABLE_DRAW_WINDOW_LO_MIN"},
12406    {"bits": [2, 2], "name": "DISABLE_DRAW_WINDOW_HI"},
12407    {"bits": [8, 8], "name": "MODE"}
12408   ]
12409  },
12410  "CP_DRAW_WINDOW_LO": {
12411   "fields": [
12412    {"bits": [0, 15], "name": "MIN"},
12413    {"bits": [16, 31], "name": "MAX"}
12414   ]
12415  },
12416  "CP_EOP_DONE_ADDR_HI": {
12417   "fields": [
12418    {"bits": [0, 15], "name": "ADDR_HI"}
12419   ]
12420  },
12421  "CP_EOP_DONE_ADDR_LO": {
12422   "fields": [
12423    {"bits": [2, 31], "name": "ADDR_LO"}
12424   ]
12425  },
12426  "CP_EOP_DONE_DATA_CNTL": {
12427   "fields": [
12428    {"bits": [16, 17], "name": "DST_SEL"},
12429    {"bits": [24, 26], "name": "INT_SEL"},
12430    {"bits": [29, 31], "name": "DATA_SEL"}
12431   ]
12432  },
12433  "CP_EOP_DONE_DOORBELL": {
12434   "fields": [
12435    {"bits": [2, 27], "name": "DOORBELL_OFFSET"}
12436   ]
12437  },
12438  "CP_EOP_DONE_EVENT_CNTL": {
12439   "fields": [
12440    {"bits": [12, 23], "name": "GCR_CNTL"},
12441    {"bits": [25, 26], "name": "CACHE_POLICY"},
12442    {"bits": [27, 27], "name": "EOP_VOLATILE"},
12443    {"bits": [28, 28], "name": "EXECUTE"}
12444   ]
12445  },
12446  "CP_IB1_OFFSET": {
12447   "fields": [
12448    {"bits": [0, 19], "name": "IB1_OFFSET"}
12449   ]
12450  },
12451  "CP_IB1_PREAMBLE_BEGIN": {
12452   "fields": [
12453    {"bits": [0, 19], "name": "IB1_PREAMBLE_BEGIN"}
12454   ]
12455  },
12456  "CP_IB1_PREAMBLE_END": {
12457   "fields": [
12458    {"bits": [0, 19], "name": "IB1_PREAMBLE_END"}
12459   ]
12460  },
12461  "CP_IB2_OFFSET": {
12462   "fields": [
12463    {"bits": [0, 19], "name": "IB2_OFFSET"}
12464   ]
12465  },
12466  "CP_IB2_PREAMBLE_BEGIN": {
12467   "fields": [
12468    {"bits": [0, 19], "name": "IB2_PREAMBLE_BEGIN"}
12469   ]
12470  },
12471  "CP_IB2_PREAMBLE_END": {
12472   "fields": [
12473    {"bits": [0, 19], "name": "IB2_PREAMBLE_END"}
12474   ]
12475  },
12476  "CP_INDEX_TYPE": {
12477   "fields": [
12478    {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}
12479   ]
12480  },
12481  "CP_ME_COHER_CNTL": {
12482   "fields": [
12483    {"bits": [0, 0], "name": "DEST_BASE_0_ENA"},
12484    {"bits": [1, 1], "name": "DEST_BASE_1_ENA"},
12485    {"bits": [6, 6], "name": "CB0_DEST_BASE_ENA"},
12486    {"bits": [7, 7], "name": "CB1_DEST_BASE_ENA"},
12487    {"bits": [8, 8], "name": "CB2_DEST_BASE_ENA"},
12488    {"bits": [9, 9], "name": "CB3_DEST_BASE_ENA"},
12489    {"bits": [10, 10], "name": "CB4_DEST_BASE_ENA"},
12490    {"bits": [11, 11], "name": "CB5_DEST_BASE_ENA"},
12491    {"bits": [12, 12], "name": "CB6_DEST_BASE_ENA"},
12492    {"bits": [13, 13], "name": "CB7_DEST_BASE_ENA"},
12493    {"bits": [14, 14], "name": "DB_DEST_BASE_ENA"},
12494    {"bits": [19, 19], "name": "DEST_BASE_2_ENA"},
12495    {"bits": [21, 21], "name": "DEST_BASE_3_ENA"}
12496   ]
12497  },
12498  "CP_ME_COHER_STATUS": {
12499   "fields": [
12500    {"bits": [0, 7], "name": "MATCHING_GFX_CNTX"},
12501    {"bits": [31, 31], "name": "STATUS"}
12502   ]
12503  },
12504  "CP_ME_MC_RADDR_HI": {
12505   "fields": [
12506    {"bits": [0, 15], "name": "ME_MC_RADDR_HI"},
12507    {"bits": [22, 23], "name": "CACHE_POLICY"}
12508   ]
12509  },
12510  "CP_ME_MC_RADDR_LO": {
12511   "fields": [
12512    {"bits": [2, 31], "name": "ME_MC_RADDR_LO"}
12513   ]
12514  },
12515  "CP_ME_MC_WADDR_HI": {
12516   "fields": [
12517    {"bits": [0, 15], "name": "ME_MC_WADDR_HI"},
12518    {"bits": [22, 23], "name": "CACHE_POLICY"}
12519   ]
12520  },
12521  "CP_ME_MC_WADDR_LO": {
12522   "fields": [
12523    {"bits": [2, 31], "name": "ME_MC_WADDR_LO"}
12524   ]
12525  },
12526  "CP_PERFMON_CNTL": {
12527   "fields": [
12528    {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"},
12529    {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"},
12530    {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"},
12531    {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"}
12532   ]
12533  },
12534  "CP_PERFMON_CNTX_CNTL": {
12535   "fields": [
12536    {"bits": [31, 31], "name": "PERFMON_ENABLE"}
12537   ]
12538  },
12539  "CP_PFP_COMPLETION_STATUS": {
12540   "fields": [
12541    {"bits": [0, 1], "name": "STATUS"}
12542   ]
12543  },
12544  "CP_PFP_IB_CONTROL": {
12545   "fields": [
12546    {"bits": [0, 7], "name": "IB_EN"}
12547   ]
12548  },
12549  "CP_PFP_LOAD_CONTROL": {
12550   "fields": [
12551    {"bits": [0, 0], "name": "CONFIG_REG_EN"},
12552    {"bits": [1, 1], "name": "CNTX_REG_EN"},
12553    {"bits": [16, 16], "name": "SH_GFX_REG_EN"},
12554    {"bits": [24, 24], "name": "SH_CS_REG_EN"}
12555   ]
12556  },
12557  "CP_PIPEID": {
12558   "fields": [
12559    {"bits": [0, 1], "name": "PIPE_ID"}
12560   ]
12561  },
12562  "CP_PIPE_STATS_ADDR_HI": {
12563   "fields": [
12564    {"bits": [0, 15], "name": "PIPE_STATS_ADDR_HI"}
12565   ]
12566  },
12567  "CP_PIPE_STATS_ADDR_LO": {
12568   "fields": [
12569    {"bits": [2, 31], "name": "PIPE_STATS_ADDR_LO"}
12570   ]
12571  },
12572  "CP_PIPE_STATS_CONTROL": {
12573   "fields": [
12574    {"bits": [25, 26], "name": "CACHE_POLICY"}
12575   ]
12576  },
12577  "CP_PRED_NOT_VISIBLE": {
12578   "fields": [
12579    {"bits": [0, 0], "name": "NOT_VISIBLE"}
12580   ]
12581  },
12582  "CP_RB_OFFSET": {
12583   "fields": [
12584    {"bits": [0, 19], "name": "RB_OFFSET"}
12585   ]
12586  },
12587  "CP_SAMPLE_STATUS": {
12588   "fields": [
12589    {"bits": [0, 0], "name": "Z_PASS_ACITVE"},
12590    {"bits": [1, 1], "name": "STREAMOUT_ACTIVE"},
12591    {"bits": [2, 2], "name": "PIPELINE_ACTIVE"},
12592    {"bits": [3, 3], "name": "STIPPLE_ACTIVE"},
12593    {"bits": [4, 4], "name": "VGT_BUFFERS_ACTIVE"},
12594    {"bits": [5, 5], "name": "SCREEN_EXT_ACTIVE"},
12595    {"bits": [6, 6], "name": "DRAW_INDIRECT_ACTIVE"},
12596    {"bits": [7, 7], "name": "DISP_INDIRECT_ACTIVE"}
12597   ]
12598  },
12599  "CP_SCRATCH_INDEX": {
12600   "fields": [
12601    {"bits": [0, 7], "name": "SCRATCH_INDEX"},
12602    {"bits": [31, 31], "name": "SCRATCH_INDEX_64BIT_MODE"}
12603   ]
12604  },
12605  "CP_SIG_SEM_ADDR_HI": {
12606   "fields": [
12607    {"bits": [0, 15], "name": "SEM_ADDR_HI"},
12608    {"bits": [16, 16], "name": "SEM_USE_MAILBOX"},
12609    {"bits": [20, 20], "name": "SEM_SIGNAL_TYPE"},
12610    {"bits": [24, 25], "name": "SEM_CLIENT_CODE"},
12611    {"bits": [29, 31], "name": "SEM_SELECT"}
12612   ]
12613  },
12614  "CP_SIG_SEM_ADDR_LO": {
12615   "fields": [
12616    {"bits": [0, 1], "name": "SEM_ADDR_SWAP"},
12617    {"bits": [3, 31], "name": "SEM_ADDR_LO"}
12618   ]
12619  },
12620  "CP_STREAM_OUT_ADDR_HI": {
12621   "fields": [
12622    {"bits": [0, 15], "name": "STREAM_OUT_ADDR_HI"}
12623   ]
12624  },
12625  "CP_STREAM_OUT_ADDR_LO": {
12626   "fields": [
12627    {"bits": [2, 31], "name": "STREAM_OUT_ADDR_LO"}
12628   ]
12629  },
12630  "CP_STRMOUT_CNTL": {
12631   "fields": [
12632    {"bits": [0, 0], "name": "OFFSET_UPDATE_DONE"}
12633   ]
12634  },
12635  "CP_ST_BASE_HI": {
12636   "fields": [
12637    {"bits": [0, 15], "name": "ST_BASE_HI"}
12638   ]
12639  },
12640  "CP_ST_BASE_LO": {
12641   "fields": [
12642    {"bits": [2, 31], "name": "ST_BASE_LO"}
12643   ]
12644  },
12645  "CP_ST_BUFSZ": {
12646   "fields": [
12647    {"bits": [0, 19], "name": "ST_BUFSZ"}
12648   ]
12649  },
12650  "CP_ST_CMD_BUFSZ": {
12651   "fields": [
12652    {"bits": [0, 19], "name": "ST_CMD_REQSZ"}
12653   ]
12654  },
12655  "CP_VMID": {
12656   "fields": [
12657    {"bits": [0, 3], "name": "VMID"}
12658   ]
12659  },
12660  "CS_COPY_STATE": {
12661   "fields": [
12662    {"bits": [0, 2], "name": "SRC_STATE_ID"}
12663   ]
12664  },
12665  "DB_ALPHA_TO_MASK": {
12666   "fields": [
12667    {"bits": [0, 0], "name": "ALPHA_TO_MASK_ENABLE"},
12668    {"bits": [8, 9], "name": "ALPHA_TO_MASK_OFFSET0"},
12669    {"bits": [10, 11], "name": "ALPHA_TO_MASK_OFFSET1"},
12670    {"bits": [12, 13], "name": "ALPHA_TO_MASK_OFFSET2"},
12671    {"bits": [14, 15], "name": "ALPHA_TO_MASK_OFFSET3"},
12672    {"bits": [16, 16], "name": "OFFSET_ROUND"}
12673   ]
12674  },
12675  "DB_COUNT_CONTROL": {
12676   "fields": [
12677    {"bits": [0, 0], "name": "ZPASS_INCREMENT_DISABLE"},
12678    {"bits": [1, 1], "name": "PERFECT_ZPASS_COUNTS"},
12679    {"bits": [2, 2], "name": "DISABLE_CONSERVATIVE_ZPASS_COUNTS"},
12680    {"bits": [3, 3], "name": "ENHANCED_CONSERVATIVE_ZPASS_COUNTS"},
12681    {"bits": [4, 6], "name": "SAMPLE_RATE"},
12682    {"bits": [8, 11], "name": "ZPASS_ENABLE"},
12683    {"bits": [12, 15], "name": "ZFAIL_ENABLE"},
12684    {"bits": [16, 19], "name": "SFAIL_ENABLE"},
12685    {"bits": [20, 23], "name": "DBFAIL_ENABLE"},
12686    {"bits": [24, 27], "name": "SLICE_EVEN_ENABLE"},
12687    {"bits": [28, 31], "name": "SLICE_ODD_ENABLE"}
12688   ]
12689  },
12690  "DB_DEPTH_CONTROL": {
12691   "fields": [
12692    {"bits": [0, 0], "name": "STENCIL_ENABLE"},
12693    {"bits": [1, 1], "name": "Z_ENABLE"},
12694    {"bits": [2, 2], "name": "Z_WRITE_ENABLE"},
12695    {"bits": [3, 3], "name": "DEPTH_BOUNDS_ENABLE"},
12696    {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"},
12697    {"bits": [7, 7], "name": "BACKFACE_ENABLE"},
12698    {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"},
12699    {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"},
12700    {"bits": [30, 30], "name": "ENABLE_COLOR_WRITES_ON_DEPTH_FAIL"},
12701    {"bits": [31, 31], "name": "DISABLE_COLOR_WRITES_ON_DEPTH_PASS"}
12702   ]
12703  },
12704  "DB_DEPTH_SIZE_XY": {
12705   "fields": [
12706    {"bits": [0, 13], "name": "X_MAX"},
12707    {"bits": [16, 29], "name": "Y_MAX"}
12708   ]
12709  },
12710  "DB_DEPTH_VIEW": {
12711   "fields": [
12712    {"bits": [0, 10], "name": "SLICE_START"},
12713    {"bits": [11, 12], "name": "SLICE_START_HI"},
12714    {"bits": [13, 23], "name": "SLICE_MAX"},
12715    {"bits": [24, 24], "name": "Z_READ_ONLY"},
12716    {"bits": [25, 25], "name": "STENCIL_READ_ONLY"},
12717    {"bits": [26, 29], "name": "MIPID"},
12718    {"bits": [30, 31], "name": "SLICE_MAX_HI"}
12719   ]
12720  },
12721  "DB_DFSM_CONTROL": {
12722   "fields": [
12723    {"bits": [0, 1], "enum_ref": "DB_DFSM_CONTROL__PUNCHOUT_MODE", "name": "PUNCHOUT_MODE"},
12724    {"bits": [2, 2], "name": "POPS_DRAIN_PS_ON_OVERLAP"},
12725    {"bits": [3, 3], "name": "DISALLOW_OVERFLOW"}
12726   ]
12727  },
12728  "DB_EQAA": {
12729   "fields": [
12730    {"bits": [0, 2], "name": "MAX_ANCHOR_SAMPLES"},
12731    {"bits": [4, 6], "name": "PS_ITER_SAMPLES"},
12732    {"bits": [8, 10], "name": "MASK_EXPORT_NUM_SAMPLES"},
12733    {"bits": [12, 14], "name": "ALPHA_TO_MASK_NUM_SAMPLES"},
12734    {"bits": [16, 16], "name": "HIGH_QUALITY_INTERSECTIONS"},
12735    {"bits": [17, 17], "name": "INCOHERENT_EQAA_READS"},
12736    {"bits": [18, 18], "name": "INTERPOLATE_COMP_Z"},
12737    {"bits": [19, 19], "name": "INTERPOLATE_SRC_Z"},
12738    {"bits": [20, 20], "name": "STATIC_ANCHOR_ASSOCIATIONS"},
12739    {"bits": [21, 21], "name": "ALPHA_TO_MASK_EQAA_DISABLE"},
12740    {"bits": [24, 26], "name": "OVERRASTERIZATION_AMOUNT"},
12741    {"bits": [27, 27], "name": "ENABLE_POSTZ_OVERRASTERIZATION"}
12742   ]
12743  },
12744  "DB_HTILE_SURFACE": {
12745   "fields": [
12746    {"bits": [0, 0], "name": "RESERVED_FIELD_1"},
12747    {"bits": [1, 1], "name": "FULL_CACHE"},
12748    {"bits": [2, 2], "name": "RESERVED_FIELD_2"},
12749    {"bits": [3, 3], "name": "RESERVED_FIELD_3"},
12750    {"bits": [4, 9], "name": "RESERVED_FIELD_4"},
12751    {"bits": [10, 15], "name": "RESERVED_FIELD_5"},
12752    {"bits": [16, 16], "name": "DST_OUTSIDE_ZERO_TO_ONE"},
12753    {"bits": [17, 17], "name": "RESERVED_FIELD_6"},
12754    {"bits": [18, 18], "name": "PIPE_ALIGNED"}
12755   ]
12756  },
12757  "DB_OCCLUSION_COUNT0_HI": {
12758   "fields": [
12759    {"bits": [0, 30], "name": "COUNT_HI"}
12760   ]
12761  },
12762  "DB_PRELOAD_CONTROL": {
12763   "fields": [
12764    {"bits": [0, 7], "name": "START_X"},
12765    {"bits": [8, 15], "name": "START_Y"},
12766    {"bits": [16, 23], "name": "MAX_X"},
12767    {"bits": [24, 31], "name": "MAX_Y"}
12768   ]
12769  },
12770  "DB_RENDER_CONTROL": {
12771   "fields": [
12772    {"bits": [0, 0], "name": "DEPTH_CLEAR_ENABLE"},
12773    {"bits": [1, 1], "name": "STENCIL_CLEAR_ENABLE"},
12774    {"bits": [2, 2], "name": "DEPTH_COPY"},
12775    {"bits": [3, 3], "name": "STENCIL_COPY"},
12776    {"bits": [4, 4], "name": "RESUMMARIZE_ENABLE"},
12777    {"bits": [5, 5], "name": "STENCIL_COMPRESS_DISABLE"},
12778    {"bits": [6, 6], "name": "DEPTH_COMPRESS_DISABLE"},
12779    {"bits": [7, 7], "name": "COPY_CENTROID"},
12780    {"bits": [8, 11], "name": "COPY_SAMPLE"},
12781    {"bits": [12, 12], "name": "DECOMPRESS_ENABLE"}
12782   ]
12783  },
12784  "DB_RENDER_OVERRIDE": {
12785   "fields": [
12786    {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"},
12787    {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"},
12788    {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"},
12789    {"bits": [6, 6], "name": "FORCE_SHADER_Z_ORDER"},
12790    {"bits": [7, 7], "name": "FAST_Z_DISABLE"},
12791    {"bits": [8, 8], "name": "FAST_STENCIL_DISABLE"},
12792    {"bits": [9, 9], "name": "NOOP_CULL_DISABLE"},
12793    {"bits": [10, 10], "name": "FORCE_COLOR_KILL"},
12794    {"bits": [11, 11], "name": "FORCE_Z_READ"},
12795    {"bits": [12, 12], "name": "FORCE_STENCIL_READ"},
12796    {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"},
12797    {"bits": [15, 15], "name": "FORCE_QC_SMASK_CONFLICT"},
12798    {"bits": [16, 16], "name": "DISABLE_VIEWPORT_CLAMP"},
12799    {"bits": [17, 17], "name": "IGNORE_SC_ZRANGE"},
12800    {"bits": [18, 18], "name": "DISABLE_FULLY_COVERED"},
12801    {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"},
12802    {"bits": [21, 25], "name": "MAX_TILES_IN_DTT"},
12803    {"bits": [26, 26], "name": "DISABLE_TILE_RATE_TILES"},
12804    {"bits": [27, 27], "name": "FORCE_Z_DIRTY"},
12805    {"bits": [28, 28], "name": "FORCE_STENCIL_DIRTY"},
12806    {"bits": [29, 29], "name": "FORCE_Z_VALID"},
12807    {"bits": [30, 30], "name": "FORCE_STENCIL_VALID"},
12808    {"bits": [31, 31], "name": "PRESERVE_COMPRESSION"}
12809   ]
12810  },
12811  "DB_RENDER_OVERRIDE2": {
12812   "fields": [
12813    {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"},
12814    {"bits": [2, 4], "name": "PARTIAL_SQUAD_LAUNCH_COUNTDOWN"},
12815    {"bits": [5, 5], "name": "DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION"},
12816    {"bits": [6, 6], "name": "DISABLE_SMEM_EXPCLEAR_OPTIMIZATION"},
12817    {"bits": [7, 7], "name": "DISABLE_COLOR_ON_VALIDATION"},
12818    {"bits": [8, 8], "name": "DECOMPRESS_Z_ON_FLUSH"},
12819    {"bits": [9, 9], "name": "DISABLE_REG_SNOOP"},
12820    {"bits": [10, 10], "name": "DEPTH_BOUNDS_HIER_DEPTH_DISABLE"},
12821    {"bits": [11, 11], "name": "SEPARATE_HIZS_FUNC_ENABLE"},
12822    {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"},
12823    {"bits": [15, 17], "name": "HIS_SFUNC_FF"},
12824    {"bits": [18, 20], "name": "HIS_SFUNC_BF"},
12825    {"bits": [21, 21], "name": "PRESERVE_ZRANGE"},
12826    {"bits": [22, 22], "name": "PRESERVE_SRESULTS"},
12827    {"bits": [23, 23], "name": "DISABLE_FAST_PASS"},
12828    {"bits": [25, 25], "name": "ALLOW_PARTIAL_RES_HIER_KILL"}
12829   ]
12830  },
12831  "DB_RESERVED_REG_1": {
12832   "fields": [
12833    {"bits": [0, 10], "name": "FIELD_1"},
12834    {"bits": [11, 21], "name": "FIELD_2"}
12835   ]
12836  },
12837  "DB_RESERVED_REG_2": {
12838   "fields": [
12839    {"bits": [0, 3], "name": "FIELD_1"},
12840    {"bits": [4, 7], "name": "FIELD_2"},
12841    {"bits": [8, 12], "name": "FIELD_3"},
12842    {"bits": [13, 14], "name": "FIELD_4"},
12843    {"bits": [15, 16], "name": "FIELD_5"},
12844    {"bits": [17, 18], "name": "FIELD_6"},
12845    {"bits": [19, 20], "name": "FIELD_7"},
12846    {"bits": [28, 31], "name": "RESOURCE_LEVEL"}
12847   ]
12848  },
12849  "DB_RESERVED_REG_3": {
12850   "fields": [
12851    {"bits": [0, 21], "name": "FIELD_1"}
12852   ]
12853  },
12854  "DB_RMI_L2_CACHE_CONTROL": {
12855   "fields": [
12856    {"bits": [0, 1], "enum_ref": "WritePolicy", "name": "Z_WR_POLICY"},
12857    {"bits": [2, 3], "enum_ref": "WritePolicy", "name": "S_WR_POLICY"},
12858    {"bits": [4, 5], "enum_ref": "WritePolicy", "name": "HTILE_WR_POLICY"},
12859    {"bits": [6, 7], "enum_ref": "WritePolicy", "name": "ZPCPSD_WR_POLICY"},
12860    {"bits": [16, 17], "enum_ref": "ReadPolicy", "name": "Z_RD_POLICY"},
12861    {"bits": [18, 19], "enum_ref": "ReadPolicy", "name": "S_RD_POLICY"},
12862    {"bits": [20, 21], "enum_ref": "ReadPolicy", "name": "HTILE_RD_POLICY"},
12863    {"bits": [24, 24], "name": "Z_BIG_PAGE"},
12864    {"bits": [25, 25], "name": "S_BIG_PAGE"}
12865   ]
12866  },
12867  "DB_SHADER_CONTROL": {
12868   "fields": [
12869    {"bits": [0, 0], "name": "Z_EXPORT_ENABLE"},
12870    {"bits": [1, 1], "name": "STENCIL_TEST_VAL_EXPORT_ENABLE"},
12871    {"bits": [2, 2], "name": "STENCIL_OP_VAL_EXPORT_ENABLE"},
12872    {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"},
12873    {"bits": [6, 6], "name": "KILL_ENABLE"},
12874    {"bits": [7, 7], "name": "COVERAGE_TO_MASK_ENABLE"},
12875    {"bits": [8, 8], "name": "MASK_EXPORT_ENABLE"},
12876    {"bits": [9, 9], "name": "EXEC_ON_HIER_FAIL"},
12877    {"bits": [10, 10], "name": "EXEC_ON_NOOP"},
12878    {"bits": [11, 11], "name": "ALPHA_TO_MASK_DISABLE"},
12879    {"bits": [12, 12], "name": "DEPTH_BEFORE_SHADER"},
12880    {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"},
12881    {"bits": [15, 15], "name": "DUAL_QUAD_DISABLE"},
12882    {"bits": [16, 16], "name": "PRIMITIVE_ORDERED_PIXEL_SHADER"},
12883    {"bits": [17, 17], "name": "EXEC_IF_OVERLAPPED"},
12884    {"bits": [20, 22], "name": "POPS_OVERLAP_NUM_SAMPLES"},
12885    {"bits": [23, 23], "name": "PRE_SHADER_DEPTH_COVERAGE_ENABLE"}
12886   ]
12887  },
12888  "DB_SRESULTS_COMPARE_STATE0": {
12889   "fields": [
12890    {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"},
12891    {"bits": [4, 11], "name": "COMPAREVALUE0"},
12892    {"bits": [12, 19], "name": "COMPAREMASK0"},
12893    {"bits": [24, 24], "name": "ENABLE0"}
12894   ]
12895  },
12896  "DB_SRESULTS_COMPARE_STATE1": {
12897   "fields": [
12898    {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"},
12899    {"bits": [4, 11], "name": "COMPAREVALUE1"},
12900    {"bits": [12, 19], "name": "COMPAREMASK1"},
12901    {"bits": [24, 24], "name": "ENABLE1"}
12902   ]
12903  },
12904  "DB_STENCILREFMASK": {
12905   "fields": [
12906    {"bits": [0, 7], "name": "STENCILTESTVAL"},
12907    {"bits": [8, 15], "name": "STENCILMASK"},
12908    {"bits": [16, 23], "name": "STENCILWRITEMASK"},
12909    {"bits": [24, 31], "name": "STENCILOPVAL"}
12910   ]
12911  },
12912  "DB_STENCILREFMASK_BF": {
12913   "fields": [
12914    {"bits": [0, 7], "name": "STENCILTESTVAL_BF"},
12915    {"bits": [8, 15], "name": "STENCILMASK_BF"},
12916    {"bits": [16, 23], "name": "STENCILWRITEMASK_BF"},
12917    {"bits": [24, 31], "name": "STENCILOPVAL_BF"}
12918   ]
12919  },
12920  "DB_STENCIL_CLEAR": {
12921   "fields": [
12922    {"bits": [0, 7], "name": "CLEAR"}
12923   ]
12924  },
12925  "DB_STENCIL_CONTROL": {
12926   "fields": [
12927    {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"},
12928    {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"},
12929    {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"},
12930    {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"},
12931    {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"},
12932    {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"}
12933   ]
12934  },
12935  "DB_STENCIL_INFO": {
12936   "fields": [
12937    {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"},
12938    {"bits": [4, 8], "name": "SW_MODE"},
12939    {"bits": [9, 10], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"},
12940    {"bits": [11, 11], "name": "ITERATE_FLUSH"},
12941    {"bits": [12, 12], "name": "PARTIALLY_RESIDENT"},
12942    {"bits": [13, 15], "name": "RESERVED_FIELD_1"},
12943    {"bits": [20, 20], "name": "ITERATE_256"},
12944    {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"},
12945    {"bits": [29, 29], "name": "TILE_STENCIL_DISABLE"}
12946   ]
12947  },
12948  "DB_Z_INFO": {
12949   "fields": [
12950    {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"},
12951    {"bits": [2, 3], "name": "NUM_SAMPLES"},
12952    {"bits": [4, 8], "name": "SW_MODE"},
12953    {"bits": [9, 10], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"},
12954    {"bits": [11, 11], "name": "ITERATE_FLUSH"},
12955    {"bits": [12, 12], "name": "PARTIALLY_RESIDENT"},
12956    {"bits": [13, 15], "name": "RESERVED_FIELD_1"},
12957    {"bits": [16, 19], "name": "MAXMIP"},
12958    {"bits": [20, 20], "name": "ITERATE_256"},
12959    {"bits": [23, 26], "name": "DECOMPRESS_ON_N_ZPLANES"},
12960    {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"},
12961    {"bits": [28, 28], "name": "READ_SIZE"},
12962    {"bits": [29, 29], "name": "TILE_SURFACE_ENABLE"},
12963    {"bits": [31, 31], "name": "ZRANGE_PRECISION"}
12964   ]
12965  },
12966  "DB_Z_READ_BASE_HI": {
12967   "fields": [
12968    {"bits": [0, 7], "name": "BASE_HI"}
12969   ]
12970  },
12971  "GB_ADDR_CONFIG": {
12972   "fields": [
12973    {"bits": [0, 2], "name": "NUM_PIPES"},
12974    {"bits": [3, 5], "name": "PIPE_INTERLEAVE_SIZE"},
12975    {"bits": [6, 7], "name": "MAX_COMPRESSED_FRAGS"},
12976    {"bits": [19, 20], "name": "NUM_SHADER_ENGINES"},
12977    {"bits": [26, 27], "name": "NUM_RB_PER_SE"}
12978   ]
12979  },
12980  "GB_MACROTILE_MODE0": {
12981   "fields": [
12982    {"bits": [0, 1], "enum_ref": "BankWidth", "name": "BANK_WIDTH"},
12983    {"bits": [2, 3], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"},
12984    {"bits": [4, 5], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"},
12985    {"bits": [6, 7], "enum_ref": "NumBanks", "name": "NUM_BANKS"}
12986   ]
12987  },
12988  "GB_TILE_MODE0": {
12989   "fields": [
12990    {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"},
12991    {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"},
12992    {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"},
12993    {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"},
12994    {"bits": [25, 26], "name": "SAMPLE_SPLIT"}
12995   ]
12996  },
12997  "GCEA_PERFCOUNTER2_MODE": {
12998   "fields": [
12999    {"bits": [0, 1], "name": "COMPARE_MODE0"},
13000    {"bits": [2, 3], "name": "COMPARE_MODE1"},
13001    {"bits": [4, 5], "name": "COMPARE_MODE2"},
13002    {"bits": [6, 7], "name": "COMPARE_MODE3"},
13003    {"bits": [8, 11], "name": "COMPARE_VALUE0"},
13004    {"bits": [12, 15], "name": "COMPARE_VALUE1"},
13005    {"bits": [16, 19], "name": "COMPARE_VALUE2"},
13006    {"bits": [20, 23], "name": "COMPARE_VALUE3"}
13007   ]
13008  },
13009  "GCR_PERFCOUNTER1_SELECT": {
13010   "fields": [
13011    {"bits": [0, 8], "name": "PERF_SEL"},
13012    {"bits": [24, 27], "name": "PERF_MODE"},
13013    {"bits": [28, 31], "name": "CNTL_MODE"}
13014   ]
13015  },
13016  "GC_ATC_L2_PERFCOUNTER0_CFG": {
13017   "fields": [
13018    {"bits": [0, 7], "name": "PERF_SEL"},
13019    {"bits": [8, 15], "name": "PERF_SEL_END"},
13020    {"bits": [24, 27], "name": "PERF_MODE"},
13021    {"bits": [28, 28], "name": "ENABLE"},
13022    {"bits": [29, 29], "name": "CLEAR"}
13023   ]
13024  },
13025  "GC_ATC_L2_PERFCOUNTER_HI": {
13026   "fields": [
13027    {"bits": [0, 15], "name": "COUNTER_HI"},
13028    {"bits": [16, 31], "name": "COMPARE_VALUE"}
13029   ]
13030  },
13031  "GC_ATC_L2_PERFCOUNTER_RSLT_CNTL": {
13032   "fields": [
13033    {"bits": [0, 3], "name": "PERF_COUNTER_SELECT"},
13034    {"bits": [8, 15], "name": "START_TRIGGER"},
13035    {"bits": [16, 23], "name": "STOP_TRIGGER"},
13036    {"bits": [24, 24], "name": "ENABLE_ANY"},
13037    {"bits": [25, 25], "name": "CLEAR_ALL"},
13038    {"bits": [26, 26], "name": "STOP_ALL_ON_SATURATE"}
13039   ]
13040  },
13041  "GDS_ATOM_BASE": {
13042   "fields": [
13043    {"bits": [0, 15], "name": "BASE"},
13044    {"bits": [16, 31], "name": "UNUSED"}
13045   ]
13046  },
13047  "GDS_ATOM_CNTL": {
13048   "fields": [
13049    {"bits": [0, 5], "name": "AINC"},
13050    {"bits": [6, 7], "name": "UNUSED1"},
13051    {"bits": [8, 9], "name": "DMODE"},
13052    {"bits": [10, 31], "name": "UNUSED2"}
13053   ]
13054  },
13055  "GDS_ATOM_COMPLETE": {
13056   "fields": [
13057    {"bits": [0, 0], "name": "COMPLETE"},
13058    {"bits": [1, 31], "name": "UNUSED"}
13059   ]
13060  },
13061  "GDS_ATOM_OFFSET0": {
13062   "fields": [
13063    {"bits": [0, 7], "name": "OFFSET0"},
13064    {"bits": [8, 31], "name": "UNUSED"}
13065   ]
13066  },
13067  "GDS_ATOM_OFFSET1": {
13068   "fields": [
13069    {"bits": [0, 7], "name": "OFFSET1"},
13070    {"bits": [8, 31], "name": "UNUSED"}
13071   ]
13072  },
13073  "GDS_ATOM_OP": {
13074   "fields": [
13075    {"bits": [0, 7], "name": "OP"},
13076    {"bits": [8, 31], "name": "UNUSED"}
13077   ]
13078  },
13079  "GDS_ATOM_SIZE": {
13080   "fields": [
13081    {"bits": [0, 15], "name": "SIZE"},
13082    {"bits": [16, 31], "name": "UNUSED"}
13083   ]
13084  },
13085  "GDS_GWS_RESOURCE": {
13086   "fields": [
13087    {"bits": [0, 0], "name": "FLAG"},
13088    {"bits": [1, 12], "name": "COUNTER"},
13089    {"bits": [13, 13], "name": "TYPE"},
13090    {"bits": [14, 14], "name": "DED"},
13091    {"bits": [15, 15], "name": "RELEASE_ALL"},
13092    {"bits": [16, 26], "name": "HEAD_QUEUE"},
13093    {"bits": [27, 27], "name": "HEAD_VALID"},
13094    {"bits": [28, 28], "name": "HEAD_FLAG"},
13095    {"bits": [29, 29], "name": "HALTED"},
13096    {"bits": [30, 31], "name": "UNUSED1"}
13097   ]
13098  },
13099  "GDS_GWS_RESOURCE_CNT": {
13100   "fields": [
13101    {"bits": [0, 15], "name": "RESOURCE_CNT"},
13102    {"bits": [16, 31], "name": "UNUSED"}
13103   ]
13104  },
13105  "GDS_GWS_RESOURCE_CNTL": {
13106   "fields": [
13107    {"bits": [0, 5], "name": "INDEX"},
13108    {"bits": [6, 31], "name": "UNUSED"}
13109   ]
13110  },
13111  "GDS_OA_ADDRESS": {
13112   "fields": [
13113    {"bits": [0, 15], "name": "DS_ADDRESS"},
13114    {"bits": [16, 19], "name": "CRAWLER_TYPE"},
13115    {"bits": [20, 23], "name": "CRAWLER"},
13116    {"bits": [24, 29], "name": "UNUSED"},
13117    {"bits": [30, 30], "name": "NO_ALLOC"},
13118    {"bits": [31, 31], "name": "ENABLE"}
13119   ]
13120  },
13121  "GDS_OA_CNTL": {
13122   "fields": [
13123    {"bits": [0, 3], "name": "INDEX"},
13124    {"bits": [4, 31], "name": "UNUSED"}
13125   ]
13126  },
13127  "GDS_OA_INCDEC": {
13128   "fields": [
13129    {"bits": [0, 30], "name": "VALUE"},
13130    {"bits": [31, 31], "name": "INCDEC"}
13131   ]
13132  },
13133  "GE_CNTL": {
13134   "fields": [
13135    {"bits": [0, 8], "name": "PRIM_GRP_SIZE"},
13136    {"bits": [9, 17], "name": "VERT_GRP_SIZE"},
13137    {"bits": [18, 18], "name": "BREAK_WAVE_AT_EOI"},
13138    {"bits": [19, 19], "name": "PACKET_TO_ONE_PA"}
13139   ]
13140  },
13141  "GE_MAX_OUTPUT_PER_SUBGROUP": {
13142   "fields": [
13143    {"bits": [0, 9], "name": "MAX_VERTS_PER_SUBGROUP"}
13144   ]
13145  },
13146  "GE_NGG_SUBGRP_CNTL": {
13147   "fields": [
13148    {"bits": [0, 8], "name": "PRIM_AMP_FACTOR"},
13149    {"bits": [9, 17], "name": "THDS_PER_SUBGRP"}
13150   ]
13151  },
13152  "GE_PC_ALLOC": {
13153   "fields": [
13154    {"bits": [0, 0], "name": "OVERSUB_EN"},
13155    {"bits": [1, 10], "name": "NUM_PC_LINES"}
13156   ]
13157  },
13158  "GE_PERFCOUNTER0_SELECT": {
13159   "fields": [
13160    {"bits": [0, 9], "name": "PERF_SEL0"},
13161    {"bits": [10, 19], "name": "PERF_SEL1"},
13162    {"bits": [20, 23], "name": "CNTR_MODE"},
13163    {"bits": [24, 27], "name": "PERF_MODE0"},
13164    {"bits": [28, 31], "name": "PERF_MODE1"}
13165   ]
13166  },
13167  "GE_PERFCOUNTER0_SELECT1": {
13168   "fields": [
13169    {"bits": [0, 9], "name": "PERF_SEL2"},
13170    {"bits": [10, 19], "name": "PERF_SEL3"},
13171    {"bits": [24, 27], "name": "PERF_MODE2"},
13172    {"bits": [28, 31], "name": "PERF_MODE3"}
13173   ]
13174  },
13175  "GE_PERFCOUNTER4_SELECT": {
13176   "fields": [
13177    {"bits": [0, 9], "name": "PERF_SEL0"},
13178    {"bits": [28, 31], "name": "PERF_MODE"}
13179   ]
13180  },
13181  "GE_STEREO_CNTL": {
13182   "fields": [
13183    {"bits": [0, 2], "name": "RT_SLICE"},
13184    {"bits": [3, 6], "name": "VIEWPORT"},
13185    {"bits": [8, 8], "name": "EN_STEREO"}
13186   ]
13187  },
13188  "GE_USER_VGPR_EN": {
13189   "fields": [
13190    {"bits": [0, 0], "name": "EN_USER_VGPR1"},
13191    {"bits": [1, 1], "name": "EN_USER_VGPR2"},
13192    {"bits": [2, 2], "name": "EN_USER_VGPR3"}
13193   ]
13194  },
13195  "GRBM_GFX_INDEX": {
13196   "fields": [
13197    {"bits": [0, 7], "name": "INSTANCE_INDEX"},
13198    {"bits": [8, 15], "name": "SA_INDEX"},
13199    {"bits": [16, 23], "name": "SE_INDEX"},
13200    {"bits": [29, 29], "name": "SA_BROADCAST_WRITES"},
13201    {"bits": [30, 30], "name": "INSTANCE_BROADCAST_WRITES"},
13202    {"bits": [31, 31], "name": "SE_BROADCAST_WRITES"}
13203   ]
13204  },
13205  "GRBM_PERFCOUNTER0_SELECT": {
13206   "fields": [
13207    {"bits": [0, 5], "name": "PERF_SEL"},
13208    {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"},
13209    {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"},
13210    {"bits": [13, 13], "name": "TA_BUSY_USER_DEFINED_MASK"},
13211    {"bits": [14, 14], "name": "SX_BUSY_USER_DEFINED_MASK"},
13212    {"bits": [16, 16], "name": "SPI_BUSY_USER_DEFINED_MASK"},
13213    {"bits": [17, 17], "name": "SC_BUSY_USER_DEFINED_MASK"},
13214    {"bits": [18, 18], "name": "PA_BUSY_USER_DEFINED_MASK"},
13215    {"bits": [19, 19], "name": "GRBM_BUSY_USER_DEFINED_MASK"},
13216    {"bits": [20, 20], "name": "DB_BUSY_USER_DEFINED_MASK"},
13217    {"bits": [21, 21], "name": "CB_BUSY_USER_DEFINED_MASK"},
13218    {"bits": [22, 22], "name": "CP_BUSY_USER_DEFINED_MASK"},
13219    {"bits": [24, 24], "name": "GDS_BUSY_USER_DEFINED_MASK"},
13220    {"bits": [25, 25], "name": "BCI_BUSY_USER_DEFINED_MASK"},
13221    {"bits": [26, 26], "name": "RLC_BUSY_USER_DEFINED_MASK"},
13222    {"bits": [27, 27], "name": "TCP_BUSY_USER_DEFINED_MASK"},
13223    {"bits": [28, 28], "name": "GE_BUSY_USER_DEFINED_MASK"},
13224    {"bits": [29, 29], "name": "UTCL2_BUSY_USER_DEFINED_MASK"},
13225    {"bits": [30, 30], "name": "EA_BUSY_USER_DEFINED_MASK"},
13226    {"bits": [31, 31], "name": "RMI_BUSY_USER_DEFINED_MASK"}
13227   ]
13228  },
13229  "GRBM_PERFCOUNTER0_SELECT_HI": {
13230   "fields": [
13231    {"bits": [1, 1], "name": "UTCL1_BUSY_USER_DEFINED_MASK"},
13232    {"bits": [2, 2], "name": "GL2CC_BUSY_USER_DEFINED_MASK"},
13233    {"bits": [3, 3], "name": "SDMA_BUSY_USER_DEFINED_MASK"},
13234    {"bits": [4, 4], "name": "CH_BUSY_USER_DEFINED_MASK"},
13235    {"bits": [5, 5], "name": "PH_BUSY_USER_DEFINED_MASK"},
13236    {"bits": [6, 6], "name": "PMM_BUSY_USER_DEFINED_MASK"},
13237    {"bits": [7, 7], "name": "GUS_BUSY_USER_DEFINED_MASK"},
13238    {"bits": [8, 8], "name": "GL1CC_BUSY_USER_DEFINED_MASK"}
13239   ]
13240  },
13241  "GRBM_SE0_PERFCOUNTER_SELECT": {
13242   "fields": [
13243    {"bits": [0, 5], "name": "PERF_SEL"},
13244    {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"},
13245    {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"},
13246    {"bits": [12, 12], "name": "TA_BUSY_USER_DEFINED_MASK"},
13247    {"bits": [13, 13], "name": "SX_BUSY_USER_DEFINED_MASK"},
13248    {"bits": [15, 15], "name": "SPI_BUSY_USER_DEFINED_MASK"},
13249    {"bits": [16, 16], "name": "SC_BUSY_USER_DEFINED_MASK"},
13250    {"bits": [17, 17], "name": "DB_BUSY_USER_DEFINED_MASK"},
13251    {"bits": [18, 18], "name": "CB_BUSY_USER_DEFINED_MASK"},
13252    {"bits": [20, 20], "name": "PA_BUSY_USER_DEFINED_MASK"},
13253    {"bits": [21, 21], "name": "BCI_BUSY_USER_DEFINED_MASK"},
13254    {"bits": [22, 22], "name": "RMI_BUSY_USER_DEFINED_MASK"},
13255    {"bits": [23, 23], "name": "UTCL1_BUSY_USER_DEFINED_MASK"},
13256    {"bits": [24, 24], "name": "TCP_BUSY_USER_DEFINED_MASK"},
13257    {"bits": [25, 25], "name": "GL1CC_BUSY_USER_DEFINED_MASK"}
13258   ]
13259  },
13260  "GRBM_STATUS": {
13261   "fields": [
13262    {"bits": [0, 3], "name": "ME0PIPE0_CMDFIFO_AVAIL"},
13263    {"bits": [5, 5], "name": "RSMU_RQ_PENDING"},
13264    {"bits": [7, 7], "name": "ME0PIPE0_CF_RQ_PENDING"},
13265    {"bits": [8, 8], "name": "ME0PIPE0_PF_RQ_PENDING"},
13266    {"bits": [9, 9], "name": "GDS_DMA_RQ_PENDING"},
13267    {"bits": [12, 12], "name": "DB_CLEAN"},
13268    {"bits": [13, 13], "name": "CB_CLEAN"},
13269    {"bits": [14, 14], "name": "TA_BUSY"},
13270    {"bits": [15, 15], "name": "GDS_BUSY"},
13271    {"bits": [16, 16], "name": "GE_BUSY_NO_DMA"},
13272    {"bits": [20, 20], "name": "SX_BUSY"},
13273    {"bits": [21, 21], "name": "GE_BUSY"},
13274    {"bits": [22, 22], "name": "SPI_BUSY"},
13275    {"bits": [23, 23], "name": "BCI_BUSY"},
13276    {"bits": [24, 24], "name": "SC_BUSY"},
13277    {"bits": [25, 25], "name": "PA_BUSY"},
13278    {"bits": [26, 26], "name": "DB_BUSY"},
13279    {"bits": [28, 28], "name": "CP_COHERENCY_BUSY"},
13280    {"bits": [29, 29], "name": "CP_BUSY"},
13281    {"bits": [30, 30], "name": "CB_BUSY"},
13282    {"bits": [31, 31], "name": "GUI_ACTIVE"}
13283   ]
13284  },
13285  "GRBM_STATUS2": {
13286   "fields": [
13287    {"bits": [0, 3], "name": "ME0PIPE1_CMDFIFO_AVAIL"},
13288    {"bits": [4, 4], "name": "ME0PIPE1_CF_RQ_PENDING"},
13289    {"bits": [5, 5], "name": "ME0PIPE1_PF_RQ_PENDING"},
13290    {"bits": [6, 6], "name": "ME1PIPE0_RQ_PENDING"},
13291    {"bits": [7, 7], "name": "ME1PIPE1_RQ_PENDING"},
13292    {"bits": [8, 8], "name": "ME1PIPE2_RQ_PENDING"},
13293    {"bits": [9, 9], "name": "ME1PIPE3_RQ_PENDING"},
13294    {"bits": [10, 10], "name": "ME2PIPE0_RQ_PENDING"},
13295    {"bits": [11, 11], "name": "ME2PIPE1_RQ_PENDING"},
13296    {"bits": [12, 12], "name": "ME2PIPE2_RQ_PENDING"},
13297    {"bits": [13, 13], "name": "ME2PIPE3_RQ_PENDING"},
13298    {"bits": [14, 14], "name": "RLC_RQ_PENDING"},
13299    {"bits": [15, 15], "name": "UTCL2_BUSY"},
13300    {"bits": [16, 16], "name": "EA_BUSY"},
13301    {"bits": [17, 17], "name": "RMI_BUSY"},
13302    {"bits": [18, 18], "name": "UTCL2_RQ_PENDING"},
13303    {"bits": [19, 19], "name": "CPF_RQ_PENDING"},
13304    {"bits": [20, 20], "name": "EA_LINK_BUSY"},
13305    {"bits": [21, 21], "name": "SDMA_BUSY"},
13306    {"bits": [22, 22], "name": "SDMA0_RQ_PENDING"},
13307    {"bits": [23, 23], "name": "SDMA1_RQ_PENDING"},
13308    {"bits": [24, 24], "name": "RLC_BUSY"},
13309    {"bits": [25, 25], "name": "TCP_BUSY"},
13310    {"bits": [28, 28], "name": "CPF_BUSY"},
13311    {"bits": [29, 29], "name": "CPC_BUSY"},
13312    {"bits": [30, 30], "name": "CPG_BUSY"},
13313    {"bits": [31, 31], "name": "CPAXI_BUSY"}
13314   ]
13315  },
13316  "GRBM_STATUS3": {
13317   "fields": [
13318    {"bits": [5, 5], "name": "GRBM_RLC_INTR_CREDIT_PENDING"},
13319    {"bits": [6, 6], "name": "GRBM_UTCL2_INTR_CREDIT_PENDING"},
13320    {"bits": [7, 7], "name": "GRBM_CPF_INTR_CREDIT_PENDING"},
13321    {"bits": [8, 8], "name": "MESPIPE0_RQ_PENDING"},
13322    {"bits": [9, 9], "name": "MESPIPE1_RQ_PENDING"},
13323    {"bits": [10, 10], "name": "MESPIPE2_RQ_PENDING"},
13324    {"bits": [11, 11], "name": "MESPIPE3_RQ_PENDING"},
13325    {"bits": [13, 13], "name": "PH_BUSY"},
13326    {"bits": [14, 14], "name": "CH_BUSY"},
13327    {"bits": [15, 15], "name": "GL2CC_BUSY"},
13328    {"bits": [16, 16], "name": "GL1CC_BUSY"},
13329    {"bits": [28, 28], "name": "GUS_LINK_BUSY"},
13330    {"bits": [29, 29], "name": "GUS_BUSY"},
13331    {"bits": [30, 30], "name": "UTCL1_BUSY"},
13332    {"bits": [31, 31], "name": "PMM_BUSY"}
13333   ]
13334  },
13335  "GRBM_STATUS_SE0": {
13336   "fields": [
13337    {"bits": [1, 1], "name": "DB_CLEAN"},
13338    {"bits": [2, 2], "name": "CB_CLEAN"},
13339    {"bits": [3, 3], "name": "UTCL1_BUSY"},
13340    {"bits": [4, 4], "name": "TCP_BUSY"},
13341    {"bits": [5, 5], "name": "GL1CC_BUSY"},
13342    {"bits": [21, 21], "name": "RMI_BUSY"},
13343    {"bits": [22, 22], "name": "BCI_BUSY"},
13344    {"bits": [24, 24], "name": "PA_BUSY"},
13345    {"bits": [25, 25], "name": "TA_BUSY"},
13346    {"bits": [26, 26], "name": "SX_BUSY"},
13347    {"bits": [27, 27], "name": "SPI_BUSY"},
13348    {"bits": [29, 29], "name": "SC_BUSY"},
13349    {"bits": [30, 30], "name": "DB_BUSY"},
13350    {"bits": [31, 31], "name": "CB_BUSY"}
13351   ]
13352  },
13353  "IA_MULTI_VGT_PARAM": {
13354   "fields": [
13355    {"bits": [0, 15], "name": "PRIMGROUP_SIZE"},
13356    {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"},
13357    {"bits": [17, 17], "name": "SWITCH_ON_EOP"},
13358    {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"},
13359    {"bits": [19, 19], "name": "SWITCH_ON_EOI"},
13360    {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"}
13361   ]
13362  },
13363  "IA_MULTI_VGT_PARAM_PIPED": {
13364   "fields": [
13365    {"bits": [0, 15], "name": "PRIMGROUP_SIZE"},
13366    {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"},
13367    {"bits": [17, 17], "name": "SWITCH_ON_EOP"},
13368    {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"},
13369    {"bits": [19, 19], "name": "SWITCH_ON_EOI"},
13370    {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"},
13371    {"bits": [21, 21], "name": "EN_INST_OPT_BASIC"},
13372    {"bits": [22, 22], "name": "EN_INST_OPT_ADV"},
13373    {"bits": [23, 23], "name": "HW_USE_ONLY"}
13374   ]
13375  },
13376  "PA_CL_CLIP_CNTL": {
13377   "fields": [
13378    {"bits": [0, 0], "name": "UCP_ENA_0"},
13379    {"bits": [1, 1], "name": "UCP_ENA_1"},
13380    {"bits": [2, 2], "name": "UCP_ENA_2"},
13381    {"bits": [3, 3], "name": "UCP_ENA_3"},
13382    {"bits": [4, 4], "name": "UCP_ENA_4"},
13383    {"bits": [5, 5], "name": "UCP_ENA_5"},
13384    {"bits": [13, 13], "name": "PS_UCP_Y_SCALE_NEG"},
13385    {"bits": [14, 15], "name": "PS_UCP_MODE"},
13386    {"bits": [16, 16], "name": "CLIP_DISABLE"},
13387    {"bits": [17, 17], "name": "UCP_CULL_ONLY_ENA"},
13388    {"bits": [18, 18], "name": "BOUNDARY_EDGE_FLAG_ENA"},
13389    {"bits": [19, 19], "name": "DX_CLIP_SPACE_DEF"},
13390    {"bits": [20, 20], "name": "DIS_CLIP_ERR_DETECT"},
13391    {"bits": [21, 21], "name": "VTX_KILL_OR"},
13392    {"bits": [22, 22], "name": "DX_RASTERIZATION_KILL"},
13393    {"bits": [24, 24], "name": "DX_LINEAR_ATTR_CLIP_ENA"},
13394    {"bits": [25, 25], "name": "VTE_VPORT_PROVOKE_DISABLE"},
13395    {"bits": [26, 26], "name": "ZCLIP_NEAR_DISABLE"},
13396    {"bits": [27, 27], "name": "ZCLIP_FAR_DISABLE"},
13397    {"bits": [28, 28], "name": "ZCLIP_PROG_NEAR_ENA"}
13398   ]
13399  },
13400  "PA_CL_NANINF_CNTL": {
13401   "fields": [
13402    {"bits": [0, 0], "name": "VTE_XY_INF_DISCARD"},
13403    {"bits": [1, 1], "name": "VTE_Z_INF_DISCARD"},
13404    {"bits": [2, 2], "name": "VTE_W_INF_DISCARD"},
13405    {"bits": [3, 3], "name": "VTE_0XNANINF_IS_0"},
13406    {"bits": [4, 4], "name": "VTE_XY_NAN_RETAIN"},
13407    {"bits": [5, 5], "name": "VTE_Z_NAN_RETAIN"},
13408    {"bits": [6, 6], "name": "VTE_W_NAN_RETAIN"},
13409    {"bits": [7, 7], "name": "VTE_W_RECIP_NAN_IS_0"},
13410    {"bits": [8, 8], "name": "VS_XY_NAN_TO_INF"},
13411    {"bits": [9, 9], "name": "VS_XY_INF_RETAIN"},
13412    {"bits": [10, 10], "name": "VS_Z_NAN_TO_INF"},
13413    {"bits": [11, 11], "name": "VS_Z_INF_RETAIN"},
13414    {"bits": [12, 12], "name": "VS_W_NAN_TO_INF"},
13415    {"bits": [13, 13], "name": "VS_W_INF_RETAIN"},
13416    {"bits": [14, 14], "name": "VS_CLIP_DIST_INF_DISCARD"},
13417    {"bits": [20, 20], "name": "VTE_NO_OUTPUT_NEG_0"}
13418   ]
13419  },
13420  "PA_CL_NGG_CNTL": {
13421   "fields": [
13422    {"bits": [0, 0], "name": "VERTEX_REUSE_OFF"},
13423    {"bits": [1, 1], "name": "INDEX_BUF_EDGE_FLAG_ENA"}
13424   ]
13425  },
13426  "PA_CL_OBJPRIM_ID_CNTL": {
13427   "fields": [
13428    {"bits": [0, 0], "name": "OBJ_ID_SEL"},
13429    {"bits": [1, 1], "name": "ADD_PIPED_PRIM_ID"}
13430   ]
13431  },
13432  "PA_CL_VS_OUT_CNTL": {
13433   "fields": [
13434    {"bits": [0, 0], "name": "CLIP_DIST_ENA_0"},
13435    {"bits": [1, 1], "name": "CLIP_DIST_ENA_1"},
13436    {"bits": [2, 2], "name": "CLIP_DIST_ENA_2"},
13437    {"bits": [3, 3], "name": "CLIP_DIST_ENA_3"},
13438    {"bits": [4, 4], "name": "CLIP_DIST_ENA_4"},
13439    {"bits": [5, 5], "name": "CLIP_DIST_ENA_5"},
13440    {"bits": [6, 6], "name": "CLIP_DIST_ENA_6"},
13441    {"bits": [7, 7], "name": "CLIP_DIST_ENA_7"},
13442    {"bits": [8, 8], "name": "CULL_DIST_ENA_0"},
13443    {"bits": [9, 9], "name": "CULL_DIST_ENA_1"},
13444    {"bits": [10, 10], "name": "CULL_DIST_ENA_2"},
13445    {"bits": [11, 11], "name": "CULL_DIST_ENA_3"},
13446    {"bits": [12, 12], "name": "CULL_DIST_ENA_4"},
13447    {"bits": [13, 13], "name": "CULL_DIST_ENA_5"},
13448    {"bits": [14, 14], "name": "CULL_DIST_ENA_6"},
13449    {"bits": [15, 15], "name": "CULL_DIST_ENA_7"},
13450    {"bits": [16, 16], "name": "USE_VTX_POINT_SIZE"},
13451    {"bits": [17, 17], "name": "USE_VTX_EDGE_FLAG"},
13452    {"bits": [18, 18], "name": "USE_VTX_RENDER_TARGET_INDX"},
13453    {"bits": [19, 19], "name": "USE_VTX_VIEWPORT_INDX"},
13454    {"bits": [20, 20], "name": "USE_VTX_KILL_FLAG"},
13455    {"bits": [21, 21], "name": "VS_OUT_MISC_VEC_ENA"},
13456    {"bits": [22, 22], "name": "VS_OUT_CCDIST0_VEC_ENA"},
13457    {"bits": [23, 23], "name": "VS_OUT_CCDIST1_VEC_ENA"},
13458    {"bits": [24, 24], "name": "VS_OUT_MISC_SIDE_BUS_ENA"},
13459    {"bits": [25, 25], "name": "USE_VTX_GS_CUT_FLAG"},
13460    {"bits": [26, 26], "name": "USE_VTX_SHD_OBJPRIM_ID"},
13461    {"bits": [27, 27], "name": "USE_VTX_LINE_WIDTH"}
13462   ]
13463  },
13464  "PA_CL_VTE_CNTL": {
13465   "fields": [
13466    {"bits": [0, 0], "name": "VPORT_X_SCALE_ENA"},
13467    {"bits": [1, 1], "name": "VPORT_X_OFFSET_ENA"},
13468    {"bits": [2, 2], "name": "VPORT_Y_SCALE_ENA"},
13469    {"bits": [3, 3], "name": "VPORT_Y_OFFSET_ENA"},
13470    {"bits": [4, 4], "name": "VPORT_Z_SCALE_ENA"},
13471    {"bits": [5, 5], "name": "VPORT_Z_OFFSET_ENA"},
13472    {"bits": [8, 8], "name": "VTX_XY_FMT"},
13473    {"bits": [9, 9], "name": "VTX_Z_FMT"},
13474    {"bits": [10, 10], "name": "VTX_W0_FMT"},
13475    {"bits": [11, 11], "name": "PERFCOUNTER_REF"}
13476   ]
13477  },
13478  "PA_SC_AA_CONFIG": {
13479   "fields": [
13480    {"bits": [0, 2], "name": "MSAA_NUM_SAMPLES"},
13481    {"bits": [4, 4], "name": "AA_MASK_CENTROID_DTMN"},
13482    {"bits": [13, 16], "name": "MAX_SAMPLE_DIST"},
13483    {"bits": [20, 22], "name": "MSAA_EXPOSED_SAMPLES"},
13484    {"bits": [24, 25], "name": "DETAIL_TO_EXPOSED_MODE"},
13485    {"bits": [26, 27], "enum_ref": "CovToShaderSel", "name": "COVERAGE_TO_SHADER_SELECT"}
13486   ]
13487  },
13488  "PA_SC_AA_MASK_X0Y0_X1Y0": {
13489   "fields": [
13490    {"bits": [0, 15], "name": "AA_MASK_X0Y0"},
13491    {"bits": [16, 31], "name": "AA_MASK_X1Y0"}
13492   ]
13493  },
13494  "PA_SC_AA_MASK_X0Y1_X1Y1": {
13495   "fields": [
13496    {"bits": [0, 15], "name": "AA_MASK_X0Y1"},
13497    {"bits": [16, 31], "name": "AA_MASK_X1Y1"}
13498   ]
13499  },
13500  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0": {
13501   "fields": [
13502    {"bits": [0, 3], "name": "S0_X"},
13503    {"bits": [4, 7], "name": "S0_Y"},
13504    {"bits": [8, 11], "name": "S1_X"},
13505    {"bits": [12, 15], "name": "S1_Y"},
13506    {"bits": [16, 19], "name": "S2_X"},
13507    {"bits": [20, 23], "name": "S2_Y"},
13508    {"bits": [24, 27], "name": "S3_X"},
13509    {"bits": [28, 31], "name": "S3_Y"}
13510   ]
13511  },
13512  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1": {
13513   "fields": [
13514    {"bits": [0, 3], "name": "S4_X"},
13515    {"bits": [4, 7], "name": "S4_Y"},
13516    {"bits": [8, 11], "name": "S5_X"},
13517    {"bits": [12, 15], "name": "S5_Y"},
13518    {"bits": [16, 19], "name": "S6_X"},
13519    {"bits": [20, 23], "name": "S6_Y"},
13520    {"bits": [24, 27], "name": "S7_X"},
13521    {"bits": [28, 31], "name": "S7_Y"}
13522   ]
13523  },
13524  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2": {
13525   "fields": [
13526    {"bits": [0, 3], "name": "S8_X"},
13527    {"bits": [4, 7], "name": "S8_Y"},
13528    {"bits": [8, 11], "name": "S9_X"},
13529    {"bits": [12, 15], "name": "S9_Y"},
13530    {"bits": [16, 19], "name": "S10_X"},
13531    {"bits": [20, 23], "name": "S10_Y"},
13532    {"bits": [24, 27], "name": "S11_X"},
13533    {"bits": [28, 31], "name": "S11_Y"}
13534   ]
13535  },
13536  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3": {
13537   "fields": [
13538    {"bits": [0, 3], "name": "S12_X"},
13539    {"bits": [4, 7], "name": "S12_Y"},
13540    {"bits": [8, 11], "name": "S13_X"},
13541    {"bits": [12, 15], "name": "S13_Y"},
13542    {"bits": [16, 19], "name": "S14_X"},
13543    {"bits": [20, 23], "name": "S14_Y"},
13544    {"bits": [24, 27], "name": "S15_X"},
13545    {"bits": [28, 31], "name": "S15_Y"}
13546   ]
13547  },
13548  "PA_SC_BINNER_CNTL_0": {
13549   "fields": [
13550    {"bits": [0, 1], "enum_ref": "BinningMode", "name": "BINNING_MODE"},
13551    {"bits": [2, 2], "name": "BIN_SIZE_X"},
13552    {"bits": [3, 3], "name": "BIN_SIZE_Y"},
13553    {"bits": [4, 6], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_X_EXTEND"},
13554    {"bits": [7, 9], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_Y_EXTEND"},
13555    {"bits": [10, 12], "name": "CONTEXT_STATES_PER_BIN"},
13556    {"bits": [13, 17], "name": "PERSISTENT_STATES_PER_BIN"},
13557    {"bits": [18, 18], "name": "DISABLE_START_OF_PRIM"},
13558    {"bits": [19, 26], "name": "FPOVS_PER_BATCH"},
13559    {"bits": [27, 27], "name": "OPTIMAL_BIN_SELECTION"},
13560    {"bits": [28, 28], "name": "FLUSH_ON_BINNING_TRANSITION"},
13561    {"bits": [29, 30], "enum_ref": "BinMapMode", "name": "BIN_MAPPING_MODE"}
13562   ]
13563  },
13564  "PA_SC_BINNER_CNTL_1": {
13565   "fields": [
13566    {"bits": [0, 15], "name": "MAX_ALLOC_COUNT"},
13567    {"bits": [16, 31], "name": "MAX_PRIM_PER_BATCH"}
13568   ]
13569  },
13570  "PA_SC_CENTROID_PRIORITY_0": {
13571   "fields": [
13572    {"bits": [0, 3], "name": "DISTANCE_0"},
13573    {"bits": [4, 7], "name": "DISTANCE_1"},
13574    {"bits": [8, 11], "name": "DISTANCE_2"},
13575    {"bits": [12, 15], "name": "DISTANCE_3"},
13576    {"bits": [16, 19], "name": "DISTANCE_4"},
13577    {"bits": [20, 23], "name": "DISTANCE_5"},
13578    {"bits": [24, 27], "name": "DISTANCE_6"},
13579    {"bits": [28, 31], "name": "DISTANCE_7"}
13580   ]
13581  },
13582  "PA_SC_CENTROID_PRIORITY_1": {
13583   "fields": [
13584    {"bits": [0, 3], "name": "DISTANCE_8"},
13585    {"bits": [4, 7], "name": "DISTANCE_9"},
13586    {"bits": [8, 11], "name": "DISTANCE_10"},
13587    {"bits": [12, 15], "name": "DISTANCE_11"},
13588    {"bits": [16, 19], "name": "DISTANCE_12"},
13589    {"bits": [20, 23], "name": "DISTANCE_13"},
13590    {"bits": [24, 27], "name": "DISTANCE_14"},
13591    {"bits": [28, 31], "name": "DISTANCE_15"}
13592   ]
13593  },
13594  "PA_SC_CLIPRECT_0_TL": {
13595   "fields": [
13596    {"bits": [0, 14], "name": "TL_X"},
13597    {"bits": [16, 30], "name": "TL_Y"}
13598   ]
13599  },
13600  "PA_SC_CLIPRECT_RULE": {
13601   "fields": [
13602    {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"}
13603   ]
13604  },
13605  "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL": {
13606   "fields": [
13607    {"bits": [0, 0], "name": "OVER_RAST_ENABLE"},
13608    {"bits": [1, 4], "name": "OVER_RAST_SAMPLE_SELECT"},
13609    {"bits": [5, 5], "name": "UNDER_RAST_ENABLE"},
13610    {"bits": [6, 9], "name": "UNDER_RAST_SAMPLE_SELECT"},
13611    {"bits": [10, 10], "name": "PBB_UNCERTAINTY_REGION_ENABLE"},
13612    {"bits": [11, 11], "name": "ZMM_TRI_EXTENT"},
13613    {"bits": [12, 12], "name": "ZMM_TRI_OFFSET"},
13614    {"bits": [13, 13], "name": "OVERRIDE_OVER_RAST_INNER_TO_NORMAL"},
13615    {"bits": [14, 14], "name": "OVERRIDE_UNDER_RAST_INNER_TO_NORMAL"},
13616    {"bits": [15, 15], "name": "DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE"},
13617    {"bits": [16, 17], "enum_ref": "ScUncertaintyRegionMode", "name": "UNCERTAINTY_REGION_MODE"},
13618    {"bits": [18, 18], "name": "OUTER_UNCERTAINTY_EDGERULE_OVERRIDE"},
13619    {"bits": [19, 19], "name": "INNER_UNCERTAINTY_EDGERULE_OVERRIDE"},
13620    {"bits": [20, 20], "name": "NULL_SQUAD_AA_MASK_ENABLE"},
13621    {"bits": [21, 21], "name": "COVERAGE_AA_MASK_ENABLE"},
13622    {"bits": [22, 22], "name": "PREZ_AA_MASK_ENABLE"},
13623    {"bits": [23, 23], "name": "POSTZ_AA_MASK_ENABLE"},
13624    {"bits": [24, 24], "name": "CENTROID_SAMPLE_OVERRIDE"},
13625    {"bits": [25, 26], "name": "UNCERTAINTY_REGION_MULT"},
13626    {"bits": [27, 28], "name": "UNCERTAINTY_REGION_PBB_MULT"}
13627   ]
13628  },
13629  "PA_SC_EDGERULE": {
13630   "fields": [
13631    {"bits": [0, 3], "name": "ER_TRI"},
13632    {"bits": [4, 7], "name": "ER_POINT"},
13633    {"bits": [8, 11], "name": "ER_RECT"},
13634    {"bits": [12, 17], "name": "ER_LINE_LR"},
13635    {"bits": [18, 23], "name": "ER_LINE_RL"},
13636    {"bits": [24, 27], "name": "ER_LINE_TB"},
13637    {"bits": [28, 31], "name": "ER_LINE_BT"}
13638   ]
13639  },
13640  "PA_SC_HORIZ_GRID": {
13641   "fields": [
13642    {"bits": [0, 7], "name": "TOP_QTR"},
13643    {"bits": [8, 15], "name": "TOP_HALF"},
13644    {"bits": [16, 23], "name": "BOT_HALF"},
13645    {"bits": [24, 31], "name": "BOT_QTR"}
13646   ]
13647  },
13648  "PA_SC_LINE_CNTL": {
13649   "fields": [
13650    {"bits": [9, 9], "name": "EXPAND_LINE_WIDTH"},
13651    {"bits": [10, 10], "name": "LAST_PIXEL"},
13652    {"bits": [11, 11], "name": "PERPENDICULAR_ENDCAP_ENA"},
13653    {"bits": [12, 12], "name": "DX10_DIAMOND_TEST_ENA"},
13654    {"bits": [13, 13], "name": "EXTRA_DX_DY_PRECISION"}
13655   ]
13656  },
13657  "PA_SC_LINE_STIPPLE": {
13658   "fields": [
13659    {"bits": [0, 15], "name": "LINE_PATTERN"},
13660    {"bits": [16, 23], "name": "REPEAT_COUNT"},
13661    {"bits": [28, 28], "name": "PATTERN_BIT_ORDER"},
13662    {"bits": [29, 30], "name": "AUTO_RESET_CNTL"}
13663   ]
13664  },
13665  "PA_SC_LINE_STIPPLE_STATE": {
13666   "fields": [
13667    {"bits": [0, 3], "name": "CURRENT_PTR"},
13668    {"bits": [8, 15], "name": "CURRENT_COUNT"}
13669   ]
13670  },
13671  "PA_SC_MODE_CNTL_0": {
13672   "fields": [
13673    {"bits": [0, 0], "name": "MSAA_ENABLE"},
13674    {"bits": [1, 1], "name": "VPORT_SCISSOR_ENABLE"},
13675    {"bits": [2, 2], "name": "LINE_STIPPLE_ENABLE"},
13676    {"bits": [3, 3], "name": "SEND_UNLIT_STILES_TO_PKR"},
13677    {"bits": [4, 4], "name": "SCALE_LINE_WIDTH_PAD"},
13678    {"bits": [5, 5], "name": "ALTERNATE_RBS_PER_TILE"},
13679    {"bits": [6, 6], "name": "COARSE_TILE_STARTS_ON_EVEN_RB"}
13680   ]
13681  },
13682  "PA_SC_MODE_CNTL_1": {
13683   "fields": [
13684    {"bits": [0, 0], "name": "WALK_SIZE"},
13685    {"bits": [1, 1], "name": "WALK_ALIGNMENT"},
13686    {"bits": [2, 2], "name": "WALK_ALIGN8_PRIM_FITS_ST"},
13687    {"bits": [3, 3], "name": "WALK_FENCE_ENABLE"},
13688    {"bits": [4, 6], "name": "WALK_FENCE_SIZE"},
13689    {"bits": [7, 7], "name": "SUPERTILE_WALK_ORDER_ENABLE"},
13690    {"bits": [8, 8], "name": "TILE_WALK_ORDER_ENABLE"},
13691    {"bits": [9, 9], "name": "TILE_COVER_DISABLE"},
13692    {"bits": [10, 10], "name": "TILE_COVER_NO_SCISSOR"},
13693    {"bits": [11, 11], "name": "ZMM_LINE_EXTENT"},
13694    {"bits": [12, 12], "name": "ZMM_LINE_OFFSET"},
13695    {"bits": [13, 13], "name": "ZMM_RECT_EXTENT"},
13696    {"bits": [14, 14], "name": "KILL_PIX_POST_HI_Z"},
13697    {"bits": [15, 15], "name": "KILL_PIX_POST_DETAIL_MASK"},
13698    {"bits": [16, 16], "name": "PS_ITER_SAMPLE"},
13699    {"bits": [17, 17], "name": "MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE"},
13700    {"bits": [18, 18], "name": "MULTI_GPU_SUPERTILE_ENABLE"},
13701    {"bits": [19, 19], "name": "GPU_ID_OVERRIDE_ENABLE"},
13702    {"bits": [20, 23], "name": "GPU_ID_OVERRIDE"},
13703    {"bits": [24, 24], "name": "MULTI_GPU_PRIM_DISCARD_ENABLE"},
13704    {"bits": [25, 25], "name": "FORCE_EOV_CNTDWN_ENABLE"},
13705    {"bits": [26, 26], "name": "FORCE_EOV_REZ_ENABLE"},
13706    {"bits": [27, 27], "name": "OUT_OF_ORDER_PRIMITIVE_ENABLE"},
13707    {"bits": [28, 30], "name": "OUT_OF_ORDER_WATER_MARK"}
13708   ]
13709  },
13710  "PA_SC_NGG_MODE_CNTL": {
13711   "fields": [
13712    {"bits": [0, 10], "name": "MAX_DEALLOCS_IN_WAVE"},
13713    {"bits": [16, 23], "name": "MAX_FPOVS_IN_WAVE"}
13714   ]
13715  },
13716  "PA_SC_P3D_TRAP_SCREEN_H": {
13717   "fields": [
13718    {"bits": [0, 13], "name": "X_COORD"}
13719   ]
13720  },
13721  "PA_SC_P3D_TRAP_SCREEN_HV_EN": {
13722   "fields": [
13723    {"bits": [0, 0], "name": "ENABLE_HV_PRE_SHADER"},
13724    {"bits": [1, 1], "name": "FORCE_PRE_SHADER_ALL_PIXELS"}
13725   ]
13726  },
13727  "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE": {
13728   "fields": [
13729    {"bits": [0, 15], "name": "COUNT"}
13730   ]
13731  },
13732  "PA_SC_P3D_TRAP_SCREEN_V": {
13733   "fields": [
13734    {"bits": [0, 13], "name": "Y_COORD"}
13735   ]
13736  },
13737  "PA_SC_PERFCOUNTER1_SELECT": {
13738   "fields": [
13739    {"bits": [0, 9], "name": "PERF_SEL"}
13740   ]
13741  },
13742  "PA_SC_RASTER_CONFIG": {
13743   "fields": [
13744    {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"},
13745    {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"},
13746    {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"},
13747    {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"},
13748    {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"},
13749    {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"},
13750    {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"},
13751    {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"},
13752    {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"},
13753    {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"},
13754    {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"},
13755    {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"},
13756    {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"},
13757    {"bits": [26, 27], "enum_ref": "SeXsel", "name": "SE_XSEL"},
13758    {"bits": [28, 29], "enum_ref": "SeYsel", "name": "SE_YSEL"}
13759   ]
13760  },
13761  "PA_SC_RASTER_CONFIG_1": {
13762   "fields": [
13763    {"bits": [0, 1], "enum_ref": "SePairMap", "name": "SE_PAIR_MAP"},
13764    {"bits": [2, 3], "enum_ref": "SePairXsel", "name": "SE_PAIR_XSEL"},
13765    {"bits": [4, 5], "enum_ref": "SePairYsel", "name": "SE_PAIR_YSEL"}
13766   ]
13767  },
13768  "PA_SC_RIGHT_VERT_GRID": {
13769   "fields": [
13770    {"bits": [0, 7], "name": "LEFT_QTR"},
13771    {"bits": [8, 15], "name": "LEFT_HALF"},
13772    {"bits": [16, 23], "name": "RIGHT_HALF"},
13773    {"bits": [24, 31], "name": "RIGHT_QTR"}
13774   ]
13775  },
13776  "PA_SC_SCREEN_EXTENT_CONTROL": {
13777   "fields": [
13778    {"bits": [0, 1], "name": "SLICE_EVEN_ENABLE"},
13779    {"bits": [2, 3], "name": "SLICE_ODD_ENABLE"}
13780   ]
13781  },
13782  "PA_SC_SCREEN_EXTENT_MIN_0": {
13783   "fields": [
13784    {"bits": [0, 15], "name": "X"},
13785    {"bits": [16, 31], "name": "Y"}
13786   ]
13787  },
13788  "PA_SC_SCREEN_SCISSOR_BR": {
13789   "fields": [
13790    {"bits": [0, 15], "name": "BR_X"},
13791    {"bits": [16, 31], "name": "BR_Y"}
13792   ]
13793  },
13794  "PA_SC_SCREEN_SCISSOR_TL": {
13795   "fields": [
13796    {"bits": [0, 15], "name": "TL_X"},
13797    {"bits": [16, 31], "name": "TL_Y"}
13798   ]
13799  },
13800  "PA_SC_SHADER_CONTROL": {
13801   "fields": [
13802    {"bits": [0, 1], "name": "REALIGN_DQUADS_AFTER_N_WAVES"},
13803    {"bits": [2, 2], "name": "LOAD_COLLISION_WAVEID"},
13804    {"bits": [3, 3], "name": "LOAD_INTRAWAVE_COLLISION"},
13805    {"bits": [5, 6], "name": "WAVE_BREAK_REGION_SIZE"}
13806   ]
13807  },
13808  "PA_SC_TILE_STEERING_OVERRIDE": {
13809   "fields": [
13810    {"bits": [0, 0], "name": "ENABLE"},
13811    {"bits": [1, 2], "name": "NUM_SE"},
13812    {"bits": [5, 6], "name": "NUM_RB_PER_SE"},
13813    {"bits": [8, 8], "name": "DISABLE_SRBSL_DB_OPTIMIZED_PACKING"},
13814    {"bits": [12, 13], "name": "NUM_SC"},
13815    {"bits": [16, 17], "name": "NUM_RB_PER_SC"},
13816    {"bits": [20, 20], "name": "NUM_PACKER_PER_SC"}
13817   ]
13818  },
13819  "PA_SC_WINDOW_OFFSET": {
13820   "fields": [
13821    {"bits": [0, 15], "name": "WINDOW_X_OFFSET"},
13822    {"bits": [16, 31], "name": "WINDOW_Y_OFFSET"}
13823   ]
13824  },
13825  "PA_SC_WINDOW_SCISSOR_BR": {
13826   "fields": [
13827    {"bits": [0, 14], "name": "BR_X"},
13828    {"bits": [16, 30], "name": "BR_Y"}
13829   ]
13830  },
13831  "PA_SC_WINDOW_SCISSOR_TL": {
13832   "fields": [
13833    {"bits": [0, 14], "name": "TL_X"},
13834    {"bits": [16, 30], "name": "TL_Y"},
13835    {"bits": [31, 31], "name": "WINDOW_OFFSET_DISABLE"}
13836   ]
13837  },
13838  "PA_STEREO_CNTL": {
13839   "fields": [
13840    {"bits": [1, 4], "name": "STEREO_MODE"},
13841    {"bits": [5, 7], "name": "RT_SLICE_MODE"},
13842    {"bits": [8, 11], "name": "RT_SLICE_OFFSET"},
13843    {"bits": [16, 18], "name": "VP_ID_MODE"},
13844    {"bits": [19, 22], "name": "VP_ID_OFFSET"}
13845   ]
13846  },
13847  "PA_SU_HARDWARE_SCREEN_OFFSET": {
13848   "fields": [
13849    {"bits": [0, 8], "name": "HW_SCREEN_OFFSET_X"},
13850    {"bits": [16, 24], "name": "HW_SCREEN_OFFSET_Y"}
13851   ]
13852  },
13853  "PA_SU_LINE_CNTL": {
13854   "fields": [
13855    {"bits": [0, 15], "name": "WIDTH"}
13856   ]
13857  },
13858  "PA_SU_LINE_STIPPLE_CNTL": {
13859   "fields": [
13860    {"bits": [0, 1], "name": "LINE_STIPPLE_RESET"},
13861    {"bits": [2, 2], "name": "EXPAND_FULL_LENGTH"},
13862    {"bits": [3, 3], "name": "FRACTIONAL_ACCUM"},
13863    {"bits": [4, 4], "name": "DIAMOND_ADJUST"}
13864   ]
13865  },
13866  "PA_SU_LINE_STIPPLE_VALUE": {
13867   "fields": [
13868    {"bits": [0, 23], "name": "LINE_STIPPLE_VALUE"}
13869   ]
13870  },
13871  "PA_SU_OVER_RASTERIZATION_CNTL": {
13872   "fields": [
13873    {"bits": [0, 0], "name": "DISCARD_0_AREA_TRIANGLES"},
13874    {"bits": [1, 1], "name": "DISCARD_0_AREA_LINES"},
13875    {"bits": [2, 2], "name": "DISCARD_0_AREA_POINTS"},
13876    {"bits": [3, 3], "name": "DISCARD_0_AREA_RECTANGLES"},
13877    {"bits": [4, 4], "name": "USE_PROVOKING_ZW"}
13878   ]
13879  },
13880  "PA_SU_PERFCOUNTER0_HI": {
13881   "fields": [
13882    {"bits": [0, 15], "name": "PERFCOUNTER_HI"}
13883   ]
13884  },
13885  "PA_SU_PERFCOUNTER0_SELECT": {
13886   "fields": [
13887    {"bits": [0, 9], "name": "PERF_SEL"},
13888    {"bits": [10, 19], "name": "PERF_SEL1"},
13889    {"bits": [20, 23], "name": "CNTR_MODE"},
13890    {"bits": [24, 27], "name": "PERF_MODE1"},
13891    {"bits": [28, 31], "name": "PERF_MODE"}
13892   ]
13893  },
13894  "PA_SU_PERFCOUNTER0_SELECT1": {
13895   "fields": [
13896    {"bits": [0, 9], "name": "PERF_SEL2"},
13897    {"bits": [10, 19], "name": "PERF_SEL3"},
13898    {"bits": [24, 27], "name": "PERF_MODE3"},
13899    {"bits": [28, 31], "name": "PERF_MODE2"}
13900   ]
13901  },
13902  "PA_SU_POINT_MINMAX": {
13903   "fields": [
13904    {"bits": [0, 15], "name": "MIN_SIZE"},
13905    {"bits": [16, 31], "name": "MAX_SIZE"}
13906   ]
13907  },
13908  "PA_SU_POINT_SIZE": {
13909   "fields": [
13910    {"bits": [0, 15], "name": "HEIGHT"},
13911    {"bits": [16, 31], "name": "WIDTH"}
13912   ]
13913  },
13914  "PA_SU_POLY_OFFSET_DB_FMT_CNTL": {
13915   "fields": [
13916    {"bits": [0, 7], "name": "POLY_OFFSET_NEG_NUM_DB_BITS"},
13917    {"bits": [8, 8], "name": "POLY_OFFSET_DB_IS_FLOAT_FMT"}
13918   ]
13919  },
13920  "PA_SU_PRIM_FILTER_CNTL": {
13921   "fields": [
13922    {"bits": [0, 0], "name": "TRIANGLE_FILTER_DISABLE"},
13923    {"bits": [1, 1], "name": "LINE_FILTER_DISABLE"},
13924    {"bits": [2, 2], "name": "POINT_FILTER_DISABLE"},
13925    {"bits": [3, 3], "name": "RECTANGLE_FILTER_DISABLE"},
13926    {"bits": [4, 4], "name": "TRIANGLE_EXPAND_ENA"},
13927    {"bits": [5, 5], "name": "LINE_EXPAND_ENA"},
13928    {"bits": [6, 6], "name": "POINT_EXPAND_ENA"},
13929    {"bits": [7, 7], "name": "RECTANGLE_EXPAND_ENA"},
13930    {"bits": [8, 15], "name": "PRIM_EXPAND_CONSTANT"},
13931    {"bits": [30, 30], "name": "XMAX_RIGHT_EXCLUSION"},
13932    {"bits": [31, 31], "name": "YMAX_BOTTOM_EXCLUSION"}
13933   ]
13934  },
13935  "PA_SU_SC_MODE_CNTL": {
13936   "fields": [
13937    {"bits": [0, 0], "name": "CULL_FRONT"},
13938    {"bits": [1, 1], "name": "CULL_BACK"},
13939    {"bits": [2, 2], "name": "FACE"},
13940    {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"},
13941    {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_FRONT_PTYPE"},
13942    {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_BACK_PTYPE"},
13943    {"bits": [11, 11], "name": "POLY_OFFSET_FRONT_ENABLE"},
13944    {"bits": [12, 12], "name": "POLY_OFFSET_BACK_ENABLE"},
13945    {"bits": [13, 13], "name": "POLY_OFFSET_PARA_ENABLE"},
13946    {"bits": [16, 16], "name": "VTX_WINDOW_OFFSET_ENABLE"},
13947    {"bits": [19, 19], "name": "PROVOKING_VTX_LAST"},
13948    {"bits": [20, 20], "name": "PERSP_CORR_DIS"},
13949    {"bits": [21, 21], "name": "MULTI_PRIM_IB_ENA"},
13950    {"bits": [22, 22], "name": "RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF"},
13951    {"bits": [23, 23], "name": "NEW_QUAD_DECOMPOSITION"},
13952    {"bits": [24, 24], "name": "KEEP_TOGETHER_ENABLE"}
13953   ]
13954  },
13955  "PA_SU_SMALL_PRIM_FILTER_CNTL": {
13956   "fields": [
13957    {"bits": [0, 0], "name": "SMALL_PRIM_FILTER_ENABLE"},
13958    {"bits": [1, 1], "name": "TRIANGLE_FILTER_DISABLE"},
13959    {"bits": [2, 2], "name": "LINE_FILTER_DISABLE"},
13960    {"bits": [3, 3], "name": "POINT_FILTER_DISABLE"},
13961    {"bits": [4, 4], "name": "RECTANGLE_FILTER_DISABLE"},
13962    {"bits": [5, 5], "name": "SRBSL_ENABLE"},
13963    {"bits": [6, 6], "name": "SC_1XMSAA_COMPATIBLE_DISABLE"}
13964   ]
13965  },
13966  "PA_SU_VTX_CNTL": {
13967   "fields": [
13968    {"bits": [0, 0], "name": "PIX_CENTER"},
13969    {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"},
13970    {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"}
13971   ]
13972  },
13973  "RLC_GPM_PERF_COUNT_0": {
13974   "fields": [
13975    {"bits": [0, 3], "name": "FEATURE_SEL"},
13976    {"bits": [4, 7], "name": "SE_INDEX"},
13977    {"bits": [8, 11], "name": "SA_INDEX"},
13978    {"bits": [12, 15], "name": "WGP_INDEX"},
13979    {"bits": [16, 17], "name": "EVENT_SEL"},
13980    {"bits": [18, 19], "name": "UNUSED"},
13981    {"bits": [20, 20], "name": "ENABLE"},
13982    {"bits": [21, 31], "name": "RESERVED"}
13983   ]
13984  },
13985  "RLC_GPU_IOV_PERF_CNT_CNTL": {
13986   "fields": [
13987    {"bits": [0, 0], "name": "ENABLE"},
13988    {"bits": [1, 1], "name": "MODE_SELECT"},
13989    {"bits": [2, 2], "name": "RESET"},
13990    {"bits": [3, 31], "name": "RESERVED"}
13991   ]
13992  },
13993  "RLC_GPU_IOV_PERF_CNT_WR_ADDR": {
13994   "fields": [
13995    {"bits": [0, 3], "name": "VFID"},
13996    {"bits": [4, 5], "name": "CNT_ID"},
13997    {"bits": [6, 31], "name": "RESERVED"}
13998   ]
13999  },
14000  "RLC_PERFCOUNTER0_SELECT": {
14001   "fields": [
14002    {"bits": [0, 7], "name": "PERFCOUNTER_SELECT"}
14003   ]
14004  },
14005  "RLC_PERFMON_CLK_CNTL": {
14006   "fields": [
14007    {"bits": [0, 0], "name": "PERFMON_CLOCK_STATE"}
14008   ]
14009  },
14010  "RLC_PERFMON_CNTL": {
14011   "fields": [
14012    {"bits": [0, 2], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"},
14013    {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"}
14014   ]
14015  },
14016  "RLC_SPM_ACCUM_CTRL": {
14017   "fields": [
14018    {"bits": [0, 0], "name": "StrobeResetPerfMonitors"},
14019    {"bits": [1, 1], "name": "StrobeStartAccumulation"},
14020    {"bits": [2, 2], "name": "StrobeRearmAccum"},
14021    {"bits": [3, 3], "name": "StrobeSpmDoneInt"},
14022    {"bits": [4, 4], "name": "StrobeAccumDoneInt"},
14023    {"bits": [5, 5], "name": "StrobeResetAccum"},
14024    {"bits": [6, 9], "name": "StrobeStartSpm"},
14025    {"bits": [10, 31], "name": "RESERVED"}
14026   ]
14027  },
14028  "RLC_SPM_ACCUM_CTRLRAM_ADDR": {
14029   "fields": [
14030    {"bits": [0, 8], "name": "addr"},
14031    {"bits": [9, 31], "name": "RESERVED"}
14032   ]
14033  },
14034  "RLC_SPM_ACCUM_CTRLRAM_DATA": {
14035   "fields": [
14036    {"bits": [0, 7], "name": "data"},
14037    {"bits": [8, 31], "name": "RESERVED"}
14038   ]
14039  },
14040  "RLC_SPM_ACCUM_DATARAM_ADDR": {
14041   "fields": [
14042    {"bits": [0, 6], "name": "addr"},
14043    {"bits": [7, 31], "name": "RESERVED"}
14044   ]
14045  },
14046  "RLC_SPM_ACCUM_DATARAM_WRCOUNT": {
14047   "fields": [
14048    {"bits": [0, 18], "name": "DataRamWrCount"},
14049    {"bits": [19, 31], "name": "RESERVED"}
14050   ]
14051  },
14052  "RLC_SPM_ACCUM_MODE": {
14053   "fields": [
14054    {"bits": [0, 0], "name": "EnableAccum"},
14055    {"bits": [1, 1], "name": "AutoAccumEn"},
14056    {"bits": [2, 2], "name": "AutoSpmEn"},
14057    {"bits": [3, 3], "name": "Globals_LoadOverride"},
14058    {"bits": [4, 4], "name": "SE0_LoadOverride"},
14059    {"bits": [5, 5], "name": "SE1_LoadOverride"},
14060    {"bits": [6, 6], "name": "AutoResetPerfmonDisable"},
14061    {"bits": [7, 31], "name": "RESERVED"}
14062   ]
14063  },
14064  "RLC_SPM_ACCUM_SAMPLES_REQUESTED": {
14065   "fields": [
14066    {"bits": [0, 7], "name": "SamplesRequested"},
14067    {"bits": [8, 31], "name": "RESERVED"}
14068   ]
14069  },
14070  "RLC_SPM_ACCUM_STATUS": {
14071   "fields": [
14072    {"bits": [0, 7], "name": "NumbSamplesCompleted"},
14073    {"bits": [8, 8], "name": "AccumDone"},
14074    {"bits": [9, 9], "name": "SpmDone"},
14075    {"bits": [10, 10], "name": "AccumOverflow"},
14076    {"bits": [11, 11], "name": "AccumArmed"},
14077    {"bits": [12, 12], "name": "SequenceInProgress"},
14078    {"bits": [13, 13], "name": "FinalSequenceInProgress"},
14079    {"bits": [14, 14], "name": "AllFifosEmpty"},
14080    {"bits": [15, 15], "name": "FSMIsIdle"},
14081    {"bits": [16, 31], "name": "RESERVED"}
14082   ]
14083  },
14084  "RLC_SPM_ACCUM_THRESHOLD": {
14085   "fields": [
14086    {"bits": [0, 15], "name": "Threshold"},
14087    {"bits": [16, 31], "name": "RESERVED"}
14088   ]
14089  },
14090  "RLC_SPM_DESER_START_SKEW": {
14091   "fields": [
14092    {"bits": [0, 6], "name": "DESER_START_SKEW"},
14093    {"bits": [7, 31], "name": "RESERVED"}
14094   ]
14095  },
14096  "RLC_SPM_GLB_SAMPLEDELAY_IND_DATA": {
14097   "fields": [
14098    {"bits": [0, 6], "name": "data"},
14099    {"bits": [7, 31], "name": "RESERVED"}
14100   ]
14101  },
14102  "RLC_SPM_GLOBALS_MUXSEL_SKEW": {
14103   "fields": [
14104    {"bits": [0, 6], "name": "GLOBALS_MUXSEL_SKEW"},
14105    {"bits": [7, 31], "name": "RESERVED"}
14106   ]
14107  },
14108  "RLC_SPM_GLOBALS_SAMPLE_SKEW": {
14109   "fields": [
14110    {"bits": [0, 6], "name": "GLOBALS_SAMPLE_SKEW"},
14111    {"bits": [7, 31], "name": "RESERVED"}
14112   ]
14113  },
14114  "RLC_SPM_GLOBAL_MUXSEL_ADDR": {
14115   "fields": [
14116    {"bits": [0, 7], "name": "PERFMON_SEL_ADDR"},
14117    {"bits": [8, 31], "name": "RESERVED"}
14118   ]
14119  },
14120  "RLC_SPM_PERFMON_CNTL": {
14121   "fields": [
14122    {"bits": [0, 11], "name": "RESERVED1"},
14123    {"bits": [12, 13], "name": "PERFMON_RING_MODE"},
14124    {"bits": [14, 15], "name": "RESERVED"},
14125    {"bits": [16, 31], "name": "PERFMON_SAMPLE_INTERVAL"}
14126   ]
14127  },
14128  "RLC_SPM_PERFMON_GLB_SEGMENT_SIZE": {
14129   "fields": [
14130    {"bits": [0, 7], "name": "PERFMON_SEGMENT_SIZE"},
14131    {"bits": [8, 15], "name": "GLOBAL_NUM_LINE"},
14132    {"bits": [16, 31], "name": "RESERVED"}
14133   ]
14134  },
14135  "RLC_SPM_PERFMON_RING_BASE_HI": {
14136   "fields": [
14137    {"bits": [0, 15], "name": "RING_BASE_HI"},
14138    {"bits": [16, 31], "name": "RESERVED"}
14139   ]
14140  },
14141  "RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE": {
14142   "fields": [
14143    {"bits": [0, 7], "name": "SE0_NUM_LINE"},
14144    {"bits": [8, 15], "name": "SE1_NUM_LINE"},
14145    {"bits": [16, 23], "name": "SE2_NUM_LINE"},
14146    {"bits": [24, 31], "name": "SE3_NUM_LINE"}
14147   ]
14148  },
14149  "RLC_SPM_PERFMON_SEGMENT_SIZE": {
14150   "fields": [
14151    {"bits": [0, 7], "name": "PERFMON_SEGMENT_SIZE"},
14152    {"bits": [8, 10], "name": "RESERVED1"},
14153    {"bits": [11, 15], "name": "GLOBAL_NUM_LINE"},
14154    {"bits": [16, 20], "name": "SE0_NUM_LINE"},
14155    {"bits": [21, 25], "name": "SE1_NUM_LINE"},
14156    {"bits": [26, 30], "name": "SE2_NUM_LINE"},
14157    {"bits": [31, 31], "name": "RESERVED"}
14158   ]
14159  },
14160  "RLC_SPM_RING_WRPTR": {
14161   "fields": [
14162    {"bits": [0, 4], "name": "RESERVED"},
14163    {"bits": [5, 31], "name": "PERFMON_RING_WRPTR"}
14164   ]
14165  },
14166  "RLC_SPM_SEGMENT_THRESHOLD": {
14167   "fields": [
14168    {"bits": [0, 7], "name": "NUM_SEGMENT_THRESHOLD"},
14169    {"bits": [8, 31], "name": "RESERVED"}
14170   ]
14171  },
14172  "RLC_SPM_SE_MUXSEL_ADDR": {
14173   "fields": [
14174    {"bits": [0, 8], "name": "PERFMON_SEL_ADDR"},
14175    {"bits": [9, 31], "name": "RESERVED"}
14176   ]
14177  },
14178  "RLC_SPM_SE_MUXSEL_SKEW": {
14179   "fields": [
14180    {"bits": [0, 6], "name": "SE_MUXSEL_SKEW"},
14181    {"bits": [7, 31], "name": "RESERVED"}
14182   ]
14183  },
14184  "RLC_SPM_SE_SAMPLE_SKEW": {
14185   "fields": [
14186    {"bits": [0, 6], "name": "SE_SAMPLE_SKEW"},
14187    {"bits": [7, 31], "name": "RESERVED"}
14188   ]
14189  },
14190  "RLC_SPM_VIRT_CTRL": {
14191   "fields": [
14192    {"bits": [0, 0], "name": "PauseSpmSamplingRequest"}
14193   ]
14194  },
14195  "RLC_SPM_VIRT_STATUS": {
14196   "fields": [
14197    {"bits": [0, 0], "name": "SpmSamplingPaused"}
14198   ]
14199  },
14200  "RMI_PERF_COUNTER_CNTL": {
14201   "fields": [
14202    {"bits": [0, 1], "name": "TRANS_BASED_PERF_EN_SEL"},
14203    {"bits": [2, 3], "name": "EVENT_BASED_PERF_EN_SEL"},
14204    {"bits": [4, 5], "name": "TC_PERF_EN_SEL"},
14205    {"bits": [6, 7], "name": "PERF_EVENT_WINDOW_MASK0"},
14206    {"bits": [8, 9], "name": "PERF_EVENT_WINDOW_MASK1"},
14207    {"bits": [10, 13], "name": "PERF_COUNTER_CID"},
14208    {"bits": [14, 18], "name": "PERF_COUNTER_VMID"},
14209    {"bits": [19, 24], "name": "PERF_COUNTER_BURST_LENGTH_THRESHOLD"},
14210    {"bits": [25, 25], "name": "PERF_SOFT_RESET"},
14211    {"bits": [26, 26], "name": "PERF_CNTR_SPM_SEL"}
14212   ]
14213  },
14214  "SCRATCH_UMSK": {
14215   "fields": [
14216    {"bits": [0, 7], "name": "OBSOLETE_UMSK"},
14217    {"bits": [16, 17], "name": "OBSOLETE_SWAP"}
14218   ]
14219  },
14220  "SPI_BARYC_CNTL": {
14221   "fields": [
14222    {"bits": [0, 0], "name": "PERSP_CENTER_CNTL"},
14223    {"bits": [4, 4], "name": "PERSP_CENTROID_CNTL"},
14224    {"bits": [8, 8], "name": "LINEAR_CENTER_CNTL"},
14225    {"bits": [12, 12], "name": "LINEAR_CENTROID_CNTL"},
14226    {"bits": [16, 17], "name": "POS_FLOAT_LOCATION"},
14227    {"bits": [20, 20], "name": "POS_FLOAT_ULC"},
14228    {"bits": [24, 24], "name": "FRONT_FACE_ALL_BITS"}
14229   ]
14230  },
14231  "SPI_CONFIG_CNTL": {
14232   "fields": [
14233    {"bits": [0, 20], "name": "GPR_WRITE_PRIORITY"},
14234    {"bits": [21, 23], "name": "EXP_PRIORITY_ORDER"},
14235    {"bits": [24, 24], "name": "ENABLE_SQG_TOP_EVENTS"},
14236    {"bits": [25, 25], "name": "ENABLE_SQG_BOP_EVENTS"},
14237    {"bits": [26, 26], "name": "RSRC_MGMT_RESET"},
14238    {"bits": [27, 27], "name": "TTRACE_STALL_ALL"},
14239    {"bits": [28, 28], "name": "ALLOC_ARB_LRU_ENA"},
14240    {"bits": [29, 29], "name": "EXP_ARB_LRU_ENA"},
14241    {"bits": [30, 31], "name": "PS_PKR_PRIORITY_CNTL"}
14242   ]
14243  },
14244  "SPI_INTERP_CONTROL_0": {
14245   "fields": [
14246    {"bits": [0, 0], "name": "FLAT_SHADE_ENA"},
14247    {"bits": [1, 1], "name": "PNT_SPRITE_ENA"},
14248    {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"},
14249    {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"},
14250    {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"},
14251    {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"},
14252    {"bits": [14, 14], "name": "PNT_SPRITE_TOP_1"}
14253   ]
14254  },
14255  "SPI_PERFCOUNTER_BINS": {
14256   "fields": [
14257    {"bits": [0, 3], "name": "BIN0_MIN"},
14258    {"bits": [4, 7], "name": "BIN0_MAX"},
14259    {"bits": [8, 11], "name": "BIN1_MIN"},
14260    {"bits": [12, 15], "name": "BIN1_MAX"},
14261    {"bits": [16, 19], "name": "BIN2_MIN"},
14262    {"bits": [20, 23], "name": "BIN2_MAX"},
14263    {"bits": [24, 27], "name": "BIN3_MIN"},
14264    {"bits": [28, 31], "name": "BIN3_MAX"}
14265   ]
14266  },
14267  "SPI_PS_INPUT_CNTL_0": {
14268   "fields": [
14269    {"bits": [0, 5], "name": "OFFSET"},
14270    {"bits": [8, 9], "name": "DEFAULT_VAL"},
14271    {"bits": [10, 10], "name": "FLAT_SHADE"},
14272    {"bits": [13, 16], "name": "CYL_WRAP"},
14273    {"bits": [17, 17], "name": "PT_SPRITE_TEX"},
14274    {"bits": [18, 18], "name": "DUP"},
14275    {"bits": [19, 19], "name": "FP16_INTERP_MODE"},
14276    {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"},
14277    {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"},
14278    {"bits": [23, 23], "name": "PT_SPRITE_TEX_ATTR1"},
14279    {"bits": [24, 24], "name": "ATTR0_VALID"},
14280    {"bits": [25, 25], "name": "ATTR1_VALID"}
14281   ]
14282  },
14283  "SPI_PS_INPUT_CNTL_20": {
14284   "fields": [
14285    {"bits": [0, 5], "name": "OFFSET"},
14286    {"bits": [8, 9], "name": "DEFAULT_VAL"},
14287    {"bits": [10, 10], "name": "FLAT_SHADE"},
14288    {"bits": [18, 18], "name": "DUP"},
14289    {"bits": [19, 19], "name": "FP16_INTERP_MODE"},
14290    {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"},
14291    {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"},
14292    {"bits": [24, 24], "name": "ATTR0_VALID"},
14293    {"bits": [25, 25], "name": "ATTR1_VALID"}
14294   ]
14295  },
14296  "SPI_PS_INPUT_ENA": {
14297   "fields": [
14298    {"bits": [0, 0], "name": "PERSP_SAMPLE_ENA"},
14299    {"bits": [1, 1], "name": "PERSP_CENTER_ENA"},
14300    {"bits": [2, 2], "name": "PERSP_CENTROID_ENA"},
14301    {"bits": [3, 3], "name": "PERSP_PULL_MODEL_ENA"},
14302    {"bits": [4, 4], "name": "LINEAR_SAMPLE_ENA"},
14303    {"bits": [5, 5], "name": "LINEAR_CENTER_ENA"},
14304    {"bits": [6, 6], "name": "LINEAR_CENTROID_ENA"},
14305    {"bits": [7, 7], "name": "LINE_STIPPLE_TEX_ENA"},
14306    {"bits": [8, 8], "name": "POS_X_FLOAT_ENA"},
14307    {"bits": [9, 9], "name": "POS_Y_FLOAT_ENA"},
14308    {"bits": [10, 10], "name": "POS_Z_FLOAT_ENA"},
14309    {"bits": [11, 11], "name": "POS_W_FLOAT_ENA"},
14310    {"bits": [12, 12], "name": "FRONT_FACE_ENA"},
14311    {"bits": [13, 13], "name": "ANCILLARY_ENA"},
14312    {"bits": [14, 14], "name": "SAMPLE_COVERAGE_ENA"},
14313    {"bits": [15, 15], "name": "POS_FIXED_PT_ENA"}
14314   ]
14315  },
14316  "SPI_PS_IN_CONTROL": {
14317   "fields": [
14318    {"bits": [0, 5], "name": "NUM_INTERP"},
14319    {"bits": [6, 6], "name": "PARAM_GEN"},
14320    {"bits": [7, 7], "name": "OFFCHIP_PARAM_EN"},
14321    {"bits": [8, 8], "name": "LATE_PC_DEALLOC"},
14322    {"bits": [14, 14], "name": "BC_OPTIMIZE_DISABLE"},
14323    {"bits": [15, 15], "name": "PS_W32_EN"}
14324   ]
14325  },
14326  "SPI_SHADER_COL_FORMAT": {
14327   "fields": [
14328    {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"},
14329    {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"},
14330    {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"},
14331    {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"},
14332    {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"},
14333    {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"},
14334    {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"},
14335    {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"}
14336   ]
14337  },
14338  "SPI_SHADER_IDX_FORMAT": {
14339   "fields": [
14340    {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "IDX0_EXPORT_FORMAT"}
14341   ]
14342  },
14343  "SPI_SHADER_LATE_ALLOC_VS": {
14344   "fields": [
14345    {"bits": [0, 5], "name": "LIMIT"}
14346   ]
14347  },
14348  "SPI_SHADER_PGM_HI_PS": {
14349   "fields": [
14350    {"bits": [0, 7], "name": "MEM_BASE"}
14351   ]
14352  },
14353  "SPI_SHADER_PGM_RSRC1_ES": {
14354   "fields": [
14355    {"bits": [0, 5], "name": "VGPRS"},
14356    {"bits": [6, 9], "name": "SGPRS"},
14357    {"bits": [10, 11], "name": "PRIORITY"},
14358    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
14359    {"bits": [20, 20], "name": "PRIV"},
14360    {"bits": [21, 21], "name": "DX10_CLAMP"},
14361    {"bits": [23, 23], "name": "IEEE_MODE"},
14362    {"bits": [24, 25], "name": "VGPR_COMP_CNT"},
14363    {"bits": [26, 26], "name": "CU_GROUP_ENABLE"},
14364    {"bits": [31, 31], "name": "FP16_OVFL"}
14365   ]
14366  },
14367  "SPI_SHADER_PGM_RSRC1_GS": {
14368   "fields": [
14369    {"bits": [0, 5], "name": "VGPRS"},
14370    {"bits": [6, 9], "name": "SGPRS"},
14371    {"bits": [10, 11], "name": "PRIORITY"},
14372    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
14373    {"bits": [20, 20], "name": "PRIV"},
14374    {"bits": [21, 21], "name": "DX10_CLAMP"},
14375    {"bits": [23, 23], "name": "IEEE_MODE"},
14376    {"bits": [24, 24], "name": "CU_GROUP_ENABLE"},
14377    {"bits": [25, 25], "name": "MEM_ORDERED"},
14378    {"bits": [26, 26], "name": "FWD_PROGRESS"},
14379    {"bits": [27, 27], "name": "WGP_MODE"},
14380    {"bits": [29, 30], "name": "GS_VGPR_COMP_CNT"},
14381    {"bits": [31, 31], "name": "FP16_OVFL"}
14382   ]
14383  },
14384  "SPI_SHADER_PGM_RSRC1_HS": {
14385   "fields": [
14386    {"bits": [0, 5], "name": "VGPRS"},
14387    {"bits": [6, 9], "name": "SGPRS"},
14388    {"bits": [10, 11], "name": "PRIORITY"},
14389    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
14390    {"bits": [20, 20], "name": "PRIV"},
14391    {"bits": [21, 21], "name": "DX10_CLAMP"},
14392    {"bits": [23, 23], "name": "IEEE_MODE"},
14393    {"bits": [24, 24], "name": "MEM_ORDERED"},
14394    {"bits": [25, 25], "name": "FWD_PROGRESS"},
14395    {"bits": [26, 26], "name": "WGP_MODE"},
14396    {"bits": [28, 29], "name": "LS_VGPR_COMP_CNT"},
14397    {"bits": [30, 30], "name": "FP16_OVFL"}
14398   ]
14399  },
14400  "SPI_SHADER_PGM_RSRC1_LS": {
14401   "fields": [
14402    {"bits": [0, 5], "name": "VGPRS"},
14403    {"bits": [6, 9], "name": "SGPRS"},
14404    {"bits": [10, 11], "name": "PRIORITY"},
14405    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
14406    {"bits": [20, 20], "name": "PRIV"},
14407    {"bits": [21, 21], "name": "DX10_CLAMP"},
14408    {"bits": [23, 23], "name": "IEEE_MODE"},
14409    {"bits": [24, 25], "name": "VGPR_COMP_CNT"},
14410    {"bits": [30, 30], "name": "FP16_OVFL"}
14411   ]
14412  },
14413  "SPI_SHADER_PGM_RSRC1_PS": {
14414   "fields": [
14415    {"bits": [0, 5], "name": "VGPRS"},
14416    {"bits": [6, 9], "name": "SGPRS"},
14417    {"bits": [10, 11], "name": "PRIORITY"},
14418    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
14419    {"bits": [20, 20], "name": "PRIV"},
14420    {"bits": [21, 21], "name": "DX10_CLAMP"},
14421    {"bits": [23, 23], "name": "IEEE_MODE"},
14422    {"bits": [24, 24], "name": "CU_GROUP_DISABLE"},
14423    {"bits": [25, 25], "name": "MEM_ORDERED"},
14424    {"bits": [26, 26], "name": "FWD_PROGRESS"},
14425    {"bits": [29, 29], "name": "FP16_OVFL"}
14426   ]
14427  },
14428  "SPI_SHADER_PGM_RSRC1_VS": {
14429   "fields": [
14430    {"bits": [0, 5], "name": "VGPRS"},
14431    {"bits": [6, 9], "name": "SGPRS"},
14432    {"bits": [10, 11], "name": "PRIORITY"},
14433    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
14434    {"bits": [20, 20], "name": "PRIV"},
14435    {"bits": [21, 21], "name": "DX10_CLAMP"},
14436    {"bits": [23, 23], "name": "IEEE_MODE"},
14437    {"bits": [24, 25], "name": "VGPR_COMP_CNT"},
14438    {"bits": [26, 26], "name": "CU_GROUP_ENABLE"},
14439    {"bits": [27, 27], "name": "MEM_ORDERED"},
14440    {"bits": [28, 28], "name": "FWD_PROGRESS"},
14441    {"bits": [31, 31], "name": "FP16_OVFL"}
14442   ]
14443  },
14444  "SPI_SHADER_PGM_RSRC2_ES_VS": {
14445   "fields": [
14446    {"bits": [0, 0], "name": "SCRATCH_EN"},
14447    {"bits": [1, 5], "name": "USER_SGPR"},
14448    {"bits": [6, 6], "name": "TRAP_PRESENT"},
14449    {"bits": [7, 7], "name": "OC_LDS_EN"},
14450    {"bits": [8, 16], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14451    {"bits": [20, 28], "name": "LDS_SIZE"}
14452   ]
14453  },
14454  "SPI_SHADER_PGM_RSRC2_GS": {
14455   "fields": [
14456    {"bits": [0, 0], "name": "SCRATCH_EN"},
14457    {"bits": [1, 5], "name": "USER_SGPR"},
14458    {"bits": [6, 6], "name": "TRAP_PRESENT"},
14459    {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14460    {"bits": [16, 17], "name": "ES_VGPR_COMP_CNT"},
14461    {"bits": [18, 18], "name": "OC_LDS_EN"},
14462    {"bits": [19, 26], "name": "LDS_SIZE"},
14463    {"bits": [27, 27], "name": "USER_SGPR_MSB"},
14464    {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
14465   ]
14466  },
14467  "SPI_SHADER_PGM_RSRC2_GS_VS": {
14468   "fields": [
14469    {"bits": [0, 0], "name": "SCRATCH_EN"},
14470    {"bits": [1, 5], "name": "USER_SGPR"},
14471    {"bits": [6, 6], "name": "TRAP_PRESENT"},
14472    {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14473    {"bits": [16, 17], "name": "VGPR_COMP_CNT"},
14474    {"bits": [18, 18], "name": "OC_LDS_EN"},
14475    {"bits": [19, 26], "name": "LDS_SIZE"},
14476    {"bits": [27, 27], "name": "SKIP_USGPR0"},
14477    {"bits": [28, 28], "name": "USER_SGPR_MSB"}
14478   ]
14479  },
14480  "SPI_SHADER_PGM_RSRC2_HS": {
14481   "fields": [
14482    {"bits": [0, 0], "name": "SCRATCH_EN"},
14483    {"bits": [1, 5], "name": "USER_SGPR"},
14484    {"bits": [6, 6], "name": "TRAP_PRESENT"},
14485    {"bits": [7, 7], "name": "OC_LDS_EN"},
14486    {"bits": [8, 8], "name": "TG_SIZE_EN"},
14487    {"bits": [9, 17], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14488    {"bits": [18, 26], "name": "LDS_SIZE"},
14489    {"bits": [27, 27], "name": "USER_SGPR_MSB"},
14490    {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
14491   ]
14492  },
14493  "SPI_SHADER_PGM_RSRC2_LS_VS": {
14494   "fields": [
14495    {"bits": [0, 0], "name": "SCRATCH_EN"},
14496    {"bits": [1, 5], "name": "USER_SGPR"},
14497    {"bits": [6, 6], "name": "TRAP_PRESENT"},
14498    {"bits": [7, 15], "name": "LDS_SIZE"},
14499    {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
14500   ]
14501  },
14502  "SPI_SHADER_PGM_RSRC2_PS": {
14503   "fields": [
14504    {"bits": [0, 0], "name": "SCRATCH_EN"},
14505    {"bits": [1, 5], "name": "USER_SGPR"},
14506    {"bits": [6, 6], "name": "TRAP_PRESENT"},
14507    {"bits": [7, 7], "name": "WAVE_CNT_EN"},
14508    {"bits": [8, 15], "name": "EXTRA_LDS_SIZE"},
14509    {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14510    {"bits": [25, 25], "name": "LOAD_COLLISION_WAVEID"},
14511    {"bits": [26, 26], "name": "LOAD_INTRAWAVE_COLLISION"},
14512    {"bits": [27, 27], "name": "USER_SGPR_MSB"},
14513    {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
14514   ]
14515  },
14516  "SPI_SHADER_PGM_RSRC2_VS": {
14517   "fields": [
14518    {"bits": [0, 0], "name": "SCRATCH_EN"},
14519    {"bits": [1, 5], "name": "USER_SGPR"},
14520    {"bits": [6, 6], "name": "TRAP_PRESENT"},
14521    {"bits": [7, 7], "name": "OC_LDS_EN"},
14522    {"bits": [8, 8], "name": "SO_BASE0_EN"},
14523    {"bits": [9, 9], "name": "SO_BASE1_EN"},
14524    {"bits": [10, 10], "name": "SO_BASE2_EN"},
14525    {"bits": [11, 11], "name": "SO_BASE3_EN"},
14526    {"bits": [12, 12], "name": "SO_EN"},
14527    {"bits": [13, 21], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14528    {"bits": [22, 22], "name": "PC_BASE_EN"},
14529    {"bits": [24, 24], "name": "DISPATCH_DRAW_EN"},
14530    {"bits": [27, 27], "name": "USER_SGPR_MSB"},
14531    {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
14532   ]
14533  },
14534  "SPI_SHADER_PGM_RSRC3_GS": {
14535   "fields": [
14536    {"bits": [0, 15], "name": "CU_EN"},
14537    {"bits": [16, 21], "name": "WAVE_LIMIT"},
14538    {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"},
14539    {"bits": [26, 31], "name": "GROUP_FIFO_DEPTH"}
14540   ]
14541  },
14542  "SPI_SHADER_PGM_RSRC3_HS": {
14543   "fields": [
14544    {"bits": [0, 5], "name": "WAVE_LIMIT"},
14545    {"bits": [6, 9], "name": "LOCK_LOW_THRESHOLD"},
14546    {"bits": [10, 15], "name": "GROUP_FIFO_DEPTH"},
14547    {"bits": [16, 31], "name": "CU_EN"}
14548   ]
14549  },
14550  "SPI_SHADER_PGM_RSRC3_PS": {
14551   "fields": [
14552    {"bits": [0, 15], "name": "CU_EN"},
14553    {"bits": [16, 21], "name": "WAVE_LIMIT"},
14554    {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"}
14555   ]
14556  },
14557  "SPI_SHADER_PGM_RSRC4_GS": {
14558   "fields": [
14559    {"bits": [0, 15], "name": "CU_EN"},
14560    {"bits": [16, 22], "name": "SPI_SHADER_LATE_ALLOC_GS"}
14561   ]
14562  },
14563  "SPI_SHADER_PGM_RSRC4_PS": {
14564   "fields": [
14565    {"bits": [0, 15], "name": "CU_EN"}
14566   ]
14567  },
14568  "SPI_SHADER_POS_FORMAT": {
14569   "fields": [
14570    {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"},
14571    {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"},
14572    {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"},
14573    {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"},
14574    {"bits": [16, 19], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS4_EXPORT_FORMAT"}
14575   ]
14576  },
14577  "SPI_SHADER_PREF_PRI_CNTR_CTRL_PS": {
14578   "fields": [
14579    {"bits": [0, 2], "name": "TOTAL_WAVE_COUNT_HIER_SELECT"},
14580    {"bits": [3, 5], "name": "PER_TYPE_WAVE_COUNT_HIER_SELECT"},
14581    {"bits": [6, 6], "name": "GROUP_UPDATE_EN"},
14582    {"bits": [8, 15], "name": "TOTAL_WAVE_COUNT_COEFFICIENT"},
14583    {"bits": [16, 23], "name": "PER_TYPE_WAVE_COUNT_COEFFICIENT"}
14584   ]
14585  },
14586  "SPI_SHADER_REQ_CTRL_PS": {
14587   "fields": [
14588    {"bits": [0, 0], "name": "SOFT_GROUPING_EN"},
14589    {"bits": [1, 4], "name": "NUMBER_OF_REQUESTS_PER_CU"},
14590    {"bits": [5, 8], "name": "SOFT_GROUPING_ALLOCATION_TIMEOUT"},
14591    {"bits": [9, 9], "name": "HARD_LOCK_HYSTERESIS"},
14592    {"bits": [10, 14], "name": "HARD_LOCK_LOW_THRESHOLD"},
14593    {"bits": [15, 15], "name": "PRODUCER_REQUEST_LOCKOUT"},
14594    {"bits": [16, 16], "name": "GLOBAL_SCANNING_EN"},
14595    {"bits": [17, 19], "name": "ALLOCATION_RATE_THROTTLING_THRESHOLD"}
14596   ]
14597  },
14598  "SPI_SHADER_USER_ACCUM_PS_0": {
14599   "fields": [
14600    {"bits": [0, 6], "name": "CONTRIBUTION"}
14601   ]
14602  },
14603  "SPI_SHADER_Z_FORMAT": {
14604   "fields": [
14605    {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"}
14606   ]
14607  },
14608  "SPI_VS_OUT_CONFIG": {
14609   "fields": [
14610    {"bits": [1, 5], "name": "VS_EXPORT_COUNT"},
14611    {"bits": [6, 6], "name": "VS_HALF_PACK"},
14612    {"bits": [7, 7], "name": "NO_PC_EXPORT"}
14613   ]
14614  },
14615  "SQC_CACHES": {
14616   "fields": [
14617    {"bits": [0, 0], "name": "TARGET_INST"},
14618    {"bits": [1, 1], "name": "TARGET_DATA"},
14619    {"bits": [2, 2], "name": "INVALIDATE"},
14620    {"bits": [3, 3], "name": "WRITEBACK"},
14621    {"bits": [4, 4], "name": "VOL"},
14622    {"bits": [16, 16], "name": "COMPLETE"},
14623    {"bits": [17, 18], "name": "L2_WB_POLICY"}
14624   ]
14625  },
14626  "SQC_WRITEBACK": {
14627   "fields": [
14628    {"bits": [0, 0], "name": "DWB"},
14629    {"bits": [1, 1], "name": "DIRTY"}
14630   ]
14631  },
14632  "SQ_PERFCOUNTER0_SELECT": {
14633   "fields": [
14634    {"bits": [0, 8], "name": "PERF_SEL"},
14635    {"bits": [12, 15], "name": "SQC_BANK_MASK"},
14636    {"bits": [20, 23], "name": "SPM_MODE"},
14637    {"bits": [28, 31], "name": "PERF_MODE"}
14638   ]
14639  },
14640  "SQ_PERFCOUNTER_CTRL": {
14641   "fields": [
14642    {"bits": [0, 0], "name": "PS_EN"},
14643    {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"},
14644    {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},
14645    {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"},
14646    {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},
14647    {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"},
14648    {"bits": [6, 6], "name": "CS_EN"},
14649    {"bits": [8, 9], "name": "CNTR_RATE"},
14650    {"bits": [13, 13], "name": "DISABLE_FLUSH"}
14651   ]
14652  },
14653  "SQ_PERFCOUNTER_CTRL2": {
14654   "fields": [
14655    {"bits": [0, 0], "name": "FORCE_EN"}
14656   ]
14657  },
14658  "SQ_THREAD_TRACE_BUF0_SIZE": {
14659   "fields": [
14660    {"bits": [0, 3], "name": "BASE_HI"},
14661    {"bits": [8, 29], "name": "SIZE"}
14662   ]
14663  },
14664  "SQ_THREAD_TRACE_CTRL": {
14665   "fields": [
14666    {"bits": [0, 1], "name": "MODE"},
14667    {"bits": [2, 2], "name": "ALL_VMID"},
14668    {"bits": [3, 3], "name": "CH_PERF_EN"},
14669    {"bits": [4, 4], "name": "INTERRUPT_EN"},
14670    {"bits": [5, 5], "name": "DOUBLE_BUFFER"},
14671    {"bits": [6, 8], "name": "HIWATER"},
14672    {"bits": [9, 9], "name": "REG_STALL_EN"},
14673    {"bits": [10, 10], "name": "SPI_STALL_EN"},
14674    {"bits": [11, 11], "name": "SQ_STALL_EN"},
14675    {"bits": [12, 12], "name": "REG_DROP_ON_STALL"},
14676    {"bits": [13, 13], "name": "UTIL_TIMER"},
14677    {"bits": [14, 15], "name": "WAVESTART_MODE"},
14678    {"bits": [16, 17], "name": "RT_FREQ"},
14679    {"bits": [18, 18], "name": "SYNC_COUNT_MARKERS"},
14680    {"bits": [19, 19], "name": "SYNC_COUNT_DRAWS"},
14681    {"bits": [30, 30], "name": "CAPTURE_ALL"},
14682    {"bits": [31, 31], "name": "DRAW_EVENT_EN"}
14683   ]
14684  },
14685  "SQ_THREAD_TRACE_MASK": {
14686   "fields": [
14687    {"bits": [0, 1], "name": "SIMD_SEL"},
14688    {"bits": [4, 7], "name": "WGP_SEL"},
14689    {"bits": [9, 9], "name": "SA_SEL"},
14690    {"bits": [10, 16], "name": "WTYPE_INCLUDE"}
14691   ]
14692  },
14693  "SQ_THREAD_TRACE_STATUS": {
14694   "fields": [
14695    {"bits": [0, 11], "name": "FINISH_PENDING"},
14696    {"bits": [12, 23], "name": "FINISH_DONE"},
14697    {"bits": [24, 24], "name": "UTC_ERR"},
14698    {"bits": [25, 25], "name": "BUSY"},
14699    {"bits": [26, 26], "name": "EVENT_CNTR_OVERFLOW"},
14700    {"bits": [27, 27], "name": "EVENT_CNTR_STALL"}
14701   ]
14702  },
14703  "SQ_THREAD_TRACE_TOKEN_MASK": {
14704   "fields": [
14705    {"bits": [0, 11], "enum_ref": "ThreadTraceTokenExclude", "name": "TOKEN_EXCLUDE"},
14706    {"bits": [16, 23], "enum_ref": "ThreadTraceRegInclude", "name": "REG_INCLUDE"},
14707    {"bits": [24, 25], "name": "INST_EXCLUDE"},
14708    {"bits": [31, 31], "name": "REG_DETAIL_ALL"}
14709   ]
14710  },
14711  "SQ_THREAD_TRACE_WPTR": {
14712   "fields": [
14713    {"bits": [0, 28], "name": "OFFSET"},
14714    {"bits": [31, 31], "name": "BUFFER_ID"}
14715   ]
14716  },
14717  "SQ_WAVE_GPR_ALLOC": {
14718   "fields": [
14719    {"bits": [0, 7], "name": "VGPR_BASE"},
14720    {"bits": [8, 15], "name": "VGPR_SIZE"},
14721    {"bits": [16, 23], "name": "SGPR_BASE"},
14722    {"bits": [24, 27], "name": "SGPR_SIZE"}
14723   ]
14724  },
14725  "SQ_WAVE_HW_ID1": {
14726   "fields": [
14727    {"bits": [0, 4], "name": "WAVE_ID"},
14728    {"bits": [8, 9], "name": "SIMD_ID"},
14729    {"bits": [10, 13], "name": "WGP_ID"},
14730    {"bits": [16, 16], "name": "SA_ID"},
14731    {"bits": [18, 19], "name": "SE_ID"}
14732   ]
14733  },
14734  "SQ_WAVE_HW_ID2": {
14735   "fields": [
14736    {"bits": [0, 3], "name": "QUEUE_ID"},
14737    {"bits": [4, 5], "name": "PIPE_ID"},
14738    {"bits": [8, 9], "name": "ME_ID"},
14739    {"bits": [12, 14], "name": "STATE_ID"},
14740    {"bits": [16, 20], "name": "WG_ID"},
14741    {"bits": [24, 27], "name": "VM_ID"},
14742    {"bits": [29, 30], "name": "COMPAT_LEVEL"}
14743   ]
14744  },
14745  "SQ_WAVE_HW_ID_LEGACY": {
14746   "fields": [
14747    {"bits": [0, 3], "name": "WAVE_ID"},
14748    {"bits": [4, 5], "name": "SIMD_ID"},
14749    {"bits": [6, 7], "name": "PIPE_ID"},
14750    {"bits": [8, 11], "name": "CU_ID"},
14751    {"bits": [12, 12], "name": "SH_ID"},
14752    {"bits": [13, 14], "name": "SE_ID"},
14753    {"bits": [15, 15], "name": "WAVE_ID_MSB"},
14754    {"bits": [16, 19], "name": "TG_ID"},
14755    {"bits": [20, 23], "name": "VM_ID"},
14756    {"bits": [24, 26], "name": "QUEUE_ID"},
14757    {"bits": [27, 29], "name": "STATE_ID"},
14758    {"bits": [30, 31], "name": "ME_ID"}
14759   ]
14760  },
14761  "SQ_WAVE_IB_DBG1": {
14762   "fields": [
14763    {"bits": [0, 0], "name": "XNACK_ERROR"},
14764    {"bits": [1, 1], "name": "XNACK"},
14765    {"bits": [2, 2], "name": "TA_NEED_RESET"},
14766    {"bits": [3, 3], "name": "XNACK_OVERRIDE"},
14767    {"bits": [4, 9], "name": "XCNT"},
14768    {"bits": [11, 16], "name": "QCNT"},
14769    {"bits": [18, 23], "name": "RCNT"},
14770    {"bits": [24, 24], "name": "WAVE_IDLE"},
14771    {"bits": [25, 31], "name": "MISC_CNT"}
14772   ]
14773  },
14774  "SQ_WAVE_IB_STS": {
14775   "fields": [
14776    {"bits": [0, 3], "name": "VM_CNT"},
14777    {"bits": [4, 6], "name": "EXP_CNT"},
14778    {"bits": [7, 7], "name": "LGKM_CNT_BIT4"},
14779    {"bits": [8, 11], "name": "LGKM_CNT"},
14780    {"bits": [12, 14], "name": "VALU_CNT"},
14781    {"bits": [15, 15], "name": "FIRST_REPLAY"},
14782    {"bits": [16, 21], "name": "RCNT"},
14783    {"bits": [22, 23], "name": "VM_CNT_HI"},
14784    {"bits": [24, 24], "name": "LGKM_CNT_BIT5"},
14785    {"bits": [25, 25], "name": "REPLAY_W64H"},
14786    {"bits": [26, 31], "name": "VS_CNT"}
14787   ]
14788  },
14789  "SQ_WAVE_IB_STS2": {
14790   "fields": [
14791    {"bits": [0, 1], "name": "INST_PREFETCH"},
14792    {"bits": [7, 7], "name": "RESOURCE_OVERRIDE"},
14793    {"bits": [8, 9], "name": "MEM_ORDER"},
14794    {"bits": [10, 10], "name": "FWD_PROGRESS"},
14795    {"bits": [11, 11], "name": "WAVE64"},
14796    {"bits": [12, 12], "name": "WAVE64HI"},
14797    {"bits": [13, 13], "name": "SUBV_LOOP"}
14798   ]
14799  },
14800  "SQ_WAVE_LDS_ALLOC": {
14801   "fields": [
14802    {"bits": [0, 8], "name": "LDS_BASE"},
14803    {"bits": [12, 20], "name": "LDS_SIZE"},
14804    {"bits": [24, 27], "name": "VGPR_SHARED_SIZE"}
14805   ]
14806  },
14807  "SQ_WAVE_MODE": {
14808   "fields": [
14809    {"bits": [0, 3], "name": "FP_ROUND"},
14810    {"bits": [4, 7], "name": "FP_DENORM"},
14811    {"bits": [8, 8], "name": "DX10_CLAMP"},
14812    {"bits": [9, 9], "name": "IEEE"},
14813    {"bits": [10, 10], "name": "LOD_CLAMPED"},
14814    {"bits": [12, 20], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14815    {"bits": [23, 23], "name": "FP16_OVFL"},
14816    {"bits": [27, 27], "name": "DISABLE_PERF"},
14817    {"bits": [28, 28], "name": "VSKIP"},
14818    {"bits": [29, 31], "name": "CSP"}
14819   ]
14820  },
14821  "SQ_WAVE_PC_HI": {
14822   "fields": [
14823    {"bits": [0, 15], "name": "PC_HI"}
14824   ]
14825  },
14826  "SQ_WAVE_POPS_PACKER": {
14827   "fields": [
14828    {"bits": [0, 0], "name": "POPS_EN"},
14829    {"bits": [1, 2], "name": "POPS_PACKER_ID"}
14830   ]
14831  },
14832  "SQ_WAVE_SCHED_MODE": {
14833   "fields": [
14834    {"bits": [0, 1], "name": "DEP_MODE"}
14835   ]
14836  },
14837  "SQ_WAVE_STATUS": {
14838   "fields": [
14839    {"bits": [0, 0], "name": "SCC"},
14840    {"bits": [1, 2], "name": "SPI_PRIO"},
14841    {"bits": [3, 4], "name": "USER_PRIO"},
14842    {"bits": [5, 5], "name": "PRIV"},
14843    {"bits": [6, 6], "name": "TRAP_EN"},
14844    {"bits": [7, 7], "name": "TTRACE_EN"},
14845    {"bits": [8, 8], "name": "EXPORT_RDY"},
14846    {"bits": [9, 9], "name": "EXECZ"},
14847    {"bits": [10, 10], "name": "VCCZ"},
14848    {"bits": [11, 11], "name": "IN_TG"},
14849    {"bits": [12, 12], "name": "IN_BARRIER"},
14850    {"bits": [13, 13], "name": "HALT"},
14851    {"bits": [14, 14], "name": "TRAP"},
14852    {"bits": [15, 15], "name": "TTRACE_SIMD_EN"},
14853    {"bits": [16, 16], "name": "VALID"},
14854    {"bits": [17, 17], "name": "ECC_ERR"},
14855    {"bits": [18, 18], "name": "SKIP_EXPORT"},
14856    {"bits": [19, 19], "name": "PERF_EN"},
14857    {"bits": [23, 23], "name": "FATAL_HALT"},
14858    {"bits": [27, 27], "name": "MUST_EXPORT"}
14859   ]
14860  },
14861  "SQ_WAVE_TRAPSTS": {
14862   "fields": [
14863    {"bits": [0, 8], "enum_ref": "EXCP_EN", "name": "EXCP"},
14864    {"bits": [10, 10], "name": "SAVECTX"},
14865    {"bits": [11, 11], "name": "ILLEGAL_INST"},
14866    {"bits": [12, 14], "name": "EXCP_HI"},
14867    {"bits": [15, 15], "name": "BUFFER_OOB"},
14868    {"bits": [16, 19], "name": "EXCP_CYCLE"},
14869    {"bits": [20, 23], "name": "EXCP_GROUP_MASK"},
14870    {"bits": [24, 24], "name": "EXCP_WAVE64HI"},
14871    {"bits": [28, 28], "name": "XNACK_ERROR"},
14872    {"bits": [29, 31], "name": "DP_RATE"}
14873   ]
14874  },
14875  "SQ_WAVE_VGPR_OFFSET": {
14876   "fields": [
14877    {"bits": [0, 5], "name": "SRC0"},
14878    {"bits": [6, 11], "name": "SRC1"},
14879    {"bits": [12, 17], "name": "SRC2"},
14880    {"bits": [18, 23], "name": "DST"}
14881   ]
14882  },
14883  "SX_BLEND_OPT_CONTROL": {
14884   "fields": [
14885    {"bits": [0, 0], "name": "MRT0_COLOR_OPT_DISABLE"},
14886    {"bits": [1, 1], "name": "MRT0_ALPHA_OPT_DISABLE"},
14887    {"bits": [4, 4], "name": "MRT1_COLOR_OPT_DISABLE"},
14888    {"bits": [5, 5], "name": "MRT1_ALPHA_OPT_DISABLE"},
14889    {"bits": [8, 8], "name": "MRT2_COLOR_OPT_DISABLE"},
14890    {"bits": [9, 9], "name": "MRT2_ALPHA_OPT_DISABLE"},
14891    {"bits": [12, 12], "name": "MRT3_COLOR_OPT_DISABLE"},
14892    {"bits": [13, 13], "name": "MRT3_ALPHA_OPT_DISABLE"},
14893    {"bits": [16, 16], "name": "MRT4_COLOR_OPT_DISABLE"},
14894    {"bits": [17, 17], "name": "MRT4_ALPHA_OPT_DISABLE"},
14895    {"bits": [20, 20], "name": "MRT5_COLOR_OPT_DISABLE"},
14896    {"bits": [21, 21], "name": "MRT5_ALPHA_OPT_DISABLE"},
14897    {"bits": [24, 24], "name": "MRT6_COLOR_OPT_DISABLE"},
14898    {"bits": [25, 25], "name": "MRT6_ALPHA_OPT_DISABLE"},
14899    {"bits": [28, 28], "name": "MRT7_COLOR_OPT_DISABLE"},
14900    {"bits": [29, 29], "name": "MRT7_ALPHA_OPT_DISABLE"},
14901    {"bits": [31, 31], "name": "PIXEN_ZERO_OPT_DISABLE"}
14902   ]
14903  },
14904  "SX_BLEND_OPT_EPSILON": {
14905   "fields": [
14906    {"bits": [0, 3], "enum_ref": "SX_BLEND_OPT_EPSILON__MRT0_EPSILON", "name": "MRT0_EPSILON"},
14907    {"bits": [4, 7], "name": "MRT1_EPSILON"},
14908    {"bits": [8, 11], "name": "MRT2_EPSILON"},
14909    {"bits": [12, 15], "name": "MRT3_EPSILON"},
14910    {"bits": [16, 19], "name": "MRT4_EPSILON"},
14911    {"bits": [20, 23], "name": "MRT5_EPSILON"},
14912    {"bits": [24, 27], "name": "MRT6_EPSILON"},
14913    {"bits": [28, 31], "name": "MRT7_EPSILON"}
14914   ]
14915  },
14916  "SX_MRT0_BLEND_OPT": {
14917   "fields": [
14918    {"bits": [0, 2], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_SRC_OPT"},
14919    {"bits": [4, 6], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_DST_OPT"},
14920    {"bits": [8, 10], "enum_ref": "SX_OPT_COMB_FCN", "name": "COLOR_COMB_FCN"},
14921    {"bits": [16, 18], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_SRC_OPT"},
14922    {"bits": [20, 22], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_DST_OPT"},
14923    {"bits": [24, 26], "enum_ref": "SX_OPT_COMB_FCN", "name": "ALPHA_COMB_FCN"}
14924   ]
14925  },
14926  "SX_PERFCOUNTER0_SELECT": {
14927   "fields": [
14928    {"bits": [0, 9], "name": "PERFCOUNTER_SELECT"},
14929    {"bits": [10, 19], "name": "PERFCOUNTER_SELECT1"},
14930    {"bits": [20, 23], "name": "CNTR_MODE"}
14931   ]
14932  },
14933  "SX_PERFCOUNTER0_SELECT1": {
14934   "fields": [
14935    {"bits": [0, 9], "name": "PERFCOUNTER_SELECT2"},
14936    {"bits": [10, 19], "name": "PERFCOUNTER_SELECT3"}
14937   ]
14938  },
14939  "SX_PS_DOWNCONVERT": {
14940   "fields": [
14941    {"bits": [0, 3], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT0"},
14942    {"bits": [4, 7], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT1"},
14943    {"bits": [8, 11], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT2"},
14944    {"bits": [12, 15], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT3"},
14945    {"bits": [16, 19], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT4"},
14946    {"bits": [20, 23], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT5"},
14947    {"bits": [24, 27], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT6"},
14948    {"bits": [28, 31], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT7"}
14949   ]
14950  },
14951  "TA_BC_BASE_ADDR_HI": {
14952   "fields": [
14953    {"bits": [0, 7], "name": "ADDRESS"}
14954   ]
14955  },
14956  "TA_PERFCOUNTER0_SELECT": {
14957   "fields": [
14958    {"bits": [0, 7], "name": "PERF_SEL"},
14959    {"bits": [10, 17], "name": "PERF_SEL1"},
14960    {"bits": [20, 23], "name": "CNTR_MODE"},
14961    {"bits": [24, 27], "name": "PERF_MODE1"},
14962    {"bits": [28, 31], "name": "PERF_MODE"}
14963   ]
14964  },
14965  "TA_PERFCOUNTER0_SELECT1": {
14966   "fields": [
14967    {"bits": [0, 7], "name": "PERF_SEL2"},
14968    {"bits": [10, 17], "name": "PERF_SEL3"},
14969    {"bits": [24, 27], "name": "PERF_MODE3"},
14970    {"bits": [28, 31], "name": "PERF_MODE2"}
14971   ]
14972  },
14973  "TA_PERFCOUNTER1_SELECT": {
14974   "fields": [
14975    {"bits": [0, 7], "name": "PERF_SEL"},
14976    {"bits": [20, 23], "name": "CNTR_MODE"},
14977    {"bits": [28, 31], "name": "PERF_MODE"}
14978   ]
14979  },
14980  "TCP_PERFCOUNTER2_SELECT": {
14981   "fields": [
14982    {"bits": [0, 9], "name": "PERF_SEL"},
14983    {"bits": [20, 23], "name": "CNTR_MODE"},
14984    {"bits": [28, 31], "name": "PERF_MODE"}
14985   ]
14986  },
14987  "UTCL1_PERFCOUNTER0_SELECT": {
14988   "fields": [
14989    {"bits": [0, 9], "name": "PERF_SEL"},
14990    {"bits": [28, 31], "name": "COUNTER_MODE"}
14991   ]
14992  },
14993  "VGT_DMA_BASE_HI": {
14994   "fields": [
14995    {"bits": [0, 15], "name": "BASE_ADDR"}
14996   ]
14997  },
14998  "VGT_DMA_INDEX_TYPE": {
14999   "fields": [
15000    {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"},
15001    {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"},
15002    {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"},
15003    {"bits": [6, 7], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"},
15004    {"bits": [8, 8], "name": "ATC"},
15005    {"bits": [9, 9], "name": "NOT_EOP"},
15006    {"bits": [10, 10], "name": "REQ_PATH"},
15007    {"bits": [11, 13], "name": "MTYPE"}
15008   ]
15009  },
15010  "VGT_DRAW_INITIATOR": {
15011   "fields": [
15012    {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"},
15013    {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"},
15014    {"bits": [4, 4], "name": "SPRITE_EN_R6XX"},
15015    {"bits": [5, 5], "name": "NOT_EOP"},
15016    {"bits": [6, 6], "name": "USE_OPAQUE"},
15017    {"bits": [7, 7], "name": "UNROLLED_INST"},
15018    {"bits": [8, 8], "name": "GRBM_SKEW_NO_DEC"},
15019    {"bits": [29, 31], "name": "REG_RT_INDEX"}
15020   ]
15021  },
15022  "VGT_DRAW_PAYLOAD_CNTL": {
15023   "fields": [
15024    {"bits": [0, 0], "name": "OBJPRIM_ID_EN"},
15025    {"bits": [1, 1], "name": "EN_REG_RT_INDEX"},
15026    {"bits": [2, 2], "name": "OBJECT_ID_INST_EN"},
15027    {"bits": [3, 3], "name": "EN_PRIM_PAYLOAD"},
15028    {"bits": [4, 4], "name": "EN_DRAW_VP"}
15029   ]
15030  },
15031  "VGT_ESGS_RING_ITEMSIZE": {
15032   "fields": [
15033    {"bits": [0, 14], "name": "ITEMSIZE"}
15034   ]
15035  },
15036  "VGT_ES_PER_GS": {
15037   "fields": [
15038    {"bits": [0, 10], "name": "ES_PER_GS"}
15039   ]
15040  },
15041  "VGT_EVENT_ADDRESS_REG": {
15042   "fields": [
15043    {"bits": [0, 27], "name": "ADDRESS_LOW"}
15044   ]
15045  },
15046  "VGT_EVENT_INITIATOR": {
15047   "fields": [
15048    {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"},
15049    {"bits": [10, 26], "name": "ADDRESS_HI"},
15050    {"bits": [27, 27], "name": "EXTENDED_EVENT"}
15051   ]
15052  },
15053  "VGT_GROUP_DECR": {
15054   "fields": [
15055    {"bits": [0, 3], "name": "DECR"}
15056   ]
15057  },
15058  "VGT_GROUP_FIRST_DECR": {
15059   "fields": [
15060    {"bits": [0, 3], "name": "FIRST_DECR"}
15061   ]
15062  },
15063  "VGT_GROUP_PRIM_TYPE": {
15064   "fields": [
15065    {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"},
15066    {"bits": [14, 14], "name": "RETAIN_ORDER"},
15067    {"bits": [15, 15], "name": "RETAIN_QUADS"},
15068    {"bits": [16, 18], "name": "PRIM_ORDER"}
15069   ]
15070  },
15071  "VGT_GROUP_VECT_0_CNTL": {
15072   "fields": [
15073    {"bits": [0, 0], "name": "COMP_X_EN"},
15074    {"bits": [1, 1], "name": "COMP_Y_EN"},
15075    {"bits": [2, 2], "name": "COMP_Z_EN"},
15076    {"bits": [3, 3], "name": "COMP_W_EN"},
15077    {"bits": [8, 15], "name": "STRIDE"},
15078    {"bits": [16, 23], "name": "SHIFT"}
15079   ]
15080  },
15081  "VGT_GROUP_VECT_0_FMT_CNTL": {
15082   "fields": [
15083    {"bits": [0, 3], "name": "X_CONV"},
15084    {"bits": [4, 7], "name": "X_OFFSET"},
15085    {"bits": [8, 11], "name": "Y_CONV"},
15086    {"bits": [12, 15], "name": "Y_OFFSET"},
15087    {"bits": [16, 19], "name": "Z_CONV"},
15088    {"bits": [20, 23], "name": "Z_OFFSET"},
15089    {"bits": [24, 27], "name": "W_CONV"},
15090    {"bits": [28, 31], "name": "W_OFFSET"}
15091   ]
15092  },
15093  "VGT_GSVS_RING_OFFSET_1": {
15094   "fields": [
15095    {"bits": [0, 14], "name": "OFFSET"}
15096   ]
15097  },
15098  "VGT_GS_INSTANCE_CNT": {
15099   "fields": [
15100    {"bits": [0, 0], "name": "ENABLE"},
15101    {"bits": [2, 8], "name": "CNT"},
15102    {"bits": [31, 31], "name": "EN_MAX_VERT_OUT_PER_GS_INSTANCE"}
15103   ]
15104  },
15105  "VGT_GS_MAX_VERT_OUT": {
15106   "fields": [
15107    {"bits": [0, 10], "name": "MAX_VERT_OUT"}
15108   ]
15109  },
15110  "VGT_GS_MODE": {
15111   "fields": [
15112    {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"},
15113    {"bits": [3, 3], "name": "RESERVED_0"},
15114    {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"},
15115    {"bits": [6, 10], "name": "RESERVED_1"},
15116    {"bits": [11, 11], "name": "GS_C_PACK_EN"},
15117    {"bits": [12, 12], "name": "RESERVED_2"},
15118    {"bits": [13, 13], "name": "ES_PASSTHRU"},
15119    {"bits": [14, 14], "name": "COMPUTE_MODE"},
15120    {"bits": [15, 15], "name": "FAST_COMPUTE_MODE"},
15121    {"bits": [16, 16], "name": "ELEMENT_INFO_EN"},
15122    {"bits": [17, 17], "name": "PARTIAL_THD_AT_EOI"},
15123    {"bits": [18, 18], "name": "SUPPRESS_CUTS"},
15124    {"bits": [19, 19], "name": "ES_WRITE_OPTIMIZE"},
15125    {"bits": [20, 20], "name": "GS_WRITE_OPTIMIZE"},
15126    {"bits": [21, 22], "name": "ONCHIP"}
15127   ]
15128  },
15129  "VGT_GS_ONCHIP_CNTL": {
15130   "fields": [
15131    {"bits": [0, 10], "name": "ES_VERTS_PER_SUBGRP"},
15132    {"bits": [11, 21], "name": "GS_PRIMS_PER_SUBGRP"},
15133    {"bits": [22, 31], "name": "GS_INST_PRIMS_IN_SUBGRP"}
15134   ]
15135  },
15136  "VGT_GS_OUT_PRIM_TYPE": {
15137   "fields": [
15138    {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"},
15139    {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"},
15140    {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"},
15141    {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"},
15142    {"bits": [31, 31], "name": "UNIQUE_TYPE_PER_STREAM"}
15143   ]
15144  },
15145  "VGT_GS_PER_ES": {
15146   "fields": [
15147    {"bits": [0, 10], "name": "GS_PER_ES"}
15148   ]
15149  },
15150  "VGT_GS_PER_VS": {
15151   "fields": [
15152    {"bits": [0, 3], "name": "GS_PER_VS"}
15153   ]
15154  },
15155  "VGT_HOS_CNTL": {
15156   "fields": [
15157    {"bits": [0, 1], "name": "TESS_MODE"}
15158   ]
15159  },
15160  "VGT_HOS_REUSE_DEPTH": {
15161   "fields": [
15162    {"bits": [0, 7], "name": "REUSE_DEPTH"}
15163   ]
15164  },
15165  "VGT_HS_OFFCHIP_PARAM": {
15166   "fields": [
15167    {"bits": [0, 8], "name": "OFFCHIP_BUFFERING"},
15168    {"bits": [9, 10], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP_GRANULARITY"}
15169   ]
15170  },
15171  "VGT_LS_HS_CONFIG": {
15172   "fields": [
15173    {"bits": [0, 7], "name": "NUM_PATCHES"},
15174    {"bits": [8, 13], "name": "HS_NUM_INPUT_CP"},
15175    {"bits": [14, 19], "name": "HS_NUM_OUTPUT_CP"}
15176   ]
15177  },
15178  "VGT_MULTI_PRIM_IB_RESET_EN": {
15179   "fields": [
15180    {"bits": [0, 0], "name": "RESET_EN"},
15181    {"bits": [1, 1], "name": "MATCH_ALL_BITS"}
15182   ]
15183  },
15184  "VGT_OUTPUT_PATH_CNTL": {
15185   "fields": [
15186    {"bits": [0, 2], "name": "PATH_SELECT"}
15187   ]
15188  },
15189  "VGT_OUT_DEALLOC_CNTL": {
15190   "fields": [
15191    {"bits": [0, 6], "name": "DEALLOC_DIST"}
15192   ]
15193  },
15194  "VGT_PRIMITIVEID_EN": {
15195   "fields": [
15196    {"bits": [0, 0], "name": "PRIMITIVEID_EN"},
15197    {"bits": [1, 1], "name": "DISABLE_RESET_ON_EOI"},
15198    {"bits": [2, 2], "name": "NGG_DISABLE_PROVOK_REUSE"}
15199   ]
15200  },
15201  "VGT_PRIMITIVE_TYPE": {
15202   "fields": [
15203    {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}
15204   ]
15205  },
15206  "VGT_REUSE_OFF": {
15207   "fields": [
15208    {"bits": [0, 0], "name": "REUSE_OFF"}
15209   ]
15210  },
15211  "VGT_SHADER_STAGES_EN": {
15212   "fields": [
15213    {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"},
15214    {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},
15215    {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"},
15216    {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},
15217    {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"},
15218    {"bits": [8, 8], "name": "DYNAMIC_HS"},
15219    {"bits": [9, 9], "name": "DISPATCH_DRAW_EN"},
15220    {"bits": [10, 10], "name": "DIS_DEALLOC_ACCUM_0"},
15221    {"bits": [11, 11], "name": "DIS_DEALLOC_ACCUM_1"},
15222    {"bits": [12, 12], "name": "VS_WAVE_ID_EN"},
15223    {"bits": [13, 13], "name": "PRIMGEN_EN"},
15224    {"bits": [14, 14], "name": "ORDERED_ID_MODE"},
15225    {"bits": [15, 18], "name": "MAX_PRIMGRP_IN_WAVE"},
15226    {"bits": [19, 20], "name": "GS_FAST_LAUNCH"},
15227    {"bits": [21, 21], "name": "HS_W32_EN"},
15228    {"bits": [22, 22], "name": "GS_W32_EN"},
15229    {"bits": [23, 23], "name": "VS_W32_EN"},
15230    {"bits": [24, 24], "name": "NGG_WAVE_ID_EN"},
15231    {"bits": [25, 25], "name": "PRIMGEN_PASSTHRU_EN"}
15232   ]
15233  },
15234  "VGT_STRMOUT_BUFFER_CONFIG": {
15235   "fields": [
15236    {"bits": [0, 3], "name": "STREAM_0_BUFFER_EN"},
15237    {"bits": [4, 7], "name": "STREAM_1_BUFFER_EN"},
15238    {"bits": [8, 11], "name": "STREAM_2_BUFFER_EN"},
15239    {"bits": [12, 15], "name": "STREAM_3_BUFFER_EN"}
15240   ]
15241  },
15242  "VGT_STRMOUT_CONFIG": {
15243   "fields": [
15244    {"bits": [0, 0], "name": "STREAMOUT_0_EN"},
15245    {"bits": [1, 1], "name": "STREAMOUT_1_EN"},
15246    {"bits": [2, 2], "name": "STREAMOUT_2_EN"},
15247    {"bits": [3, 3], "name": "STREAMOUT_3_EN"},
15248    {"bits": [4, 6], "name": "RAST_STREAM"},
15249    {"bits": [7, 7], "name": "EN_PRIMS_NEEDED_CNT"},
15250    {"bits": [8, 11], "name": "RAST_STREAM_MASK"},
15251    {"bits": [31, 31], "name": "USE_RAST_STREAM_MASK"}
15252   ]
15253  },
15254  "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE": {
15255   "fields": [
15256    {"bits": [0, 8], "name": "VERTEX_STRIDE"}
15257   ]
15258  },
15259  "VGT_STRMOUT_VTX_STRIDE_0": {
15260   "fields": [
15261    {"bits": [0, 9], "name": "STRIDE"}
15262   ]
15263  },
15264  "VGT_TESS_DISTRIBUTION": {
15265   "fields": [
15266    {"bits": [0, 7], "name": "ACCUM_ISOLINE"},
15267    {"bits": [8, 15], "name": "ACCUM_TRI"},
15268    {"bits": [16, 23], "name": "ACCUM_QUAD"},
15269    {"bits": [24, 28], "name": "DONUT_SPLIT"},
15270    {"bits": [29, 31], "name": "TRAP_SPLIT"}
15271   ]
15272  },
15273  "VGT_TF_PARAM": {
15274   "fields": [
15275    {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"},
15276    {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"},
15277    {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"},
15278    {"bits": [8, 8], "name": "RESERVED_REDUC_AXIS"},
15279    {"bits": [9, 9], "name": "DEPRECATED"},
15280    {"bits": [10, 13], "name": "NUM_DS_WAVES_PER_SIMD"},
15281    {"bits": [14, 14], "name": "DISABLE_DONUTS"},
15282    {"bits": [15, 16], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"},
15283    {"bits": [17, 18], "enum_ref": "VGT_DIST_MODE", "name": "DISTRIBUTION_MODE"},
15284    {"bits": [19, 19], "enum_ref": "VGT_DETECT_ONE", "name": "DETECT_ONE"},
15285    {"bits": [20, 20], "enum_ref": "VGT_DETECT_ZERO", "name": "DETECT_ZERO"},
15286    {"bits": [23, 25], "name": "MTYPE"}
15287   ]
15288  },
15289  "VGT_TF_RING_SIZE": {
15290   "fields": [
15291    {"bits": [0, 15], "name": "SIZE"}
15292   ]
15293  },
15294  "VGT_VERTEX_REUSE_BLOCK_CNTL": {
15295   "fields": [
15296    {"bits": [0, 7], "name": "VTX_REUSE_DEPTH"}
15297   ]
15298  },
15299  "VGT_VTX_CNT_EN": {
15300   "fields": [
15301    {"bits": [0, 0], "name": "VTX_CNT_EN"}
15302   ]
15303  }
15304 }
15305}
15306