1/* 2 * Copyright © 2020 Valve Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24#include "helpers.h" 25#include <stdarg.h> 26 27using namespace aco; 28 29BEGIN_TEST(validate.sdwa.allow) 30 for (unsigned i = GFX8; i <= GFX10; i++) { 31 //>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm 32 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) 33 continue; 34 //>> Validation results: 35 //! Validation passed 36 37 SDWA_instruction *sdwa = &bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]).instr->sdwa(); 38 sdwa->neg[0] = sdwa->neg[1] = sdwa->abs[0] = sdwa->abs[1] = true; 39 40 sdwa = &bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1b), inputs[0], inputs[1]).instr->sdwa(); 41 42 sdwa = &bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]).instr->sdwa(); 43 sdwa->sel[0] = SubdwordSel::sbyte2; 44 sdwa->sel[1] = SubdwordSel::uword1; 45 46 finish_validator_test(); 47 } 48END_TEST 49 50BEGIN_TEST(validate.sdwa.support) 51 for (unsigned i = GFX7; i <= GFX11; i++) { 52 //>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm 53 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) 54 continue; 55 //>> Validation results: 56 57 //~gfx(7|11)! SDWA is GFX8 to GFX10.3 only: v1: %t0 = v_mul_f32 %a, %b dst_sel:dword src0_sel:dword src1_sel:dword 58 //~gfx(7|11)! Validation failed 59 //~gfx([89]|10)! Validation passed 60 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 61 62 finish_validator_test(); 63 } 64END_TEST 65 66BEGIN_TEST(validate.sdwa.operands) 67 for (unsigned i = GFX8; i <= GFX10; i++) { 68 //>> v1: %vgpr0, v1: %vgp1, s1: %sgpr0, s1: %sgpr1 = p_startpgm 69 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) 70 continue; 71 //>> Validation results: 72 73 //~gfx8! Wrong source position for SGPR argument: v1: %_ = v_mul_f32 %sgpr0, %vgpr1 dst_sel:dword src0_sel:dword src1_sel:dword 74 //~gfx8! Wrong source position for SGPR argument: v1: %_ = v_mul_f32 %vgpr0, %sgpr1 dst_sel:dword src0_sel:dword src1_sel:dword 75 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[2], inputs[1]); 76 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[3]); 77 78 //~gfx8! Wrong source position for constant argument: v1: %_ = v_mul_f32 4, %vgpr1 dst_sel:dword src0_sel:dword src1_sel:dword 79 //~gfx8! Wrong source position for constant argument: v1: %_ = v_mul_f32 %vgpr0, 4 dst_sel:dword src0_sel:dword src1_sel:dword 80 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), Operand::c32(4u), inputs[1]); 81 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], Operand::c32(4u)); 82 83 //! Literal applied on wrong instruction format: v1: %_ = v_mul_f32 0x1234, %vgpr1 dst_sel:dword src0_sel:dword src1_sel:dword 84 //! Literal applied on wrong instruction format: v1: %_ = v_mul_f32 %vgpr0, 0x1234 dst_sel:dword src0_sel:dword src1_sel:dword 85 //! Wrong source position for Literal argument: v1: %_ = v_mul_f32 %vgpr0, 0x1234 dst_sel:dword src0_sel:dword src1_sel:dword 86 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), Operand::c32(0x1234u), inputs[1]); 87 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], Operand::c32(0x1234u)); 88 89 //! Validation failed 90 91 finish_validator_test(); 92 } 93END_TEST 94 95BEGIN_TEST(validate.sdwa.vopc) 96 for (unsigned i = GFX8; i <= GFX10; i++) { 97 //>> v1: %vgpr0, v1: %vgp1, s1: %sgpr0, s1: %sgpr1 = p_startpgm 98 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) 99 continue; 100 //>> Validation results: 101 102 bld.vopc_sdwa(aco_opcode::v_cmp_gt_f32, bld.def(bld.lm, vcc), inputs[0], inputs[1]); 103 104 //~gfx8! SDWA+VOPC definition must be fixed to vcc on GFX8: s2: %_ = v_cmp_lt_f32 %vgpr0, %vgpr1 src0_sel:dword src1_sel:dword 105 bld.vopc_sdwa(aco_opcode::v_cmp_lt_f32, bld.def(bld.lm), inputs[0], inputs[1]); 106 107 //~gfx(9|10)! SDWA VOPC clamp only supported on GFX8: s2: %_:vcc = v_cmp_eq_f32 %vgpr0, %vgpr1 clamp src0_sel:dword src1_sel:dword 108 bld.vopc_sdwa(aco_opcode::v_cmp_eq_f32, bld.def(bld.lm, vcc), inputs[0], inputs[1]).instr->sdwa().clamp = true; 109 110 //! Validation failed 111 112 finish_validator_test(); 113 } 114END_TEST 115 116BEGIN_TEST(validate.sdwa.omod) 117 for (unsigned i = GFX8; i <= GFX10; i++) { 118 //>> v1: %vgpr0, v1: %vgp1, s1: %sgpr0, s1: %sgpr1 = p_startpgm 119 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) 120 continue; 121 //>> Validation results: 122 123 //~gfx8! SDWA omod only supported on GFX9+: v1: %_ = v_mul_f32 %vgpr0, %vgpr1 *2 dst_sel:dword src0_sel:dword src1_sel:dword 124 //~gfx8! Validation failed 125 //~gfx(9|10)! Validation passed 126 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]).instr->sdwa().omod = 1; 127 128 finish_validator_test(); 129 } 130END_TEST 131 132BEGIN_TEST(validate.sdwa.vcc) 133 for (unsigned i = GFX8; i <= GFX10; i++) { 134 //>> v1: %vgpr0, v1: %vgpr1, s2: %sgpr0 = p_startpgm 135 if (!setup_cs("v1 v1 s2", (amd_gfx_level)i)) 136 continue; 137 //>> Validation results: 138 139 //! 3rd operand must be fixed to vcc with SDWA: v1: %_ = v_cndmask_b32 %vgpr0, %vgpr1, %_ dst_sel:dword src0_sel:dword src1_sel:dword 140 bld.vop2_sdwa(aco_opcode::v_cndmask_b32, bld.def(v1), inputs[0], inputs[1], inputs[2]); 141 bld.vop2_sdwa(aco_opcode::v_cndmask_b32, bld.def(v1), inputs[0], inputs[1], bld.vcc(inputs[2])); 142 143 //! 2nd definition must be fixed to vcc with SDWA: v1: %_, s2: %_ = v_add_co_u32 %vgpr0, %vgpr1 dst_sel:dword src0_sel:dword src1_sel:dword 144 bld.vop2_sdwa(aco_opcode::v_add_co_u32, bld.def(v1), bld.def(bld.lm), inputs[0], inputs[1]); 145 bld.vop2_sdwa(aco_opcode::v_add_co_u32, bld.def(v1), bld.def(bld.lm, vcc), inputs[0], inputs[1]); 146 147 //! Validation failed 148 149 finish_validator_test(); 150 } 151END_TEST 152 153BEGIN_TEST(optimize.sdwa.extract) 154 for (unsigned i = GFX7; i <= GFX10; i++) { 155 for (unsigned is_signed = 0; is_signed <= 1; is_signed++) { 156 //>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm 157 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i, CHIP_UNKNOWN, is_signed ? "_signed" : "_unsigned")) 158 continue; 159 160 //; def standard_test(index, sel): 161 //; res = 'v1: %%res%s = v_mul_f32 %%a, %%b dst_sel:dword src0_sel:dword src1_sel:%c%s\n' % (index, 's' if variant.endswith('_signed') else 'u', sel) 162 //; res += 'p_unit_test %s, %%res%s' % (index, index) 163 //; return res 164 //; funcs['standard_test'] = lambda a: standard_test(*(v for v in a.split(','))) 165 166 aco_opcode ext = aco_opcode::p_extract; 167 aco_opcode ins = aco_opcode::p_insert; 168 169 { 170 //~gfx[^7].*! @standard_test(0,byte0) 171 Temp bfe_byte0_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(8u), 172 Operand::c32(is_signed)); 173 writeout(0, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfe_byte0_b)); 174 175 //~gfx[^7].*! @standard_test(1,byte1) 176 Temp bfe_byte1_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(1u), Operand::c32(8u), 177 Operand::c32(is_signed)); 178 writeout(1, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfe_byte1_b)); 179 180 //~gfx[^7].*! @standard_test(2,byte2) 181 Temp bfe_byte2_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(2u), Operand::c32(8u), 182 Operand::c32(is_signed)); 183 writeout(2, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfe_byte2_b)); 184 185 //~gfx[^7].*! @standard_test(3,byte3) 186 Temp bfe_byte3_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(3u), Operand::c32(8u), 187 Operand::c32(is_signed)); 188 writeout(3, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfe_byte3_b)); 189 190 //~gfx[^7].*! @standard_test(4,word0) 191 Temp bfe_word0_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(16u), 192 Operand::c32(is_signed)); 193 writeout(4, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfe_word0_b)); 194 195 //~gfx[^7].*! @standard_test(5,word1) 196 Temp bfe_word1_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(1u), 197 Operand::c32(16u), Operand::c32(is_signed)); 198 writeout(5, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfe_word1_b)); 199 200 //~gfx[^7]_unsigned! @standard_test(6,byte0) 201 Temp bfi_byte0_b = bld.pseudo(ins, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(8u)); 202 writeout(6, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfi_byte0_b)); 203 204 //~gfx[^7]_unsigned! @standard_test(7,word0) 205 Temp bfi_word0_b = 206 bld.pseudo(ins, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(16u)); 207 writeout(7, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfi_word0_b)); 208 } 209 210 //>> p_unit_test 63 211 writeout(63); 212 213 { 214 //! v1: %tmp8 = p_insert %b, 1, 8 215 //! v1: %res8 = v_mul_f32 %a, %tmp8 216 //! p_unit_test 8, %res8 217 Temp bfi_byte1_b = 218 bld.pseudo(ins, bld.def(v1), inputs[1], Operand::c32(1u), Operand::c32(8u)); 219 writeout(8, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfi_byte1_b)); 220 221 /* v_cvt_f32_ubyte[0-3] can be used instead of v_cvt_f32_u32+sdwa */ 222 //~gfx7_signed! v1: %bfe_byte0_b = p_extract %b, 0, 8, 1 223 //~gfx7_signed! v1: %res9 = v_cvt_f32_u32 %bfe_byte0_b 224 //~gfx[^7]+_signed! v1: %res9 = v_cvt_f32_u32 %b dst_sel:dword src0_sel:sbyte0 225 //~gfx\d+_unsigned! v1: %res9 = v_cvt_f32_ubyte0 %b 226 //! p_unit_test 9, %res9 227 Temp bfe_byte0_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(8u), 228 Operand::c32(is_signed)); 229 writeout(9, bld.vop1(aco_opcode::v_cvt_f32_u32, bld.def(v1), bfe_byte0_b)); 230 231 //~gfx7_signed! v1: %bfe_byte1_b = p_extract %b, 1, 8, 1 232 //~gfx7_signed! v1: %res10 = v_cvt_f32_u32 %bfe_byte1_b 233 //~gfx[^7]+_signed! v1: %res10 = v_cvt_f32_u32 %b dst_sel:dword src0_sel:sbyte1 234 //~gfx\d+_unsigned! v1: %res10 = v_cvt_f32_ubyte1 %b 235 //! p_unit_test 10, %res10 236 Temp bfe_byte1_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(1u), Operand::c32(8u), 237 Operand::c32(is_signed)); 238 writeout(10, bld.vop1(aco_opcode::v_cvt_f32_u32, bld.def(v1), bfe_byte1_b)); 239 240 //~gfx7_signed! v1: %bfe_byte2_b = p_extract %b, 2, 8, 1 241 //~gfx7_signed! v1: %res11 = v_cvt_f32_u32 %bfe_byte2_b 242 //~gfx[^7]+_signed! v1: %res11 = v_cvt_f32_u32 %b dst_sel:dword src0_sel:sbyte2 243 //~gfx\d+_unsigned! v1: %res11 = v_cvt_f32_ubyte2 %b 244 //! p_unit_test 11, %res11 245 Temp bfe_byte2_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(2u), Operand::c32(8u), 246 Operand::c32(is_signed)); 247 writeout(11, bld.vop1(aco_opcode::v_cvt_f32_u32, bld.def(v1), bfe_byte2_b)); 248 249 //~gfx7_signed! v1: %bfe_byte3_b = p_extract %b, 3, 8, 1 250 //~gfx7_signed! v1: %res12 = v_cvt_f32_u32 %bfe_byte3_b 251 //~gfx[^7]+_signed! v1: %res12 = v_cvt_f32_u32 %b dst_sel:dword src0_sel:sbyte3 252 //~gfx\d+_unsigned! v1: %res12 = v_cvt_f32_ubyte3 %b 253 //! p_unit_test 12, %res12 254 Temp bfe_byte3_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(3u), Operand::c32(8u), 255 Operand::c32(is_signed)); 256 writeout(12, bld.vop1(aco_opcode::v_cvt_f32_u32, bld.def(v1), bfe_byte3_b)); 257 258 /* VOP3-only instructions can't use SDWA but they can use opsel on GFX9+ instead */ 259 //~gfx(9|10).*! v1: %res13 = v_add_i16 %a, %b 260 //~gfx(9|10).*! p_unit_test 13, %res13 261 Temp bfe_word0_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(16u), 262 Operand::c32(is_signed)); 263 writeout(13, bld.vop3(aco_opcode::v_add_i16, bld.def(v1), inputs[0], bfe_word0_b)); 264 265 //~gfx(9|10).*! v1: %res14 = v_add_i16 %a, hi(%b) 266 //~gfx(9|10).*! p_unit_test 14, %res14 267 Temp bfe_word1_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(1u), 268 Operand::c32(16u), Operand::c32(is_signed)); 269 writeout(14, bld.vop3(aco_opcode::v_add_i16, bld.def(v1), inputs[0], bfe_word1_b)); 270 } 271 272 finish_opt_test(); 273 } 274 } 275END_TEST 276 277BEGIN_TEST(optimize.sdwa.extract_modifiers) 278 for (unsigned i = GFX8; i <= GFX10; i++) { 279 //>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm 280 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) 281 continue; 282 283 aco_opcode ext = aco_opcode::p_extract; 284 285 //! v1: %res0 = v_mul_f32 %a, -%b dst_sel:dword src0_sel:dword src1_sel:ubyte0 286 //! p_unit_test 0, %res0 287 Temp byte0 = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(8u), 288 Operand::zero()); 289 Temp neg_byte0 = fneg(byte0); 290 writeout(0, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], neg_byte0)); 291 292 //~gfx8! v1: %neg = v_mul_f32 -1.0, %b 293 //~gfx8! v1: %res1 = v_mul_f32 %a, %neg dst_sel:dword src0_sel:dword src1_sel:ubyte0 294 //~gfx(9|10)! v1: %neg_byte0 = v_mul_f32 -1.0, %b dst_sel:ubyte0 src0_sel:dword src1_sel:dword 295 //~gfx(9|10)! v1: %res1 = v_mul_f32 %a, %neg_byte0 296 //! p_unit_test 1, %res1 297 Temp neg = fneg(inputs[1]); 298 Temp byte0_neg = 299 bld.pseudo(ext, bld.def(v1), neg, Operand::zero(), Operand::c32(8u), Operand::zero()); 300 writeout(1, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], byte0_neg)); 301 302 //! v1: %res2 = v_mul_f32 %a, |%b| dst_sel:dword src0_sel:dword src1_sel:ubyte0 303 //! p_unit_test 2, %res2 304 Temp abs_byte0 = fabs(byte0); 305 writeout(2, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], abs_byte0)); 306 307 //! v1: %abs = v_mul_f32 1.0, |%b| 308 //! v1: %res3 = v_mul_f32 %a, %abs dst_sel:dword src0_sel:dword src1_sel:ubyte0 309 //! p_unit_test 3, %res3 310 Temp abs = fabs(inputs[1]); 311 Temp byte0_abs = 312 bld.pseudo(ext, bld.def(v1), abs, Operand::zero(), Operand::c32(8u), Operand::zero()); 313 writeout(3, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], byte0_abs)); 314 315 //! v1: %res4 = v_mul_f32 %1, -|%2| dst_sel:dword src0_sel:dword src1_sel:ubyte0 316 //! p_unit_test 4, %res4 317 Temp neg_abs_byte0 = fneg(abs_byte0); 318 writeout(4, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], neg_abs_byte0)); 319 320 //~gfx8! v1: %neg_abs = v_mul_f32 -1.0, %abs 321 //~gfx8! v1: %res5 = v_mul_f32 %a, %neg_abs dst_sel:dword src0_sel:dword src1_sel:ubyte0 322 //~gfx(9|10)! v1: %neg_abs_byte0 = v_mul_f32 -1.0, %abs dst_sel:ubyte0 src0_sel:dword src1_sel:dword 323 //~gfx(9|10)! v1: %res5 = v_mul_f32 %a, %neg_abs_byte0 324 //! p_unit_test 5, %res5 325 Temp neg_abs = fneg(abs); 326 Temp byte0_neg_abs = 327 bld.pseudo(ext, bld.def(v1), neg_abs, Operand::zero(), Operand::c32(8u), Operand::zero()); 328 writeout(5, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], byte0_neg_abs)); 329 330 finish_opt_test(); 331 } 332END_TEST 333 334BEGIN_TEST(optimize.sdwa.extract.sgpr) 335 for (unsigned i = GFX8; i <= GFX10; i++) { 336 //>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm 337 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) 338 continue; 339 340 aco_opcode ext = aco_opcode::p_extract; 341 342 //~gfx8! v1: %byte0_b = p_extract %b, 0, 8, 0 343 //~gfx8! v1: %res1 = v_mul_f32 %c, %byte0_b 344 //~gfx(9|10)! v1: %res1 = v_mul_f32 %c, %b dst_sel:dword src0_sel:dword src1_sel:ubyte0 345 //! p_unit_test 1, %res1 346 Temp byte0_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(8u), 347 Operand::zero()); 348 writeout(1, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[2], byte0_b)); 349 350 //~gfx8! v1: %byte0_c = p_extract %c, 0, 8, 0 351 //~gfx8! v1: %res2 = v_mul_f32 %a, %byte0_c 352 //~gfx(9|10)! v1: %res2 = v_mul_f32 %a, %c dst_sel:dword src0_sel:dword src1_sel:ubyte0 353 //! p_unit_test 2, %res2 354 Temp byte0_c = bld.pseudo(ext, bld.def(v1), inputs[2], Operand::zero(), Operand::c32(8u), 355 Operand::zero()); 356 writeout(2, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], byte0_c)); 357 358 //~gfx8! v1: %byte0_c_2 = p_extract %c, 0, 8, 0 359 //~gfx8! v1: %res3 = v_mul_f32 %c, %byte0_c_2 360 //~gfx(9|10)! v1: %res3 = v_mul_f32 %c, %c dst_sel:dword src0_sel:dword src1_sel:ubyte0 361 //! p_unit_test 3, %res3 362 byte0_c = bld.pseudo(ext, bld.def(v1), inputs[2], Operand::zero(), Operand::c32(8u), 363 Operand::zero()); 364 writeout(3, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[2], byte0_c)); 365 366 //~gfx(8|9)! v1: %byte0_c_3 = p_extract %c, 0, 8, 0 367 //~gfx(8|9)! v1: %res4 = v_mul_f32 %d, %byte0_c_3 368 //~gfx10! v1: %res4 = v_mul_f32 %d, %c dst_sel:dword src0_sel:dword src1_sel:ubyte0 369 //! p_unit_test 4, %res4 370 byte0_c = bld.pseudo(ext, bld.def(v1), inputs[2], Operand::zero(), Operand::c32(8u), 371 Operand::zero()); 372 writeout(4, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[3], byte0_c)); 373 374 finish_opt_test(); 375 } 376END_TEST 377 378BEGIN_TEST(optimize.sdwa.from_vop3) 379 for (unsigned i = GFX8; i <= GFX10; i++) { 380 //>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm 381 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) 382 continue; 383 384 //! v1: %res0 = v_mul_f32 -|%a|, %b dst_sel:dword src0_sel:dword src1_sel:ubyte0 385 //! p_unit_test 0, %res0 386 Temp byte0_b = bld.pseudo(aco_opcode::p_extract, bld.def(v1), inputs[1], Operand::zero(), 387 Operand::c32(8u), Operand::zero()); 388 VOP3_instruction *mul = &bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], byte0_b).instr->vop3(); 389 mul->neg[0] = true; 390 mul->abs[0] = true; 391 writeout(0, mul->definitions[0].getTemp()); 392 393 //~gfx8! v1: %byte0_b_0 = p_extract %b, 0, 8, 0 394 //~gfx8! v1: %res1 = v_mul_f32 %a, %byte0_b_0 *4 395 //~gfx(9|10)! v1: %res1 = v_mul_f32 %a, %b *4 dst_sel:dword src0_sel:dword src1_sel:ubyte0 396 //! p_unit_test 1, %res1 397 byte0_b = bld.pseudo(aco_opcode::p_extract, bld.def(v1), inputs[1], Operand::zero(), 398 Operand::c32(8u), Operand::zero()); 399 mul = &bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], byte0_b).instr->vop3(); 400 mul->omod = 2; 401 writeout(1, mul->definitions[0].getTemp()); 402 403 //~gfx8! v1: %byte0_b_1 = p_extract %b, 0, 8, 0 404 //~gfx8! v1: %res2 = v_mul_f32 %byte0_b_1, %c 405 //~gfx(9|10)! v1: %res2 = v_mul_f32 %b, %c dst_sel:dword src0_sel:ubyte0 src1_sel:dword 406 //! p_unit_test 2, %res2 407 byte0_b = bld.pseudo(aco_opcode::p_extract, bld.def(v1), inputs[1], Operand::zero(), 408 Operand::c32(8u), Operand::zero()); 409 writeout(2, bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), byte0_b, inputs[2])); 410 411 if (i >= GFX10) { 412 //~gfx10! v1: %byte0_b_2 = p_extract %b, 0, 8, 0 413 //~gfx10! v1: %res3 = v_mul_f32 %byte0_b_2, 0x1234 414 //~gfx10! p_unit_test 3, %res3 415 byte0_b = bld.pseudo(aco_opcode::p_extract, bld.def(v1), inputs[1], Operand::zero(), 416 Operand::c32(8u), Operand::zero()); 417 writeout(3, 418 bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), byte0_b, Operand::c32(0x1234u))); 419 } 420 421 finish_opt_test(); 422 } 423END_TEST 424 425BEGIN_TEST(optimize.sdwa.insert) 426 for (unsigned i = GFX7; i <= GFX10; i++) { 427 //>> v1: %a, v1: %b = p_startpgm 428 if (!setup_cs("v1 v1", (amd_gfx_level)i)) 429 continue; 430 431 aco_opcode ext = aco_opcode::p_extract; 432 aco_opcode ins = aco_opcode::p_insert; 433 434 //~gfx[^7]! v1: %res0 = v_mul_f32 %a, %b dst_sel:ubyte0 src0_sel:dword src1_sel:dword 435 //~gfx[^7]! p_unit_test 0, %res0 436 Temp val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 437 writeout(0, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u))); 438 439 //~gfx[^7]! v1: %res1 = v_mul_f32 %a, %b dst_sel:ubyte1 src0_sel:dword src1_sel:dword 440 //~gfx[^7]! p_unit_test 1, %res1 441 val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 442 writeout(1, bld.pseudo(ins, bld.def(v1), val, Operand::c32(1u), Operand::c32(8u))); 443 444 //~gfx[^7]! v1: %res2 = v_mul_f32 %a, %b dst_sel:ubyte2 src0_sel:dword src1_sel:dword 445 //~gfx[^7]! p_unit_test 2, %res2 446 val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 447 writeout(2, bld.pseudo(ins, bld.def(v1), val, Operand::c32(2u), Operand::c32(8u))); 448 449 //~gfx[^7]! v1: %res3 = v_mul_f32 %a, %b dst_sel:ubyte3 src0_sel:dword src1_sel:dword 450 //~gfx[^7]! p_unit_test 3, %res3 451 val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 452 writeout(3, bld.pseudo(ins, bld.def(v1), val, Operand::c32(3u), Operand::c32(8u))); 453 454 //~gfx[^7]! v1: %res4 = v_mul_f32 %a, %b dst_sel:uword0 src0_sel:dword src1_sel:dword 455 //~gfx[^7]! p_unit_test 4, %res4 456 val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 457 writeout(4, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(16u))); 458 459 //~gfx[^7]! v1: %res5 = v_mul_f32 %a, %b dst_sel:uword1 src0_sel:dword src1_sel:dword 460 //~gfx[^7]! p_unit_test 5, %res5 461 val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 462 writeout(5, bld.pseudo(ins, bld.def(v1), val, Operand::c32(1u), Operand::c32(16u))); 463 464 //~gfx[^7]! v1: %res6 = v_mul_f32 %a, %b dst_sel:ubyte0 src0_sel:dword src1_sel:dword 465 //~gfx[^7]! p_unit_test 6, %res6 466 val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 467 writeout( 468 6, bld.pseudo(ext, bld.def(v1), val, Operand::zero(), Operand::c32(8u), Operand::zero())); 469 470 //~gfx[^7]! v1: %res7 = v_mul_f32 %a, %b dst_sel:uword0 src0_sel:dword src1_sel:dword 471 //~gfx[^7]! p_unit_test 7, %res7 472 val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 473 writeout( 474 7, bld.pseudo(ext, bld.def(v1), val, Operand::zero(), Operand::c32(16u), Operand::zero())); 475 476 //~gfx[^7]! v1: %tmp8 = v_mul_f32 %a, %b 477 //~gfx[^7]! v1: %res8 = p_extract %tmp8, 2, 8, 0 478 //~gfx[^7]! p_unit_test 8, %res8 479 val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 480 writeout( 481 8, bld.pseudo(ext, bld.def(v1), val, Operand::c32(2u), Operand::c32(8u), Operand::zero())); 482 483 //~gfx[^7]! v1: %tmp9 = v_mul_f32 %a, %b 484 //~gfx[^7]! v1: %res9 = p_extract %tmp9, 0, 8, 1 485 //~gfx[^7]! p_unit_test 9, %res9 486 val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 487 writeout( 488 9, bld.pseudo(ext, bld.def(v1), val, Operand::zero(), Operand::c32(8u), Operand::c32(1u))); 489 490 //>> p_unit_test 63 491 writeout(63); 492 493 //! v1: %res10 = v_mul_f32 %a, %b 494 //! p_unit_test 10, %res10 495 val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 496 bld.pseudo(ins, bld.def(v1), val, Operand::c32(1u), Operand::c32(16u)); 497 writeout(10, val); 498 499 //~gfx[^7]! v1: %tmp11 = v_sub_i16 %a, %b 500 //~gfx[^7]! v1: %res11 = p_insert %tmp11, 0, 16 501 //~gfx[^7]! p_unit_test 11, %res11 502 val = bld.vop3(aco_opcode::v_sub_i16, bld.def(v1), inputs[0], inputs[1]); 503 writeout(11, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(16u))); 504 505 //~gfx[^7]! v1: %tmp12 = v_sub_i16 %a, %b 506 //~gfx[^7]! v1: %res12 = p_insert %tmp12, 1, 16 507 //~gfx[^7]! p_unit_test 12, %res12 508 val = bld.vop3(aco_opcode::v_sub_i16, bld.def(v1), inputs[0], inputs[1]); 509 writeout(12, bld.pseudo(ins, bld.def(v1), val, Operand::c32(1u), Operand::c32(16u))); 510 511 //~gfx[^7]! v1: %tmp13 = v_sub_i16 %a, %b 512 //~gfx[^7]! v1: %res13 = p_insert %tmp13, 0, 8 513 //~gfx[^7]! p_unit_test 13, %res13 514 val = bld.vop3(aco_opcode::v_sub_i16, bld.def(v1), inputs[0], inputs[1]); 515 writeout(13, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u))); 516 517 finish_opt_test(); 518 } 519END_TEST 520 521BEGIN_TEST(optimize.sdwa.insert_modifiers) 522 for (unsigned i = GFX8; i <= GFX9; i++) { 523 //>> v1: %a = p_startpgm 524 if (!setup_cs("v1", (amd_gfx_level)i)) 525 continue; 526 527 aco_opcode ins = aco_opcode::p_insert; 528 529 //~gfx8! v1: %tmp0 = v_rcp_f32 %a *2 530 //~gfx8! v1: %res0 = p_insert %tmp0, 0, 8 531 //~gfx9! v1: %res0 = v_rcp_f32 %a *2 dst_sel:ubyte0 src0_sel:dword 532 //! p_unit_test 0, %res0 533 Temp val = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), inputs[0]); 534 val = bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), val, Operand::c32(0x40000000u)); 535 writeout(0, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u))); 536 537 //! v1: %res1 = v_rcp_f32 %a clamp dst_sel:ubyte0 src0_sel:dword 538 //! p_unit_test 1, %res1 539 val = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), inputs[0]); 540 val = bld.vop3(aco_opcode::v_med3_f32, bld.def(v1), val, Operand::zero(), 541 Operand::c32(0x3f800000u)); 542 writeout(1, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u))); 543 544 //! v1: %tmp2 = v_rcp_f32 %a dst_sel:ubyte0 src0_sel:dword 545 //! v1: %res2 = v_mul_f32 %tmp2, 2.0 546 //! p_unit_test 2, %res2 547 val = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), inputs[0]); 548 val = bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u)); 549 val = bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), val, Operand::c32(0x40000000u)); 550 writeout(2, val); 551 552 //! v1: %tmp3 = v_rcp_f32 %a dst_sel:ubyte0 src0_sel:dword 553 //! v1: %res3 = v_med3_f32 %tmp3, 0, 1.0 554 //! p_unit_test 3, %res3 555 val = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), inputs[0]); 556 val = bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u)); 557 val = bld.vop3(aco_opcode::v_med3_f32, bld.def(v1), val, Operand::zero(), 558 Operand::c32(0x3f800000u)); 559 writeout(3, val); 560 561 //~gfx8! v1: %tmp4 = v_rcp_f32 %a *2 clamp 562 //~gfx8! v1: %res4 = p_insert %tmp4, 0, 8 563 //~gfx9! v1: %res4 = v_rcp_f32 %a *2 clamp dst_sel:ubyte0 src0_sel:dword 564 //! p_unit_test 4, %res4 565 val = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), inputs[0]); 566 val = bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), val, Operand::c32(0x40000000u)); 567 val = bld.vop3(aco_opcode::v_med3_f32, bld.def(v1), val, Operand::zero(), 568 Operand::c32(0x3f800000u)); 569 writeout(4, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u))); 570 571 finish_opt_test(); 572 } 573END_TEST 574