1/*
2 * Copyright © 2018 Valve Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25#ifndef ACO_INSTRUCTION_SELECTION_H
26#define ACO_INSTRUCTION_SELECTION_H
27
28#include "aco_ir.h"
29
30#include "vulkan/radv_shader_args.h"
31
32#include <array>
33#include <unordered_map>
34#include <vector>
35
36namespace aco {
37
38enum aco_color_output_type {
39   ACO_TYPE_ANY32,
40   ACO_TYPE_FLOAT16,
41   ACO_TYPE_INT16,
42   ACO_TYPE_UINT16,
43};
44
45struct shader_io_state {
46   uint8_t mask[VARYING_SLOT_MAX];
47   Temp temps[VARYING_SLOT_MAX * 4u];
48
49   shader_io_state()
50   {
51      memset(mask, 0, sizeof(mask));
52      std::fill_n(temps, VARYING_SLOT_MAX * 4u, Temp(0, RegClass::v1));
53   }
54};
55
56struct isel_context {
57   const struct aco_compiler_options* options;
58   const struct radv_shader_args* args;
59   Program* program;
60   nir_shader* shader;
61   uint32_t constant_data_offset;
62   Block* block;
63   uint32_t first_temp_id;
64   std::unordered_map<unsigned, std::array<Temp, NIR_MAX_VEC_COMPONENTS>> allocated_vec;
65   Stage stage;
66   struct {
67      bool has_branch;
68      struct {
69         unsigned header_idx;
70         Block* exit;
71         bool has_divergent_continue = false;
72         bool has_divergent_branch = false;
73      } parent_loop;
74      struct {
75         bool is_divergent = false;
76      } parent_if;
77      bool exec_potentially_empty_discard =
78         false; /* set to false when loop_nest_depth==0 && parent_if.is_divergent==false */
79      uint16_t exec_potentially_empty_break_depth = UINT16_MAX;
80      /* Set to false when loop_nest_depth==exec_potentially_empty_break_depth
81       * and parent_if.is_divergent==false. Called _break but it's also used for
82       * loop continues. */
83      bool exec_potentially_empty_break = false;
84      std::unique_ptr<unsigned[]> nir_to_aco; /* NIR block index to ACO block index */
85   } cf_info;
86
87   /* NIR range analysis. */
88   struct hash_table* range_ht;
89   nir_unsigned_upper_bound_config ub_config;
90
91   Temp arg_temps[AC_MAX_ARGS];
92
93   /* FS inputs */
94   Temp persp_centroid, linear_centroid;
95
96   /* GS inputs */
97   Temp gs_wave_id;
98
99   /* VS output information */
100   bool export_clip_dists;
101   unsigned num_clip_distances;
102   unsigned num_cull_distances;
103
104   /* tessellation information */
105   uint64_t tcs_temp_only_inputs;
106   uint32_t tcs_num_patches;
107   bool tcs_in_out_eq = false;
108
109   /* Fragment color output information */
110   uint16_t output_color_types;
111
112   /* I/O information */
113   shader_io_state inputs;
114   shader_io_state outputs;
115};
116
117inline Temp
118get_arg(isel_context* ctx, struct ac_arg arg)
119{
120   assert(arg.used);
121   return ctx->arg_temps[arg.arg_index];
122}
123
124void init_context(isel_context* ctx, nir_shader* shader);
125void cleanup_context(isel_context* ctx);
126
127isel_context setup_isel_context(Program* program, unsigned shader_count,
128                                struct nir_shader* const* shaders, ac_shader_config* config,
129                                const struct aco_compiler_options* options,
130                                const struct aco_shader_info* info,
131                                const struct radv_shader_args* args,
132                                bool is_gs_copy_shader, bool is_ps_epilog);
133
134} // namespace aco
135
136#endif /* ACO_INSTRUCTION_SELECTION_H */
137