1/* 2 * Southern Islands Register documentation 3 * 4 * Copyright (C) 2011 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24#ifndef SID_H 25#define SID_H 26 27#include "amdgfxregs.h" 28 29/* si values */ 30#define SI_CONFIG_REG_OFFSET 0x00008000 31#define SI_CONFIG_REG_END 0x0000B000 32#define SI_SH_REG_OFFSET 0x0000B000 33#define SI_SH_REG_END 0x0000C000 34#define SI_CONTEXT_REG_OFFSET 0x00028000 35#define SI_CONTEXT_REG_END 0x00030000 36#define CIK_UCONFIG_REG_OFFSET 0x00030000 37#define CIK_UCONFIG_REG_END 0x00040000 38#define SI_UCONFIG_PERF_REG_OFFSET 0x00034000 39#define SI_UCONFIG_PERF_REG_END 0x00038000 40 41/* For register shadowing: */ 42#define SI_SH_REG_SPACE_SIZE (SI_SH_REG_END - SI_SH_REG_OFFSET) 43#define SI_CONTEXT_REG_SPACE_SIZE (SI_CONTEXT_REG_END - SI_CONTEXT_REG_OFFSET) 44#define SI_UCONFIG_REG_SPACE_SIZE (CIK_UCONFIG_REG_END - CIK_UCONFIG_REG_OFFSET) 45#define SI_UCONFIG_PERF_REG_SPACE_SIZE (SI_UCONFIG_PERF_REG_END - SI_UCONFIG_PERF_REG_OFFSET) 46 47#define SI_SHADOWED_SH_REG_OFFSET 0 48#define SI_SHADOWED_CONTEXT_REG_OFFSET SI_SH_REG_SPACE_SIZE 49#define SI_SHADOWED_UCONFIG_REG_OFFSET (SI_SH_REG_SPACE_SIZE + SI_CONTEXT_REG_SPACE_SIZE) 50#define SI_SHADOWED_REG_BUFFER_SIZE \ 51 (SI_SH_REG_SPACE_SIZE + SI_CONTEXT_REG_SPACE_SIZE + SI_UCONFIG_REG_SPACE_SIZE) 52 53#define EVENT_TYPE_CACHE_FLUSH 0x6 54#define EVENT_TYPE_PS_PARTIAL_FLUSH 0x10 55#define EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT 0x14 56#define EVENT_TYPE_ZPASS_DONE 0x15 57#define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT 0x16 58#define EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH 0x1f 59#define EVENT_TYPE_SAMPLE_STREAMOUTSTATS 0x20 60#define EVENT_TYPE(x) ((x) << 0) 61#define EVENT_INDEX(x) ((x) << 8) 62/* 0 - any non-TS event 63 * 1 - ZPASS_DONE 64 * 2 - SAMPLE_PIPELINESTAT 65 * 3 - SAMPLE_STREAMOUTSTAT* 66 * 4 - *S_PARTIAL_FLUSH 67 * 5 - TS events 68 */ 69#define PIXEL_PIPE_STATE_CNTL_COUNTER_ID(x) ((x) << 3) 70#define PIXEL_PIPE_STATE_CNTL_STRIDE(x) ((x) << 9) 71/* 0 - 32 bits 72 * 1 - 64 bits 73 * 2 - 128 bits 74 * 3 - 256 bits 75 */ 76#define PIXEL_PIPE_STATE_CNTL_INSTANCE_EN_LO(x) ((x) << 11) 77#define PIXEL_PIPE_STATE_CNTL_INSTANCE_EN_HI(x) ((x) >> 21) 78 79/* EVENT_WRITE_EOP (SI-VI) & RELEASE_MEM (GFX9) */ 80#define EVENT_TCL1_VOL_ACTION_ENA (1 << 12) 81#define EVENT_TC_VOL_ACTION_ENA (1 << 13) 82#define EVENT_TC_WB_ACTION_ENA (1 << 15) 83#define EVENT_TCL1_ACTION_ENA (1 << 16) 84#define EVENT_TC_ACTION_ENA (1 << 17) 85#define EVENT_TC_NC_ACTION_ENA (1 << 19) /* GFX9+ */ 86#define EVENT_TC_WC_ACTION_ENA (1 << 20) /* GFX9+ */ 87#define EVENT_TC_MD_ACTION_ENA (1 << 21) /* GFX9+ */ 88 89#define PREDICATION_OP_CLEAR 0x0 90#define PREDICATION_OP_ZPASS 0x1 91#define PREDICATION_OP_PRIMCOUNT 0x2 92#define PREDICATION_OP_BOOL64 0x3 93#define PREDICATION_OP_BOOL32 0x4 94 95#define PRED_OP(x) ((x) << 16) 96 97#define PREDICATION_CONTINUE (1 << 31) 98 99#define PREDICATION_HINT_WAIT (0 << 12) 100#define PREDICATION_HINT_NOWAIT_DRAW (1 << 12) 101 102#define PREDICATION_DRAW_NOT_VISIBLE (0 << 8) 103#define PREDICATION_DRAW_VISIBLE (1 << 8) 104 105#define R600_TEXEL_PITCH_ALIGNMENT_MASK 0x7 106 107/* All registers defined in this packet section don't exist and the only 108 * purpose of these definitions is to define packet encoding that 109 * the IB parser understands, and also to have an accurate documentation. 110 */ 111#define PKT3_NOP 0x10 112#define PKT3_SET_BASE 0x11 113#define PKT3_CLEAR_STATE 0x12 114#define PKT3_INDEX_BUFFER_SIZE 0x13 115#define PKT3_DISPATCH_DIRECT 0x15 116#define PKT3_DISPATCH_INDIRECT 0x16 117#define PKT3_ATOMIC_MEM 0x1E 118#define ATOMIC_OP(x) ((unsigned)((x)&0x7f) << 0) 119#define TC_OP_ATOMIC_CMPSWAP_32 0x48 120#define ATOMIC_COMMAND(x) ((unsigned)((x)&0x3) << 8) 121#define ATOMIC_COMMAND_SINGLE_PASS 0x0 122#define ATOMIC_COMMAND_LOOP 0x1 123#define PKT3_OCCLUSION_QUERY 0x1F /* new for CIK */ 124#define PKT3_SET_PREDICATION 0x20 125#define PKT3_COND_EXEC 0x22 126#define PKT3_PRED_EXEC 0x23 127#define PKT3_DRAW_INDIRECT 0x24 128#define PKT3_DRAW_INDEX_INDIRECT 0x25 129#define PKT3_INDEX_BASE 0x26 130#define PKT3_DRAW_INDEX_2 0x27 131#define PKT3_CONTEXT_CONTROL 0x28 132#define CC0_LOAD_GLOBAL_CONFIG(x) (((unsigned)(x)&0x1) << 0) 133#define CC0_LOAD_PER_CONTEXT_STATE(x) (((unsigned)(x)&0x1) << 1) 134#define CC0_LOAD_GLOBAL_UCONFIG(x) (((unsigned)(x)&0x1) << 15) 135#define CC0_LOAD_GFX_SH_REGS(x) (((unsigned)(x)&0x1) << 16) 136#define CC0_LOAD_CS_SH_REGS(x) (((unsigned)(x)&0x1) << 24) 137#define CC0_LOAD_CE_RAM(x) (((unsigned)(x)&0x1) << 28) 138#define CC0_UPDATE_LOAD_ENABLES(x) (((unsigned)(x)&0x1) << 31) 139#define CC1_SHADOW_GLOBAL_CONFIG(x) (((unsigned)(x)&0x1) << 0) 140#define CC1_SHADOW_PER_CONTEXT_STATE(x) (((unsigned)(x)&0x1) << 1) 141#define CC1_SHADOW_GLOBAL_UCONFIG(x) (((unsigned)(x)&0x1) << 15) 142#define CC1_SHADOW_GFX_SH_REGS(x) (((unsigned)(x)&0x1) << 16) 143#define CC1_SHADOW_CS_SH_REGS(x) (((unsigned)(x)&0x1) << 24) 144#define CC1_UPDATE_SHADOW_ENABLES(x) (((unsigned)(x)&0x1) << 31) 145#define PKT3_INDEX_TYPE 0x2A /* not on GFX9 */ 146#define PKT3_DRAW_INDIRECT_MULTI 0x2C 147#define R_2C3_DRAW_INDEX_LOC 0x2C3 148#define S_2C3_COUNT_INDIRECT_ENABLE(x) (((unsigned)(x)&0x1) << 30) 149#define S_2C3_DRAW_INDEX_ENABLE(x) (((unsigned)(x)&0x1) << 31) 150#define PKT3_DRAW_INDEX_AUTO 0x2D 151#define PKT3_DRAW_INDEX_IMMD 0x2E /* not on CIK */ 152#define PKT3_NUM_INSTANCES 0x2F 153#define PKT3_DRAW_INDEX_MULTI_AUTO 0x30 154#define PKT3_INDIRECT_BUFFER_SI 0x32 /* not on CIK */ 155#define PKT3_INDIRECT_BUFFER_CONST 0x33 156#define PKT3_STRMOUT_BUFFER_UPDATE 0x34 157#define STRMOUT_STORE_BUFFER_FILLED_SIZE 1 158#define STRMOUT_OFFSET_SOURCE(x) (((unsigned)(x)&0x3) << 1) 159#define STRMOUT_OFFSET_FROM_PACKET 0 160#define STRMOUT_OFFSET_FROM_VGT_FILLED_SIZE 1 161#define STRMOUT_OFFSET_FROM_MEM 2 162#define STRMOUT_OFFSET_NONE 3 163#define STRMOUT_DATA_TYPE(x) (((unsigned)(x)&0x1) << 7) 164#define STRMOUT_SELECT_BUFFER(x) (((unsigned)(x)&0x3) << 8) 165#define PKT3_DRAW_INDEX_OFFSET_2 0x35 166#define PKT3_WRITE_DATA 0x37 167#define PKT3_DRAW_INDEX_INDIRECT_MULTI 0x38 168#define PKT3_MEM_SEMAPHORE 0x39 169#define PKT3_MPEG_INDEX 0x3A /* not on CIK */ 170#define PKT3_WAIT_REG_MEM 0x3C 171#define WAIT_REG_MEM_EQUAL 3 172#define WAIT_REG_MEM_NOT_EQUAL 4 173#define WAIT_REG_MEM_GREATER_OR_EQUAL 5 174#define WAIT_REG_MEM_MEM_SPACE(x) (((unsigned)(x)&0x3) << 4) 175#define WAIT_REG_MEM_PFP (1 << 8) 176#define PKT3_MEM_WRITE 0x3D /* not on CIK */ 177#define PKT3_INDIRECT_BUFFER_CIK 0x3F /* new on CIK */ 178 179#define PKT3_COPY_DATA 0x40 180#define COPY_DATA_SRC_SEL(x) ((x)&0xf) 181#define COPY_DATA_REG 0 182#define COPY_DATA_SRC_MEM 1 /* only valid as source */ 183#define COPY_DATA_TC_L2 2 184#define COPY_DATA_GDS 3 185#define COPY_DATA_PERF 4 186#define COPY_DATA_IMM 5 187#define COPY_DATA_TIMESTAMP 9 188#define COPY_DATA_DST_SEL(x) (((unsigned)(x)&0xf) << 8) 189#define COPY_DATA_DST_MEM_GRBM 1 /* sync across GRBM, deprecated */ 190#define COPY_DATA_TC_L2 2 191#define COPY_DATA_GDS 3 192#define COPY_DATA_PERF 4 193#define COPY_DATA_DST_MEM 5 194#define COPY_DATA_COUNT_SEL (1 << 16) 195#define COPY_DATA_WR_CONFIRM (1 << 20) 196#define COPY_DATA_ENGINE_PFP (1 << 30) 197#define PKT3_PFP_SYNC_ME 0x42 198#define PKT3_SURFACE_SYNC 0x43 /* deprecated on CIK, use ACQUIRE_MEM */ 199#define PKT3_ME_INITIALIZE 0x44 /* not on CIK */ 200#define PKT3_COND_WRITE 0x45 201#define PKT3_EVENT_WRITE 0x46 202#define PKT3_EVENT_WRITE_EOP 0x47 /* not on GFX9 */ 203#define PKT3_EVENT_WRITE_EOS 0x48 /* not on GFX9 */ 204#define EOP_DST_SEL(x) ((x) << 16) 205#define EOP_DST_SEL_MEM 0 206#define EOP_DST_SEL_TC_L2 1 207#define EOP_INT_SEL(x) ((x) << 24) 208#define EOP_INT_SEL_NONE 0 209#define EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM 3 210#define EOP_DATA_SEL(x) ((x) << 29) 211#define EOP_DATA_SEL_DISCARD 0 212#define EOP_DATA_SEL_VALUE_32BIT 1 213#define EOP_DATA_SEL_VALUE_64BIT 2 214#define EOP_DATA_SEL_TIMESTAMP 3 215#define EOP_DATA_SEL_GDS 5 216#define EOP_DATA_GDS(dw_offset, num_dwords) ((dw_offset) | ((unsigned)(num_dwords) << 16)) 217 218#define EOS_DATA_SEL(x) ((x) << 29) 219#define EOS_DATA_SEL_APPEND_COUNT 0 220#define EOS_DATA_SEL_GDS 1 221#define EOS_DATA_SEL_VALUE_32BIT 2 222 223/* CP DMA bug: Any use of CP_DMA.DST_SEL=TC must be avoided when EOS packets 224 * are used. Use DST_SEL=MC instead. For prefetch, use SRC_SEL=TC and 225 * DST_SEL=MC. Only CIK chips are affected. 226 */ 227/* fix CP DMA before uncommenting: */ 228/*#define PKT3_EVENT_WRITE_EOS 0x48*/ /* not on GFX9 */ 229#define PKT3_RELEASE_MEM 0x49 /* GFX9+ [any ring] or GFX8 [compute ring only] */ 230#define PKT3_CONTEXT_REG_RMW 0x51 /* older firmware versions on older chips don't have this */ 231#define PKT3_ONE_REG_WRITE 0x57 /* not on CIK */ 232#define PKT3_ACQUIRE_MEM 0x58 /* new for CIK */ 233#define PKT3_REWIND 0x59 /* VI+ [any ring] or CIK [compute ring only] */ 234#define PKT3_LOAD_UCONFIG_REG 0x5E /* GFX7+ */ 235#define PKT3_LOAD_SH_REG 0x5F 236#define PKT3_LOAD_CONTEXT_REG 0x61 237#define PKT3_LOAD_SH_REG_INDEX 0x63 /* GFX8+ */ 238#define PKT3_SET_CONFIG_REG 0x68 239#define PKT3_SET_CONTEXT_REG 0x69 240#define PKT3_SET_SH_REG 0x76 241#define PKT3_SET_SH_REG_OFFSET 0x77 242#define PKT3_SET_UCONFIG_REG 0x79 /* new for CIK */ 243#define PKT3_SET_UCONFIG_REG_INDEX 0x7A /* new for GFX9, CP ucode version >= 26 */ 244#define PKT3_LOAD_CONST_RAM 0x80 245#define PKT3_WRITE_CONST_RAM 0x81 246#define PKT3_DUMP_CONST_RAM 0x83 247#define PKT3_INCREMENT_CE_COUNTER 0x84 248#define PKT3_INCREMENT_DE_COUNTER 0x85 249#define PKT3_WAIT_ON_CE_COUNTER 0x86 250#define PKT3_SET_SH_REG_INDEX 0x9B 251#define PKT3_LOAD_CONTEXT_REG_INDEX 0x9F /* new for VI */ 252 253#define PKT3_DISPATCH_TASK_STATE_INIT 0xA9 /* Tells the HW about the task control buffer */ 254#define PKT3_DISPATCH_MESH_INDIRECT_MULTI 0x4C /* Indirect mesh shader only dispatch [GFX only] */ 255#define PKT3_DISPATCH_TASKMESH_GFX 0x4D /* Task+mesh shader dispatch [GFX side] */ 256#define PKT3_DISPATCH_TASKMESH_DIRECT_ACE 0xAA /* Direct task+mesh shader dispatch [ACE side] */ 257#define PKT3_DISPATCH_TASKMESH_INDIRECT_MULTI_ACE 0xAD /* Indirect task+mesh shader dispatch [ACE side] */ 258 259#define PKT_TYPE_S(x) (((unsigned)(x)&0x3) << 30) 260#define PKT_TYPE_G(x) (((x) >> 30) & 0x3) 261#define PKT_TYPE_C 0x3FFFFFFF 262#define PKT_COUNT_S(x) (((unsigned)(x)&0x3FFF) << 16) 263#define PKT_COUNT_G(x) (((x) >> 16) & 0x3FFF) 264#define PKT_COUNT_C 0xC000FFFF 265#define PKT0_BASE_INDEX_S(x) (((unsigned)(x)&0xFFFF) << 0) 266#define PKT0_BASE_INDEX_G(x) (((x) >> 0) & 0xFFFF) 267#define PKT0_BASE_INDEX_C 0xFFFF0000 268#define PKT3_IT_OPCODE_S(x) (((unsigned)(x)&0xFF) << 8) 269#define PKT3_IT_OPCODE_G(x) (((x) >> 8) & 0xFF) 270#define PKT3_IT_OPCODE_C 0xFFFF00FF 271#define PKT3_PREDICATE(x) (((x) >> 0) & 0x1) 272#define PKT3_SHADER_TYPE_S(x) (((unsigned)(x)&0x1) << 1) 273#define PKT3_RESET_FILTER_CAM(x) (((unsigned)(x)&0x1) << 2) 274#define PKT0(index, count) (PKT_TYPE_S(0) | PKT0_BASE_INDEX_S(index) | PKT_COUNT_S(count)) 275#define PKT3(op, count, predicate) \ 276 (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate)) 277 278#define PKT2_NOP_PAD PKT_TYPE_S(2) 279#define PKT3_NOP_PAD PKT3(PKT3_NOP, 0x3fff, 0) /* header-only version */ 280 281#define PKT3_CP_DMA 0x41 282/* 1. header 283 * 2. SRC_ADDR_LO [31:0] or DATA [31:0] 284 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | SRC_ADDR_HI [15:0] 285 * 4. DST_ADDR_LO [31:0] 286 * 5. DST_ADDR_HI [15:0] 287 * 6. COMMAND [29:22] | BYTE_COUNT [20:0] 288 */ 289 290#define PKT3_DMA_DATA 0x50 /* new for CIK */ 291/* 1. header 292 * 2. CP_SYNC [31] | SRC_SEL [30:29] | DST_SEL [21:20] | ENGINE [0] 293 * 2. SRC_ADDR_LO [31:0] or DATA [31:0] 294 * 3. SRC_ADDR_HI [31:0] 295 * 4. DST_ADDR_LO [31:0] 296 * 5. DST_ADDR_HI [31:0] 297 * 6. COMMAND [29:22] | BYTE_COUNT [20:0] 298 */ 299 300/* SI async DMA packets */ 301#define SI_DMA_PACKET(cmd, sub_cmd, n) \ 302 ((((unsigned)(cmd)&0xF) << 28) | (((unsigned)(sub_cmd)&0xFF) << 20) | \ 303 (((unsigned)(n)&0xFFFFF) << 0)) 304/* SI async DMA Packet types */ 305#define SI_DMA_PACKET_WRITE 0x2 306#define SI_DMA_PACKET_COPY 0x3 307#define SI_DMA_COPY_MAX_BYTE_ALIGNED_SIZE 0xfffe0 308/* The documentation says 0xffff8 is the maximum size in dwords, which is 309 * 0x3fffe0 in bytes. */ 310#define SI_DMA_COPY_MAX_DWORD_ALIGNED_SIZE 0x3fffe0 311#define SI_DMA_COPY_DWORD_ALIGNED 0x00 312#define SI_DMA_COPY_BYTE_ALIGNED 0x40 313#define SI_DMA_COPY_TILED 0x8 314#define SI_DMA_PACKET_INDIRECT_BUFFER 0x4 315#define SI_DMA_PACKET_SEMAPHORE 0x5 316#define SI_DMA_PACKET_FENCE 0x6 317#define SI_DMA_PACKET_TRAP 0x7 318#define SI_DMA_PACKET_SRBM_WRITE 0x9 319#define SI_DMA_PACKET_CONSTANT_FILL 0xd 320#define SI_DMA_PACKET_NOP 0xf 321 322/* CIK async DMA packets */ 323#define CIK_SDMA_PACKET(op, sub_op, n) \ 324 ((((unsigned)(n)&0xFFFF) << 16) | (((unsigned)(sub_op)&0xFF) << 8) | \ 325 (((unsigned)(op)&0xFF) << 0)) 326/* CIK async DMA packet types */ 327#define CIK_SDMA_OPCODE_NOP 0x0 328#define CIK_SDMA_OPCODE_COPY 0x1 329#define CIK_SDMA_COPY_SUB_OPCODE_LINEAR 0x0 330#define CIK_SDMA_COPY_SUB_OPCODE_TILED 0x1 331#define CIK_SDMA_COPY_SUB_OPCODE_SOA 0x3 332#define CIK_SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 0x4 333#define CIK_SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 0x5 334#define CIK_SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 0x6 335#define CIK_SDMA_OPCODE_WRITE 0x2 336#define SDMA_WRITE_SUB_OPCODE_LINEAR 0x0 337#define SDMA_WRTIE_SUB_OPCODE_TILED 0x1 338#define CIK_SDMA_OPCODE_INDIRECT_BUFFER 0x4 339#define CIK_SDMA_PACKET_FENCE 0x5 340#define CIK_SDMA_PACKET_TRAP 0x6 341#define CIK_SDMA_PACKET_SEMAPHORE 0x7 342#define CIK_SDMA_PACKET_CONSTANT_FILL 0xb 343#define CIK_SDMA_OPCODE_TIMESTAMP 0xd 344#define SDMA_TS_SUB_OPCODE_SET_LOCAL_TIMESTAMP 0x0 345#define SDMA_TS_SUB_OPCODE_GET_LOCAL_TIMESTAMP 0x1 346#define SDMA_TS_SUB_OPCODE_GET_GLOBAL_TIMESTAMP 0x2 347#define CIK_SDMA_PACKET_SRBM_WRITE 0xe 348/* There is apparently an undocumented HW limitation that 349 prevents the HW from copying the last 255 bytes of (1 << 22) - 1 */ 350#define CIK_SDMA_COPY_MAX_SIZE 0x3fff00 /* almost 4 MB*/ 351#define GFX103_SDMA_COPY_MAX_SIZE 0x3fffff00 /* almost 1 GB */ 352 353#define SDMA_NOP_PAD CIK_SDMA_PACKET(CIK_SDMA_OPCODE_NOP, 0, 0) /* header-only version */ 354 355enum amd_cmp_class_flags 356{ 357 S_NAN = 1 << 0, // Signaling NaN 358 Q_NAN = 1 << 1, // Quiet NaN 359 N_INFINITY = 1 << 2, // Negative infinity 360 N_NORMAL = 1 << 3, // Negative normal 361 N_SUBNORMAL = 1 << 4, // Negative subnormal 362 N_ZERO = 1 << 5, // Negative zero 363 P_ZERO = 1 << 6, // Positive zero 364 P_SUBNORMAL = 1 << 7, // Positive subnormal 365 P_NORMAL = 1 << 8, // Positive normal 366 P_INFINITY = 1 << 9 // Positive infinity 367}; 368 369#endif /* _SID_H */ 370