1/* 2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com> 3 * Copyright 2010 Marek Olšák <maraeo@gmail.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * on the rights to use, copy, modify, merge, publish, distribute, sub 9 * license, and/or sell copies of the Software, and to permit persons to whom 10 * the Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */ 23 24#ifndef AMD_FAMILY_H 25#define AMD_FAMILY_H 26 27#ifdef __cplusplus 28extern "C" { 29#endif 30 31enum radeon_family 32{ 33 CHIP_UNKNOWN = 0, 34 /* R3xx-based cores. (GFX2) */ 35 CHIP_R300, 36 CHIP_R350, 37 CHIP_RV350, 38 CHIP_RV370, 39 CHIP_RV380, 40 CHIP_RS400, 41 CHIP_RC410, 42 CHIP_RS480, 43 /* R4xx-based cores. (GFX2) */ 44 CHIP_R420, 45 CHIP_R423, 46 CHIP_R430, 47 CHIP_R480, 48 CHIP_R481, 49 CHIP_RV410, 50 CHIP_RS600, 51 CHIP_RS690, 52 CHIP_RS740, 53 /* R5xx-based cores. (GFX2) */ 54 CHIP_RV515, 55 CHIP_R520, 56 CHIP_RV530, 57 CHIP_R580, 58 CHIP_RV560, 59 CHIP_RV570, 60 /* GFX3 (R6xx) */ 61 CHIP_R600, 62 CHIP_RV610, 63 CHIP_RV630, 64 CHIP_RV670, 65 CHIP_RV620, 66 CHIP_RV635, 67 CHIP_RS780, 68 CHIP_RS880, 69 /* GFX3 (R7xx) */ 70 CHIP_RV770, 71 CHIP_RV730, 72 CHIP_RV710, 73 CHIP_RV740, 74 /* GFX4 (Evergreen) */ 75 CHIP_CEDAR, 76 CHIP_REDWOOD, 77 CHIP_JUNIPER, 78 CHIP_CYPRESS, 79 CHIP_HEMLOCK, 80 CHIP_PALM, 81 CHIP_SUMO, 82 CHIP_SUMO2, 83 CHIP_BARTS, 84 CHIP_TURKS, 85 CHIP_CAICOS, 86 /* GFX5 (Northern Islands) */ 87 CHIP_CAYMAN, 88 CHIP_ARUBA, 89 /* GFX6 (Southern Islands) */ 90 CHIP_TAHITI, 91 CHIP_PITCAIRN, 92 CHIP_VERDE, 93 CHIP_OLAND, 94 CHIP_HAINAN, 95 /* GFX7 (Sea Islands) */ 96 CHIP_BONAIRE, 97 CHIP_KAVERI, 98 CHIP_KABINI, 99 CHIP_HAWAII, /* Radeon 290, 390 */ 100 /* GFX8 (Volcanic Islands & Polaris) */ 101 CHIP_TONGA, /* Radeon 285, 380 */ 102 CHIP_ICELAND, 103 CHIP_CARRIZO, 104 CHIP_FIJI, /* Radeon Fury */ 105 CHIP_STONEY, 106 CHIP_POLARIS10, /* Radeon 470, 480, 570, 580, 590 */ 107 CHIP_POLARIS11, /* Radeon 460, 560 */ 108 CHIP_POLARIS12, /* Radeon 540, 550 */ 109 CHIP_VEGAM, 110 /* GFX9 (Vega) */ 111 CHIP_VEGA10, /* Vega 56, 64 */ 112 CHIP_VEGA12, 113 CHIP_VEGA20, /* Radeon VII, MI50 */ 114 CHIP_RAVEN, /* Ryzen 2000, 3000 */ 115 CHIP_RAVEN2, /* Ryzen 2200U, 3200U */ 116 CHIP_RENOIR, /* Ryzen 4000, 5000 */ 117 CHIP_ARCTURUS, /* MI100 */ 118 CHIP_ALDEBARAN, /* MI200 */ 119 /* GFX10.1 (RDNA 1) */ 120 CHIP_NAVI10, /* Radeon 5600, 5700 */ 121 CHIP_NAVI12, /* Radeon Pro 5600M */ 122 CHIP_NAVI14, /* Radeon 5300, 5500 */ 123 /* GFX10.3 (RDNA 2) */ 124 CHIP_NAVI21, /* Radeon 6800, 6900 (formerly "Sienna Cichlid") */ 125 CHIP_NAVI22, /* Radeon 6700 (formerly "Navy Flounder") */ 126 CHIP_VANGOGH, /* Steam Deck */ 127 CHIP_NAVI23, /* Radeon 6600 (formerly "Dimgrey Cavefish") */ 128 CHIP_NAVI24, /* Radeon 6400, 6500 (formerly "Beige Goby") */ 129 CHIP_REMBRANDT, /* Ryzen 6000 (formerly "Yellow Carp") */ 130 CHIP_GFX1036, 131 CHIP_GFX1100, 132 CHIP_GFX1101, 133 CHIP_GFX1102, 134 CHIP_GFX1103, 135 CHIP_LAST, 136}; 137 138enum amd_gfx_level 139{ 140 CLASS_UNKNOWN = 0, 141 R300, 142 R400, 143 R500, 144 R600, 145 R700, 146 EVERGREEN, 147 CAYMAN, 148 GFX6, 149 GFX7, 150 GFX8, 151 GFX9, 152 GFX10, 153 GFX10_3, 154 GFX11, 155 156 NUM_GFX_VERSIONS, 157}; 158 159enum amd_ip_type 160{ 161 AMD_IP_GFX = 0, 162 AMD_IP_COMPUTE, 163 AMD_IP_SDMA, 164 AMD_IP_UVD, 165 AMD_IP_VCE, 166 AMD_IP_UVD_ENC, 167 AMD_IP_VCN_DEC, 168 AMD_IP_VCN_ENC, 169 AMD_IP_VCN_UNIFIED = AMD_IP_VCN_ENC, 170 AMD_IP_VCN_JPEG, 171 AMD_NUM_IP_TYPES, 172}; 173 174const char *ac_get_family_name(enum radeon_family family); 175 176#ifdef __cplusplus 177} 178#endif 179 180#endif 181