1/*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24#ifndef AC_SHADER_UTIL_H
25#define AC_SHADER_UTIL_H
26
27#include "ac_binary.h"
28#include "amd_family.h"
29#include "compiler/nir/nir.h"
30#include "compiler/shader_enums.h"
31
32#include <stdbool.h>
33#include <stdint.h>
34
35#ifdef __cplusplus
36extern "C" {
37#endif
38
39enum ac_image_dim
40{
41   ac_image_1d,
42   ac_image_2d,
43   ac_image_3d,
44   ac_image_cube, // includes cube arrays
45   ac_image_1darray,
46   ac_image_2darray,
47   ac_image_2dmsaa,
48   ac_image_2darraymsaa,
49};
50
51struct ac_data_format_info {
52   uint8_t element_size;
53   uint8_t num_channels;
54   uint8_t chan_byte_size;
55   uint8_t chan_format;
56};
57
58struct ac_spi_color_formats {
59   unsigned normal : 8;
60   unsigned alpha : 8;
61   unsigned blend : 8;
62   unsigned blend_alpha : 8;
63};
64
65/* For ac_build_fetch_format.
66 *
67 * Note: FLOAT must be 0 (used for convenience of encoding in radeonsi).
68 */
69enum ac_fetch_format
70{
71   AC_FETCH_FORMAT_FLOAT = 0,
72   AC_FETCH_FORMAT_FIXED,
73   AC_FETCH_FORMAT_UNORM,
74   AC_FETCH_FORMAT_SNORM,
75   AC_FETCH_FORMAT_USCALED,
76   AC_FETCH_FORMAT_SSCALED,
77   AC_FETCH_FORMAT_UINT,
78   AC_FETCH_FORMAT_SINT,
79   AC_FETCH_FORMAT_NONE,
80};
81
82enum ac_descriptor_type
83{
84   AC_DESC_IMAGE,
85   AC_DESC_FMASK,
86   AC_DESC_SAMPLER,
87   AC_DESC_BUFFER,
88   AC_DESC_PLANE_0,
89   AC_DESC_PLANE_1,
90   AC_DESC_PLANE_2,
91};
92
93unsigned ac_get_spi_shader_z_format(bool writes_z, bool writes_stencil, bool writes_samplemask,
94                                    bool writes_mrt0_alpha);
95
96unsigned ac_get_cb_shader_mask(unsigned spi_shader_col_format);
97
98uint32_t ac_vgt_gs_mode(unsigned gs_max_vert_out, enum amd_gfx_level gfx_level);
99
100unsigned ac_get_tbuffer_format(enum amd_gfx_level gfx_level, unsigned dfmt, unsigned nfmt);
101
102const struct ac_data_format_info *ac_get_data_format_info(unsigned dfmt);
103
104enum ac_image_dim ac_get_sampler_dim(enum amd_gfx_level gfx_level, enum glsl_sampler_dim dim,
105                                     bool is_array);
106
107enum ac_image_dim ac_get_image_dim(enum amd_gfx_level gfx_level, enum glsl_sampler_dim sdim,
108                                   bool is_array);
109
110unsigned ac_get_fs_input_vgpr_cnt(const struct ac_shader_config *config,
111                                  signed char *face_vgpr_index, signed char *ancillary_vgpr_index,
112                                  signed char *sample_coverage_vgpr_index_ptr);
113
114void ac_choose_spi_color_formats(unsigned format, unsigned swap, unsigned ntype,
115                                 bool is_depth, bool use_rbplus,
116                                 struct ac_spi_color_formats *formats);
117
118void ac_compute_late_alloc(const struct radeon_info *info, bool ngg, bool ngg_culling,
119                           bool uses_scratch, unsigned *late_alloc_wave64, unsigned *cu_mask);
120
121unsigned ac_compute_cs_workgroup_size(uint16_t sizes[3], bool variable, unsigned max);
122
123unsigned ac_compute_lshs_workgroup_size(enum amd_gfx_level gfx_level, gl_shader_stage stage,
124                                        unsigned tess_num_patches,
125                                        unsigned tess_patch_in_vtx,
126                                        unsigned tess_patch_out_vtx);
127
128unsigned ac_compute_esgs_workgroup_size(enum amd_gfx_level gfx_level, unsigned wave_size,
129                                        unsigned es_verts, unsigned gs_inst_prims);
130
131unsigned ac_compute_ngg_workgroup_size(unsigned es_verts, unsigned gs_inst_prims,
132                                       unsigned max_vtx_out, unsigned prim_amp_factor);
133
134void ac_set_reg_cu_en(void *cs, unsigned reg_offset, uint32_t value, uint32_t clear_mask,
135                      unsigned value_shift, const struct radeon_info *info,
136                      void set_sh_reg(void*, unsigned, uint32_t));
137
138void ac_get_scratch_tmpring_size(const struct radeon_info *info,
139                                 unsigned bytes_per_wave, unsigned *max_seen_bytes_per_wave,
140                                 uint32_t *tmpring_size);
141
142#ifdef __cplusplus
143}
144#endif
145
146#endif
147