1/* 2 * Copyright © 2021 Valve Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 26#ifndef AC_NIR_H 27#define AC_NIR_H 28 29#include "nir.h" 30#include "ac_shader_args.h" 31#include "ac_shader_util.h" 32#include "amd_family.h" 33 34#ifdef __cplusplus 35extern "C" { 36#endif 37 38enum 39{ 40 /* SPI_PS_INPUT_CNTL_i.OFFSET[0:4] */ 41 AC_EXP_PARAM_OFFSET_0 = 0, 42 AC_EXP_PARAM_OFFSET_31 = 31, 43 /* SPI_PS_INPUT_CNTL_i.DEFAULT_VAL[0:1] */ 44 AC_EXP_PARAM_DEFAULT_VAL_0000 = 64, 45 AC_EXP_PARAM_DEFAULT_VAL_0001, 46 AC_EXP_PARAM_DEFAULT_VAL_1110, 47 AC_EXP_PARAM_DEFAULT_VAL_1111, 48 AC_EXP_PARAM_UNDEFINED = 255, /* deprecated, use AC_EXP_PARAM_DEFAULT_VAL_0000 instead */ 49}; 50 51/* Maps I/O semantics to the actual location used by the lowering pass. */ 52typedef unsigned (*ac_nir_map_io_driver_location)(unsigned semantic); 53 54/* Forward declaration of nir_builder so we don't have to include nir_builder.h here */ 55struct nir_builder; 56typedef struct nir_builder nir_builder; 57 58nir_ssa_def * 59ac_nir_load_arg(nir_builder *b, const struct ac_shader_args *ac_args, struct ac_arg arg); 60 61nir_ssa_def * 62ac_nir_calc_io_offset(nir_builder *b, 63 nir_intrinsic_instr *intrin, 64 nir_ssa_def *base_stride, 65 unsigned component_stride, 66 ac_nir_map_io_driver_location map_io); 67 68bool ac_nir_optimize_outputs(nir_shader *nir, bool sprite_tex_disallowed, 69 int8_t slot_remap[NUM_TOTAL_VARYING_SLOTS], 70 uint8_t param_export_index[NUM_TOTAL_VARYING_SLOTS]); 71 72void 73ac_nir_lower_ls_outputs_to_mem(nir_shader *ls, 74 ac_nir_map_io_driver_location map, 75 bool tcs_in_out_eq, 76 uint64_t tcs_temp_only_inputs); 77 78void 79ac_nir_lower_hs_inputs_to_mem(nir_shader *shader, 80 ac_nir_map_io_driver_location map, 81 bool tcs_in_out_eq); 82 83void 84ac_nir_lower_hs_outputs_to_mem(nir_shader *shader, 85 ac_nir_map_io_driver_location map, 86 enum amd_gfx_level gfx_level, 87 bool tes_reads_tessfactors, 88 uint64_t tes_inputs_read, 89 uint64_t tes_patch_inputs_read, 90 unsigned num_reserved_tcs_outputs, 91 unsigned num_reserved_tcs_patch_outputs, 92 unsigned wave_size, 93 bool no_inputs_in_lds, 94 bool pass_tessfactors_by_reg, 95 bool emit_tess_factor_write); 96 97void 98ac_nir_lower_tes_inputs_to_mem(nir_shader *shader, 99 ac_nir_map_io_driver_location map); 100 101void 102ac_nir_lower_es_outputs_to_mem(nir_shader *shader, 103 ac_nir_map_io_driver_location map, 104 enum amd_gfx_level gfx_level, 105 unsigned esgs_itemsize); 106 107void 108ac_nir_lower_gs_inputs_to_mem(nir_shader *shader, 109 ac_nir_map_io_driver_location map, 110 enum amd_gfx_level gfx_level, 111 bool triangle_strip_adjacency_fix); 112 113bool 114ac_nir_lower_indirect_derefs(nir_shader *shader, 115 enum amd_gfx_level gfx_level); 116 117void 118ac_nir_lower_ngg_nogs(nir_shader *shader, 119 enum radeon_family family, 120 unsigned max_num_es_vertices, 121 unsigned num_vertices_per_primitive, 122 unsigned max_workgroup_size, 123 unsigned wave_size, 124 bool can_cull, 125 bool early_prim_export, 126 bool passthrough, 127 bool export_prim_id, 128 bool provoking_vtx_last, 129 bool use_edgeflags, 130 bool has_prim_query, 131 uint32_t instance_rate_inputs); 132 133void 134ac_nir_lower_ngg_gs(nir_shader *shader, 135 unsigned wave_size, 136 unsigned max_workgroup_size, 137 unsigned esgs_ring_lds_bytes, 138 unsigned gs_out_vtx_bytes, 139 unsigned gs_total_out_vtx_bytes, 140 bool provoking_vtx_last); 141 142void 143ac_nir_lower_ngg_ms(nir_shader *shader, 144 bool *out_needs_scratch_ring, 145 unsigned wave_size, 146 bool multiview); 147 148void 149ac_nir_apply_first_task_to_task_shader(nir_shader *shader); 150 151void 152ac_nir_lower_task_outputs_to_mem(nir_shader *shader, 153 unsigned task_payload_entry_bytes, 154 unsigned task_num_entries); 155 156void 157ac_nir_lower_mesh_inputs_to_mem(nir_shader *shader, 158 unsigned task_payload_entry_bytes, 159 unsigned task_num_entries); 160 161nir_ssa_def * 162ac_nir_cull_triangle(nir_builder *b, 163 nir_ssa_def *initially_accepted, 164 nir_ssa_def *pos[3][4]); 165 166bool 167ac_nir_lower_global_access(nir_shader *shader); 168 169#ifdef __cplusplus 170} 171#endif 172 173#endif /* AC_NIR_H */ 174