1/* 2************************************************************************************************************************ 3* 4* Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved. 5* 6* Permission is hereby granted, free of charge, to any person obtaining a 7* copy of this software and associated documentation files (the "Software"), 8* to deal in the Software without restriction, including without limitation 9* the rights to use, copy, modify, merge, publish, distribute, sublicense, 10* and/or sell copies of the Software, and to permit persons to whom the 11* Software is furnished to do so, subject to the following conditions: 12* 13* The above copyright notice and this permission notice shall be included in 14* all copies or substantial portions of the Software. 15* 16* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22* OTHER DEALINGS IN THE SOFTWARE 23* 24***********************************************************************************************************************/ 25 26/** 27**************************************************************************************************** 28* @file addrinterface.h 29* @brief Contains the addrlib interfaces declaration and parameter defines 30**************************************************************************************************** 31*/ 32#ifndef __ADDR_INTERFACE_H__ 33#define __ADDR_INTERFACE_H__ 34 35// Includes should be before extern "C" 36#include "addrtypes.h" 37 38#if defined(__cplusplus) 39extern "C" 40{ 41#endif 42 43#define ADDRLIB_VERSION_MAJOR 6 44#define ADDRLIB_VERSION_MINOR 2 45#define ADDRLIB_VERSION ((ADDRLIB_VERSION_MAJOR << 16) | ADDRLIB_VERSION_MINOR) 46 47/// Virtually all interface functions need ADDR_HANDLE as first parameter 48typedef VOID* ADDR_HANDLE; 49 50/// Client handle used in callbacks 51typedef VOID* ADDR_CLIENT_HANDLE; 52 53/** 54* ///////////////////////////////////////////////////////////////////////////////////////////////// 55* // Callback functions 56* ///////////////////////////////////////////////////////////////////////////////////////////////// 57* typedef VOID* (ADDR_API* ADDR_ALLOCSYSMEM)( 58* const ADDR_ALLOCSYSMEM_INPUT* pInput); 59* typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_FREESYSMEM)( 60* VOID* pVirtAddr); 61* typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_DEBUGPRINT)( 62* const ADDR_DEBUGPRINT_INPUT* pInput); 63* 64* ///////////////////////////////////////////////////////////////////////////////////////////////// 65* // Create/Destroy/Config functions 66* ///////////////////////////////////////////////////////////////////////////////////////////////// 67* AddrCreate() 68* AddrDestroy() 69* 70* ///////////////////////////////////////////////////////////////////////////////////////////////// 71* // Surface functions 72* ///////////////////////////////////////////////////////////////////////////////////////////////// 73* AddrComputeSurfaceInfo() 74* AddrComputeSurfaceAddrFromCoord() 75* AddrComputeSurfaceCoordFromAddr() 76* 77* ///////////////////////////////////////////////////////////////////////////////////////////////// 78* // HTile functions 79* ///////////////////////////////////////////////////////////////////////////////////////////////// 80* AddrComputeHtileInfo() 81* AddrComputeHtileAddrFromCoord() 82* AddrComputeHtileCoordFromAddr() 83* 84* ///////////////////////////////////////////////////////////////////////////////////////////////// 85* // C-mask functions 86* ///////////////////////////////////////////////////////////////////////////////////////////////// 87* AddrComputeCmaskInfo() 88* AddrComputeCmaskAddrFromCoord() 89* AddrComputeCmaskCoordFromAddr() 90* 91* ///////////////////////////////////////////////////////////////////////////////////////////////// 92* // F-mask functions 93* ///////////////////////////////////////////////////////////////////////////////////////////////// 94* AddrComputeFmaskInfo() 95* AddrComputeFmaskAddrFromCoord() 96* AddrComputeFmaskCoordFromAddr() 97* 98* ///////////////////////////////////////////////////////////////////////////////////////////////// 99* // Element/Utility functions 100* ///////////////////////////////////////////////////////////////////////////////////////////////// 101* ElemFlt32ToDepthPixel() 102* ElemFlt32ToColorPixel() 103* AddrExtractBankPipeSwizzle() 104* AddrCombineBankPipeSwizzle() 105* AddrComputeSliceSwizzle() 106* AddrConvertTileInfoToHW() 107* AddrConvertTileIndex() 108* AddrConvertTileIndex1() 109* AddrGetTileIndex() 110* AddrComputeBaseSwizzle() 111* AddrUseTileIndex() 112* AddrUseCombinedSwizzle() 113* 114**/ 115 116//////////////////////////////////////////////////////////////////////////////////////////////////// 117// Callback functions 118//////////////////////////////////////////////////////////////////////////////////////////////////// 119 120/** 121**************************************************************************************************** 122* @brief channel setting structure 123**************************************************************************************************** 124*/ 125typedef union _ADDR_CHANNEL_SETTING 126{ 127 struct 128 { 129 UINT_8 valid : 1; ///< Indicate whehter this channel setting is valid 130 UINT_8 channel : 2; ///< 0 for x channel, 1 for y channel, 2 for z channel 131 UINT_8 index : 5; ///< Channel index 132 }; 133 UINT_8 value; ///< Value 134} ADDR_CHANNEL_SETTING; 135 136/** 137**************************************************************************************************** 138* @brief address equation key structure 139**************************************************************************************************** 140*/ 141typedef union _ADDR_EQUATION_KEY 142{ 143 struct 144 { 145 UINT_32 log2ElementBytes : 3; ///< Log2 of Bytes per pixel 146 UINT_32 tileMode : 5; ///< Tile mode 147 UINT_32 microTileType : 3; ///< Micro tile type 148 UINT_32 pipeConfig : 5; ///< pipe config 149 UINT_32 numBanksLog2 : 3; ///< Number of banks log2 150 UINT_32 bankWidth : 4; ///< Bank width 151 UINT_32 bankHeight : 4; ///< Bank height 152 UINT_32 macroAspectRatio : 3; ///< Macro tile aspect ratio 153 UINT_32 prt : 1; ///< SI only, indicate whether this equation is for prt 154 UINT_32 reserved : 1; ///< Reserved bit 155 } fields; 156 UINT_32 value; 157} ADDR_EQUATION_KEY; 158 159/** 160**************************************************************************************************** 161* @brief address equation structure 162**************************************************************************************************** 163*/ 164#define ADDR_MAX_EQUATION_BIT 20u 165 166// Invalid equation index 167#define ADDR_INVALID_EQUATION_INDEX 0xFFFFFFFF 168 169typedef struct _ADDR_EQUATION 170{ 171 ADDR_CHANNEL_SETTING addr[ADDR_MAX_EQUATION_BIT]; ///< addr setting 172 ///< each bit is result of addr ^ xor ^ xor2 173 ADDR_CHANNEL_SETTING xor1[ADDR_MAX_EQUATION_BIT]; ///< xor setting 174 ADDR_CHANNEL_SETTING xor2[ADDR_MAX_EQUATION_BIT]; ///< xor2 setting 175 UINT_32 numBits; ///< The number of bits in equation 176 BOOL_32 stackedDepthSlices; ///< TRUE if depth slices are treated as being 177 ///< stacked vertically prior to swizzling 178} ADDR_EQUATION; 179 180 181/** 182**************************************************************************************************** 183* @brief Alloc system memory flags. 184* @note These flags are reserved for future use and if flags are added will minimize the impact 185* of the client. 186**************************************************************************************************** 187*/ 188typedef union _ADDR_ALLOCSYSMEM_FLAGS 189{ 190 struct 191 { 192 UINT_32 reserved : 32; ///< Reserved for future use. 193 } fields; 194 UINT_32 value; 195 196} ADDR_ALLOCSYSMEM_FLAGS; 197 198/** 199**************************************************************************************************** 200* @brief Alloc system memory input structure 201**************************************************************************************************** 202*/ 203typedef struct _ADDR_ALLOCSYSMEM_INPUT 204{ 205 UINT_32 size; ///< Size of this structure in bytes 206 207 ADDR_ALLOCSYSMEM_FLAGS flags; ///< System memory flags. 208 UINT_32 sizeInBytes; ///< System memory allocation size in bytes. 209 ADDR_CLIENT_HANDLE hClient; ///< Client handle 210} ADDR_ALLOCSYSMEM_INPUT; 211 212/** 213**************************************************************************************************** 214* ADDR_ALLOCSYSMEM 215* @brief 216* Allocate system memory callback function. Returns valid pointer on success. 217**************************************************************************************************** 218*/ 219typedef VOID* (ADDR_API* ADDR_ALLOCSYSMEM)( 220 const ADDR_ALLOCSYSMEM_INPUT* pInput); 221 222/** 223**************************************************************************************************** 224* @brief Free system memory input structure 225**************************************************************************************************** 226*/ 227typedef struct _ADDR_FREESYSMEM_INPUT 228{ 229 UINT_32 size; ///< Size of this structure in bytes 230 231 VOID* pVirtAddr; ///< Virtual address 232 ADDR_CLIENT_HANDLE hClient; ///< Client handle 233} ADDR_FREESYSMEM_INPUT; 234 235/** 236**************************************************************************************************** 237* ADDR_FREESYSMEM 238* @brief 239* Free system memory callback function. 240* Returns ADDR_OK on success. 241**************************************************************************************************** 242*/ 243typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_FREESYSMEM)( 244 const ADDR_FREESYSMEM_INPUT* pInput); 245 246/** 247**************************************************************************************************** 248* @brief Print debug message input structure 249**************************************************************************************************** 250*/ 251typedef struct _ADDR_DEBUGPRINT_INPUT 252{ 253 UINT_32 size; ///< Size of this structure in bytes 254 255 CHAR* pDebugString; ///< Debug print string 256 va_list ap; ///< Variable argument list 257 ADDR_CLIENT_HANDLE hClient; ///< Client handle 258} ADDR_DEBUGPRINT_INPUT; 259 260/** 261**************************************************************************************************** 262* ADDR_DEBUGPRINT 263* @brief 264* Print debug message callback function. 265* Returns ADDR_OK on success. 266**************************************************************************************************** 267*/ 268typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_DEBUGPRINT)( 269 const ADDR_DEBUGPRINT_INPUT* pInput); 270 271/** 272**************************************************************************************************** 273* ADDR_CALLBACKS 274* 275* @brief 276* Address Library needs client to provide system memory alloc/free routines. 277**************************************************************************************************** 278*/ 279typedef struct _ADDR_CALLBACKS 280{ 281 ADDR_ALLOCSYSMEM allocSysMem; ///< Routine to allocate system memory 282 ADDR_FREESYSMEM freeSysMem; ///< Routine to free system memory 283 ADDR_DEBUGPRINT debugPrint; ///< Routine to print debug message 284} ADDR_CALLBACKS; 285 286//////////////////////////////////////////////////////////////////////////////////////////////////// 287// Create/Destroy functions 288//////////////////////////////////////////////////////////////////////////////////////////////////// 289 290/** 291**************************************************************************************************** 292* ADDR_CREATE_FLAGS 293* 294* @brief 295* This structure is used to pass some setup in creation of AddrLib 296* @note 297**************************************************************************************************** 298*/ 299typedef union _ADDR_CREATE_FLAGS 300{ 301 struct 302 { 303 UINT_32 noCubeMipSlicesPad : 1; ///< Turn cubemap faces padding off 304 UINT_32 fillSizeFields : 1; ///< If clients fill size fields in all input and 305 /// output structure 306 UINT_32 useTileIndex : 1; ///< Make tileIndex field in input valid 307 UINT_32 useCombinedSwizzle : 1; ///< Use combined tile swizzle 308 UINT_32 checkLast2DLevel : 1; ///< Check the last 2D mip sub level 309 UINT_32 useHtileSliceAlign : 1; ///< Do htile single slice alignment 310 UINT_32 allowLargeThickTile : 1; ///< Allow 64*thickness*bytesPerPixel > rowSize 311 UINT_32 forceDccAndTcCompat : 1; ///< Force enable DCC and TC compatibility 312 UINT_32 nonPower2MemConfig : 1; ///< Video memory bit width is not power of 2 313 UINT_32 enableAltTiling : 1; ///< Enable alt tile mode 314 UINT_32 reserved : 22; ///< Reserved bits for future use 315 }; 316 317 UINT_32 value; 318} ADDR_CREATE_FLAGS; 319 320/** 321**************************************************************************************************** 322* ADDR_REGISTER_VALUE 323* 324* @brief 325* Data from registers to setup AddrLib global data, used in AddrCreate 326**************************************************************************************************** 327*/ 328typedef struct _ADDR_REGISTER_VALUE 329{ 330 UINT_32 gbAddrConfig; ///< For R8xx, use GB_ADDR_CONFIG register value. 331 /// For R6xx/R7xx, use GB_TILING_CONFIG. 332 /// But they can be treated as the same. 333 /// if this value is 0, use chip to set default value 334 UINT_32 backendDisables; ///< 1 bit per backend, starting with LSB. 1=disabled,0=enabled. 335 /// Register value of CC_RB_BACKEND_DISABLE.BACKEND_DISABLE 336 337 /// R800 registers----------------------------------------------- 338 UINT_32 noOfBanks; ///< Number of h/w ram banks - For r800: MC_ARB_RAMCFG.NOOFBANK 339 /// No enums for this value in h/w header files 340 /// 0: 4 341 /// 1: 8 342 /// 2: 16 343 UINT_32 noOfRanks; /// MC_ARB_RAMCFG.NOOFRANK 344 /// 0: 1 345 /// 1: 2 346 /// SI (R1000) registers----------------------------------------- 347 const UINT_32* pTileConfig; ///< Global tile setting tables 348 UINT_32 noOfEntries; ///< Number of entries in pTileConfig 349 350 ///< CI registers------------------------------------------------- 351 const UINT_32* pMacroTileConfig; ///< Global macro tile mode table 352 UINT_32 noOfMacroEntries; ///< Number of entries in pMacroTileConfig 353} ADDR_REGISTER_VALUE; 354 355/** 356**************************************************************************************************** 357* ADDR_CREATE_INPUT 358* 359* @brief 360* Parameters use to create an AddrLib Object. Caller must provide all fields. 361* 362**************************************************************************************************** 363*/ 364typedef struct _ADDR_CREATE_INPUT 365{ 366 UINT_32 size; ///< Size of this structure in bytes 367 368 UINT_32 chipEngine; ///< Chip Engine 369 UINT_32 chipFamily; ///< Chip Family 370 UINT_32 chipRevision; ///< Chip Revision 371 ADDR_CALLBACKS callbacks; ///< Callbacks for sysmem alloc/free/print 372 ADDR_CREATE_FLAGS createFlags; ///< Flags to setup AddrLib 373 ADDR_REGISTER_VALUE regValue; ///< Data from registers to setup AddrLib global data 374 ADDR_CLIENT_HANDLE hClient; ///< Client handle 375 UINT_32 minPitchAlignPixels; ///< Minimum pitch alignment in pixels 376} ADDR_CREATE_INPUT; 377 378/** 379**************************************************************************************************** 380* ADDR_CREATEINFO_OUTPUT 381* 382* @brief 383* Return AddrLib handle to client driver 384* 385**************************************************************************************************** 386*/ 387typedef struct _ADDR_CREATE_OUTPUT 388{ 389 UINT_32 size; ///< Size of this structure in bytes 390 391 ADDR_HANDLE hLib; ///< Address lib handle 392 393 UINT_32 numEquations; ///< Number of equations in the table 394 const ADDR_EQUATION* pEquationTable; ///< Pointer to the equation table 395} ADDR_CREATE_OUTPUT; 396 397/** 398**************************************************************************************************** 399* AddrCreate 400* 401* @brief 402* Create AddrLib object, must be called before any interface calls 403* 404* @return 405* ADDR_OK if successful 406**************************************************************************************************** 407*/ 408ADDR_E_RETURNCODE ADDR_API AddrCreate( 409 const ADDR_CREATE_INPUT* pAddrCreateIn, 410 ADDR_CREATE_OUTPUT* pAddrCreateOut); 411 412 413 414/** 415**************************************************************************************************** 416* AddrDestroy 417* 418* @brief 419* Destroy AddrLib object, must be called to free internally allocated resources. 420* 421* @return 422* ADDR_OK if successful 423**************************************************************************************************** 424*/ 425ADDR_E_RETURNCODE ADDR_API AddrDestroy( 426 ADDR_HANDLE hLib); 427 428 429 430//////////////////////////////////////////////////////////////////////////////////////////////////// 431// Surface functions 432//////////////////////////////////////////////////////////////////////////////////////////////////// 433 434/** 435**************************************************************************************************** 436* @brief 437* Bank/tiling parameters. On function input, these can be set as desired or 438* left 0 for AddrLib to calculate/default. On function output, these are the actual 439* parameters used. 440* @note 441* Valid bankWidth/bankHeight value: 442* 1,2,4,8. They are factors instead of pixels or bytes. 443* 444* The bank number remains constant across each row of the 445* macro tile as each pipe is selected, so the number of 446* tiles in the x direction with the same bank number will 447* be bank_width * num_pipes. 448**************************************************************************************************** 449*/ 450typedef struct _ADDR_TILEINFO 451{ 452 /// Any of these parameters can be set to 0 to use the HW default. 453 UINT_32 banks; ///< Number of banks, numerical value 454 UINT_32 bankWidth; ///< Number of tiles in the X direction in the same bank 455 UINT_32 bankHeight; ///< Number of tiles in the Y direction in the same bank 456 UINT_32 macroAspectRatio; ///< Macro tile aspect ratio. 1-1:1, 2-4:1, 4-16:1, 8-64:1 457 UINT_32 tileSplitBytes; ///< Tile split size, in bytes 458 AddrPipeCfg pipeConfig; ///< Pipe Config = HW enum + 1 459} ADDR_TILEINFO; 460 461// Create a define to avoid client change. The removal of R800 is because we plan to implement SI 462// within 800 HWL - An AddrPipeCfg is added in above data structure 463typedef ADDR_TILEINFO ADDR_R800_TILEINFO; 464 465/** 466**************************************************************************************************** 467* @brief 468* Information needed by quad buffer stereo support 469**************************************************************************************************** 470*/ 471typedef struct _ADDR_QBSTEREOINFO 472{ 473 UINT_32 eyeHeight; ///< Height (in pixel rows) to right eye 474 UINT_32 rightOffset; ///< Offset (in bytes) to right eye 475 UINT_32 rightSwizzle; ///< TileSwizzle for right eyes 476} ADDR_QBSTEREOINFO; 477 478/** 479**************************************************************************************************** 480* ADDR_SURFACE_FLAGS 481* 482* @brief 483* Surface flags 484**************************************************************************************************** 485*/ 486typedef union _ADDR_SURFACE_FLAGS 487{ 488 struct 489 { 490 UINT_32 color : 1; ///< Flag indicates this is a color buffer 491 UINT_32 depth : 1; ///< Flag indicates this is a depth/stencil buffer 492 UINT_32 stencil : 1; ///< Flag indicates this is a stencil buffer 493 UINT_32 texture : 1; ///< Flag indicates this is a texture 494 UINT_32 cube : 1; ///< Flag indicates this is a cubemap 495 UINT_32 volume : 1; ///< Flag indicates this is a volume texture 496 UINT_32 fmask : 1; ///< Flag indicates this is an fmask 497 UINT_32 cubeAsArray : 1; ///< Flag indicates if treat cubemap as arrays 498 UINT_32 compressZ : 1; ///< Flag indicates z buffer is compressed 499 UINT_32 overlay : 1; ///< Flag indicates this is an overlay surface 500 UINT_32 noStencil : 1; ///< Flag indicates this depth has no separate stencil 501 UINT_32 display : 1; ///< Flag indicates this should match display controller req. 502 UINT_32 opt4Space : 1; ///< Flag indicates this surface should be optimized for space 503 /// i.e. save some memory but may lose performance 504 UINT_32 prt : 1; ///< Flag for partially resident texture 505 UINT_32 qbStereo : 1; ///< Quad buffer stereo surface 506 UINT_32 pow2Pad : 1; ///< SI: Pad to pow2, must set for mipmap (include level0) 507 UINT_32 interleaved : 1; ///< Special flag for interleaved YUV surface padding 508 UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable 509 UINT_32 dispTileType : 1; ///< NI: force display Tiling for 128 bit shared resoruce 510 UINT_32 dccCompatible : 1; ///< VI: whether to make MSAA surface support dcc fast clear 511 UINT_32 dccPipeWorkaround : 1; ///< VI: whether to workaround the HW limit that 512 /// dcc can't be enabled if pipe config of tile mode 513 /// is different from that of ASIC, this flag 514 /// is address lib internal flag, client should ignore it 515 UINT_32 czDispCompatible : 1; ///< SI+: CZ family has a HW bug needs special alignment. 516 /// This flag indicates we need to follow the 517 /// alignment with CZ families or other ASICs under 518 /// PX configuration + CZ. 519 UINT_32 nonSplit : 1; ///< CI: depth texture should not be split 520 UINT_32 disableLinearOpt : 1; ///< Disable tile mode optimization to linear 521 UINT_32 needEquation : 1; ///< Make the surface tile setting equation compatible. 522 /// This flag indicates we need to override tile 523 /// mode to PRT_* tile mode to disable slice rotation, 524 /// which is needed by swizzle pattern equation. 525 UINT_32 skipIndicesOutput : 1; ///< Skipping indices in output. 526 UINT_32 rotateDisplay : 1; ///< Rotate micro tile type 527 UINT_32 minimizeAlignment : 1; ///< Minimize alignment 528 UINT_32 preferEquation : 1; ///< Return equation index without adjusting tile mode 529 UINT_32 matchStencilTileCfg : 1; ///< Select tile index of stencil as well as depth surface 530 /// to make sure they share same tile config parameters 531 UINT_32 disallowLargeThickDegrade : 1; ///< Disallow large thick tile degrade 532 UINT_32 reserved : 1; ///< Reserved bits 533 }; 534 535 UINT_32 value; 536} ADDR_SURFACE_FLAGS; 537 538/** 539**************************************************************************************************** 540* ADDR_COMPUTE_SURFACE_INFO_INPUT 541* 542* @brief 543* Input structure for AddrComputeSurfaceInfo 544**************************************************************************************************** 545*/ 546typedef struct _ADDR_COMPUTE_SURFACE_INFO_INPUT 547{ 548 UINT_32 size; ///< Size of this structure in bytes 549 550 AddrTileMode tileMode; ///< Tile mode 551 AddrFormat format; ///< If format is set to valid one, bpp/width/height 552 /// might be overwritten 553 UINT_32 bpp; ///< Bits per pixel 554 UINT_32 numSamples; ///< Number of samples 555 UINT_32 width; ///< Width, in pixels 556 UINT_32 height; ///< Height, in pixels 557 UINT_32 numSlices; ///< Number of surface slices or depth 558 UINT_32 slice; ///< Slice index 559 UINT_32 mipLevel; ///< Current mipmap level 560 UINT_32 numMipLevels; ///< Number of mips in mip chain 561 ADDR_SURFACE_FLAGS flags; ///< Surface type flags 562 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 563 /// number of samples for normal AA; Set it to the 564 /// number of fragments for EQAA 565 /// r800 and later HWL parameters 566 // Needed by 2D tiling, for linear and 1D tiling, just keep them 0's 567 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Set to 0 to default/calculate 568 AddrTileType tileType; ///< Micro tiling type, not needed when tileIndex != -1 569 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 570 /// while the global useTileIndex is set to 1 571 UINT_32 basePitch; ///< Base level pitch in pixels, 0 means ignored, is a 572 /// must for mip levels from SI+. 573 /// Don't use pitch in blocks for compressed formats! 574 UINT_32 maxBaseAlign; ///< Max base alignment request from client 575 UINT_32 pitchAlign; ///< Pitch alignment request from client 576 UINT_32 heightAlign; ///< Height alignment request from client 577} ADDR_COMPUTE_SURFACE_INFO_INPUT; 578 579/** 580**************************************************************************************************** 581* ADDR_COMPUTE_SURFACE_INFO_OUTPUT 582* 583* @brief 584* Output structure for AddrComputeSurfInfo 585* @note 586 Element: AddrLib unit for computing. e.g. BCn: 4x4 blocks; R32B32B32: 32bit with 3x pitch 587 Pixel: Original pixel 588**************************************************************************************************** 589*/ 590typedef struct _ADDR_COMPUTE_SURFACE_INFO_OUTPUT 591{ 592 UINT_32 size; ///< Size of this structure in bytes 593 594 UINT_32 pitch; ///< Pitch in elements (in blocks for compressed formats) 595 UINT_32 height; ///< Height in elements (in blocks for compressed formats) 596 UINT_32 depth; ///< Number of slice/depth 597 UINT_64 surfSize; ///< Surface size in bytes 598 AddrTileMode tileMode; ///< Actual tile mode. May differ from that in input 599 UINT_32 baseAlign; ///< Base address alignment 600 UINT_32 pitchAlign; ///< Pitch alignment, in elements 601 UINT_32 heightAlign; ///< Height alignment, in elements 602 UINT_32 depthAlign; ///< Depth alignment, aligned to thickness, for 3d texture 603 UINT_32 bpp; ///< Bits per elements (e.g. blocks for BCn, 1/3 for 96bit) 604 UINT_32 pixelPitch; ///< Pitch in original pixels 605 UINT_32 pixelHeight; ///< Height in original pixels 606 UINT_32 pixelBits; ///< Original bits per pixel, passed from input 607 UINT_64 sliceSize; ///< Size of slice specified by input's slice 608 /// The result is controlled by surface flags & createFlags 609 /// By default this value equals to surfSize for volume 610 UINT_32 pitchTileMax; ///< PITCH_TILE_MAX value for h/w register 611 UINT_32 heightTileMax; ///< HEIGHT_TILE_MAX value for h/w register 612 UINT_32 sliceTileMax; ///< SLICE_TILE_MAX value for h/w register 613 614 UINT_32 numSamples; ///< Pass the effective numSamples processed in this call 615 616 /// r800 and later HWL parameters 617 ADDR_TILEINFO* pTileInfo; ///< Tile parameters used. Filled in if 0 on input 618 AddrTileType tileType; ///< Micro tiling type, only valid when tileIndex != -1 619 INT_32 tileIndex; ///< Tile index, MAY be "downgraded" 620 621 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 622 /// Output flags 623 struct 624 { 625 /// Special information to work around SI mipmap swizzle bug UBTS #317508 626 UINT_32 last2DLevel : 1; ///< TRUE if this is the last 2D(3D) tiled 627 ///< Only meaningful when create flag checkLast2DLevel is set 628 UINT_32 tcCompatible : 1; ///< If the surface can be shader compatible 629 UINT_32 dccUnsupport : 1; ///< If the surface can support DCC compressed rendering 630 UINT_32 prtTileIndex : 1; ///< SI only, indicate the returned tile index is for PRT 631 ///< If address lib return true for mip 0, client should set prt flag 632 ///< for child mips in subsequent compute surface info calls 633 UINT_32 reserved :28; ///< Reserved bits 634 }; 635 636 UINT_32 equationIndex; ///< Equation index in the equation table; 637 638 UINT_32 blockWidth; ///< Width in element inside one block(1D->Micro, 2D->Macro) 639 UINT_32 blockHeight; ///< Height in element inside one block(1D->Micro, 2D->Macro) 640 UINT_32 blockSlices; ///< Slice number inside one block(1D->Micro, 2D->Macro) 641 642 /// Stereo info 643 ADDR_QBSTEREOINFO* pStereoInfo;///< Stereo information, needed when .qbStereo flag is TRUE 644 645 INT_32 stencilTileIdx; ///< stencil tile index output when matchStencilTileCfg was set 646} ADDR_COMPUTE_SURFACE_INFO_OUTPUT; 647 648/** 649**************************************************************************************************** 650* AddrComputeSurfaceInfo 651* 652* @brief 653* Compute surface width/height/depth/alignments and suitable tiling mode 654**************************************************************************************************** 655*/ 656ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceInfo( 657 ADDR_HANDLE hLib, 658 const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, 659 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut); 660 661 662 663/** 664**************************************************************************************************** 665* ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT 666* 667* @brief 668* Input structure for AddrComputeSurfaceAddrFromCoord 669**************************************************************************************************** 670*/ 671typedef struct _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT 672{ 673 UINT_32 size; ///< Size of this structure in bytes 674 675 UINT_32 x; ///< X coordinate 676 UINT_32 y; ///< Y coordinate 677 UINT_32 slice; ///< Slice index 678 UINT_32 sample; ///< Sample index, use fragment index for EQAA 679 680 UINT_32 bpp; ///< Bits per pixel 681 UINT_32 pitch; ///< Surface pitch, in pixels 682 UINT_32 height; ///< Surface height, in pixels 683 UINT_32 numSlices; ///< Surface depth 684 UINT_32 numSamples; ///< Number of samples 685 686 AddrTileMode tileMode; ///< Tile mode 687 BOOL_32 isDepth; ///< TRUE if the surface uses depth sample ordering within 688 /// micro tile. Textures can also choose depth sample order 689 UINT_32 tileBase; ///< Base offset (in bits) inside micro tile which handles 690 /// the case that components are stored separately 691 UINT_32 compBits; ///< The component bits actually needed(for planar surface) 692 693 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 694 /// number of samples for normal AA; Set it to the 695 /// number of fragments for EQAA 696 /// r800 and later HWL parameters 697 // Used for 1D tiling above 698 AddrTileType tileType; ///< See defintion of AddrTileType 699 struct 700 { 701 UINT_32 ignoreSE : 1; ///< TRUE if shader engines are ignored. This is texture 702 /// only flag. Only non-RT texture can set this to TRUE 703 UINT_32 reserved :31; ///< Reserved for future use. 704 }; 705 // 2D tiling needs following structure 706 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 707 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 708 /// while the global useTileIndex is set to 1 709 union 710 { 711 struct 712 { 713 UINT_32 bankSwizzle; ///< Bank swizzle 714 UINT_32 pipeSwizzle; ///< Pipe swizzle 715 }; 716 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE 717 }; 718} ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT; 719 720/** 721**************************************************************************************************** 722* ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 723* 724* @brief 725* Output structure for AddrComputeSurfaceAddrFromCoord 726**************************************************************************************************** 727*/ 728typedef struct _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 729{ 730 UINT_32 size; ///< Size of this structure in bytes 731 732 UINT_64 addr; ///< Byte address 733 UINT_32 bitPosition; ///< Bit position within surfaceAddr, 0-7. 734 /// For surface bpp < 8, e.g. FMT_1. 735 UINT_32 prtBlockIndex; ///< Index of a PRT tile (64K block) 736} ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT; 737 738/** 739**************************************************************************************************** 740* AddrComputeSurfaceAddrFromCoord 741* 742* @brief 743* Compute surface address from a given coordinate. 744**************************************************************************************************** 745*/ 746ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceAddrFromCoord( 747 ADDR_HANDLE hLib, 748 const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 749 ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut); 750 751 752 753/** 754**************************************************************************************************** 755* ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT 756* 757* @brief 758* Input structure for AddrComputeSurfaceCoordFromAddr 759**************************************************************************************************** 760*/ 761typedef struct _ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT 762{ 763 UINT_32 size; ///< Size of this structure in bytes 764 765 UINT_64 addr; ///< Address in bytes 766 UINT_32 bitPosition; ///< Bit position in addr. 0-7. for surface bpp < 8, 767 /// e.g. FMT_1; 768 UINT_32 bpp; ///< Bits per pixel 769 UINT_32 pitch; ///< Pitch, in pixels 770 UINT_32 height; ///< Height in pixels 771 UINT_32 numSlices; ///< Surface depth 772 UINT_32 numSamples; ///< Number of samples 773 774 AddrTileMode tileMode; ///< Tile mode 775 BOOL_32 isDepth; ///< Surface uses depth sample ordering within micro tile. 776 /// Note: Textures can choose depth sample order as well. 777 UINT_32 tileBase; ///< Base offset (in bits) inside micro tile which handles 778 /// the case that components are stored separately 779 UINT_32 compBits; ///< The component bits actually needed(for planar surface) 780 781 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 782 /// number of samples for normal AA; Set it to the 783 /// number of fragments for EQAA 784 /// r800 and later HWL parameters 785 // Used for 1D tiling above 786 AddrTileType tileType; ///< See defintion of AddrTileType 787 struct 788 { 789 UINT_32 ignoreSE : 1; ///< TRUE if shader engines are ignored. This is texture 790 /// only flag. Only non-RT texture can set this to TRUE 791 UINT_32 reserved :31; ///< Reserved for future use. 792 }; 793 // 2D tiling needs following structure 794 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 795 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 796 /// while the global useTileIndex is set to 1 797 union 798 { 799 struct 800 { 801 UINT_32 bankSwizzle; ///< Bank swizzle 802 UINT_32 pipeSwizzle; ///< Pipe swizzle 803 }; 804 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE 805 }; 806} ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT; 807 808/** 809**************************************************************************************************** 810* ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT 811* 812* @brief 813* Output structure for AddrComputeSurfaceCoordFromAddr 814**************************************************************************************************** 815*/ 816typedef struct _ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT 817{ 818 UINT_32 size; ///< Size of this structure in bytes 819 820 UINT_32 x; ///< X coordinate 821 UINT_32 y; ///< Y coordinate 822 UINT_32 slice; ///< Index of slices 823 UINT_32 sample; ///< Index of samples, means fragment index for EQAA 824} ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT; 825 826/** 827**************************************************************************************************** 828* AddrComputeSurfaceCoordFromAddr 829* 830* @brief 831* Compute coordinate from a given surface address 832**************************************************************************************************** 833*/ 834ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceCoordFromAddr( 835 ADDR_HANDLE hLib, 836 const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn, 837 ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut); 838 839//////////////////////////////////////////////////////////////////////////////////////////////////// 840// HTile functions 841//////////////////////////////////////////////////////////////////////////////////////////////////// 842 843/** 844**************************************************************************************************** 845* ADDR_HTILE_FLAGS 846* 847* @brief 848* HTILE flags 849**************************************************************************************************** 850*/ 851typedef union _ADDR_HTILE_FLAGS 852{ 853 struct 854 { 855 UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable 856 UINT_32 skipTcCompatSizeAlign : 1; ///< Flag indicates that addrLib will not align htile 857 /// size to 256xBankxPipe when computing tc-compatible 858 /// htile info. 859 UINT_32 reserved : 30; ///< Reserved bits 860 }; 861 862 UINT_32 value; 863} ADDR_HTILE_FLAGS; 864 865/** 866**************************************************************************************************** 867* ADDR_COMPUTE_HTILE_INFO_INPUT 868* 869* @brief 870* Input structure of AddrComputeHtileInfo 871**************************************************************************************************** 872*/ 873typedef struct _ADDR_COMPUTE_HTILE_INFO_INPUT 874{ 875 UINT_32 size; ///< Size of this structure in bytes 876 877 ADDR_HTILE_FLAGS flags; ///< HTILE flags 878 UINT_32 pitch; ///< Surface pitch, in pixels 879 UINT_32 height; ///< Surface height, in pixels 880 UINT_32 numSlices; ///< Number of slices 881 BOOL_32 isLinear; ///< Linear or tiled HTILE layout 882 AddrHtileBlockSize blockWidth; ///< 4 or 8. EG above only support 8 883 AddrHtileBlockSize blockHeight; ///< 4 or 8. EG above only support 8 884 ADDR_TILEINFO* pTileInfo; ///< Tile info 885 886 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 887 /// while the global useTileIndex is set to 1 888 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 889 ///< README: When tileIndex is not -1, this must be valid 890} ADDR_COMPUTE_HTILE_INFO_INPUT; 891 892/** 893**************************************************************************************************** 894* ADDR_COMPUTE_HTILE_INFO_OUTPUT 895* 896* @brief 897* Output structure of AddrComputeHtileInfo 898**************************************************************************************************** 899*/ 900typedef struct _ADDR_COMPUTE_HTILE_INFO_OUTPUT 901{ 902 UINT_32 size; ///< Size of this structure in bytes 903 904 UINT_32 pitch; ///< Pitch in pixels of depth buffer represented in this 905 /// HTile buffer. This might be larger than original depth 906 /// buffer pitch when called with an unaligned pitch. 907 UINT_32 height; ///< Height in pixels, as above 908 UINT_64 htileBytes; ///< Size of HTILE buffer, in bytes 909 UINT_32 baseAlign; ///< Base alignment 910 UINT_32 bpp; ///< Bits per pixel for HTILE is how many bits for an 8x8 block! 911 UINT_32 macroWidth; ///< Macro width in pixels, actually squared cache shape 912 UINT_32 macroHeight; ///< Macro height in pixels 913 UINT_64 sliceSize; ///< Slice size, in bytes. 914 BOOL_32 sliceInterleaved; ///< Flag to indicate if different slice's htile is interleaved 915 /// Compute engine clear can't be used if htile is interleaved 916 BOOL_32 nextMipLevelCompressible; ///< Flag to indicate whether HTILE can be enabled in 917 /// next mip level, it also indicates if memory set based 918 /// fast clear can be used for current mip level. 919} ADDR_COMPUTE_HTILE_INFO_OUTPUT; 920 921/** 922**************************************************************************************************** 923* AddrComputeHtileInfo 924* 925* @brief 926* Compute Htile pitch, height, base alignment and size in bytes 927**************************************************************************************************** 928*/ 929ADDR_E_RETURNCODE ADDR_API AddrComputeHtileInfo( 930 ADDR_HANDLE hLib, 931 const ADDR_COMPUTE_HTILE_INFO_INPUT* pIn, 932 ADDR_COMPUTE_HTILE_INFO_OUTPUT* pOut); 933 934 935 936/** 937**************************************************************************************************** 938* ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT 939* 940* @brief 941* Input structure for AddrComputeHtileAddrFromCoord 942**************************************************************************************************** 943*/ 944typedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT 945{ 946 UINT_32 size; ///< Size of this structure in bytes 947 948 UINT_32 pitch; ///< Pitch, in pixels 949 UINT_32 height; ///< Height in pixels 950 UINT_32 x; ///< X coordinate 951 UINT_32 y; ///< Y coordinate 952 UINT_32 slice; ///< Index of slice 953 UINT_32 numSlices; ///< Number of slices 954 BOOL_32 isLinear; ///< Linear or tiled HTILE layout 955 ADDR_HTILE_FLAGS flags; ///< htile flags 956 AddrHtileBlockSize blockWidth; ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8 957 AddrHtileBlockSize blockHeight; ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8 958 ADDR_TILEINFO* pTileInfo; ///< Tile info 959 960 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 961 /// while the global useTileIndex is set to 1 962 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 963 ///< README: When tileIndex is not -1, this must be valid 964 UINT_32 bpp; ///< depth/stencil buffer bit per pixel size 965 UINT_32 zStencilAddr; ///< tcCompatible Z/Stencil surface address 966} ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT; 967 968/** 969**************************************************************************************************** 970* ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT 971* 972* @brief 973* Output structure for AddrComputeHtileAddrFromCoord 974**************************************************************************************************** 975*/ 976typedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT 977{ 978 UINT_32 size; ///< Size of this structure in bytes 979 980 UINT_64 addr; ///< Address in bytes 981 UINT_32 bitPosition; ///< Bit position, 0 or 4. CMASK and HTILE shares some lib method. 982 /// So we keep bitPosition for HTILE as well 983} ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT; 984 985/** 986**************************************************************************************************** 987* AddrComputeHtileAddrFromCoord 988* 989* @brief 990* Compute Htile address according to coordinates (of depth buffer) 991**************************************************************************************************** 992*/ 993ADDR_E_RETURNCODE ADDR_API AddrComputeHtileAddrFromCoord( 994 ADDR_HANDLE hLib, 995 const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 996 ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut); 997 998 999 1000/** 1001**************************************************************************************************** 1002* ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT 1003* 1004* @brief 1005* Input structure for AddrComputeHtileCoordFromAddr 1006**************************************************************************************************** 1007*/ 1008typedef struct _ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT 1009{ 1010 UINT_32 size; ///< Size of this structure in bytes 1011 1012 UINT_64 addr; ///< Address 1013 UINT_32 bitPosition; ///< Bit position 0 or 4. CMASK and HTILE share some methods 1014 /// so we keep bitPosition for HTILE as well 1015 UINT_32 pitch; ///< Pitch, in pixels 1016 UINT_32 height; ///< Height, in pixels 1017 UINT_32 numSlices; ///< Number of slices 1018 BOOL_32 isLinear; ///< Linear or tiled HTILE layout 1019 AddrHtileBlockSize blockWidth; ///< 4 or 8. 1 means 8, 0 means 4. R8xx/R9xx only support 8 1020 AddrHtileBlockSize blockHeight; ///< 4 or 8. 1 means 8, 0 means 4. R8xx/R9xx only support 8 1021 ADDR_TILEINFO* pTileInfo; ///< Tile info 1022 1023 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1024 /// while the global useTileIndex is set to 1 1025 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1026 ///< README: When tileIndex is not -1, this must be valid 1027} ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT; 1028 1029/** 1030**************************************************************************************************** 1031* ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT 1032* 1033* @brief 1034* Output structure for AddrComputeHtileCoordFromAddr 1035**************************************************************************************************** 1036*/ 1037typedef struct _ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT 1038{ 1039 UINT_32 size; ///< Size of this structure in bytes 1040 1041 UINT_32 x; ///< X coordinate 1042 UINT_32 y; ///< Y coordinate 1043 UINT_32 slice; ///< Slice index 1044} ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT; 1045 1046/** 1047**************************************************************************************************** 1048* AddrComputeHtileCoordFromAddr 1049* 1050* @brief 1051* Compute coordinates within depth buffer (1st pixel of a micro tile) according to 1052* Htile address 1053**************************************************************************************************** 1054*/ 1055ADDR_E_RETURNCODE ADDR_API AddrComputeHtileCoordFromAddr( 1056 ADDR_HANDLE hLib, 1057 const ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 1058 ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut); 1059 1060 1061 1062//////////////////////////////////////////////////////////////////////////////////////////////////// 1063// C-mask functions 1064//////////////////////////////////////////////////////////////////////////////////////////////////// 1065 1066/** 1067**************************************************************************************************** 1068* ADDR_CMASK_FLAGS 1069* 1070* @brief 1071* CMASK flags 1072**************************************************************************************************** 1073*/ 1074typedef union _ADDR_CMASK_FLAGS 1075{ 1076 struct 1077 { 1078 UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable 1079 UINT_32 reserved :31; ///< Reserved bits 1080 }; 1081 1082 UINT_32 value; 1083} ADDR_CMASK_FLAGS; 1084 1085/** 1086**************************************************************************************************** 1087* ADDR_COMPUTE_CMASK_INFO_INPUT 1088* 1089* @brief 1090* Input structure of AddrComputeCmaskInfo 1091**************************************************************************************************** 1092*/ 1093typedef struct _ADDR_COMPUTE_CMASKINFO_INPUT 1094{ 1095 UINT_32 size; ///< Size of this structure in bytes 1096 1097 ADDR_CMASK_FLAGS flags; ///< CMASK flags 1098 UINT_32 pitch; ///< Pitch, in pixels, of color buffer 1099 UINT_32 height; ///< Height, in pixels, of color buffer 1100 UINT_32 numSlices; ///< Number of slices, of color buffer 1101 BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear 1102 ADDR_TILEINFO* pTileInfo; ///< Tile info 1103 1104 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1105 /// while the global useTileIndex is set to 1 1106 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1107 ///< README: When tileIndex is not -1, this must be valid 1108} ADDR_COMPUTE_CMASK_INFO_INPUT; 1109 1110/** 1111**************************************************************************************************** 1112* ADDR_COMPUTE_CMASK_INFO_OUTPUT 1113* 1114* @brief 1115* Output structure of AddrComputeCmaskInfo 1116**************************************************************************************************** 1117*/ 1118typedef struct _ADDR_COMPUTE_CMASK_INFO_OUTPUT 1119{ 1120 UINT_32 size; ///< Size of this structure in bytes 1121 1122 UINT_32 pitch; ///< Pitch in pixels of color buffer which 1123 /// this Cmask matches. The size might be larger than 1124 /// original color buffer pitch when called with 1125 /// an unaligned pitch. 1126 UINT_32 height; ///< Height in pixels, as above 1127 UINT_64 cmaskBytes; ///< Size in bytes of CMask buffer 1128 UINT_32 baseAlign; ///< Base alignment 1129 UINT_32 blockMax; ///< Cmask block size. Need this to set CB_COLORn_MASK register 1130 UINT_32 macroWidth; ///< Macro width in pixels, actually squared cache shape 1131 UINT_32 macroHeight; ///< Macro height in pixels 1132 UINT_64 sliceSize; ///< Slice size, in bytes. 1133} ADDR_COMPUTE_CMASK_INFO_OUTPUT; 1134 1135/** 1136**************************************************************************************************** 1137* AddrComputeCmaskInfo 1138* 1139* @brief 1140* Compute Cmask pitch, height, base alignment and size in bytes from color buffer 1141* info 1142**************************************************************************************************** 1143*/ 1144ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskInfo( 1145 ADDR_HANDLE hLib, 1146 const ADDR_COMPUTE_CMASK_INFO_INPUT* pIn, 1147 ADDR_COMPUTE_CMASK_INFO_OUTPUT* pOut); 1148 1149 1150 1151/** 1152**************************************************************************************************** 1153* ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT 1154* 1155* @brief 1156* Input structure for AddrComputeCmaskAddrFromCoord 1157* 1158**************************************************************************************************** 1159*/ 1160typedef struct _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT 1161{ 1162 UINT_32 size; ///< Size of this structure in bytes 1163 UINT_32 x; ///< X coordinate 1164 UINT_32 y; ///< Y coordinate 1165 UINT_64 fmaskAddr; ///< Fmask addr for tc compatible Cmask 1166 UINT_32 slice; ///< Slice index 1167 UINT_32 pitch; ///< Pitch in pixels, of color buffer 1168 UINT_32 height; ///< Height in pixels, of color buffer 1169 UINT_32 numSlices; ///< Number of slices 1170 UINT_32 bpp; 1171 BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear 1172 ADDR_CMASK_FLAGS flags; ///< CMASK flags 1173 ADDR_TILEINFO* pTileInfo; ///< Tile info 1174 1175 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1176 ///< while the global useTileIndex is set to 1 1177 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1178 ///< README: When tileIndex is not -1, this must be valid 1179} ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT; 1180 1181/** 1182**************************************************************************************************** 1183* ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 1184* 1185* @brief 1186* Output structure for AddrComputeCmaskAddrFromCoord 1187**************************************************************************************************** 1188*/ 1189typedef struct _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 1190{ 1191 UINT_32 size; ///< Size of this structure in bytes 1192 1193 UINT_64 addr; ///< CMASK address in bytes 1194 UINT_32 bitPosition; ///< Bit position within addr, 0-7. CMASK is 4 bpp, 1195 /// so the address may be located in bit 0 (0) or 4 (4) 1196} ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT; 1197 1198/** 1199**************************************************************************************************** 1200* AddrComputeCmaskAddrFromCoord 1201* 1202* @brief 1203* Compute Cmask address according to coordinates (of MSAA color buffer) 1204**************************************************************************************************** 1205*/ 1206ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskAddrFromCoord( 1207 ADDR_HANDLE hLib, 1208 const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, 1209 ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut); 1210 1211 1212 1213/** 1214**************************************************************************************************** 1215* ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT 1216* 1217* @brief 1218* Input structure for AddrComputeCmaskCoordFromAddr 1219**************************************************************************************************** 1220*/ 1221typedef struct _ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT 1222{ 1223 UINT_32 size; ///< Size of this structure in bytes 1224 1225 UINT_64 addr; ///< CMASK address in bytes 1226 UINT_32 bitPosition; ///< Bit position within addr, 0-7. CMASK is 4 bpp, 1227 /// so the address may be located in bit 0 (0) or 4 (4) 1228 UINT_32 pitch; ///< Pitch, in pixels 1229 UINT_32 height; ///< Height in pixels 1230 UINT_32 numSlices; ///< Number of slices 1231 BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear 1232 ADDR_TILEINFO* pTileInfo; ///< Tile info 1233 1234 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1235 /// while the global useTileIndex is set to 1 1236 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1237 ///< README: When tileIndex is not -1, this must be valid 1238} ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT; 1239 1240/** 1241**************************************************************************************************** 1242* ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT 1243* 1244* @brief 1245* Output structure for AddrComputeCmaskCoordFromAddr 1246**************************************************************************************************** 1247*/ 1248typedef struct _ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT 1249{ 1250 UINT_32 size; ///< Size of this structure in bytes 1251 1252 UINT_32 x; ///< X coordinate 1253 UINT_32 y; ///< Y coordinate 1254 UINT_32 slice; ///< Slice index 1255} ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT; 1256 1257/** 1258**************************************************************************************************** 1259* AddrComputeCmaskCoordFromAddr 1260* 1261* @brief 1262* Compute coordinates within color buffer (1st pixel of a micro tile) according to 1263* Cmask address 1264**************************************************************************************************** 1265*/ 1266ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskCoordFromAddr( 1267 ADDR_HANDLE hLib, 1268 const ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn, 1269 ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut); 1270 1271 1272 1273//////////////////////////////////////////////////////////////////////////////////////////////////// 1274// F-mask functions 1275//////////////////////////////////////////////////////////////////////////////////////////////////// 1276 1277/** 1278**************************************************************************************************** 1279* ADDR_COMPUTE_FMASK_INFO_INPUT 1280* 1281* @brief 1282* Input structure for AddrComputeFmaskInfo 1283**************************************************************************************************** 1284*/ 1285typedef struct _ADDR_COMPUTE_FMASK_INFO_INPUT 1286{ 1287 UINT_32 size; ///< Size of this structure in bytes 1288 1289 AddrTileMode tileMode; ///< Tile mode 1290 UINT_32 pitch; ///< Surface pitch, in pixels 1291 UINT_32 height; ///< Surface height, in pixels 1292 UINT_32 numSlices; ///< Number of slice/depth 1293 UINT_32 numSamples; ///< Number of samples 1294 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 1295 /// number of samples for normal AA; Set it to the 1296 /// number of fragments for EQAA 1297 /// r800 and later HWL parameters 1298 struct 1299 { 1300 UINT_32 resolved: 1; ///< TRUE if the surface is for resolved fmask, only used 1301 /// by H/W clients. S/W should always set it to FALSE. 1302 UINT_32 reserved: 31; ///< Reserved for future use. 1303 }; 1304 ADDR_TILEINFO* pTileInfo; ///< 2D tiling parameters. Clients must give valid data 1305 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1306 /// while the global useTileIndex is set to 1 1307} ADDR_COMPUTE_FMASK_INFO_INPUT; 1308 1309/** 1310**************************************************************************************************** 1311* ADDR_COMPUTE_FMASK_INFO_OUTPUT 1312* 1313* @brief 1314* Output structure for AddrComputeFmaskInfo 1315**************************************************************************************************** 1316*/ 1317typedef struct _ADDR_COMPUTE_FMASK_INFO_OUTPUT 1318{ 1319 UINT_32 size; ///< Size of this structure in bytes 1320 1321 UINT_32 pitch; ///< Pitch of fmask in pixels 1322 UINT_32 height; ///< Height of fmask in pixels 1323 UINT_32 numSlices; ///< Slices of fmask 1324 UINT_64 fmaskBytes; ///< Size of fmask in bytes 1325 UINT_32 baseAlign; ///< Base address alignment 1326 UINT_32 pitchAlign; ///< Pitch alignment 1327 UINT_32 heightAlign; ///< Height alignment 1328 UINT_32 bpp; ///< Bits per pixel of FMASK is: number of bit planes 1329 UINT_32 numSamples; ///< Number of samples, used for dump, export this since input 1330 /// may be changed in 9xx and above 1331 /// r800 and later HWL parameters 1332 ADDR_TILEINFO* pTileInfo; ///< Tile parameters used. Fmask can have different 1333 /// bank_height from color buffer 1334 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1335 /// while the global useTileIndex is set to 1 1336 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1337 UINT_64 sliceSize; ///< Size of slice in bytes 1338} ADDR_COMPUTE_FMASK_INFO_OUTPUT; 1339 1340/** 1341**************************************************************************************************** 1342* AddrComputeFmaskInfo 1343* 1344* @brief 1345* Compute Fmask pitch/height/depth/alignments and size in bytes 1346**************************************************************************************************** 1347*/ 1348ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskInfo( 1349 ADDR_HANDLE hLib, 1350 const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn, 1351 ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut); 1352 1353 1354 1355/** 1356**************************************************************************************************** 1357* ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT 1358* 1359* @brief 1360* Input structure for AddrComputeFmaskAddrFromCoord 1361**************************************************************************************************** 1362*/ 1363typedef struct _ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT 1364{ 1365 UINT_32 size; ///< Size of this structure in bytes 1366 1367 UINT_32 x; ///< X coordinate 1368 UINT_32 y; ///< Y coordinate 1369 UINT_32 slice; ///< Slice index 1370 UINT_32 plane; ///< Plane number 1371 UINT_32 sample; ///< Sample index (fragment index for EQAA) 1372 1373 UINT_32 pitch; ///< Surface pitch, in pixels 1374 UINT_32 height; ///< Surface height, in pixels 1375 UINT_32 numSamples; ///< Number of samples 1376 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 1377 /// number of samples for normal AA; Set it to the 1378 /// number of fragments for EQAA 1379 1380 AddrTileMode tileMode; ///< Tile mode 1381 union 1382 { 1383 struct 1384 { 1385 UINT_32 bankSwizzle; ///< Bank swizzle 1386 UINT_32 pipeSwizzle; ///< Pipe swizzle 1387 }; 1388 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE 1389 }; 1390 1391 /// r800 and later HWL parameters 1392 struct 1393 { 1394 UINT_32 resolved: 1; ///< TRUE if this is a resolved fmask, used by H/W clients 1395 UINT_32 ignoreSE: 1; ///< TRUE if shader engines are ignored. 1396 UINT_32 reserved: 30; ///< Reserved for future use. 1397 }; 1398 ADDR_TILEINFO* pTileInfo; ///< 2D tiling parameters. Client must provide all data 1399 1400} ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT; 1401 1402/** 1403**************************************************************************************************** 1404* ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT 1405* 1406* @brief 1407* Output structure for AddrComputeFmaskAddrFromCoord 1408**************************************************************************************************** 1409*/ 1410typedef struct _ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT 1411{ 1412 UINT_32 size; ///< Size of this structure in bytes 1413 1414 UINT_64 addr; ///< Fmask address 1415 UINT_32 bitPosition; ///< Bit position within fmaskAddr, 0-7. 1416} ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT; 1417 1418/** 1419**************************************************************************************************** 1420* AddrComputeFmaskAddrFromCoord 1421* 1422* @brief 1423* Compute Fmask address according to coordinates (x,y,slice,sample,plane) 1424**************************************************************************************************** 1425*/ 1426ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskAddrFromCoord( 1427 ADDR_HANDLE hLib, 1428 const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn, 1429 ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut); 1430 1431 1432 1433/** 1434**************************************************************************************************** 1435* ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT 1436* 1437* @brief 1438* Input structure for AddrComputeFmaskCoordFromAddr 1439**************************************************************************************************** 1440*/ 1441typedef struct _ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT 1442{ 1443 UINT_32 size; ///< Size of this structure in bytes 1444 1445 UINT_64 addr; ///< Address 1446 UINT_32 bitPosition; ///< Bit position within addr, 0-7. 1447 1448 UINT_32 pitch; ///< Pitch, in pixels 1449 UINT_32 height; ///< Height in pixels 1450 UINT_32 numSamples; ///< Number of samples 1451 UINT_32 numFrags; ///< Number of fragments 1452 AddrTileMode tileMode; ///< Tile mode 1453 union 1454 { 1455 struct 1456 { 1457 UINT_32 bankSwizzle; ///< Bank swizzle 1458 UINT_32 pipeSwizzle; ///< Pipe swizzle 1459 }; 1460 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE 1461 }; 1462 1463 /// r800 and later HWL parameters 1464 struct 1465 { 1466 UINT_32 resolved: 1; ///< TRUE if this is a resolved fmask, used by HW components 1467 UINT_32 ignoreSE: 1; ///< TRUE if shader engines are ignored. 1468 UINT_32 reserved: 30; ///< Reserved for future use. 1469 }; 1470 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 1471 1472} ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT; 1473 1474/** 1475**************************************************************************************************** 1476* ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT 1477* 1478* @brief 1479* Output structure for AddrComputeFmaskCoordFromAddr 1480**************************************************************************************************** 1481*/ 1482typedef struct _ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT 1483{ 1484 UINT_32 size; ///< Size of this structure in bytes 1485 1486 UINT_32 x; ///< X coordinate 1487 UINT_32 y; ///< Y coordinate 1488 UINT_32 slice; ///< Slice index 1489 UINT_32 plane; ///< Plane number 1490 UINT_32 sample; ///< Sample index (fragment index for EQAA) 1491} ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT; 1492 1493/** 1494**************************************************************************************************** 1495* AddrComputeFmaskCoordFromAddr 1496* 1497* @brief 1498* Compute FMASK coordinate from an given address 1499**************************************************************************************************** 1500*/ 1501ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskCoordFromAddr( 1502 ADDR_HANDLE hLib, 1503 const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn, 1504 ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut); 1505 1506 1507 1508//////////////////////////////////////////////////////////////////////////////////////////////////// 1509// Element/utility functions 1510//////////////////////////////////////////////////////////////////////////////////////////////////// 1511 1512/** 1513**************************************************************************************************** 1514* AddrGetVersion 1515* 1516* @brief 1517* Get AddrLib version number 1518**************************************************************************************************** 1519*/ 1520UINT_32 ADDR_API AddrGetVersion(ADDR_HANDLE hLib); 1521 1522/** 1523**************************************************************************************************** 1524* AddrUseTileIndex 1525* 1526* @brief 1527* Return TRUE if tileIndex is enabled in this address library 1528**************************************************************************************************** 1529*/ 1530BOOL_32 ADDR_API AddrUseTileIndex(ADDR_HANDLE hLib); 1531 1532/** 1533**************************************************************************************************** 1534* AddrUseCombinedSwizzle 1535* 1536* @brief 1537* Return TRUE if combined swizzle is enabled in this address library 1538**************************************************************************************************** 1539*/ 1540BOOL_32 ADDR_API AddrUseCombinedSwizzle(ADDR_HANDLE hLib); 1541 1542/** 1543**************************************************************************************************** 1544* ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT 1545* 1546* @brief 1547* Input structure of AddrExtractBankPipeSwizzle 1548**************************************************************************************************** 1549*/ 1550typedef struct _ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT 1551{ 1552 UINT_32 size; ///< Size of this structure in bytes 1553 1554 UINT_32 base256b; ///< Base256b value 1555 1556 /// r800 and later HWL parameters 1557 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 1558 1559 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1560 /// while the global useTileIndex is set to 1 1561 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1562 ///< README: When tileIndex is not -1, this must be valid 1563} ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT; 1564 1565/** 1566**************************************************************************************************** 1567* ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT 1568* 1569* @brief 1570* Output structure of AddrExtractBankPipeSwizzle 1571**************************************************************************************************** 1572*/ 1573typedef struct _ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT 1574{ 1575 UINT_32 size; ///< Size of this structure in bytes 1576 1577 UINT_32 bankSwizzle; ///< Bank swizzle 1578 UINT_32 pipeSwizzle; ///< Pipe swizzle 1579} ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT; 1580 1581/** 1582**************************************************************************************************** 1583* AddrExtractBankPipeSwizzle 1584* 1585* @brief 1586* Extract Bank and Pipe swizzle from base256b 1587* @return 1588* ADDR_OK if no error 1589**************************************************************************************************** 1590*/ 1591ADDR_E_RETURNCODE ADDR_API AddrExtractBankPipeSwizzle( 1592 ADDR_HANDLE hLib, 1593 const ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT* pIn, 1594 ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT* pOut); 1595 1596 1597/** 1598**************************************************************************************************** 1599* ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT 1600* 1601* @brief 1602* Input structure of AddrCombineBankPipeSwizzle 1603**************************************************************************************************** 1604*/ 1605typedef struct _ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT 1606{ 1607 UINT_32 size; ///< Size of this structure in bytes 1608 1609 UINT_32 bankSwizzle; ///< Bank swizzle 1610 UINT_32 pipeSwizzle; ///< Pipe swizzle 1611 UINT_64 baseAddr; ///< Base address (leave it zero for driver clients) 1612 1613 /// r800 and later HWL parameters 1614 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 1615 1616 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1617 /// while the global useTileIndex is set to 1 1618 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1619 ///< README: When tileIndex is not -1, this must be valid 1620} ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT; 1621 1622/** 1623**************************************************************************************************** 1624* ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT 1625* 1626* @brief 1627* Output structure of AddrCombineBankPipeSwizzle 1628**************************************************************************************************** 1629*/ 1630typedef struct _ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT 1631{ 1632 UINT_32 size; ///< Size of this structure in bytes 1633 1634 UINT_32 tileSwizzle; ///< Combined swizzle 1635} ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT; 1636 1637/** 1638**************************************************************************************************** 1639* AddrCombineBankPipeSwizzle 1640* 1641* @brief 1642* Combine Bank and Pipe swizzle 1643* @return 1644* ADDR_OK if no error 1645* @note 1646* baseAddr here is full MCAddress instead of base256b 1647**************************************************************************************************** 1648*/ 1649ADDR_E_RETURNCODE ADDR_API AddrCombineBankPipeSwizzle( 1650 ADDR_HANDLE hLib, 1651 const ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT* pIn, 1652 ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT* pOut); 1653 1654 1655 1656/** 1657**************************************************************************************************** 1658* ADDR_COMPUTE_SLICESWIZZLE_INPUT 1659* 1660* @brief 1661* Input structure of AddrComputeSliceSwizzle 1662**************************************************************************************************** 1663*/ 1664typedef struct _ADDR_COMPUTE_SLICESWIZZLE_INPUT 1665{ 1666 UINT_32 size; ///< Size of this structure in bytes 1667 1668 AddrTileMode tileMode; ///< Tile Mode 1669 UINT_32 baseSwizzle; ///< Base tile swizzle 1670 UINT_32 slice; ///< Slice index 1671 UINT_64 baseAddr; ///< Base address, driver should leave it 0 in most cases 1672 1673 /// r800 and later HWL parameters 1674 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Actually banks needed here! 1675 1676 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1677 /// while the global useTileIndex is set to 1 1678 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1679 ///< README: When tileIndex is not -1, this must be valid 1680} ADDR_COMPUTE_SLICESWIZZLE_INPUT; 1681 1682 1683 1684/** 1685**************************************************************************************************** 1686* ADDR_COMPUTE_SLICESWIZZLE_OUTPUT 1687* 1688* @brief 1689* Output structure of AddrComputeSliceSwizzle 1690**************************************************************************************************** 1691*/ 1692typedef struct _ADDR_COMPUTE_SLICESWIZZLE_OUTPUT 1693{ 1694 UINT_32 size; ///< Size of this structure in bytes 1695 1696 UINT_32 tileSwizzle; ///< Recalculated tileSwizzle value 1697} ADDR_COMPUTE_SLICESWIZZLE_OUTPUT; 1698 1699/** 1700**************************************************************************************************** 1701* AddrComputeSliceSwizzle 1702* 1703* @brief 1704* Extract Bank and Pipe swizzle from base256b 1705* @return 1706* ADDR_OK if no error 1707**************************************************************************************************** 1708*/ 1709ADDR_E_RETURNCODE ADDR_API AddrComputeSliceSwizzle( 1710 ADDR_HANDLE hLib, 1711 const ADDR_COMPUTE_SLICESWIZZLE_INPUT* pIn, 1712 ADDR_COMPUTE_SLICESWIZZLE_OUTPUT* pOut); 1713 1714 1715/** 1716**************************************************************************************************** 1717* AddrSwizzleGenOption 1718* 1719* @brief 1720* Which swizzle generating options: legacy or linear 1721**************************************************************************************************** 1722*/ 1723typedef enum _AddrSwizzleGenOption 1724{ 1725 ADDR_SWIZZLE_GEN_DEFAULT = 0, ///< As is in client driver implemention for swizzle 1726 ADDR_SWIZZLE_GEN_LINEAR = 1, ///< Using a linear increment of swizzle 1727} AddrSwizzleGenOption; 1728 1729/** 1730**************************************************************************************************** 1731* AddrSwizzleOption 1732* 1733* @brief 1734* Controls how swizzle is generated 1735**************************************************************************************************** 1736*/ 1737typedef union _ADDR_SWIZZLE_OPTION 1738{ 1739 struct 1740 { 1741 UINT_32 genOption : 1; ///< The way swizzle is generated, see AddrSwizzleGenOption 1742 UINT_32 reduceBankBit : 1; ///< TRUE if we need reduce swizzle bits 1743 UINT_32 reserved :30; ///< Reserved bits 1744 }; 1745 1746 UINT_32 value; 1747 1748} ADDR_SWIZZLE_OPTION; 1749 1750/** 1751**************************************************************************************************** 1752* ADDR_COMPUTE_BASE_SWIZZLE_INPUT 1753* 1754* @brief 1755* Input structure of AddrComputeBaseSwizzle 1756**************************************************************************************************** 1757*/ 1758typedef struct _ADDR_COMPUTE_BASE_SWIZZLE_INPUT 1759{ 1760 UINT_32 size; ///< Size of this structure in bytes 1761 1762 ADDR_SWIZZLE_OPTION option; ///< Swizzle option 1763 UINT_32 surfIndex; ///< Index of this surface type 1764 AddrTileMode tileMode; ///< Tile Mode 1765 1766 /// r800 and later HWL parameters 1767 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Actually banks needed here! 1768 1769 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1770 /// while the global useTileIndex is set to 1 1771 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1772 ///< README: When tileIndex is not -1, this must be valid 1773} ADDR_COMPUTE_BASE_SWIZZLE_INPUT; 1774 1775/** 1776**************************************************************************************************** 1777* ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT 1778* 1779* @brief 1780* Output structure of AddrComputeBaseSwizzle 1781**************************************************************************************************** 1782*/ 1783typedef struct _ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT 1784{ 1785 UINT_32 size; ///< Size of this structure in bytes 1786 1787 UINT_32 tileSwizzle; ///< Combined swizzle 1788} ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT; 1789 1790/** 1791**************************************************************************************************** 1792* AddrComputeBaseSwizzle 1793* 1794* @brief 1795* Return a Combined Bank and Pipe swizzle base on surface based on surface type/index 1796* @return 1797* ADDR_OK if no error 1798**************************************************************************************************** 1799*/ 1800ADDR_E_RETURNCODE ADDR_API AddrComputeBaseSwizzle( 1801 ADDR_HANDLE hLib, 1802 const ADDR_COMPUTE_BASE_SWIZZLE_INPUT* pIn, 1803 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT* pOut); 1804 1805 1806 1807/** 1808**************************************************************************************************** 1809* ELEM_GETEXPORTNORM_INPUT 1810* 1811* @brief 1812* Input structure for ElemGetExportNorm 1813* 1814**************************************************************************************************** 1815*/ 1816typedef struct _ELEM_GETEXPORTNORM_INPUT 1817{ 1818 UINT_32 size; ///< Size of this structure in bytes 1819 1820 AddrColorFormat format; ///< Color buffer format; Client should use ColorFormat 1821 AddrSurfaceNumber num; ///< Surface number type; Client should use NumberType 1822 AddrSurfaceSwap swap; ///< Surface swap byte swap; Client should use SurfaceSwap 1823 UINT_32 numSamples; ///< Number of samples 1824} ELEM_GETEXPORTNORM_INPUT; 1825 1826/** 1827**************************************************************************************************** 1828* ElemGetExportNorm 1829* 1830* @brief 1831* Helper function to check one format can be EXPORT_NUM, which is a register 1832* CB_COLOR_INFO.SURFACE_FORMAT. FP16 can be reported as EXPORT_NORM for rv770 in r600 1833* family 1834* @note 1835* The implementation is only for r600. 1836* 00 - EXPORT_FULL: PS exports are 4 pixels with 4 components with 32-bits-per-component. (two 1837* clocks per export) 1838* 01 - EXPORT_NORM: PS exports are 4 pixels with 4 components with 16-bits-per-component. (one 1839* clock per export) 1840* 1841**************************************************************************************************** 1842*/ 1843BOOL_32 ADDR_API ElemGetExportNorm( 1844 ADDR_HANDLE hLib, 1845 const ELEM_GETEXPORTNORM_INPUT* pIn); 1846 1847 1848 1849/** 1850**************************************************************************************************** 1851* ELEM_FLT32TODEPTHPIXEL_INPUT 1852* 1853* @brief 1854* Input structure for addrFlt32ToDepthPixel 1855* 1856**************************************************************************************************** 1857*/ 1858typedef struct _ELEM_FLT32TODEPTHPIXEL_INPUT 1859{ 1860 UINT_32 size; ///< Size of this structure in bytes 1861 1862 AddrDepthFormat format; ///< Depth buffer format 1863 ADDR_FLT_32 comps[2]; ///< Component values (Z/stencil) 1864} ELEM_FLT32TODEPTHPIXEL_INPUT; 1865 1866/** 1867**************************************************************************************************** 1868* ELEM_FLT32TODEPTHPIXEL_INPUT 1869* 1870* @brief 1871* Output structure for ElemFlt32ToDepthPixel 1872* 1873**************************************************************************************************** 1874*/ 1875typedef struct _ELEM_FLT32TODEPTHPIXEL_OUTPUT 1876{ 1877 UINT_32 size; ///< Size of this structure in bytes 1878 1879 UINT_8* pPixel; ///< Real depth value. Same data type as depth buffer. 1880 /// Client must provide enough storage for this type. 1881 UINT_32 depthBase; ///< Tile base in bits for depth bits 1882 UINT_32 stencilBase; ///< Tile base in bits for stencil bits 1883 UINT_32 depthBits; ///< Bits for depth 1884 UINT_32 stencilBits; ///< Bits for stencil 1885} ELEM_FLT32TODEPTHPIXEL_OUTPUT; 1886 1887/** 1888**************************************************************************************************** 1889* ElemFlt32ToDepthPixel 1890* 1891* @brief 1892* Convert a FLT_32 value to a depth/stencil pixel value 1893* 1894* @return 1895* Return code 1896* 1897**************************************************************************************************** 1898*/ 1899ADDR_E_RETURNCODE ADDR_API ElemFlt32ToDepthPixel( 1900 ADDR_HANDLE hLib, 1901 const ELEM_FLT32TODEPTHPIXEL_INPUT* pIn, 1902 ELEM_FLT32TODEPTHPIXEL_OUTPUT* pOut); 1903 1904 1905 1906/** 1907**************************************************************************************************** 1908* ELEM_FLT32TOCOLORPIXEL_INPUT 1909* 1910* @brief 1911* Input structure for addrFlt32ToColorPixel 1912* 1913**************************************************************************************************** 1914*/ 1915typedef struct _ELEM_FLT32TOCOLORPIXEL_INPUT 1916{ 1917 UINT_32 size; ///< Size of this structure in bytes 1918 1919 AddrColorFormat format; ///< Color buffer format 1920 AddrSurfaceNumber surfNum; ///< Surface number 1921 AddrSurfaceSwap surfSwap; ///< Surface swap 1922 ADDR_FLT_32 comps[4]; ///< Component values (r/g/b/a) 1923} ELEM_FLT32TOCOLORPIXEL_INPUT; 1924 1925/** 1926**************************************************************************************************** 1927* ELEM_FLT32TOCOLORPIXEL_INPUT 1928* 1929* @brief 1930* Output structure for ElemFlt32ToColorPixel 1931* 1932**************************************************************************************************** 1933*/ 1934typedef struct _ELEM_FLT32TOCOLORPIXEL_OUTPUT 1935{ 1936 UINT_32 size; ///< Size of this structure in bytes 1937 1938 UINT_8* pPixel; ///< Real color value. Same data type as color buffer. 1939 /// Client must provide enough storage for this type. 1940} ELEM_FLT32TOCOLORPIXEL_OUTPUT; 1941 1942/** 1943**************************************************************************************************** 1944* ElemFlt32ToColorPixel 1945* 1946* @brief 1947* Convert a FLT_32 value to a red/green/blue/alpha pixel value 1948* 1949* @return 1950* Return code 1951* 1952**************************************************************************************************** 1953*/ 1954ADDR_E_RETURNCODE ADDR_API ElemFlt32ToColorPixel( 1955 ADDR_HANDLE hLib, 1956 const ELEM_FLT32TOCOLORPIXEL_INPUT* pIn, 1957 ELEM_FLT32TOCOLORPIXEL_OUTPUT* pOut); 1958 1959/** 1960**************************************************************************************************** 1961* ElemSize 1962* 1963* @brief 1964* Get bits-per-element for specified format 1965* 1966* @return 1967* Bits-per-element of specified format 1968* 1969**************************************************************************************************** 1970*/ 1971UINT_32 ADDR_API ElemSize( 1972 ADDR_HANDLE hLib, 1973 AddrFormat format); 1974 1975/** 1976**************************************************************************************************** 1977* ADDR_CONVERT_TILEINFOTOHW_INPUT 1978* 1979* @brief 1980* Input structure for AddrConvertTileInfoToHW 1981* @note 1982* When reverse is TRUE, indices are igonred 1983**************************************************************************************************** 1984*/ 1985typedef struct _ADDR_CONVERT_TILEINFOTOHW_INPUT 1986{ 1987 UINT_32 size; ///< Size of this structure in bytes 1988 BOOL_32 reverse; ///< Convert control flag. 1989 /// FALSE: convert from real value to HW value; 1990 /// TRUE: convert from HW value to real value. 1991 1992 /// r800 and later HWL parameters 1993 ADDR_TILEINFO* pTileInfo; ///< Tile parameters with real value 1994 1995 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1996 /// while the global useTileIndex is set to 1 1997 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1998 ///< README: When tileIndex is not -1, this must be valid 1999 UINT_32 bpp; ///< Bits per pixel 2000} ADDR_CONVERT_TILEINFOTOHW_INPUT; 2001 2002/** 2003**************************************************************************************************** 2004* ADDR_CONVERT_TILEINFOTOHW_OUTPUT 2005* 2006* @brief 2007* Output structure for AddrConvertTileInfoToHW 2008**************************************************************************************************** 2009*/ 2010typedef struct _ADDR_CONVERT_TILEINFOTOHW_OUTPUT 2011{ 2012 UINT_32 size; ///< Size of this structure in bytes 2013 2014 /// r800 and later HWL parameters 2015 ADDR_TILEINFO* pTileInfo; ///< Tile parameters with hardware register value 2016 2017} ADDR_CONVERT_TILEINFOTOHW_OUTPUT; 2018 2019/** 2020**************************************************************************************************** 2021* AddrConvertTileInfoToHW 2022* 2023* @brief 2024* Convert tile info from real value to hardware register value 2025**************************************************************************************************** 2026*/ 2027ADDR_E_RETURNCODE ADDR_API AddrConvertTileInfoToHW( 2028 ADDR_HANDLE hLib, 2029 const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn, 2030 ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut); 2031 2032 2033 2034/** 2035**************************************************************************************************** 2036* ADDR_CONVERT_TILEINDEX_INPUT 2037* 2038* @brief 2039* Input structure for AddrConvertTileIndex 2040**************************************************************************************************** 2041*/ 2042typedef struct _ADDR_CONVERT_TILEINDEX_INPUT 2043{ 2044 UINT_32 size; ///< Size of this structure in bytes 2045 2046 INT_32 tileIndex; ///< Tile index 2047 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 2048 UINT_32 bpp; ///< Bits per pixel 2049 BOOL_32 tileInfoHw; ///< Set to TRUE if client wants HW enum, otherwise actual 2050} ADDR_CONVERT_TILEINDEX_INPUT; 2051 2052/** 2053**************************************************************************************************** 2054* ADDR_CONVERT_TILEINDEX_OUTPUT 2055* 2056* @brief 2057* Output structure for AddrConvertTileIndex 2058**************************************************************************************************** 2059*/ 2060typedef struct _ADDR_CONVERT_TILEINDEX_OUTPUT 2061{ 2062 UINT_32 size; ///< Size of this structure in bytes 2063 2064 AddrTileMode tileMode; ///< Tile mode 2065 AddrTileType tileType; ///< Tile type 2066 ADDR_TILEINFO* pTileInfo; ///< Tile info 2067 2068} ADDR_CONVERT_TILEINDEX_OUTPUT; 2069 2070/** 2071**************************************************************************************************** 2072* AddrConvertTileIndex 2073* 2074* @brief 2075* Convert tile index to tile mode/type/info 2076**************************************************************************************************** 2077*/ 2078ADDR_E_RETURNCODE ADDR_API AddrConvertTileIndex( 2079 ADDR_HANDLE hLib, 2080 const ADDR_CONVERT_TILEINDEX_INPUT* pIn, 2081 ADDR_CONVERT_TILEINDEX_OUTPUT* pOut); 2082 2083/** 2084**************************************************************************************************** 2085* ADDR_GET_MACROMODEINDEX_INPUT 2086* 2087* @brief 2088* Input structure for AddrGetMacroModeIndex 2089**************************************************************************************************** 2090*/ 2091typedef struct _ADDR_GET_MACROMODEINDEX_INPUT 2092{ 2093 UINT_32 size; ///< Size of this structure in bytes 2094 ADDR_SURFACE_FLAGS flags; ///< Surface flag 2095 INT_32 tileIndex; ///< Tile index 2096 UINT_32 bpp; ///< Bits per pixel 2097 UINT_32 numFrags; ///< Number of color fragments 2098} ADDR_GET_MACROMODEINDEX_INPUT; 2099 2100/** 2101**************************************************************************************************** 2102* ADDR_GET_MACROMODEINDEX_OUTPUT 2103* 2104* @brief 2105* Output structure for AddrGetMacroModeIndex 2106**************************************************************************************************** 2107*/ 2108typedef struct _ADDR_GET_MACROMODEINDEX_OUTPUT 2109{ 2110 UINT_32 size; ///< Size of this structure in bytes 2111 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 2112} ADDR_GET_MACROMODEINDEX_OUTPUT; 2113 2114/** 2115**************************************************************************************************** 2116* AddrGetMacroModeIndex 2117* 2118* @brief 2119* Get macro mode index based on input parameters 2120**************************************************************************************************** 2121*/ 2122ADDR_E_RETURNCODE ADDR_API AddrGetMacroModeIndex( 2123 ADDR_HANDLE hLib, 2124 const ADDR_GET_MACROMODEINDEX_INPUT* pIn, 2125 ADDR_GET_MACROMODEINDEX_OUTPUT* pOut); 2126 2127/** 2128**************************************************************************************************** 2129* ADDR_CONVERT_TILEINDEX1_INPUT 2130* 2131* @brief 2132* Input structure for AddrConvertTileIndex1 (without macro mode index) 2133**************************************************************************************************** 2134*/ 2135typedef struct _ADDR_CONVERT_TILEINDEX1_INPUT 2136{ 2137 UINT_32 size; ///< Size of this structure in bytes 2138 2139 INT_32 tileIndex; ///< Tile index 2140 UINT_32 bpp; ///< Bits per pixel 2141 UINT_32 numSamples; ///< Number of samples 2142 BOOL_32 tileInfoHw; ///< Set to TRUE if client wants HW enum, otherwise actual 2143} ADDR_CONVERT_TILEINDEX1_INPUT; 2144 2145/** 2146**************************************************************************************************** 2147* AddrConvertTileIndex1 2148* 2149* @brief 2150* Convert tile index to tile mode/type/info 2151**************************************************************************************************** 2152*/ 2153ADDR_E_RETURNCODE ADDR_API AddrConvertTileIndex1( 2154 ADDR_HANDLE hLib, 2155 const ADDR_CONVERT_TILEINDEX1_INPUT* pIn, 2156 ADDR_CONVERT_TILEINDEX_OUTPUT* pOut); 2157 2158 2159 2160/** 2161**************************************************************************************************** 2162* ADDR_GET_TILEINDEX_INPUT 2163* 2164* @brief 2165* Input structure for AddrGetTileIndex 2166**************************************************************************************************** 2167*/ 2168typedef struct _ADDR_GET_TILEINDEX_INPUT 2169{ 2170 UINT_32 size; ///< Size of this structure in bytes 2171 2172 AddrTileMode tileMode; ///< Tile mode 2173 AddrTileType tileType; ///< Tile-type: disp/non-disp/... 2174 ADDR_TILEINFO* pTileInfo; ///< Pointer to tile-info structure, can be NULL for linear/1D 2175} ADDR_GET_TILEINDEX_INPUT; 2176 2177/** 2178**************************************************************************************************** 2179* ADDR_GET_TILEINDEX_OUTPUT 2180* 2181* @brief 2182* Output structure for AddrGetTileIndex 2183**************************************************************************************************** 2184*/ 2185typedef struct _ADDR_GET_TILEINDEX_OUTPUT 2186{ 2187 UINT_32 size; ///< Size of this structure in bytes 2188 2189 INT_32 index; ///< index in table 2190} ADDR_GET_TILEINDEX_OUTPUT; 2191 2192/** 2193**************************************************************************************************** 2194* AddrGetTileIndex 2195* 2196* @brief 2197* Get the tiling mode index in table 2198**************************************************************************************************** 2199*/ 2200ADDR_E_RETURNCODE ADDR_API AddrGetTileIndex( 2201 ADDR_HANDLE hLib, 2202 const ADDR_GET_TILEINDEX_INPUT* pIn, 2203 ADDR_GET_TILEINDEX_OUTPUT* pOut); 2204 2205 2206 2207/** 2208**************************************************************************************************** 2209* ADDR_PRT_INFO_INPUT 2210* 2211* @brief 2212* Input structure for AddrComputePrtInfo 2213**************************************************************************************************** 2214*/ 2215typedef struct _ADDR_PRT_INFO_INPUT 2216{ 2217 AddrFormat format; ///< Surface format 2218 UINT_32 baseMipWidth; ///< Base mipmap width 2219 UINT_32 baseMipHeight; ///< Base mipmap height 2220 UINT_32 baseMipDepth; ///< Base mipmap depth 2221 UINT_32 numFrags; ///< Number of fragments, 2222} ADDR_PRT_INFO_INPUT; 2223 2224/** 2225**************************************************************************************************** 2226* ADDR_PRT_INFO_OUTPUT 2227* 2228* @brief 2229* Input structure for AddrComputePrtInfo 2230**************************************************************************************************** 2231*/ 2232typedef struct _ADDR_PRT_INFO_OUTPUT 2233{ 2234 UINT_32 prtTileWidth; 2235 UINT_32 prtTileHeight; 2236} ADDR_PRT_INFO_OUTPUT; 2237 2238/** 2239**************************************************************************************************** 2240* AddrComputePrtInfo 2241* 2242* @brief 2243* Compute prt surface related information 2244**************************************************************************************************** 2245*/ 2246ADDR_E_RETURNCODE ADDR_API AddrComputePrtInfo( 2247 ADDR_HANDLE hLib, 2248 const ADDR_PRT_INFO_INPUT* pIn, 2249 ADDR_PRT_INFO_OUTPUT* pOut); 2250 2251 2252 2253//////////////////////////////////////////////////////////////////////////////////////////////////// 2254// DCC key functions 2255//////////////////////////////////////////////////////////////////////////////////////////////////// 2256 2257/** 2258**************************************************************************************************** 2259* _ADDR_COMPUTE_DCCINFO_INPUT 2260* 2261* @brief 2262* Input structure of AddrComputeDccInfo 2263**************************************************************************************************** 2264*/ 2265typedef struct _ADDR_COMPUTE_DCCINFO_INPUT 2266{ 2267 UINT_32 size; ///< Size of this structure in bytes 2268 UINT_32 bpp; ///< BitPP of color surface 2269 UINT_32 numSamples; ///< Sample number of color surface 2270 UINT_64 colorSurfSize; ///< Size of color surface to which dcc key is bound 2271 AddrTileMode tileMode; ///< Tile mode of color surface 2272 ADDR_TILEINFO tileInfo; ///< Tile info of color surface 2273 UINT_32 tileSwizzle; ///< Tile swizzle 2274 INT_32 tileIndex; ///< Tile index of color surface, 2275 ///< MUST be -1 if you don't want to use it 2276 ///< while the global useTileIndex is set to 1 2277 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 2278 ///< README: When tileIndex is not -1, this must be valid 2279} ADDR_COMPUTE_DCCINFO_INPUT; 2280 2281/** 2282**************************************************************************************************** 2283* ADDR_COMPUTE_DCCINFO_OUTPUT 2284* 2285* @brief 2286* Output structure of AddrComputeDccInfo 2287**************************************************************************************************** 2288*/ 2289typedef struct _ADDR_COMPUTE_DCCINFO_OUTPUT 2290{ 2291 UINT_32 size; ///< Size of this structure in bytes 2292 UINT_32 dccRamBaseAlign; ///< Base alignment of dcc key 2293 UINT_64 dccRamSize; ///< Size of dcc key 2294 UINT_64 dccFastClearSize; ///< Size of dcc key portion that can be fast cleared 2295 BOOL_32 subLvlCompressible; ///< Whether sub resource is compressiable 2296 BOOL_32 dccRamSizeAligned; ///< Whether the dcc key size is aligned 2297} ADDR_COMPUTE_DCCINFO_OUTPUT; 2298 2299/** 2300**************************************************************************************************** 2301* AddrComputeDccInfo 2302* 2303* @brief 2304* Compute DCC key size, base alignment 2305* info 2306**************************************************************************************************** 2307*/ 2308ADDR_E_RETURNCODE ADDR_API AddrComputeDccInfo( 2309 ADDR_HANDLE hLib, 2310 const ADDR_COMPUTE_DCCINFO_INPUT* pIn, 2311 ADDR_COMPUTE_DCCINFO_OUTPUT* pOut); 2312 2313 2314 2315/** 2316**************************************************************************************************** 2317* ADDR_GET_MAX_ALIGNMENTS_OUTPUT 2318* 2319* @brief 2320* Output structure of AddrGetMaxAlignments 2321**************************************************************************************************** 2322*/ 2323typedef struct ADDR_GET_MAX_ALINGMENTS_OUTPUT 2324{ 2325 UINT_32 size; ///< Size of this structure in bytes 2326 UINT_32 baseAlign; ///< Maximum base alignment in bytes 2327} ADDR_GET_MAX_ALIGNMENTS_OUTPUT; 2328 2329/** 2330**************************************************************************************************** 2331* AddrGetMaxAlignments 2332* 2333* @brief 2334* Gets maximnum alignments 2335**************************************************************************************************** 2336*/ 2337ADDR_E_RETURNCODE ADDR_API AddrGetMaxAlignments( 2338 ADDR_HANDLE hLib, 2339 ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut); 2340 2341/** 2342**************************************************************************************************** 2343* AddrGetMaxMetaAlignments 2344* 2345* @brief 2346* Gets maximnum alignments for metadata 2347**************************************************************************************************** 2348*/ 2349ADDR_E_RETURNCODE ADDR_API AddrGetMaxMetaAlignments( 2350 ADDR_HANDLE hLib, 2351 ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut); 2352 2353/** 2354**************************************************************************************************** 2355* Address library interface version 2 2356* available from Gfx9 hardware 2357**************************************************************************************************** 2358* Addr2ComputeSurfaceInfo() 2359* Addr2ComputeSurfaceAddrFromCoord() 2360* Addr2ComputeSurfaceCoordFromAddr() 2361 2362* Addr2ComputeHtileInfo() 2363* Addr2ComputeHtileAddrFromCoord() 2364* Addr2ComputeHtileCoordFromAddr() 2365* 2366* Addr2ComputeCmaskInfo() 2367* Addr2ComputeCmaskAddrFromCoord() 2368* Addr2ComputeCmaskCoordFromAddr() 2369* 2370* Addr2ComputeFmaskInfo() 2371* Addr2ComputeFmaskAddrFromCoord() 2372* Addr2ComputeFmaskCoordFromAddr() 2373* 2374* Addr2ComputeDccInfo() 2375* 2376**/ 2377 2378 2379//////////////////////////////////////////////////////////////////////////////////////////////////// 2380// Surface functions for Gfx9 2381//////////////////////////////////////////////////////////////////////////////////////////////////// 2382 2383/** 2384**************************************************************************************************** 2385* ADDR2_SURFACE_FLAGS 2386* 2387* @brief 2388* Surface flags 2389**************************************************************************************************** 2390*/ 2391typedef union _ADDR2_SURFACE_FLAGS 2392{ 2393 struct 2394 { 2395 UINT_32 color : 1; ///< This resource is a color buffer, can be used with RTV 2396 UINT_32 depth : 1; ///< Thie resource is a depth buffer, can be used with DSV 2397 UINT_32 stencil : 1; ///< Thie resource is a stencil buffer, can be used with DSV 2398 UINT_32 fmask : 1; ///< This is an fmask surface 2399 UINT_32 overlay : 1; ///< This is an overlay surface 2400 UINT_32 display : 1; ///< This resource is displable, can be used with DRV 2401 UINT_32 prt : 1; ///< This is a partially resident texture 2402 UINT_32 qbStereo : 1; ///< This is a quad buffer stereo surface 2403 UINT_32 interleaved : 1; ///< Special flag for interleaved YUV surface padding 2404 UINT_32 texture : 1; ///< This resource can be used with SRV 2405 UINT_32 unordered : 1; ///< This resource can be used with UAV 2406 UINT_32 rotated : 1; ///< This resource is rotated and displable 2407 UINT_32 needEquation : 1; ///< This resource needs equation to be generated if possible 2408 UINT_32 opt4space : 1; ///< This resource should be optimized for space 2409 UINT_32 minimizeAlign : 1; ///< This resource should use minimum alignment 2410 UINT_32 noMetadata : 1; ///< This resource has no metadata 2411 UINT_32 metaRbUnaligned : 1; ///< This resource has rb unaligned metadata 2412 UINT_32 metaPipeUnaligned : 1; ///< This resource has pipe unaligned metadata 2413 UINT_32 view3dAs2dArray : 1; ///< This resource is a 3D resource viewed as 2D array 2414 UINT_32 reserved : 13; ///< Reserved bits 2415 }; 2416 2417 UINT_32 value; 2418} ADDR2_SURFACE_FLAGS; 2419 2420/** 2421**************************************************************************************************** 2422* ADDR2_COMPUTE_SURFACE_INFO_INPUT 2423* 2424* @brief 2425* Input structure for Addr2ComputeSurfaceInfo 2426**************************************************************************************************** 2427*/ 2428typedef struct _ADDR2_COMPUTE_SURFACE_INFO_INPUT 2429{ 2430 UINT_32 size; ///< Size of this structure in bytes 2431 2432 ADDR2_SURFACE_FLAGS flags; ///< Surface flags 2433 AddrSwizzleMode swizzleMode; ///< Swizzle Mode for Gfx9 2434 AddrResourceType resourceType; ///< Surface type 2435 AddrFormat format; ///< Surface format 2436 UINT_32 bpp; ///< bits per pixel 2437 UINT_32 width; ///< Width (of mip0), in pixels 2438 UINT_32 height; ///< Height (of mip0), in pixels 2439 UINT_32 numSlices; ///< Number surface slice/depth (of mip0), 2440 UINT_32 numMipLevels; ///< Total mipmap levels. 2441 UINT_32 numSamples; ///< Number of samples 2442 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 2443 /// number of samples for normal AA; Set it to the 2444 /// number of fragments for EQAA 2445 UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats) 2446 UINT_32 sliceAlign; ///< Required slice size in bytes 2447} ADDR2_COMPUTE_SURFACE_INFO_INPUT; 2448 2449/** 2450**************************************************************************************************** 2451* ADDR2_MIP_INFO 2452* 2453* @brief 2454* Structure that contains information for mip level 2455* 2456**************************************************************************************************** 2457*/ 2458typedef struct _ADDR2_MIP_INFO 2459{ 2460 UINT_32 pitch; ///< Pitch in elements 2461 UINT_32 height; ///< Padded height in elements 2462 UINT_32 depth; ///< Padded depth 2463 UINT_32 pixelPitch; ///< Pitch in pixels 2464 UINT_32 pixelHeight; ///< Padded height in pixels 2465 UINT_32 equationIndex; ///< Equation index in the equation table 2466 UINT_64 offset; ///< Offset in bytes from mip base, should only be used 2467 ///< to setup vam surface descriptor, can't be used 2468 ///< to setup swizzle pattern 2469 UINT_64 macroBlockOffset; ///< macro block offset in bytes from mip base 2470 UINT_32 mipTailOffset; ///< mip tail offset in bytes 2471 UINT_32 mipTailCoordX; ///< mip tail coord x 2472 UINT_32 mipTailCoordY; ///< mip tail coord y 2473 UINT_32 mipTailCoordZ; ///< mip tail coord z 2474} ADDR2_MIP_INFO; 2475 2476/** 2477**************************************************************************************************** 2478* ADDR2_COMPUTE_SURFACE_INFO_OUTPUT 2479* 2480* @brief 2481* Output structure for Addr2ComputeSurfInfo 2482* @note 2483 Element: AddrLib unit for computing. e.g. BCn: 4x4 blocks; R32B32B32: 32bit with 3x pitch 2484 Pixel: Original pixel 2485**************************************************************************************************** 2486*/ 2487typedef struct _ADDR2_COMPUTE_SURFACE_INFO_OUTPUT 2488{ 2489 UINT_32 size; ///< Size of this structure in bytes 2490 2491 UINT_32 pitch; ///< Pitch in elements (blocks for compressed formats) 2492 UINT_32 height; ///< Padded height (of mip0) in elements 2493 UINT_32 numSlices; ///< Padded depth for 3d resource 2494 ///< or padded number of slices for 2d array resource 2495 UINT_32 mipChainPitch; ///< Pitch (of total mip chain) in elements 2496 UINT_32 mipChainHeight; ///< Padded height (of total mip chain) in elements 2497 UINT_32 mipChainSlice; ///< Padded depth (of total mip chain) 2498 UINT_64 sliceSize; ///< Slice (total mip chain) size in bytes 2499 UINT_64 surfSize; ///< Surface (total mip chain) size in bytes 2500 UINT_32 baseAlign; ///< Base address alignment 2501 UINT_32 bpp; ///< Bits per elements 2502 /// (e.g. blocks for BCn, 1/3 for 96bit) 2503 UINT_32 pixelMipChainPitch; ///< Mip chain pitch in original pixels 2504 UINT_32 pixelMipChainHeight; ///< Mip chain height in original pixels 2505 UINT_32 pixelPitch; ///< Pitch in original pixels 2506 UINT_32 pixelHeight; ///< Height in original pixels 2507 UINT_32 pixelBits; ///< Original bits per pixel, passed from input 2508 2509 UINT_32 blockWidth; ///< Width in element inside one block 2510 UINT_32 blockHeight; ///< Height in element inside one block 2511 UINT_32 blockSlices; ///< Slice number inside one block 2512 ///< Prt tile is one block, its width/height/slice 2513 ///< equals to blcok width/height/slice 2514 2515 BOOL_32 epitchIsHeight; ///< Whether to use height to program epitch register 2516 /// Stereo info 2517 ADDR_QBSTEREOINFO* pStereoInfo; ///< Stereo info, needed if qbStereo flag is TRUE 2518 /// Mip info 2519 ADDR2_MIP_INFO* pMipInfo; ///< Pointer to mip information array 2520 /// if it is not NULL, the array is assumed to 2521 /// contain numMipLevels entries 2522 2523 UINT_32 equationIndex; ///< Equation index in the equation table of mip0 2524 BOOL_32 mipChainInTail; ///< If whole mipchain falls into mip tail block 2525 UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if there is no mip 2526 /// in tail, it will be set to number of mip levels 2527} ADDR2_COMPUTE_SURFACE_INFO_OUTPUT; 2528 2529/** 2530**************************************************************************************************** 2531* Addr2ComputeSurfaceInfo 2532* 2533* @brief 2534* Compute surface width/height/slices/alignments and suitable tiling mode 2535**************************************************************************************************** 2536*/ 2537ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceInfo( 2538 ADDR_HANDLE hLib, 2539 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 2540 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut); 2541 2542 2543 2544/** 2545**************************************************************************************************** 2546* ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT 2547* 2548* @brief 2549* Input structure for Addr2ComputeSurfaceAddrFromCoord 2550**************************************************************************************************** 2551*/ 2552typedef struct _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT 2553{ 2554 UINT_32 size; ///< Size of this structure in bytes 2555 2556 UINT_32 x; ///< X coordinate 2557 UINT_32 y; ///< Y coordinate 2558 UINT_32 slice; ///< Slice index 2559 UINT_32 sample; ///< Sample index, use fragment index for EQAA 2560 UINT_32 mipId; ///< the mip ID in mip chain 2561 2562 AddrSwizzleMode swizzleMode; ///< Swizzle mode for Gfx9 2563 ADDR2_SURFACE_FLAGS flags; ///< Surface flags 2564 AddrResourceType resourceType; ///< Surface type 2565 UINT_32 bpp; ///< Bits per pixel 2566 UINT_32 unalignedWidth; ///< Surface original width (of mip0) 2567 UINT_32 unalignedHeight; ///< Surface original height (of mip0) 2568 UINT_32 numSlices; ///< Surface original slices (of mip0) 2569 UINT_32 numMipLevels; ///< Total mipmap levels 2570 UINT_32 numSamples; ///< Number of samples 2571 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 2572 /// number of samples for normal AA; Set it to the 2573 /// number of fragments for EQAA 2574 2575 UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation 2576 UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats) 2577} ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT; 2578 2579/** 2580**************************************************************************************************** 2581* ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 2582* 2583* @brief 2584* Output structure for Addr2ComputeSurfaceAddrFromCoord 2585**************************************************************************************************** 2586*/ 2587typedef struct _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 2588{ 2589 UINT_32 size; ///< Size of this structure in bytes 2590 2591 UINT_64 addr; ///< Byte address 2592 UINT_32 bitPosition; ///< Bit position within surfaceAddr, 0-7. 2593 /// For surface bpp < 8, e.g. FMT_1. 2594 UINT_32 prtBlockIndex; ///< Index of a PRT tile (64K block) 2595} ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT; 2596 2597/** 2598**************************************************************************************************** 2599* Addr2ComputeSurfaceAddrFromCoord 2600* 2601* @brief 2602* Compute surface address from a given coordinate. 2603**************************************************************************************************** 2604*/ 2605ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceAddrFromCoord( 2606 ADDR_HANDLE hLib, 2607 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 2608 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut); 2609 2610 2611 2612/** 2613**************************************************************************************************** 2614* ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT 2615* 2616* @brief 2617* Input structure for Addr2ComputeSurfaceCoordFromAddr 2618**************************************************************************************************** 2619*/ 2620typedef struct _ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT 2621{ 2622 UINT_32 size; ///< Size of this structure in bytes 2623 2624 UINT_64 addr; ///< Address in bytes 2625 UINT_32 bitPosition; ///< Bit position in addr. 0-7. for surface bpp < 8, 2626 /// e.g. FMT_1; 2627 2628 AddrSwizzleMode swizzleMode; ///< Swizzle mode for Gfx9 2629 ADDR2_SURFACE_FLAGS flags; ///< Surface flags 2630 AddrResourceType resourceType; ///< Surface type 2631 UINT_32 bpp; ///< Bits per pixel 2632 UINT_32 unalignedWidth; ///< Surface original width (of mip0) 2633 UINT_32 unalignedHeight; ///< Surface original height (of mip0) 2634 UINT_32 numSlices; ///< Surface original slices (of mip0) 2635 UINT_32 numMipLevels; ///< Total mipmap levels. 2636 UINT_32 numSamples; ///< Number of samples 2637 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 2638 /// number of samples for normal AA; Set it to the 2639 /// number of fragments for EQAA 2640 2641 UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation 2642 UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats) 2643} ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT; 2644 2645/** 2646**************************************************************************************************** 2647* ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT 2648* 2649* @brief 2650* Output structure for Addr2ComputeSurfaceCoordFromAddr 2651**************************************************************************************************** 2652*/ 2653typedef struct _ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT 2654{ 2655 UINT_32 size; ///< Size of this structure in bytes 2656 2657 UINT_32 x; ///< X coordinate 2658 UINT_32 y; ///< Y coordinate 2659 UINT_32 slice; ///< Index of slices 2660 UINT_32 sample; ///< Index of samples, means fragment index for EQAA 2661 UINT_32 mipId; ///< mipmap level id 2662} ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT; 2663 2664/** 2665**************************************************************************************************** 2666* Addr2ComputeSurfaceCoordFromAddr 2667* 2668* @brief 2669* Compute coordinate from a given surface address 2670**************************************************************************************************** 2671*/ 2672ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceCoordFromAddr( 2673 ADDR_HANDLE hLib, 2674 const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn, 2675 ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut); 2676 2677 2678 2679//////////////////////////////////////////////////////////////////////////////////////////////////// 2680// HTile functions for Gfx9 2681//////////////////////////////////////////////////////////////////////////////////////////////////// 2682 2683/** 2684**************************************************************************************************** 2685* ADDR2_META_FLAGS 2686* 2687* @brief 2688* Metadata flags 2689**************************************************************************************************** 2690*/ 2691typedef union _ADDR2_META_FLAGS 2692{ 2693 struct 2694 { 2695 UINT_32 pipeAligned : 1; ///< if Metadata being pipe aligned 2696 UINT_32 rbAligned : 1; ///< if Metadata being RB aligned 2697 UINT_32 linear : 1; ///< if Metadata linear, GFX9 does not suppord this! 2698 UINT_32 reserved : 29; ///< Reserved bits 2699 }; 2700 2701 UINT_32 value; 2702} ADDR2_META_FLAGS; 2703 2704/** 2705**************************************************************************************************** 2706* ADDR2_META_MIP_INFO 2707* 2708* @brief 2709* Structure to store per mip metadata information 2710**************************************************************************************************** 2711*/ 2712typedef struct _ADDR2_META_MIP_INFO 2713{ 2714 BOOL_32 inMiptail; 2715 union 2716 { 2717 struct 2718 { 2719 UINT_32 startX; 2720 UINT_32 startY; 2721 UINT_32 startZ; 2722 UINT_32 width; 2723 UINT_32 height; 2724 UINT_32 depth; 2725 }; 2726 2727 // GFX10 2728 struct 2729 { 2730 UINT_32 offset; ///< Metadata offset within one slice, 2731 /// the thickness of a slice is meta block depth. 2732 UINT_32 sliceSize; ///< Metadata size within one slice, 2733 /// the thickness of a slice is meta block depth. 2734 }; 2735 }; 2736} ADDR2_META_MIP_INFO; 2737 2738/** 2739**************************************************************************************************** 2740* ADDR2_COMPUTE_HTILE_INFO_INPUT 2741* 2742* @brief 2743* Input structure of Addr2ComputeHtileInfo 2744**************************************************************************************************** 2745*/ 2746typedef struct _ADDR2_COMPUTE_HTILE_INFO_INPUT 2747{ 2748 UINT_32 size; ///< Size of this structure in bytes 2749 2750 ADDR2_META_FLAGS hTileFlags; ///< HTILE flags 2751 ADDR2_SURFACE_FLAGS depthFlags; ///< Depth surface flags 2752 AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode 2753 UINT_32 unalignedWidth; ///< Depth surface original width (of mip0) 2754 UINT_32 unalignedHeight; ///< Depth surface original height (of mip0) 2755 UINT_32 numSlices; ///< Number of slices of depth surface (of mip0) 2756 UINT_32 numMipLevels; ///< Total mipmap levels of color surface 2757 UINT_32 firstMipIdInTail; /// Id of the first mip in tail, 2758 /// if no mip is in tail, it should be set to 2759 /// number of mip levels 2760 /// Only for GFX10 2761} ADDR2_COMPUTE_HTILE_INFO_INPUT; 2762 2763/** 2764**************************************************************************************************** 2765* ADDR2_COMPUTE_HTILE_INFO_OUTPUT 2766* 2767* @brief 2768* Output structure of Addr2ComputeHtileInfo 2769**************************************************************************************************** 2770*/ 2771typedef struct _ADDR2_COMPUTE_HTILE_INFO_OUTPUT 2772{ 2773 UINT_32 size; ///< Size of this structure in bytes 2774 2775 UINT_32 pitch; ///< Pitch in pixels of depth buffer represented in this 2776 /// HTile buffer. This might be larger than original depth 2777 /// buffer pitch when called with an unaligned pitch. 2778 UINT_32 height; ///< Height in pixels, as above 2779 UINT_32 baseAlign; ///< Base alignment 2780 UINT_32 sliceSize; ///< Slice size, in bytes. 2781 UINT_32 htileBytes; ///< Size of HTILE buffer, in bytes 2782 UINT_32 metaBlkWidth; ///< Meta block width 2783 UINT_32 metaBlkHeight; ///< Meta block height 2784 UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice 2785 2786 ADDR2_META_MIP_INFO* pMipInfo; ///< HTILE mip information 2787 2788 struct { 2789 UINT_16* gfx10_bits; /* 72 2-byte elements */ 2790 } equation; 2791} ADDR2_COMPUTE_HTILE_INFO_OUTPUT; 2792 2793/** 2794**************************************************************************************************** 2795* Addr2ComputeHtileInfo 2796* 2797* @brief 2798* Compute Htile pitch, height, base alignment and size in bytes 2799**************************************************************************************************** 2800*/ 2801ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileInfo( 2802 ADDR_HANDLE hLib, 2803 const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn, 2804 ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut); 2805 2806 2807 2808/** 2809**************************************************************************************************** 2810* ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT 2811* 2812* @brief 2813* Input structure for Addr2ComputeHtileAddrFromCoord 2814**************************************************************************************************** 2815*/ 2816typedef struct _ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT 2817{ 2818 UINT_32 size; ///< Size of this structure in bytes 2819 2820 UINT_32 x; ///< X coordinate 2821 UINT_32 y; ///< Y coordinate 2822 UINT_32 slice; ///< Index of slices 2823 UINT_32 mipId; ///< mipmap level id 2824 2825 ADDR2_META_FLAGS hTileFlags; ///< HTILE flags 2826 ADDR2_SURFACE_FLAGS depthflags; ///< Depth surface flags 2827 AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode 2828 UINT_32 bpp; ///< Depth surface bits per pixel 2829 UINT_32 unalignedWidth; ///< Depth surface original width (of mip0) 2830 UINT_32 unalignedHeight; ///< Depth surface original height (of mip0) 2831 UINT_32 numSlices; ///< Depth surface original depth (of mip0) 2832 UINT_32 numMipLevels; ///< Depth surface total mipmap levels 2833 UINT_32 numSamples; ///< Depth surface number of samples 2834 UINT_32 pipeXor; ///< Pipe xor setting 2835} ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT; 2836 2837/** 2838**************************************************************************************************** 2839* ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT 2840* 2841* @brief 2842* Output structure for Addr2ComputeHtileAddrFromCoord 2843**************************************************************************************************** 2844*/ 2845typedef struct _ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT 2846{ 2847 UINT_32 size; ///< Size of this structure in bytes 2848 2849 UINT_64 addr; ///< Address in bytes 2850} ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT; 2851 2852/** 2853**************************************************************************************************** 2854* Addr2ComputeHtileAddrFromCoord 2855* 2856* @brief 2857* Compute Htile address according to coordinates (of depth buffer) 2858**************************************************************************************************** 2859*/ 2860ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileAddrFromCoord( 2861 ADDR_HANDLE hLib, 2862 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 2863 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut); 2864 2865 2866 2867/** 2868**************************************************************************************************** 2869* ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT 2870* 2871* @brief 2872* Input structure for Addr2ComputeHtileCoordFromAddr 2873**************************************************************************************************** 2874*/ 2875typedef struct _ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT 2876{ 2877 UINT_32 size; ///< Size of this structure in bytes 2878 2879 UINT_64 addr; ///< Address 2880 2881 ADDR2_META_FLAGS hTileFlags; ///< HTILE flags 2882 ADDR2_SURFACE_FLAGS depthFlags; ///< Depth surface flags 2883 AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode 2884 UINT_32 bpp; ///< Depth surface bits per pixel 2885 UINT_32 unalignedWidth; ///< Depth surface original width (of mip0) 2886 UINT_32 unalignedHeight; ///< Depth surface original height (of mip0) 2887 UINT_32 numSlices; ///< Depth surface original depth (of mip0) 2888 UINT_32 numMipLevels; ///< Depth surface total mipmap levels 2889 UINT_32 numSamples; ///< Depth surface number of samples 2890 UINT_32 pipeXor; ///< Pipe xor setting 2891} ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT; 2892 2893/** 2894**************************************************************************************************** 2895* ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT 2896* 2897* @brief 2898* Output structure for Addr2ComputeHtileCoordFromAddr 2899**************************************************************************************************** 2900*/ 2901typedef struct _ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT 2902{ 2903 UINT_32 size; ///< Size of this structure in bytes 2904 2905 UINT_32 x; ///< X coordinate 2906 UINT_32 y; ///< Y coordinate 2907 UINT_32 slice; ///< Index of slices 2908 UINT_32 mipId; ///< mipmap level id 2909} ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT; 2910 2911/** 2912**************************************************************************************************** 2913* Addr2ComputeHtileCoordFromAddr 2914* 2915* @brief 2916* Compute coordinates within depth buffer (1st pixel of a micro tile) according to 2917* Htile address 2918**************************************************************************************************** 2919*/ 2920ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileCoordFromAddr( 2921 ADDR_HANDLE hLib, 2922 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 2923 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut); 2924 2925 2926 2927//////////////////////////////////////////////////////////////////////////////////////////////////// 2928// C-mask functions for Gfx9 2929//////////////////////////////////////////////////////////////////////////////////////////////////// 2930 2931/** 2932**************************************************************************************************** 2933* ADDR2_COMPUTE_CMASK_INFO_INPUT 2934* 2935* @brief 2936* Input structure of Addr2ComputeCmaskInfo 2937**************************************************************************************************** 2938*/ 2939typedef struct _ADDR2_COMPUTE_CMASKINFO_INPUT 2940{ 2941 UINT_32 size; ///< Size of this structure in bytes 2942 2943 ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags 2944 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags 2945 AddrResourceType resourceType; ///< Color surface type 2946 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 2947 UINT_32 unalignedWidth; ///< Color surface original width 2948 UINT_32 unalignedHeight; ///< Color surface original height 2949 UINT_32 numSlices; ///< Number of slices of color buffer 2950 UINT_32 numMipLevels; ///< Number of mip levels 2951 UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if no mip is in tail, 2952 /// it should be number of mip levels 2953 /// Only for GFX10 2954} ADDR2_COMPUTE_CMASK_INFO_INPUT; 2955 2956/* DCC addr meta equation for GFX9. */ 2957struct gfx9_addr_meta_equation { 2958 UINT_8 num_bits; 2959 2960 struct { 2961 struct { 2962 UINT_8 dim; /* 0..4 as index, 5 means invalid */ 2963 UINT_8 ord; /* 0..31 */ 2964 } coord[8]; /* 0..num_coords */ 2965 } bit[32]; /* 0..num_bits */ 2966 2967 UINT_8 numPipeBits; 2968}; 2969 2970/** 2971**************************************************************************************************** 2972* ADDR2_COMPUTE_CMASK_INFO_OUTPUT 2973* 2974* @brief 2975* Output structure of Addr2ComputeCmaskInfo 2976**************************************************************************************************** 2977*/ 2978typedef struct _ADDR2_COMPUTE_CMASK_INFO_OUTPUT 2979{ 2980 UINT_32 size; ///< Size of this structure in bytes 2981 2982 UINT_32 pitch; ///< Pitch in pixels of color buffer which 2983 /// this Cmask matches. The size might be larger than 2984 /// original color buffer pitch when called with 2985 /// an unaligned pitch. 2986 UINT_32 height; ///< Height in pixels, as above 2987 UINT_32 baseAlign; ///< Base alignment 2988 UINT_32 sliceSize; ///< Slice size, in bytes. 2989 UINT_32 cmaskBytes; ///< Size in bytes of CMask buffer 2990 UINT_32 metaBlkWidth; ///< Meta block width 2991 UINT_32 metaBlkHeight; ///< Meta block height 2992 2993 UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice 2994 2995 ADDR2_META_MIP_INFO* pMipInfo; ///< CMASK mip information 2996 2997 /* The equation for doing CMASK address computations in shaders. */ 2998 union { 2999 /* This is chip-specific, and it varies with: 3000 * - resource type 3001 * - swizzle_mode 3002 * - bpp 3003 * - pipe_aligned 3004 * - rb_aligned 3005 */ 3006 struct gfx9_addr_meta_equation gfx9; 3007 3008 /* This is chip-specific, it requires 64KB_Z_X. */ 3009 UINT_16 *gfx10_bits; /* 68 2-byte elements */ 3010 } equation; 3011} ADDR2_COMPUTE_CMASK_INFO_OUTPUT; 3012 3013/** 3014**************************************************************************************************** 3015* Addr2ComputeCmaskInfo 3016* 3017* @brief 3018* Compute Cmask pitch, height, base alignment and size in bytes from color buffer 3019* info 3020**************************************************************************************************** 3021*/ 3022ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskInfo( 3023 ADDR_HANDLE hLib, 3024 const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn, 3025 ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut); 3026 3027 3028 3029/** 3030**************************************************************************************************** 3031* ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT 3032* 3033* @brief 3034* Input structure for Addr2ComputeCmaskAddrFromCoord 3035* 3036**************************************************************************************************** 3037*/ 3038typedef struct _ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT 3039{ 3040 UINT_32 size; ///< Size of this structure in bytes 3041 3042 UINT_32 x; ///< X coordinate 3043 UINT_32 y; ///< Y coordinate 3044 UINT_32 slice; ///< Index of slices 3045 3046 ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags 3047 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags 3048 AddrResourceType resourceType; ///< Color surface type 3049 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3050 3051 UINT_32 unalignedWidth; ///< Color surface original width (of mip0) 3052 UINT_32 unalignedHeight; ///< Color surface original height (of mip0) 3053 UINT_32 numSlices; ///< Color surface original slices (of mip0) 3054 3055 UINT_32 numSamples; ///< Color surfae sample number 3056 UINT_32 numFrags; ///< Color surface fragment number 3057 3058 UINT_32 pipeXor; ///< pipe Xor setting 3059} ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT; 3060 3061/** 3062**************************************************************************************************** 3063* ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 3064* 3065* @brief 3066* Output structure for Addr2ComputeCmaskAddrFromCoord 3067**************************************************************************************************** 3068*/ 3069typedef struct _ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 3070{ 3071 UINT_32 size; ///< Size of this structure in bytes 3072 3073 UINT_64 addr; ///< CMASK address in bytes 3074 UINT_32 bitPosition; ///< Bit position within addr, 0 or 4 3075} ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT; 3076 3077/** 3078**************************************************************************************************** 3079* Addr2ComputeCmaskAddrFromCoord 3080* 3081* @brief 3082* Compute Cmask address according to coordinates (of MSAA color buffer) 3083**************************************************************************************************** 3084*/ 3085ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskAddrFromCoord( 3086 ADDR_HANDLE hLib, 3087 const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, 3088 ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut); 3089 3090 3091 3092/** 3093**************************************************************************************************** 3094* ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT 3095* 3096* @brief 3097* Input structure for Addr2ComputeCmaskCoordFromAddr 3098**************************************************************************************************** 3099*/ 3100typedef struct _ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT 3101{ 3102 UINT_32 size; ///< Size of this structure in bytes 3103 3104 UINT_64 addr; ///< CMASK address in bytes 3105 UINT_32 bitPosition; ///< Bit position within addr, 0 or 4 3106 3107 ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags 3108 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags 3109 AddrResourceType resourceType; ///< Color surface type 3110 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3111 3112 UINT_32 unalignedWidth; ///< Color surface original width (of mip0) 3113 UINT_32 unalignedHeight; ///< Color surface original height (of mip0) 3114 UINT_32 numSlices; ///< Color surface original slices (of mip0) 3115 UINT_32 numMipLevels; ///< Color surface total mipmap levels. 3116} ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT; 3117 3118/** 3119**************************************************************************************************** 3120* ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT 3121* 3122* @brief 3123* Output structure for Addr2ComputeCmaskCoordFromAddr 3124**************************************************************************************************** 3125*/ 3126typedef struct _ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT 3127{ 3128 UINT_32 size; ///< Size of this structure in bytes 3129 3130 UINT_32 x; ///< X coordinate 3131 UINT_32 y; ///< Y coordinate 3132 UINT_32 slice; ///< Index of slices 3133 UINT_32 mipId; ///< mipmap level id 3134} ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT; 3135 3136/** 3137**************************************************************************************************** 3138* Addr2ComputeCmaskCoordFromAddr 3139* 3140* @brief 3141* Compute coordinates within color buffer (1st pixel of a micro tile) according to 3142* Cmask address 3143**************************************************************************************************** 3144*/ 3145ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskCoordFromAddr( 3146 ADDR_HANDLE hLib, 3147 const ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn, 3148 ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut); 3149 3150 3151 3152//////////////////////////////////////////////////////////////////////////////////////////////////// 3153// F-mask functions for Gfx9 3154//////////////////////////////////////////////////////////////////////////////////////////////////// 3155 3156/** 3157**************************************************************************************************** 3158* ADDR2_FMASK_FLAGS 3159* 3160* @brief 3161* FMASK flags 3162**************************************************************************************************** 3163*/ 3164typedef union _ADDR2_FMASK_FLAGS 3165{ 3166 struct 3167 { 3168 UINT_32 resolved : 1; ///< TRUE if this is a resolved fmask, used by H/W clients 3169 /// by H/W clients. S/W should always set it to FALSE. 3170 UINT_32 reserved : 31; ///< Reserved for future use. 3171 }; 3172 3173 UINT_32 value; 3174} ADDR2_FMASK_FLAGS; 3175 3176/** 3177**************************************************************************************************** 3178* ADDR2_COMPUTE_FMASK_INFO_INPUT 3179* 3180* @brief 3181* Input structure for Addr2ComputeFmaskInfo 3182**************************************************************************************************** 3183*/ 3184typedef struct _ADDR2_COMPUTE_FMASK_INFO_INPUT 3185{ 3186 UINT_32 size; ///< Size of this structure in bytes 3187 3188 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3189 UINT_32 unalignedWidth; ///< Color surface original width 3190 UINT_32 unalignedHeight; ///< Color surface original height 3191 UINT_32 numSlices; ///< Number of slices/depth 3192 UINT_32 numSamples; ///< Number of samples 3193 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 3194 /// number of samples for normal AA; Set it to the 3195 /// number of fragments for EQAA 3196 ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags 3197} ADDR2_COMPUTE_FMASK_INFO_INPUT; 3198 3199/** 3200**************************************************************************************************** 3201* ADDR2_COMPUTE_FMASK_INFO_OUTPUT 3202* 3203* @brief 3204* Output structure for Addr2ComputeFmaskInfo 3205**************************************************************************************************** 3206*/ 3207typedef struct _ADDR2_COMPUTE_FMASK_INFO_OUTPUT 3208{ 3209 UINT_32 size; ///< Size of this structure in bytes 3210 3211 UINT_32 pitch; ///< Pitch of fmask in pixels 3212 UINT_32 height; ///< Height of fmask in pixels 3213 UINT_32 baseAlign; ///< Base alignment 3214 UINT_32 numSlices; ///< Slices of fmask 3215 UINT_32 fmaskBytes; ///< Size of fmask in bytes 3216 UINT_32 bpp; ///< Bits per pixel of FMASK is: number of bit planes 3217 UINT_32 numSamples; ///< Number of samples 3218 UINT_32 sliceSize; ///< Size of slice in bytes 3219} ADDR2_COMPUTE_FMASK_INFO_OUTPUT; 3220 3221/** 3222**************************************************************************************************** 3223* Addr2ComputeFmaskInfo 3224* 3225* @brief 3226* Compute Fmask pitch/height/slices/alignments and size in bytes 3227**************************************************************************************************** 3228*/ 3229ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskInfo( 3230 ADDR_HANDLE hLib, 3231 const ADDR2_COMPUTE_FMASK_INFO_INPUT* pIn, 3232 ADDR2_COMPUTE_FMASK_INFO_OUTPUT* pOut); 3233 3234 3235 3236/** 3237**************************************************************************************************** 3238* ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT 3239* 3240* @brief 3241* Input structure for Addr2ComputeFmaskAddrFromCoord 3242**************************************************************************************************** 3243*/ 3244typedef struct _ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT 3245{ 3246 UINT_32 size; ///< Size of this structure in bytes 3247 3248 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3249 UINT_32 x; ///< X coordinate 3250 UINT_32 y; ///< Y coordinate 3251 UINT_32 slice; ///< Slice index 3252 UINT_32 sample; ///< Sample index (fragment index for EQAA) 3253 UINT_32 plane; ///< Plane number 3254 3255 UINT_32 unalignedWidth; ///< Color surface original width 3256 UINT_32 unalignedHeight; ///< Color surface original height 3257 UINT_32 numSamples; ///< Number of samples 3258 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 3259 /// number of samples for normal AA; Set it to the 3260 /// number of fragments for EQAA 3261 UINT_32 tileSwizzle; ///< Combined swizzle used to do bank/pipe rotation 3262 3263 ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags 3264} ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT; 3265 3266/** 3267**************************************************************************************************** 3268* ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT 3269* 3270* @brief 3271* Output structure for Addr2ComputeFmaskAddrFromCoord 3272**************************************************************************************************** 3273*/ 3274typedef struct _ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT 3275{ 3276 UINT_32 size; ///< Size of this structure in bytes 3277 3278 UINT_64 addr; ///< Fmask address 3279 UINT_32 bitPosition; ///< Bit position within fmaskAddr, 0-7. 3280} ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT; 3281 3282/** 3283**************************************************************************************************** 3284* Addr2ComputeFmaskAddrFromCoord 3285* 3286* @brief 3287* Compute Fmask address according to coordinates (x,y,slice,sample,plane) 3288**************************************************************************************************** 3289*/ 3290ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskAddrFromCoord( 3291 ADDR_HANDLE hLib, 3292 const ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn, 3293 ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut); 3294 3295 3296 3297/** 3298**************************************************************************************************** 3299* ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT 3300* 3301* @brief 3302* Input structure for Addr2ComputeFmaskCoordFromAddr 3303**************************************************************************************************** 3304*/ 3305typedef struct _ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT 3306{ 3307 UINT_32 size; ///< Size of this structure in bytes 3308 3309 UINT_64 addr; ///< Address 3310 UINT_32 bitPosition; ///< Bit position within addr, 0-7. 3311 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3312 3313 UINT_32 unalignedWidth; ///< Color surface original width 3314 UINT_32 unalignedHeight; ///< Color surface original height 3315 UINT_32 numSamples; ///< Number of samples 3316 UINT_32 numFrags; ///< Number of fragments 3317 3318 UINT_32 tileSwizzle; ///< Combined swizzle used to do bank/pipe rotation 3319 3320 ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags 3321} ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT; 3322 3323/** 3324**************************************************************************************************** 3325* ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT 3326* 3327* @brief 3328* Output structure for Addr2ComputeFmaskCoordFromAddr 3329**************************************************************************************************** 3330*/ 3331typedef struct _ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT 3332{ 3333 UINT_32 size; ///< Size of this structure in bytes 3334 3335 UINT_32 x; ///< X coordinate 3336 UINT_32 y; ///< Y coordinate 3337 UINT_32 slice; ///< Slice index 3338 UINT_32 sample; ///< Sample index (fragment index for EQAA) 3339 UINT_32 plane; ///< Plane number 3340} ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT; 3341 3342/** 3343**************************************************************************************************** 3344* Addr2ComputeFmaskCoordFromAddr 3345* 3346* @brief 3347* Compute FMASK coordinate from an given address 3348**************************************************************************************************** 3349*/ 3350ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskCoordFromAddr( 3351 ADDR_HANDLE hLib, 3352 const ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn, 3353 ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut); 3354 3355 3356 3357//////////////////////////////////////////////////////////////////////////////////////////////////// 3358// DCC key functions for Gfx9 3359//////////////////////////////////////////////////////////////////////////////////////////////////// 3360 3361/** 3362**************************************************************************************************** 3363* _ADDR2_COMPUTE_DCCINFO_INPUT 3364* 3365* @brief 3366* Input structure of Addr2ComputeDccInfo 3367**************************************************************************************************** 3368*/ 3369typedef struct _ADDR2_COMPUTE_DCCINFO_INPUT 3370{ 3371 UINT_32 size; ///< Size of this structure in bytes 3372 3373 ADDR2_META_FLAGS dccKeyFlags; ///< DCC key flags 3374 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags 3375 AddrResourceType resourceType; ///< Color surface type 3376 AddrSwizzleMode swizzleMode; ///< Color surface swizzle mode 3377 UINT_32 bpp; ///< bits per pixel 3378 UINT_32 unalignedWidth; ///< Color surface original width (of mip0) 3379 UINT_32 unalignedHeight; ///< Color surface original height (of mip0) 3380 UINT_32 numSlices; ///< Number of slices, of color surface (of mip0) 3381 UINT_32 numFrags; ///< Fragment number of color surface 3382 UINT_32 numMipLevels; ///< Total mipmap levels of color surface 3383 UINT_32 dataSurfaceSize; ///< The padded size of all slices and mip levels 3384 ///< useful in meta linear case 3385 UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if no mip is in tail, 3386 /// it should be number of mip levels 3387 /// Only for GFX10 3388} ADDR2_COMPUTE_DCCINFO_INPUT; 3389 3390/** 3391**************************************************************************************************** 3392* ADDR2_COMPUTE_DCCINFO_OUTPUT 3393* 3394* @brief 3395* Output structure of Addr2ComputeDccInfo 3396**************************************************************************************************** 3397*/ 3398typedef struct _ADDR2_COMPUTE_DCCINFO_OUTPUT 3399{ 3400 UINT_32 size; ///< Size of this structure in bytes 3401 3402 UINT_32 dccRamBaseAlign; ///< Base alignment of dcc key 3403 UINT_32 dccRamSize; ///< Size of dcc key 3404 3405 UINT_32 pitch; ///< DCC surface mip chain pitch 3406 UINT_32 height; ///< DCC surface mip chain height 3407 UINT_32 depth; ///< DCC surface mip chain depth 3408 3409 UINT_32 compressBlkWidth; ///< DCC compress block width 3410 UINT_32 compressBlkHeight; ///< DCC compress block height 3411 UINT_32 compressBlkDepth; ///< DCC compress block depth 3412 3413 UINT_32 metaBlkWidth; ///< DCC meta block width 3414 UINT_32 metaBlkHeight; ///< DCC meta block height 3415 UINT_32 metaBlkDepth; ///< DCC meta block depth 3416 UINT_32 metaBlkSize; ///< DCC meta block size in bytes 3417 UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice 3418 3419 union 3420 { 3421 UINT_32 fastClearSizePerSlice; ///< Size of DCC within a slice should be fast cleared 3422 UINT_32 dccRamSliceSize; ///< DCC ram size per slice. For mipmap, it's 3423 /// the slize size of a mip chain, the thickness of a 3424 /// a slice is meta block depth 3425 /// Only for GFX10 3426 }; 3427 3428 ADDR2_META_MIP_INFO* pMipInfo; ///< DCC mip information 3429 3430 /* The equation for doing DCC address computations in shaders. */ 3431 union { 3432 /* This is chip-specific, and it varies with: 3433 * - resource type 3434 * - swizzle_mode 3435 * - bpp 3436 * - number of fragments 3437 * - pipe_aligned 3438 * - rb_aligned 3439 */ 3440 struct gfx9_addr_meta_equation gfx9; 3441 3442 /* This is chip-specific, it requires 64KB_R_X, and it varies with: 3443 * - bpp 3444 * - pipe_aligned 3445 */ 3446 UINT_16 *gfx10_bits; /* 68 2-byte elements */ 3447 } equation; 3448} ADDR2_COMPUTE_DCCINFO_OUTPUT; 3449 3450/** 3451**************************************************************************************************** 3452* Addr2ComputeDccInfo 3453* 3454* @brief 3455* Compute DCC key size, base alignment 3456* info 3457**************************************************************************************************** 3458*/ 3459ADDR_E_RETURNCODE ADDR_API Addr2ComputeDccInfo( 3460 ADDR_HANDLE hLib, 3461 const ADDR2_COMPUTE_DCCINFO_INPUT* pIn, 3462 ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut); 3463 3464 3465/** 3466**************************************************************************************************** 3467* ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT 3468* 3469* @brief 3470* Input structure for Addr2ComputeDccAddrFromCoord 3471* 3472**************************************************************************************************** 3473*/ 3474typedef struct _ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT 3475{ 3476 UINT_32 size; ///< Size of this structure in bytes 3477 3478 UINT_32 x; ///< X coordinate 3479 UINT_32 y; ///< Y coordinate 3480 UINT_32 slice; ///< Index of slices 3481 UINT_32 sample; ///< Index of samples, means fragment index for EQAA 3482 UINT_32 mipId; ///< mipmap level id 3483 3484 ADDR2_META_FLAGS dccKeyFlags; ///< DCC flags 3485 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags 3486 AddrResourceType resourceType; ///< Color surface type 3487 AddrSwizzleMode swizzleMode; ///< Color surface swizzle mode 3488 UINT_32 bpp; ///< Color surface bits per pixel 3489 UINT_32 unalignedWidth; ///< Color surface original width (of mip0) 3490 UINT_32 unalignedHeight; ///< Color surface original height (of mip0) 3491 UINT_32 numSlices; ///< Color surface original slices (of mip0) 3492 UINT_32 numMipLevels; ///< Color surface mipmap levels 3493 UINT_32 numFrags; ///< Color surface fragment number 3494 3495 UINT_32 pipeXor; ///< pipe Xor setting 3496 UINT_32 pitch; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::pitch 3497 UINT_32 height; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::height 3498 UINT_32 compressBlkWidth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::compressBlkWidth 3499 UINT_32 compressBlkHeight; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::compressBlkHeight 3500 UINT_32 compressBlkDepth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::compressBlkDepth 3501 UINT_32 metaBlkWidth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::metaBlkWidth 3502 UINT_32 metaBlkHeight; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::metaBlkHeight 3503 UINT_32 metaBlkDepth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::metaBlkDepth 3504 UINT_32 dccRamSliceSize; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::dccRamSliceSize 3505} ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT; 3506 3507/** 3508**************************************************************************************************** 3509* ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT 3510* 3511* @brief 3512* Output structure for Addr2ComputeDccAddrFromCoord 3513**************************************************************************************************** 3514*/ 3515typedef struct _ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT 3516{ 3517 UINT_32 size; ///< Size of this structure in bytes 3518 3519 UINT_64 addr; ///< DCC address in bytes 3520} ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT; 3521 3522/** 3523**************************************************************************************************** 3524* Addr2ComputeDccAddrFromCoord 3525* 3526* @brief 3527* Compute DCC address according to coordinates (of MSAA color buffer) 3528**************************************************************************************************** 3529*/ 3530ADDR_E_RETURNCODE ADDR_API Addr2ComputeDccAddrFromCoord( 3531 ADDR_HANDLE hLib, 3532 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, 3533 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut); 3534 3535//////////////////////////////////////////////////////////////////////////////////////////////////// 3536// Misc functions for Gfx9 3537//////////////////////////////////////////////////////////////////////////////////////////////////// 3538 3539/** 3540**************************************************************************************************** 3541* ADDR2_COMPUTE_PIPEBANKXOR_INPUT 3542* 3543* @brief 3544* Input structure of Addr2ComputePipebankXor 3545**************************************************************************************************** 3546*/ 3547typedef struct _ADDR2_COMPUTE_PIPEBANKXOR_INPUT 3548{ 3549 UINT_32 size; ///< Size of this structure in bytes 3550 UINT_32 surfIndex; ///< Input surface index 3551 ADDR2_SURFACE_FLAGS flags; ///< Surface flag 3552 AddrSwizzleMode swizzleMode; ///< Surface swizzle mode 3553 AddrResourceType resourceType; ///< Surface resource type 3554 AddrFormat format; ///< Surface format 3555 UINT_32 numSamples; ///< Number of samples 3556 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 3557 /// number of samples for normal AA; Set it to the 3558 /// number of fragments for EQAA 3559} ADDR2_COMPUTE_PIPEBANKXOR_INPUT; 3560 3561/** 3562**************************************************************************************************** 3563* ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT 3564* 3565* @brief 3566* Output structure of Addr2ComputePipebankXor 3567**************************************************************************************************** 3568*/ 3569typedef struct _ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT 3570{ 3571 UINT_32 size; ///< Size of this structure in bytes 3572 UINT_32 pipeBankXor; ///< Pipe bank xor 3573} ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT; 3574 3575/** 3576**************************************************************************************************** 3577* Addr2ComputePipeBankXor 3578* 3579* @brief 3580* Calculate a valid bank pipe xor value for client to use. 3581**************************************************************************************************** 3582*/ 3583ADDR_E_RETURNCODE ADDR_API Addr2ComputePipeBankXor( 3584 ADDR_HANDLE hLib, 3585 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn, 3586 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut); 3587 3588/** 3589**************************************************************************************************** 3590* ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT 3591* 3592* @brief 3593* Input structure of Addr2ComputeSlicePipeBankXor 3594**************************************************************************************************** 3595*/ 3596typedef struct _ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT 3597{ 3598 UINT_32 size; ///< Size of this structure in bytes 3599 AddrSwizzleMode swizzleMode; ///< Surface swizzle mode 3600 AddrResourceType resourceType; ///< Surface resource type 3601 UINT_32 bpe; ///< bits per element (e.g. block size for BCn format) 3602 UINT_32 basePipeBankXor; ///< Base pipe bank xor 3603 UINT_32 slice; ///< Slice id 3604 UINT_32 numSamples; ///< Number of samples 3605} ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT; 3606 3607/** 3608**************************************************************************************************** 3609* ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT 3610* 3611* @brief 3612* Output structure of Addr2ComputeSlicePipeBankXor 3613**************************************************************************************************** 3614*/ 3615typedef struct _ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT 3616{ 3617 UINT_32 size; ///< Size of this structure in bytes 3618 UINT_32 pipeBankXor; ///< Pipe bank xor 3619} ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT; 3620 3621/** 3622**************************************************************************************************** 3623* Addr2ComputeSlicePipeBankXor 3624* 3625* @brief 3626* Calculate slice pipe bank xor value based on base pipe bank xor and slice id. 3627**************************************************************************************************** 3628*/ 3629ADDR_E_RETURNCODE ADDR_API Addr2ComputeSlicePipeBankXor( 3630 ADDR_HANDLE hLib, 3631 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn, 3632 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut); 3633 3634/** 3635**************************************************************************************************** 3636* ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT 3637* 3638* @brief 3639* Input structure of Addr2ComputeSubResourceOffsetForSwizzlePattern 3640**************************************************************************************************** 3641*/ 3642typedef struct _ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT 3643{ 3644 UINT_32 size; ///< Size of this structure in bytes 3645 AddrSwizzleMode swizzleMode; ///< Surface swizzle mode 3646 AddrResourceType resourceType; ///< Surface resource type 3647 UINT_32 pipeBankXor; ///< Per resource xor 3648 UINT_32 slice; ///< Slice id 3649 UINT_64 sliceSize; ///< Slice size of a mip chain 3650 UINT_64 macroBlockOffset; ///< Macro block offset, returned in ADDR2_MIP_INFO 3651 UINT_32 mipTailOffset; ///< Mip tail offset, returned in ADDR2_MIP_INFO 3652} ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT; 3653 3654/** 3655**************************************************************************************************** 3656* ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT 3657* 3658* @brief 3659* Output structure of Addr2ComputeSubResourceOffsetForSwizzlePattern 3660**************************************************************************************************** 3661*/ 3662typedef struct _ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT 3663{ 3664 UINT_32 size; ///< Size of this structure in bytes 3665 UINT_64 offset; ///< offset 3666} ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT; 3667 3668/** 3669**************************************************************************************************** 3670* Addr2ComputeSubResourceOffsetForSwizzlePattern 3671* 3672* @brief 3673* Calculate sub resource offset to support swizzle pattern. 3674**************************************************************************************************** 3675*/ 3676ADDR_E_RETURNCODE ADDR_API Addr2ComputeSubResourceOffsetForSwizzlePattern( 3677 ADDR_HANDLE hLib, 3678 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn, 3679 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut); 3680 3681/** 3682**************************************************************************************************** 3683* ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT 3684* 3685* @brief 3686* Input structure of Addr2ComputeNonBlockCompressedView 3687**************************************************************************************************** 3688*/ 3689typedef struct _ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT 3690{ 3691 UINT_32 size; ///< Size of this structure in bytes 3692 ADDR2_SURFACE_FLAGS flags; ///< Surface flags 3693 AddrSwizzleMode swizzleMode; ///< Swizzle Mode for Gfx9 3694 AddrResourceType resourceType; ///< Surface type 3695 AddrFormat format; ///< Surface format 3696 UINT_32 width; ///< Width of mip0 in texels (not in compressed block) 3697 UINT_32 height; ///< Height of mip0 in texels (not in compressed block) 3698 UINT_32 numSlices; ///< Number surface slice/depth of mip0 3699 UINT_32 numMipLevels; ///< Total mipmap levels. 3700 UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation 3701 UINT_32 slice; ///< Index of slice to view 3702 UINT_32 mipId; ///< Id of mip to view 3703} ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT; 3704 3705/** 3706**************************************************************************************************** 3707* ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT 3708* 3709* @brief 3710* Output structure of Addr2ComputeNonBlockCompressedView 3711**************************************************************************************************** 3712*/ 3713typedef struct _ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT 3714{ 3715 UINT_32 size; ///< Size of this structure in bytes 3716 UINT_64 offset; ///< Offset shifted from resource base for the view 3717 UINT_32 pipeBankXor; ///< Pipe bank xor for the view 3718 UINT_32 unalignedWidth; ///< Mip0 width (in element) for the view 3719 UINT_32 unalignedHeight; ///< Mip0 height (in element) for the view 3720 UINT_32 numMipLevels; ///< Total mipmap levels for the view 3721 UINT_32 mipId; ///< Mip ID for the view 3722} ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT; 3723 3724/** 3725**************************************************************************************************** 3726* Addr2ComputeNonBlockCompressedView 3727* 3728* @brief 3729* Compute non-block-compressed view for a given mipmap level/slice 3730**************************************************************************************************** 3731*/ 3732ADDR_E_RETURNCODE ADDR_API Addr2ComputeNonBlockCompressedView( 3733 ADDR_HANDLE hLib, 3734 const ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT* pIn, 3735 ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT* pOut); 3736 3737/** 3738**************************************************************************************************** 3739* ADDR2_BLOCK_SET 3740* 3741* @brief 3742* Bit field that defines block type 3743**************************************************************************************************** 3744*/ 3745typedef union _ADDR2_BLOCK_SET 3746{ 3747 struct 3748 { 3749 UINT_32 micro : 1; // 256B block for 2D resource 3750 UINT_32 macroThin4KB : 1; // Thin 4KB for 2D/3D resource 3751 UINT_32 macroThick4KB : 1; // Thick 4KB for 3D resource 3752 UINT_32 macroThin64KB : 1; // Thin 64KB for 2D/3D resource 3753 UINT_32 macroThick64KB : 1; // Thick 64KB for 3D resource 3754 UINT_32 var : 1; // VAR block 3755 UINT_32 : 1; 3756 UINT_32 linear : 1; // Linear block 3757 UINT_32 reserved : 24; 3758 }; 3759 3760 struct 3761 { 3762 UINT_32 : 5; 3763 UINT_32 thin256KB : 1; // Thin 256KB block 3764 UINT_32 thick256KB : 1; // Thick 256KB block 3765 UINT_32 : 25; 3766 } gfx11; 3767 3768 UINT_32 value; 3769} ADDR2_BLOCK_SET; 3770 3771/** 3772**************************************************************************************************** 3773* ADDR2_SWTYPE_SET 3774* 3775* @brief 3776* Bit field that defines swizzle type 3777**************************************************************************************************** 3778*/ 3779typedef union _ADDR2_SWTYPE_SET 3780{ 3781 struct 3782 { 3783 UINT_32 sw_Z : 1; // SW_*_Z_* 3784 UINT_32 sw_S : 1; // SW_*_S_* 3785 UINT_32 sw_D : 1; // SW_*_D_* 3786 UINT_32 sw_R : 1; // SW_*_R_* 3787 UINT_32 reserved : 28; 3788 }; 3789 3790 UINT_32 value; 3791} ADDR2_SWTYPE_SET; 3792 3793/** 3794**************************************************************************************************** 3795* ADDR2_SWMODE_SET 3796* 3797* @brief 3798* Bit field that defines swizzle type 3799**************************************************************************************************** 3800*/ 3801typedef union _ADDR2_SWMODE_SET 3802{ 3803 struct 3804 { 3805 UINT_32 swLinear : 1; 3806 UINT_32 sw256B_S : 1; 3807 UINT_32 sw256B_D : 1; 3808 UINT_32 sw256B_R : 1; 3809 UINT_32 sw4KB_Z : 1; 3810 UINT_32 sw4KB_S : 1; 3811 UINT_32 sw4KB_D : 1; 3812 UINT_32 sw4KB_R : 1; 3813 UINT_32 sw64KB_Z : 1; 3814 UINT_32 sw64KB_S : 1; 3815 UINT_32 sw64KB_D : 1; 3816 UINT_32 sw64KB_R : 1; 3817 UINT_32 swMiscDef12 : 1; 3818 UINT_32 swMiscDef13 : 1; 3819 UINT_32 swMiscDef14 : 1; 3820 UINT_32 swMiscDef15 : 1; 3821 UINT_32 sw64KB_Z_T : 1; 3822 UINT_32 sw64KB_S_T : 1; 3823 UINT_32 sw64KB_D_T : 1; 3824 UINT_32 sw64KB_R_T : 1; 3825 UINT_32 sw4KB_Z_X : 1; 3826 UINT_32 sw4KB_S_X : 1; 3827 UINT_32 sw4KB_D_X : 1; 3828 UINT_32 sw4KB_R_X : 1; 3829 UINT_32 sw64KB_Z_X : 1; 3830 UINT_32 sw64KB_S_X : 1; 3831 UINT_32 sw64KB_D_X : 1; 3832 UINT_32 sw64KB_R_X : 1; 3833 UINT_32 swMiscDef28 : 1; 3834 UINT_32 swMiscDef29 : 1; 3835 UINT_32 swMiscDef30 : 1; 3836 UINT_32 swMiscDef31 : 1; 3837 }; 3838 3839 struct 3840 { 3841 UINT_32 : 28; 3842 UINT_32 swVar_Z_X : 1; 3843 UINT_32 : 2; 3844 UINT_32 swVar_R_X : 1; 3845 } gfx10; 3846 3847 struct 3848 { 3849 UINT_32 : 28; 3850 UINT_32 sw256KB_Z_X : 1; 3851 UINT_32 sw256KB_S_X : 1; 3852 UINT_32 sw256KB_D_X : 1; 3853 UINT_32 sw256KB_R_X : 1; 3854 } gfx11; 3855 3856 UINT_32 value; 3857} ADDR2_SWMODE_SET; 3858 3859/** 3860**************************************************************************************************** 3861* ADDR2_GET_PREFERRED_SURF_SETTING_INPUT 3862* 3863* @brief 3864* Input structure of Addr2GetPreferredSurfaceSetting 3865**************************************************************************************************** 3866*/ 3867typedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_INPUT 3868{ 3869 UINT_32 size; ///< Size of this structure in bytes 3870 3871 ADDR2_SURFACE_FLAGS flags; ///< Surface flags 3872 AddrResourceType resourceType; ///< Surface type 3873 AddrFormat format; ///< Surface format 3874 AddrResrouceLocation resourceLoction; ///< Surface heap choice 3875 ADDR2_BLOCK_SET forbiddenBlock; ///< Client can use it to disable some block setting 3876 ///< such as linear for DXTn, tiled for YUV 3877 ADDR2_SWTYPE_SET preferredSwSet; ///< Client can use it to specify sw type(s) wanted 3878 BOOL_32 noXor; ///< Do not use xor mode for this resource 3879 UINT_32 bpp; ///< bits per pixel 3880 UINT_32 width; ///< Width (of mip0), in pixels 3881 UINT_32 height; ///< Height (of mip0), in pixels 3882 UINT_32 numSlices; ///< Number surface slice/depth (of mip0), 3883 UINT_32 numMipLevels; ///< Total mipmap levels. 3884 UINT_32 numSamples; ///< Number of samples 3885 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 3886 /// number of samples for normal AA; Set it to the 3887 /// number of fragments for EQAA 3888 UINT_32 maxAlign; ///< maximum base/size alignment requested by client 3889 UINT_32 minSizeAlign; ///< memory allocated for surface in client driver will 3890 /// be padded to multiple of this value (in bytes) 3891 DOUBLE memoryBudget; ///< Memory consumption ratio based on minimum possible 3892 /// size. 3893} ADDR2_GET_PREFERRED_SURF_SETTING_INPUT; 3894 3895/** 3896**************************************************************************************************** 3897* ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT 3898* 3899* @brief 3900* Output structure of Addr2GetPreferredSurfaceSetting 3901**************************************************************************************************** 3902*/ 3903typedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT 3904{ 3905 UINT_32 size; ///< Size of this structure in bytes 3906 3907 AddrSwizzleMode swizzleMode; ///< Suggested swizzle mode to be used 3908 AddrResourceType resourceType; ///< Suggested resource type to program HW 3909 ADDR2_BLOCK_SET validBlockSet; ///< Valid block type bit conbination 3910 BOOL_32 canXor; ///< If client can use xor on a valid macro block 3911 /// type 3912 ADDR2_SWTYPE_SET validSwTypeSet; ///< Valid swizzle type bit combination 3913 ADDR2_SWTYPE_SET clientPreferredSwSet; ///< Client-preferred swizzle type bit combination 3914 ADDR2_SWMODE_SET validSwModeSet; ///< Valid swizzle mode bit combination 3915} ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT; 3916 3917/** 3918**************************************************************************************************** 3919* Addr2GetPreferredSurfaceSetting 3920* 3921* @brief 3922* Suggest a preferred setting for client driver to program HW register 3923**************************************************************************************************** 3924*/ 3925ADDR_E_RETURNCODE ADDR_API Addr2GetPreferredSurfaceSetting( 3926 ADDR_HANDLE hLib, 3927 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 3928 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut); 3929 3930/** 3931**************************************************************************************************** 3932* Addr2IsValidDisplaySwizzleMode 3933* 3934* @brief 3935* Return whether the swizzle mode is supported by display engine 3936**************************************************************************************************** 3937*/ 3938ADDR_E_RETURNCODE ADDR_API Addr2IsValidDisplaySwizzleMode( 3939 ADDR_HANDLE hLib, 3940 AddrSwizzleMode swizzleMode, 3941 UINT_32 bpp, 3942 BOOL_32 *pResult); 3943 3944#if defined(__cplusplus) 3945} 3946#endif 3947 3948#endif // __ADDR_INTERFACE_H__ 3949