1/* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22*/ 23 24#include "CUnit/Basic.h" 25 26#include "amdgpu_test.h" 27#include "amdgpu_drm.h" 28#include "amdgpu_internal.h" 29 30static amdgpu_device_handle device_handle; 31static uint32_t major_version; 32static uint32_t minor_version; 33static uint32_t family_id; 34static uint32_t chip_id; 35static uint32_t chip_rev; 36 37static void amdgpu_vmid_reserve_test(void); 38static void amdgpu_vm_unaligned_map(void); 39static void amdgpu_vm_mapping_test(void); 40 41CU_BOOL suite_vm_tests_enable(void) 42{ 43 CU_BOOL enable = CU_TRUE; 44 45 if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, 46 &minor_version, &device_handle)) 47 return CU_FALSE; 48 49 if (device_handle->info.family_id == AMDGPU_FAMILY_SI) { 50 printf("\n\nCurrently hangs the CP on this ASIC, VM suite disabled\n"); 51 enable = CU_FALSE; 52 } 53 54 if (amdgpu_device_deinitialize(device_handle)) 55 return CU_FALSE; 56 57 return enable; 58} 59 60int suite_vm_tests_init(void) 61{ 62 int r; 63 64 r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, 65 &minor_version, &device_handle); 66 67 if (r) { 68 if ((r == -EACCES) && (errno == EACCES)) 69 printf("\n\nError:%s. " 70 "Hint:Try to run this test program as root.", 71 strerror(errno)); 72 return CUE_SINIT_FAILED; 73 } 74 75 return CUE_SUCCESS; 76} 77 78int suite_vm_tests_clean(void) 79{ 80 int r = amdgpu_device_deinitialize(device_handle); 81 82 if (r == 0) 83 return CUE_SUCCESS; 84 else 85 return CUE_SCLEAN_FAILED; 86} 87 88 89CU_TestInfo vm_tests[] = { 90 { "resere vmid test", amdgpu_vmid_reserve_test }, 91 { "unaligned map", amdgpu_vm_unaligned_map }, 92 { "vm mapping test", amdgpu_vm_mapping_test }, 93 CU_TEST_INFO_NULL, 94}; 95 96static void amdgpu_vmid_reserve_test(void) 97{ 98 amdgpu_context_handle context_handle; 99 amdgpu_bo_handle ib_result_handle; 100 void *ib_result_cpu; 101 uint64_t ib_result_mc_address; 102 struct amdgpu_cs_request ibs_request; 103 struct amdgpu_cs_ib_info ib_info; 104 struct amdgpu_cs_fence fence_status; 105 uint32_t expired, flags; 106 int i, r; 107 amdgpu_bo_list_handle bo_list; 108 amdgpu_va_handle va_handle; 109 static uint32_t *ptr; 110 struct amdgpu_gpu_info gpu_info = {0}; 111 unsigned gc_ip_type; 112 113 r = amdgpu_query_gpu_info(device_handle, &gpu_info); 114 CU_ASSERT_EQUAL(r, 0); 115 116 family_id = device_handle->info.family_id; 117 chip_id = device_handle->info.chip_external_rev; 118 chip_rev = device_handle->info.chip_rev; 119 120 gc_ip_type = (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) ? 121 AMDGPU_HW_IP_COMPUTE : AMDGPU_HW_IP_GFX; 122 123 r = amdgpu_cs_ctx_create(device_handle, &context_handle); 124 CU_ASSERT_EQUAL(r, 0); 125 126 flags = 0; 127 r = amdgpu_vm_reserve_vmid(device_handle, flags); 128 CU_ASSERT_EQUAL(r, 0); 129 130 131 r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, 132 AMDGPU_GEM_DOMAIN_GTT, 0, 133 &ib_result_handle, &ib_result_cpu, 134 &ib_result_mc_address, &va_handle); 135 CU_ASSERT_EQUAL(r, 0); 136 137 r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, 138 &bo_list); 139 CU_ASSERT_EQUAL(r, 0); 140 141 ptr = ib_result_cpu; 142 143 for (i = 0; i < 16; ++i) 144 ptr[i] = 0xffff1000; 145 146 memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info)); 147 ib_info.ib_mc_address = ib_result_mc_address; 148 ib_info.size = 16; 149 150 memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request)); 151 ibs_request.ip_type = gc_ip_type; 152 ibs_request.ring = 0; 153 ibs_request.number_of_ibs = 1; 154 ibs_request.ibs = &ib_info; 155 ibs_request.resources = bo_list; 156 ibs_request.fence_info.handle = NULL; 157 158 r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1); 159 CU_ASSERT_EQUAL(r, 0); 160 161 162 memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence)); 163 fence_status.context = context_handle; 164 fence_status.ip_type = gc_ip_type; 165 fence_status.ip_instance = 0; 166 fence_status.ring = 0; 167 fence_status.fence = ibs_request.seq_no; 168 169 r = amdgpu_cs_query_fence_status(&fence_status, 170 AMDGPU_TIMEOUT_INFINITE,0, &expired); 171 CU_ASSERT_EQUAL(r, 0); 172 173 r = amdgpu_bo_list_destroy(bo_list); 174 CU_ASSERT_EQUAL(r, 0); 175 176 r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, 177 ib_result_mc_address, 4096); 178 CU_ASSERT_EQUAL(r, 0); 179 180 flags = 0; 181 r = amdgpu_vm_unreserve_vmid(device_handle, flags); 182 CU_ASSERT_EQUAL(r, 0); 183 184 185 r = amdgpu_cs_ctx_free(context_handle); 186 CU_ASSERT_EQUAL(r, 0); 187} 188 189static void amdgpu_vm_unaligned_map(void) 190{ 191 const uint64_t map_size = (4ULL << 30) - (2 << 12); 192 struct amdgpu_bo_alloc_request request = {}; 193 amdgpu_bo_handle buf_handle; 194 amdgpu_va_handle handle; 195 uint64_t vmc_addr; 196 int r; 197 198 request.alloc_size = 4ULL << 30; 199 request.phys_alignment = 4096; 200 request.preferred_heap = AMDGPU_GEM_DOMAIN_VRAM; 201 request.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 202 203 r = amdgpu_bo_alloc(device_handle, &request, &buf_handle); 204 /* Don't let the test fail if the device doesn't have enough VRAM */ 205 if (r) 206 return; 207 208 r = amdgpu_va_range_alloc(device_handle, amdgpu_gpu_va_range_general, 209 4ULL << 30, 1ULL << 30, 0, &vmc_addr, 210 &handle, 0); 211 CU_ASSERT_EQUAL(r, 0); 212 if (r) 213 goto error_va_alloc; 214 215 vmc_addr += 1 << 12; 216 217 r = amdgpu_bo_va_op(buf_handle, 0, map_size, vmc_addr, 0, 218 AMDGPU_VA_OP_MAP); 219 CU_ASSERT_EQUAL(r, 0); 220 if (r) 221 goto error_va_alloc; 222 223 amdgpu_bo_va_op(buf_handle, 0, map_size, vmc_addr, 0, 224 AMDGPU_VA_OP_UNMAP); 225 226error_va_alloc: 227 amdgpu_bo_free(buf_handle); 228} 229 230static void amdgpu_vm_mapping_test(void) 231{ 232 struct amdgpu_bo_alloc_request req = {0}; 233 struct drm_amdgpu_info_device dev_info; 234 const uint64_t size = 4096; 235 amdgpu_bo_handle buf; 236 uint64_t addr; 237 int r; 238 239 req.alloc_size = size; 240 req.phys_alignment = 0; 241 req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT; 242 req.flags = 0; 243 244 r = amdgpu_bo_alloc(device_handle, &req, &buf); 245 CU_ASSERT_EQUAL(r, 0); 246 247 r = amdgpu_query_info(device_handle, AMDGPU_INFO_DEV_INFO, 248 sizeof(dev_info), &dev_info); 249 CU_ASSERT_EQUAL(r, 0); 250 251 addr = dev_info.virtual_address_offset; 252 r = amdgpu_bo_va_op(buf, 0, size, addr, 0, AMDGPU_VA_OP_MAP); 253 CU_ASSERT_EQUAL(r, 0); 254 255 addr = dev_info.virtual_address_max - size; 256 r = amdgpu_bo_va_op(buf, 0, size, addr, 0, AMDGPU_VA_OP_MAP); 257 CU_ASSERT_EQUAL(r, 0); 258 259 if (dev_info.high_va_offset) { 260 addr = dev_info.high_va_offset; 261 r = amdgpu_bo_va_op(buf, 0, size, addr, 0, AMDGPU_VA_OP_MAP); 262 CU_ASSERT_EQUAL(r, 0); 263 264 addr = dev_info.high_va_max - size; 265 r = amdgpu_bo_va_op(buf, 0, size, addr, 0, AMDGPU_VA_OP_MAP); 266 CU_ASSERT_EQUAL(r, 0); 267 } 268 269 amdgpu_bo_free(buf); 270} 271