1/* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#include <inttypes.h> 25#include <stdio.h> 26 27#include "CUnit/Basic.h" 28 29#include "util_math.h" 30 31#include "amdgpu_drm.h" 32#include "amdgpu_internal.h" 33#include "amdgpu_test.h" 34#include "decode_messages.h" 35 36/* jpeg registers */ 37#define mmUVD_JPEG_CNTL 0x0200 38#define mmUVD_JPEG_RB_BASE 0x0201 39#define mmUVD_JPEG_RB_WPTR 0x0202 40#define mmUVD_JPEG_RB_RPTR 0x0203 41#define mmUVD_JPEG_RB_SIZE 0x0204 42#define mmUVD_JPEG_TIER_CNTL2 0x021a 43#define mmUVD_JPEG_UV_TILING_CTRL 0x021c 44#define mmUVD_JPEG_TILING_CTRL 0x021e 45#define mmUVD_JPEG_OUTBUF_RPTR 0x0220 46#define mmUVD_JPEG_OUTBUF_WPTR 0x0221 47#define mmUVD_JPEG_PITCH 0x0222 48#define mmUVD_JPEG_INT_EN 0x0229 49#define mmUVD_JPEG_UV_PITCH 0x022b 50#define mmUVD_JPEG_INDEX 0x023e 51#define mmUVD_JPEG_DATA 0x023f 52#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x0438 53#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x0439 54#define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x045a 55#define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x045b 56#define mmUVD_CTX_INDEX 0x0528 57#define mmUVD_CTX_DATA 0x0529 58#define mmUVD_SOFT_RESET 0x05a0 59 60#define vcnipUVD_JPEG_DEC_SOFT_RST 0x402f 61#define vcnipUVD_JRBC_IB_COND_RD_TIMER 0x408e 62#define vcnipUVD_JRBC_IB_REF_DATA 0x408f 63#define vcnipUVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x40e1 64#define vcnipUVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x40e0 65#define vcnipUVD_JPEG_RB_BASE 0x4001 66#define vcnipUVD_JPEG_RB_SIZE 0x4004 67#define vcnipUVD_JPEG_RB_WPTR 0x4002 68#define vcnipUVD_JPEG_PITCH 0x401f 69#define vcnipUVD_JPEG_UV_PITCH 0x4020 70#define vcnipJPEG_DEC_ADDR_MODE 0x4027 71#define vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE 0x4024 72#define vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE 0x4025 73#define vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x40e3 74#define vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x40e2 75#define vcnipUVD_JPEG_INDEX 0x402c 76#define vcnipUVD_JPEG_DATA 0x402d 77#define vcnipUVD_JPEG_TIER_CNTL2 0x400f 78#define vcnipUVD_JPEG_OUTBUF_RPTR 0x401e 79#define vcnipUVD_JPEG_OUTBUF_CNTL 0x401c 80#define vcnipUVD_JPEG_INT_EN 0x400a 81#define vcnipUVD_JPEG_CNTL 0x4000 82#define vcnipUVD_JPEG_RB_RPTR 0x4003 83#define vcnipUVD_JPEG_OUTBUF_WPTR 0x401d 84 85 86#define RDECODE_PKT_REG_J(x) ((unsigned)(x)&0x3FFFF) 87#define RDECODE_PKT_RES_J(x) (((unsigned)(x)&0x3F) << 18) 88#define RDECODE_PKT_COND_J(x) (((unsigned)(x)&0xF) << 24) 89#define RDECODE_PKT_TYPE_J(x) (((unsigned)(x)&0xF) << 28) 90#define RDECODE_PKTJ(reg, cond, type) (RDECODE_PKT_REG_J(reg) | \ 91 RDECODE_PKT_RES_J(0) | \ 92 RDECODE_PKT_COND_J(cond) | \ 93 RDECODE_PKT_TYPE_J(type)) 94 95#define UVD_BASE_INST0_SEG1 0x00007E00 96#define SOC15_REG_ADDR(reg) (UVD_BASE_INST0_SEG1 + reg) 97 98#define COND0 0 99#define COND1 1 100#define COND3 3 101#define TYPE0 0 102#define TYPE1 1 103#define TYPE3 3 104#define JPEG_DEC_DT_PITCH 0x100 105#define JPEG_DEC_BSD_SIZE 0x180 106#define JPEG_DEC_LUMA_OFFSET 0 107#define JPEG_DEC_CHROMA_OFFSET 0x1000 108#define JPEG_DEC_SUM 4096 109#define IB_SIZE 4096 110#define MAX_RESOURCES 16 111 112struct amdgpu_jpeg_bo { 113 amdgpu_bo_handle handle; 114 amdgpu_va_handle va_handle; 115 uint64_t addr; 116 uint64_t size; 117 uint8_t *ptr; 118}; 119 120static amdgpu_device_handle device_handle; 121static uint32_t major_version; 122static uint32_t minor_version; 123static uint32_t family_id; 124static uint32_t chip_rev; 125static uint32_t chip_id; 126static uint32_t asic_id; 127static uint32_t chip_rev; 128static uint32_t chip_id; 129 130static amdgpu_context_handle context_handle; 131static amdgpu_bo_handle ib_handle; 132static amdgpu_va_handle ib_va_handle; 133static uint64_t ib_mc_address; 134static uint32_t *ib_cpu; 135static uint32_t len; 136 137static amdgpu_bo_handle resources[MAX_RESOURCES]; 138static unsigned num_resources; 139bool jpeg_direct_reg; 140 141static void set_reg_jpeg(unsigned reg, unsigned cond, unsigned type, 142 uint32_t val); 143static void send_cmd_bitstream(uint64_t addr); 144static void send_cmd_target(uint64_t addr); 145static void send_cmd_bitstream_direct(uint64_t addr); 146static void send_cmd_target_direct(uint64_t addr); 147 148static void amdgpu_cs_jpeg_decode(void); 149 150CU_TestInfo jpeg_tests[] = { 151 {"JPEG decode", amdgpu_cs_jpeg_decode}, 152 CU_TEST_INFO_NULL, 153}; 154 155CU_BOOL suite_jpeg_tests_enable(void) 156{ 157 struct drm_amdgpu_info_hw_ip info; 158 int r; 159 160 if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, &minor_version, 161 &device_handle)) 162 return CU_FALSE; 163 164 family_id = device_handle->info.family_id; 165 asic_id = device_handle->info.asic_id; 166 chip_rev = device_handle->info.chip_rev; 167 chip_id = device_handle->info.chip_external_rev; 168 169 r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_VCN_JPEG, 0, &info); 170 171 if (amdgpu_device_deinitialize(device_handle)) 172 return CU_FALSE; 173 174 if (r != 0 || !info.available_rings || 175 (family_id < AMDGPU_FAMILY_RV && 176 (family_id == AMDGPU_FAMILY_AI && 177 (chip_id - chip_rev) < 0x32))) { /* Arcturus */ 178 printf("\n\nThe ASIC NOT support JPEG, suite disabled\n"); 179 return CU_FALSE; 180 } 181 182 if (info.hw_ip_version_major == 1) 183 jpeg_direct_reg = false; 184 else if (info.hw_ip_version_major > 1 && info.hw_ip_version_major <= 3) 185 jpeg_direct_reg = true; 186 else 187 return CU_FALSE; 188 189 return CU_TRUE; 190} 191 192int suite_jpeg_tests_init(void) 193{ 194 int r; 195 196 r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, &minor_version, 197 &device_handle); 198 if (r) 199 return CUE_SINIT_FAILED; 200 201 family_id = device_handle->info.family_id; 202 203 r = amdgpu_cs_ctx_create(device_handle, &context_handle); 204 if (r) 205 return CUE_SINIT_FAILED; 206 207 r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096, 208 AMDGPU_GEM_DOMAIN_GTT, 0, &ib_handle, 209 (void **)&ib_cpu, &ib_mc_address, &ib_va_handle); 210 if (r) 211 return CUE_SINIT_FAILED; 212 213 return CUE_SUCCESS; 214} 215 216int suite_jpeg_tests_clean(void) 217{ 218 int r; 219 220 r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, ib_mc_address, IB_SIZE); 221 if (r) 222 return CUE_SCLEAN_FAILED; 223 224 r = amdgpu_cs_ctx_free(context_handle); 225 if (r) 226 return CUE_SCLEAN_FAILED; 227 228 r = amdgpu_device_deinitialize(device_handle); 229 if (r) 230 return CUE_SCLEAN_FAILED; 231 232 return CUE_SUCCESS; 233} 234 235static int submit(unsigned ndw, unsigned ip) 236{ 237 struct amdgpu_cs_request ibs_request = {0}; 238 struct amdgpu_cs_ib_info ib_info = {0}; 239 struct amdgpu_cs_fence fence_status = {0}; 240 uint32_t expired; 241 int r; 242 243 ib_info.ib_mc_address = ib_mc_address; 244 ib_info.size = ndw; 245 246 ibs_request.ip_type = ip; 247 248 r = amdgpu_bo_list_create(device_handle, num_resources, resources, NULL, 249 &ibs_request.resources); 250 if (r) 251 return r; 252 253 ibs_request.number_of_ibs = 1; 254 ibs_request.ibs = &ib_info; 255 ibs_request.fence_info.handle = NULL; 256 257 r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1); 258 if (r) 259 return r; 260 261 r = amdgpu_bo_list_destroy(ibs_request.resources); 262 if (r) 263 return r; 264 265 fence_status.context = context_handle; 266 fence_status.ip_type = ip; 267 fence_status.fence = ibs_request.seq_no; 268 269 r = amdgpu_cs_query_fence_status(&fence_status, AMDGPU_TIMEOUT_INFINITE, 0, 270 &expired); 271 if (r) 272 return r; 273 274 return 0; 275} 276 277static void alloc_resource(struct amdgpu_jpeg_bo *jpeg_bo, unsigned size, 278 unsigned domain) 279{ 280 struct amdgpu_bo_alloc_request req = {0}; 281 amdgpu_bo_handle buf_handle; 282 amdgpu_va_handle va_handle; 283 uint64_t va = 0; 284 int r; 285 286 req.alloc_size = ALIGN(size, 4096); 287 req.preferred_heap = domain; 288 r = amdgpu_bo_alloc(device_handle, &req, &buf_handle); 289 CU_ASSERT_EQUAL(r, 0); 290 r = amdgpu_va_range_alloc(device_handle, amdgpu_gpu_va_range_general, 291 req.alloc_size, 1, 0, &va, &va_handle, 0); 292 CU_ASSERT_EQUAL(r, 0); 293 r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, AMDGPU_VA_OP_MAP); 294 CU_ASSERT_EQUAL(r, 0); 295 jpeg_bo->addr = va; 296 jpeg_bo->handle = buf_handle; 297 jpeg_bo->size = req.alloc_size; 298 jpeg_bo->va_handle = va_handle; 299 r = amdgpu_bo_cpu_map(jpeg_bo->handle, (void **)&jpeg_bo->ptr); 300 CU_ASSERT_EQUAL(r, 0); 301 memset(jpeg_bo->ptr, 0, size); 302 r = amdgpu_bo_cpu_unmap(jpeg_bo->handle); 303 CU_ASSERT_EQUAL(r, 0); 304} 305 306static void free_resource(struct amdgpu_jpeg_bo *jpeg_bo) 307{ 308 int r; 309 310 r = amdgpu_bo_va_op(jpeg_bo->handle, 0, jpeg_bo->size, jpeg_bo->addr, 0, 311 AMDGPU_VA_OP_UNMAP); 312 CU_ASSERT_EQUAL(r, 0); 313 314 r = amdgpu_va_range_free(jpeg_bo->va_handle); 315 CU_ASSERT_EQUAL(r, 0); 316 317 r = amdgpu_bo_free(jpeg_bo->handle); 318 CU_ASSERT_EQUAL(r, 0); 319 memset(jpeg_bo, 0, sizeof(*jpeg_bo)); 320} 321 322static void set_reg_jpeg(unsigned reg, unsigned cond, unsigned type, 323 uint32_t val) 324{ 325 ib_cpu[len++] = RDECODE_PKTJ(reg, cond, type); 326 ib_cpu[len++] = val; 327} 328 329/* send a bitstream buffer command */ 330static void send_cmd_bitstream(uint64_t addr) 331{ 332 333 /* jpeg soft reset */ 334 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 1); 335 336 /* ensuring the Reset is asserted in SCLK domain */ 337 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C2); 338 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0x01400200); 339 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3); 340 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (1 << 9)); 341 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9)); 342 343 /* wait mem */ 344 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0); 345 346 /* ensuring the Reset is de-asserted in SCLK domain */ 347 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3); 348 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (0 << 9)); 349 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9)); 350 351 /* set UVD_LMI_JPEG_READ_64BIT_BAR_LOW/HIGH based on bitstream buffer address */ 352 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH), COND0, TYPE0, 353 (addr >> 32)); 354 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW), COND0, TYPE0, 355 (unsigned int)addr); 356 357 /* set jpeg_rb_base */ 358 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_RB_BASE), COND0, TYPE0, 0); 359 360 /* set jpeg_rb_base */ 361 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_RB_SIZE), COND0, TYPE0, 0xFFFFFFF0); 362 363 /* set jpeg_rb_wptr */ 364 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_RB_WPTR), COND0, TYPE0, 365 (JPEG_DEC_BSD_SIZE >> 2)); 366} 367 368/* send a target buffer command */ 369static void send_cmd_target(uint64_t addr) 370{ 371 372 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_PITCH), COND0, TYPE0, 373 (JPEG_DEC_DT_PITCH >> 4)); 374 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_UV_PITCH), COND0, TYPE0, 375 (JPEG_DEC_DT_PITCH >> 4)); 376 377 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_TILING_CTRL), COND0, TYPE0, 0); 378 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_UV_TILING_CTRL), COND0, TYPE0, 0); 379 380 /* set UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW/HIGH based on target buffer address */ 381 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH), COND0, 382 TYPE0, (addr >> 32)); 383 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW), COND0, TYPE0, 384 (unsigned int)addr); 385 386 /* set output buffer data address */ 387 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_INDEX), COND0, TYPE0, 0); 388 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_DATA), COND0, TYPE0, 389 JPEG_DEC_LUMA_OFFSET); 390 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_INDEX), COND0, TYPE0, 1); 391 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_DATA), COND0, TYPE0, 392 JPEG_DEC_CHROMA_OFFSET); 393 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_TIER_CNTL2), COND0, TYPE3, 0); 394 395 /* set output buffer read pointer */ 396 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_OUTBUF_RPTR), COND0, TYPE0, 0); 397 398 /* enable error interrupts */ 399 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_INT_EN), COND0, TYPE0, 0xFFFFFFFE); 400 401 /* start engine command */ 402 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0x6); 403 404 /* wait for job completion, wait for job JBSI fetch done */ 405 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3); 406 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 407 (JPEG_DEC_BSD_SIZE >> 2)); 408 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C2); 409 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0x01400200); 410 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_RB_RPTR), COND0, TYPE3, 0xFFFFFFFF); 411 412 /* wait for job jpeg outbuf idle */ 413 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3); 414 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0xFFFFFFFF); 415 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_OUTBUF_WPTR), COND0, TYPE3, 416 0x00000001); 417 418 /* stop engine */ 419 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0x4); 420 421 /* asserting jpeg lmi drop */ 422 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x0005); 423 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 424 (1 << 23 | 1 << 0)); 425 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE1, 0); 426 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0); 427 428 /* asserting jpeg reset */ 429 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 1); 430 431 /* ensure reset is asserted in sclk domain */ 432 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3); 433 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (1 << 9)); 434 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9)); 435 436 /* de-assert jpeg reset */ 437 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0); 438 439 /* ensure reset is de-asserted in sclk domain */ 440 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3); 441 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (0 << 9)); 442 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9)); 443 444 /* de-asserting jpeg lmi drop */ 445 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x0005); 446 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0); 447} 448 449/* send a bitstream buffer command */ 450static void send_cmd_bitstream_direct(uint64_t addr) 451{ 452 453 /* jpeg soft reset */ 454 set_reg_jpeg(vcnipUVD_JPEG_DEC_SOFT_RST, COND0, TYPE0, 1); 455 456 /* ensuring the Reset is asserted in SCLK domain */ 457 set_reg_jpeg(vcnipUVD_JRBC_IB_COND_RD_TIMER, COND0, TYPE0, 0x01400200); 458 set_reg_jpeg(vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, (0x1 << 0x10)); 459 set_reg_jpeg(vcnipUVD_JPEG_DEC_SOFT_RST, COND3, TYPE3, (0x1 << 0x10)); 460 461 /* wait mem */ 462 set_reg_jpeg(vcnipUVD_JPEG_DEC_SOFT_RST, COND0, TYPE0, 0); 463 464 /* ensuring the Reset is de-asserted in SCLK domain */ 465 set_reg_jpeg(vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, (0 << 0x10)); 466 set_reg_jpeg(vcnipUVD_JPEG_DEC_SOFT_RST, COND3, TYPE3, (0x1 << 0x10)); 467 468 /* set UVD_LMI_JPEG_READ_64BIT_BAR_LOW/HIGH based on bitstream buffer address */ 469 set_reg_jpeg(vcnipUVD_LMI_JPEG_READ_64BIT_BAR_HIGH, COND0, TYPE0, 470 (addr >> 32)); 471 set_reg_jpeg(vcnipUVD_LMI_JPEG_READ_64BIT_BAR_LOW, COND0, TYPE0, addr); 472 473 /* set jpeg_rb_base */ 474 set_reg_jpeg(vcnipUVD_JPEG_RB_BASE, COND0, TYPE0, 0); 475 476 /* set jpeg_rb_base */ 477 set_reg_jpeg(vcnipUVD_JPEG_RB_SIZE, COND0, TYPE0, 0xFFFFFFF0); 478 479 /* set jpeg_rb_wptr */ 480 set_reg_jpeg(vcnipUVD_JPEG_RB_WPTR, COND0, TYPE0, (JPEG_DEC_BSD_SIZE >> 2)); 481} 482 483/* send a target buffer command */ 484static void send_cmd_target_direct(uint64_t addr) 485{ 486 487 set_reg_jpeg(vcnipUVD_JPEG_PITCH, COND0, TYPE0, (JPEG_DEC_DT_PITCH >> 4)); 488 set_reg_jpeg(vcnipUVD_JPEG_UV_PITCH, COND0, TYPE0, (JPEG_DEC_DT_PITCH >> 4)); 489 490 set_reg_jpeg(vcnipJPEG_DEC_ADDR_MODE, COND0, TYPE0, 0); 491 set_reg_jpeg(vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE, COND0, TYPE0, 0); 492 set_reg_jpeg(vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE, COND0, TYPE0, 0); 493 494 /* set UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW/HIGH based on target buffer address */ 495 set_reg_jpeg(vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH, COND0, TYPE0, 496 (addr >> 32)); 497 set_reg_jpeg(vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW, COND0, TYPE0, addr); 498 499 /* set output buffer data address */ 500 set_reg_jpeg(vcnipUVD_JPEG_INDEX, COND0, TYPE0, 0); 501 set_reg_jpeg(vcnipUVD_JPEG_DATA, COND0, TYPE0, JPEG_DEC_LUMA_OFFSET); 502 set_reg_jpeg(vcnipUVD_JPEG_INDEX, COND0, TYPE0, 1); 503 set_reg_jpeg(vcnipUVD_JPEG_DATA, COND0, TYPE0, JPEG_DEC_CHROMA_OFFSET); 504 set_reg_jpeg(vcnipUVD_JPEG_TIER_CNTL2, COND0, 0, 0); 505 506 /* set output buffer read pointer */ 507 set_reg_jpeg(vcnipUVD_JPEG_OUTBUF_RPTR, COND0, TYPE0, 0); 508 set_reg_jpeg(vcnipUVD_JPEG_OUTBUF_CNTL, COND0, TYPE0, 509 ((0x00001587 & (~0x00000180L)) | (0x1 << 0x7) | (0x1 << 0x6))); 510 511 /* enable error interrupts */ 512 set_reg_jpeg(vcnipUVD_JPEG_INT_EN, COND0, TYPE0, 0xFFFFFFFE); 513 514 /* start engine command */ 515 set_reg_jpeg(vcnipUVD_JPEG_CNTL, COND0, TYPE0, 0xE); 516 517 /* wait for job completion, wait for job JBSI fetch done */ 518 set_reg_jpeg(vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, 519 (JPEG_DEC_BSD_SIZE >> 2)); 520 set_reg_jpeg(vcnipUVD_JRBC_IB_COND_RD_TIMER, COND0, TYPE0, 0x01400200); 521 set_reg_jpeg(vcnipUVD_JPEG_RB_RPTR, COND3, TYPE3, 0xFFFFFFFF); 522 523 /* wait for job jpeg outbuf idle */ 524 set_reg_jpeg(vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, 0xFFFFFFFF); 525 set_reg_jpeg(vcnipUVD_JPEG_OUTBUF_WPTR, COND3, TYPE3, 0x00000001); 526 527 /* stop engine */ 528 set_reg_jpeg(vcnipUVD_JPEG_CNTL, COND0, TYPE0, 0x4); 529} 530 531static void amdgpu_cs_jpeg_decode(void) 532{ 533 534 struct amdgpu_jpeg_bo dec_buf; 535 int size, r; 536 uint8_t *dec; 537 int sum = 0, i, j; 538 539 size = 16 * 1024; /* 8K bitstream + 8K output */ 540 num_resources = 0; 541 alloc_resource(&dec_buf, size, AMDGPU_GEM_DOMAIN_VRAM); 542 resources[num_resources++] = dec_buf.handle; 543 resources[num_resources++] = ib_handle; 544 r = amdgpu_bo_cpu_map(dec_buf.handle, (void **)&dec_buf.ptr); 545 CU_ASSERT_EQUAL(r, 0); 546 memcpy(dec_buf.ptr, jpeg_bitstream, sizeof(jpeg_bitstream)); 547 548 len = 0; 549 550 if (jpeg_direct_reg == true) { 551 send_cmd_bitstream_direct(dec_buf.addr); 552 send_cmd_target_direct(dec_buf.addr + (size / 2)); 553 } else { 554 send_cmd_bitstream(dec_buf.addr); 555 send_cmd_target(dec_buf.addr + (size / 2)); 556 } 557 558 amdgpu_bo_cpu_unmap(dec_buf.handle); 559 r = submit(len, AMDGPU_HW_IP_VCN_JPEG); 560 CU_ASSERT_EQUAL(r, 0); 561 562 r = amdgpu_bo_cpu_map(dec_buf.handle, (void **)&dec_buf.ptr); 563 CU_ASSERT_EQUAL(r, 0); 564 565 dec = dec_buf.ptr + (size / 2); 566 567 /* calculate result checksum */ 568 for (i = 0; i < 8; i++) 569 for (j = 0; j < 8; j++) 570 sum += *((dec + JPEG_DEC_LUMA_OFFSET + i * JPEG_DEC_DT_PITCH) + j); 571 for (i = 0; i < 4; i++) 572 for (j = 0; j < 8; j++) 573 sum += *((dec + JPEG_DEC_CHROMA_OFFSET + i * JPEG_DEC_DT_PITCH) + j); 574 575 amdgpu_bo_cpu_unmap(dec_buf.handle); 576 CU_ASSERT_EQUAL(sum, JPEG_DEC_SUM); 577 578 free_resource(&dec_buf); 579} 580