1d722e3fbSopenharmony_ci/* AUTOMATICALLY GENERATED by gen_table_fourcc.py. You should modify 2d722e3fbSopenharmony_ci that script instead of adding here entries manually! */ 3d722e3fbSopenharmony_cistatic const struct drmFormatModifierInfo drm_format_modifier_table[] = { 4d722e3fbSopenharmony_ci { DRM_MODIFIER_INVALID(NONE, INVALID_MODIFIER) }, 5d722e3fbSopenharmony_ci { DRM_MODIFIER_LINEAR(NONE, LINEAR) }, 6d722e3fbSopenharmony_ci { DRM_MODIFIER_INTEL(X_TILED, X_TILED) }, 7d722e3fbSopenharmony_ci { DRM_MODIFIER_INTEL(Y_TILED, Y_TILED) }, 8d722e3fbSopenharmony_ci { DRM_MODIFIER_INTEL(Yf_TILED, Yf_TILED) }, 9d722e3fbSopenharmony_ci { DRM_MODIFIER_INTEL(Y_TILED_CCS, Y_TILED_CCS) }, 10d722e3fbSopenharmony_ci { DRM_MODIFIER_INTEL(Yf_TILED_CCS, Yf_TILED_CCS) }, 11d722e3fbSopenharmony_ci { DRM_MODIFIER_INTEL(Y_TILED_GEN12_RC_CCS, Y_TILED_GEN12_RC_CCS) }, 12d722e3fbSopenharmony_ci { DRM_MODIFIER_INTEL(Y_TILED_GEN12_MC_CCS, Y_TILED_GEN12_MC_CCS) }, 13d722e3fbSopenharmony_ci { DRM_MODIFIER_INTEL(Y_TILED_GEN12_RC_CCS_CC, Y_TILED_GEN12_RC_CCS_CC) }, 14d722e3fbSopenharmony_ci { DRM_MODIFIER(SAMSUNG, 64_32_TILE, 64_32_TILE) }, 15d722e3fbSopenharmony_ci { DRM_MODIFIER(SAMSUNG, 16_16_TILE, 16_16_TILE) }, 16d722e3fbSopenharmony_ci { DRM_MODIFIER(QCOM, COMPRESSED, COMPRESSED) }, 17d722e3fbSopenharmony_ci { DRM_MODIFIER(VIVANTE, TILED, TILED) }, 18d722e3fbSopenharmony_ci { DRM_MODIFIER(VIVANTE, SUPER_TILED, SUPER_TILED) }, 19d722e3fbSopenharmony_ci { DRM_MODIFIER(VIVANTE, SPLIT_TILED, SPLIT_TILED) }, 20d722e3fbSopenharmony_ci { DRM_MODIFIER(VIVANTE, SPLIT_SUPER_TILED, SPLIT_SUPER_TILED) }, 21d722e3fbSopenharmony_ci { DRM_MODIFIER(NVIDIA, TEGRA_TILED, TEGRA_TILED) }, 22d722e3fbSopenharmony_ci { DRM_MODIFIER(NVIDIA, 16BX2_BLOCK_ONE_GOB, 16BX2_BLOCK_ONE_GOB) }, 23d722e3fbSopenharmony_ci { DRM_MODIFIER(NVIDIA, 16BX2_BLOCK_TWO_GOB, 16BX2_BLOCK_TWO_GOB) }, 24d722e3fbSopenharmony_ci { DRM_MODIFIER(NVIDIA, 16BX2_BLOCK_FOUR_GOB, 16BX2_BLOCK_FOUR_GOB) }, 25d722e3fbSopenharmony_ci { DRM_MODIFIER(NVIDIA, 16BX2_BLOCK_EIGHT_GOB, 16BX2_BLOCK_EIGHT_GOB) }, 26d722e3fbSopenharmony_ci { DRM_MODIFIER(NVIDIA, 16BX2_BLOCK_SIXTEEN_GOB, 16BX2_BLOCK_SIXTEEN_GOB) }, 27d722e3fbSopenharmony_ci { DRM_MODIFIER(NVIDIA, 16BX2_BLOCK_THIRTYTWO_GOB, 16BX2_BLOCK_THIRTYTWO_GOB) }, 28d722e3fbSopenharmony_ci { DRM_MODIFIER(BROADCOM, VC4_T_TILED, VC4_T_TILED) }, 29d722e3fbSopenharmony_ci { DRM_MODIFIER(BROADCOM, SAND32, SAND32) }, 30d722e3fbSopenharmony_ci { DRM_MODIFIER(BROADCOM, SAND64, SAND64) }, 31d722e3fbSopenharmony_ci { DRM_MODIFIER(BROADCOM, SAND128, SAND128) }, 32d722e3fbSopenharmony_ci { DRM_MODIFIER(BROADCOM, SAND256, SAND256) }, 33d722e3fbSopenharmony_ci { DRM_MODIFIER(BROADCOM, UIF, UIF) }, 34d722e3fbSopenharmony_ci { DRM_MODIFIER(ARM, 16X16_BLOCK_U_INTERLEAVED, 16X16_BLOCK_U_INTERLEAVED) }, 35d722e3fbSopenharmony_ci { DRM_MODIFIER(ALLWINNER, TILED, TILED) }, 36d722e3fbSopenharmony_ci}; 37d722e3fbSopenharmony_cistatic const struct drmFormatModifierVendorInfo drm_format_modifier_vendor_table[] = { 38d722e3fbSopenharmony_ci { DRM_FORMAT_MOD_VENDOR_NONE, "NONE" }, 39d722e3fbSopenharmony_ci { DRM_FORMAT_MOD_VENDOR_INTEL, "INTEL" }, 40d722e3fbSopenharmony_ci { DRM_FORMAT_MOD_VENDOR_AMD, "AMD" }, 41d722e3fbSopenharmony_ci { DRM_FORMAT_MOD_VENDOR_NVIDIA, "NVIDIA" }, 42d722e3fbSopenharmony_ci { DRM_FORMAT_MOD_VENDOR_SAMSUNG, "SAMSUNG" }, 43d722e3fbSopenharmony_ci { DRM_FORMAT_MOD_VENDOR_QCOM, "QCOM" }, 44d722e3fbSopenharmony_ci { DRM_FORMAT_MOD_VENDOR_VIVANTE, "VIVANTE" }, 45d722e3fbSopenharmony_ci { DRM_FORMAT_MOD_VENDOR_BROADCOM, "BROADCOM" }, 46d722e3fbSopenharmony_ci { DRM_FORMAT_MOD_VENDOR_ARM, "ARM" }, 47d722e3fbSopenharmony_ci { DRM_FORMAT_MOD_VENDOR_ALLWINNER, "ALLWINNER" }, 48d722e3fbSopenharmony_ci { DRM_FORMAT_MOD_VENDOR_AMLOGIC, "AMLOGIC" }, 49d722e3fbSopenharmony_ci}; 50