1/* 2 * Copyright (c) 2012 3 * MIPS Technologies, Inc., California. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of the MIPS Technologies, Inc., nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE MIPS TECHNOLOGIES, INC. ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE MIPS TECHNOLOGIES, INC. BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * Authors: Darko Laus (darko@mips.com) 30 * Djordje Pesut (djordje@mips.com) 31 * Mirjana Vulin (mvulin@mips.com) 32 * 33 * AAC Spectral Band Replication decoding functions optimized for MIPS 34 * 35 * This file is part of FFmpeg. 36 * 37 * FFmpeg is free software; you can redistribute it and/or 38 * modify it under the terms of the GNU Lesser General Public 39 * License as published by the Free Software Foundation; either 40 * version 2.1 of the License, or (at your option) any later version. 41 * 42 * FFmpeg is distributed in the hope that it will be useful, 43 * but WITHOUT ANY WARRANTY; without even the implied warranty of 44 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 45 * Lesser General Public License for more details. 46 * 47 * You should have received a copy of the GNU Lesser General Public 48 * License along with FFmpeg; if not, write to the Free Software 49 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 50 */ 51 52/** 53 * @file 54 * Reference: libavcodec/aacdec.c 55 */ 56 57#ifndef AVCODEC_MIPS_AACDEC_MIPS_H 58#define AVCODEC_MIPS_AACDEC_MIPS_H 59 60#include "libavcodec/aac.h" 61#include "libavutil/mips/asmdefs.h" 62 63#if HAVE_INLINE_ASM && HAVE_MIPSFPU 64#if !HAVE_MIPS32R6 && !HAVE_MIPS64R6 65static inline float *VMUL2_mips(float *dst, const float *v, unsigned idx, 66 const float *scale) 67{ 68 float temp0, temp1, temp2; 69 int temp3, temp4; 70 float *ret; 71 72 __asm__ volatile( 73 "andi %[temp3], %[idx], 0x0F \n\t" 74 "andi %[temp4], %[idx], 0xF0 \n\t" 75 "sll %[temp3], %[temp3], 2 \n\t" 76 "srl %[temp4], %[temp4], 2 \n\t" 77 "lwc1 %[temp2], 0(%[scale]) \n\t" 78 "lwxc1 %[temp0], %[temp3](%[v]) \n\t" 79 "lwxc1 %[temp1], %[temp4](%[v]) \n\t" 80 "mul.s %[temp0], %[temp0], %[temp2] \n\t" 81 "mul.s %[temp1], %[temp1], %[temp2] \n\t" 82 PTR_ADDIU "%[ret], %[dst], 8 \n\t" 83 "swc1 %[temp0], 0(%[dst]) \n\t" 84 "swc1 %[temp1], 4(%[dst]) \n\t" 85 86 : [temp0]"=&f"(temp0), [temp1]"=&f"(temp1), 87 [temp2]"=&f"(temp2), [temp3]"=&r"(temp3), 88 [temp4]"=&r"(temp4), [ret]"=&r"(ret) 89 : [idx]"r"(idx), [scale]"r"(scale), [v]"r"(v), 90 [dst]"r"(dst) 91 : "memory" 92 ); 93 return ret; 94} 95 96static inline float *VMUL4_mips(float *dst, const float *v, unsigned idx, 97 const float *scale) 98{ 99 int temp0, temp1, temp2, temp3; 100 float temp4, temp5, temp6, temp7, temp8; 101 float *ret; 102 103 __asm__ volatile( 104 "andi %[temp0], %[idx], 0x03 \n\t" 105 "andi %[temp1], %[idx], 0x0C \n\t" 106 "andi %[temp2], %[idx], 0x30 \n\t" 107 "andi %[temp3], %[idx], 0xC0 \n\t" 108 "sll %[temp0], %[temp0], 2 \n\t" 109 "srl %[temp2], %[temp2], 2 \n\t" 110 "srl %[temp3], %[temp3], 4 \n\t" 111 "lwc1 %[temp4], 0(%[scale]) \n\t" 112 "lwxc1 %[temp5], %[temp0](%[v]) \n\t" 113 "lwxc1 %[temp6], %[temp1](%[v]) \n\t" 114 "lwxc1 %[temp7], %[temp2](%[v]) \n\t" 115 "lwxc1 %[temp8], %[temp3](%[v]) \n\t" 116 "mul.s %[temp5], %[temp5], %[temp4] \n\t" 117 "mul.s %[temp6], %[temp6], %[temp4] \n\t" 118 "mul.s %[temp7], %[temp7], %[temp4] \n\t" 119 "mul.s %[temp8], %[temp8], %[temp4] \n\t" 120 PTR_ADDIU "%[ret], %[dst], 16 \n\t" 121 "swc1 %[temp5], 0(%[dst]) \n\t" 122 "swc1 %[temp6], 4(%[dst]) \n\t" 123 "swc1 %[temp7], 8(%[dst]) \n\t" 124 "swc1 %[temp8], 12(%[dst]) \n\t" 125 126 : [temp0]"=&r"(temp0), [temp1]"=&r"(temp1), 127 [temp2]"=&r"(temp2), [temp3]"=&r"(temp3), 128 [temp4]"=&f"(temp4), [temp5]"=&f"(temp5), 129 [temp6]"=&f"(temp6), [temp7]"=&f"(temp7), 130 [temp8]"=&f"(temp8), [ret]"=&r"(ret) 131 : [idx]"r"(idx), [scale]"r"(scale), [v]"r"(v), 132 [dst]"r"(dst) 133 : "memory" 134 ); 135 return ret; 136} 137 138static inline float *VMUL2S_mips(float *dst, const float *v, unsigned idx, 139 unsigned sign, const float *scale) 140{ 141 int temp0, temp1, temp2, temp3, temp4, temp5; 142 float temp6, temp7, temp8, temp9; 143 float *ret; 144 145 __asm__ volatile( 146 "andi %[temp0], %[idx], 0x0F \n\t" 147 "andi %[temp1], %[idx], 0xF0 \n\t" 148 "lw %[temp4], 0(%[scale]) \n\t" 149 "srl %[temp2], %[sign], 1 \n\t" 150 "sll %[temp3], %[sign], 31 \n\t" 151 "sll %[temp2], %[temp2], 31 \n\t" 152 "sll %[temp0], %[temp0], 2 \n\t" 153 "srl %[temp1], %[temp1], 2 \n\t" 154 "lwxc1 %[temp8], %[temp0](%[v]) \n\t" 155 "lwxc1 %[temp9], %[temp1](%[v]) \n\t" 156 "xor %[temp5], %[temp4], %[temp2] \n\t" 157 "xor %[temp4], %[temp4], %[temp3] \n\t" 158 "mtc1 %[temp5], %[temp6] \n\t" 159 "mtc1 %[temp4], %[temp7] \n\t" 160 "mul.s %[temp8], %[temp8], %[temp6] \n\t" 161 "mul.s %[temp9], %[temp9], %[temp7] \n\t" 162 PTR_ADDIU "%[ret], %[dst], 8 \n\t" 163 "swc1 %[temp8], 0(%[dst]) \n\t" 164 "swc1 %[temp9], 4(%[dst]) \n\t" 165 166 : [temp0]"=&r"(temp0), [temp1]"=&r"(temp1), 167 [temp2]"=&r"(temp2), [temp3]"=&r"(temp3), 168 [temp4]"=&r"(temp4), [temp5]"=&r"(temp5), 169 [temp6]"=&f"(temp6), [temp7]"=&f"(temp7), 170 [temp8]"=&f"(temp8), [temp9]"=&f"(temp9), 171 [ret]"=&r"(ret) 172 : [idx]"r"(idx), [scale]"r"(scale), [v]"r"(v), 173 [dst]"r"(dst), [sign]"r"(sign) 174 : "memory" 175 ); 176 return ret; 177} 178 179static inline float *VMUL4S_mips(float *dst, const float *v, unsigned idx, 180 unsigned sign, const float *scale) 181{ 182 int temp0, temp1, temp2, temp3, temp4; 183 float temp10, temp11, temp12, temp13, temp14, temp15, temp16, temp17; 184 float *ret; 185 unsigned int mask = 1U << 31; 186 187 __asm__ volatile( 188 "lw %[temp0], 0(%[scale]) \n\t" 189 "andi %[temp1], %[idx], 0x03 \n\t" 190 "andi %[temp2], %[idx], 0x0C \n\t" 191 "andi %[temp3], %[idx], 0x30 \n\t" 192 "andi %[temp4], %[idx], 0xC0 \n\t" 193 "sll %[temp1], %[temp1], 2 \n\t" 194 "srl %[temp3], %[temp3], 2 \n\t" 195 "srl %[temp4], %[temp4], 4 \n\t" 196 "lwxc1 %[temp10], %[temp1](%[v]) \n\t" 197 "lwxc1 %[temp11], %[temp2](%[v]) \n\t" 198 "lwxc1 %[temp12], %[temp3](%[v]) \n\t" 199 "lwxc1 %[temp13], %[temp4](%[v]) \n\t" 200 "and %[temp1], %[sign], %[mask] \n\t" 201 "srl %[temp2], %[idx], 12 \n\t" 202 "srl %[temp3], %[idx], 13 \n\t" 203 "srl %[temp4], %[idx], 14 \n\t" 204 "andi %[temp2], %[temp2], 1 \n\t" 205 "andi %[temp3], %[temp3], 1 \n\t" 206 "andi %[temp4], %[temp4], 1 \n\t" 207 "sllv %[sign], %[sign], %[temp2] \n\t" 208 "xor %[temp1], %[temp0], %[temp1] \n\t" 209 "and %[temp2], %[sign], %[mask] \n\t" 210 "mtc1 %[temp1], %[temp14] \n\t" 211 "xor %[temp2], %[temp0], %[temp2] \n\t" 212 "sllv %[sign], %[sign], %[temp3] \n\t" 213 "mtc1 %[temp2], %[temp15] \n\t" 214 "and %[temp3], %[sign], %[mask] \n\t" 215 "sllv %[sign], %[sign], %[temp4] \n\t" 216 "xor %[temp3], %[temp0], %[temp3] \n\t" 217 "and %[temp4], %[sign], %[mask] \n\t" 218 "mtc1 %[temp3], %[temp16] \n\t" 219 "xor %[temp4], %[temp0], %[temp4] \n\t" 220 "mtc1 %[temp4], %[temp17] \n\t" 221 "mul.s %[temp10], %[temp10], %[temp14] \n\t" 222 "mul.s %[temp11], %[temp11], %[temp15] \n\t" 223 "mul.s %[temp12], %[temp12], %[temp16] \n\t" 224 "mul.s %[temp13], %[temp13], %[temp17] \n\t" 225 PTR_ADDIU "%[ret], %[dst], 16 \n\t" 226 "swc1 %[temp10], 0(%[dst]) \n\t" 227 "swc1 %[temp11], 4(%[dst]) \n\t" 228 "swc1 %[temp12], 8(%[dst]) \n\t" 229 "swc1 %[temp13], 12(%[dst]) \n\t" 230 231 : [temp0]"=&r"(temp0), [temp1]"=&r"(temp1), 232 [temp2]"=&r"(temp2), [temp3]"=&r"(temp3), 233 [temp4]"=&r"(temp4), [temp10]"=&f"(temp10), 234 [temp11]"=&f"(temp11), [temp12]"=&f"(temp12), 235 [temp13]"=&f"(temp13), [temp14]"=&f"(temp14), 236 [temp15]"=&f"(temp15), [temp16]"=&f"(temp16), 237 [temp17]"=&f"(temp17), [ret]"=&r"(ret), 238 [sign]"+r"(sign) 239 : [idx]"r"(idx), [scale]"r"(scale), [v]"r"(v), 240 [dst]"r"(dst), [mask]"r"(mask) 241 : "memory" 242 ); 243 return ret; 244} 245 246#define VMUL2 VMUL2_mips 247#define VMUL4 VMUL4_mips 248#define VMUL2S VMUL2S_mips 249#define VMUL4S VMUL4S_mips 250#endif /* !HAVE_MIPS32R6 && !HAVE_MIPS64R6 */ 251#endif /* HAVE_INLINE_ASM && HAVE_MIPSFPU */ 252 253#endif /* AVCODEC_MIPS_AACDEC_MIPS_H */ 254