1// SPDX-License-Identifier: BSD-3-Clause
2//
3// Copyright(c) 2021 Intel Corporation. All rights reserved.
4//
5// Author: Jaska Uimonen <jaska.uimonen@linux.intel.com>
6
7#include "aconfig.h"
8#include <stdio.h>
9#include <stdint.h>
10#include <alsa/global.h>
11#include "ssp-debug.h"
12#include "../intel-nhlt.h"
13
14#ifdef NHLT_DEBUG
15
16void ssp_print_calculated(struct intel_ssp_params *ssp)
17{
18	struct ssp_intel_config_data *blob;
19	struct ssp_intel_config_data_1_5 *blob15;
20	struct ssp_aux_blob *blob_aux;
21	int ssp_index = ssp->ssp_count;
22	uint32_t *ptr;
23	int i, j;
24
25	fprintf(stdout, "printing ssp nhlt calculated data:\n");
26
27	/* top level struct */
28	fprintf(stdout, "ssp index %d\n", ssp_index);
29
30	fprintf(stdout, "ssp %d dai_index: %u\n", ssp_index, ssp->ssp_dai_index[ssp_index]);
31
32	fprintf(stdout, "ssp blob version %u\n", ssp->ssp_prm[ssp_index].version);
33
34	fprintf(stdout, "ssp %d hw_config_count: %u\n", ssp_index,
35		ssp->ssp_hw_config_count[ssp_index]);
36
37	fprintf(stdout, "\n");
38
39	for (i = 0; i < ssp->ssp_hw_config_count[ssp_index]; i++) {
40		fprintf(stdout, "ssp blob %d hw_config %d\n", ssp->ssp_count, i);
41		if (ssp->ssp_prm[ssp_index].version == SSP_BLOB_VER_1_5) {
42			blob15 = &ssp->ssp_blob_1_5[ssp_index][i];
43			fprintf(stdout, "gateway_attributes %u\n", blob15->gateway_attributes);
44			fprintf(stdout, "version %u\n", blob15->version);
45			fprintf(stdout, "size %u\n", blob15->size);
46			fprintf(stdout, "ts_group[0] 0x%08x\n", blob15->ts_group[0]);
47			fprintf(stdout, "ts_group[1] 0x%08x\n", blob15->ts_group[1]);
48			fprintf(stdout, "ts_group[2] 0x%08x\n", blob15->ts_group[2]);
49			fprintf(stdout, "ts_group[3] 0x%08x\n", blob15->ts_group[3]);
50			fprintf(stdout, "ts_group[4] 0x%08x\n", blob15->ts_group[4]);
51			fprintf(stdout, "ts_group[5] 0x%08x\n", blob15->ts_group[5]);
52			fprintf(stdout, "ts_group[6] 0x%08x\n", blob15->ts_group[6]);
53			fprintf(stdout, "ts_group[7] 0x%08x\n", blob15->ts_group[7]);
54			fprintf(stdout, "ssc0 0x%08x\n", blob15->ssc0);
55			fprintf(stdout, "ssc1 0x%08x\n", blob15->ssc1);
56			fprintf(stdout, "sscto 0x%08x\n", blob15->sscto);
57			fprintf(stdout, "sspsp 0x%08x\n", blob15->sspsp);
58			fprintf(stdout, "sstsa 0x%08x\n", blob15->sstsa);
59			fprintf(stdout, "ssrsa 0x%08x\n", blob15->ssrsa);
60			fprintf(stdout, "ssc2 0x%08x\n", blob15->ssc2);
61			fprintf(stdout, "sspsp2 0x%08x\n", blob15->sspsp2);
62			fprintf(stdout, "ssc3 0x%08x\n", blob15->ssc3);
63			fprintf(stdout, "ssioc 0x%08x\n", blob15->ssioc);
64			fprintf(stdout, "mdivc 0x%08x\n", blob15->mdivctlr);
65			fprintf(stdout, "mdivr count 0x%08x\n", blob15->mdivrcnt);
66			for (j = 0; j < blob15->mdivrcnt; j++)
67				fprintf(stdout, "mdivr 0x%08x\n",
68					ssp->ssp_prm[ssp_index].mdivr[i].mdivrs[j]);
69		} else {
70			blob = &ssp->ssp_blob[ssp_index][i];
71			fprintf(stdout, "gateway_attributes %u\n", blob->gateway_attributes);
72			fprintf(stdout, "ts_group[0] 0x%08x\n", blob->ts_group[0]);
73			fprintf(stdout, "ts_group[1] 0x%08x\n", blob->ts_group[1]);
74			fprintf(stdout, "ts_group[2] 0x%08x\n", blob->ts_group[2]);
75			fprintf(stdout, "ts_group[3] 0x%08x\n", blob->ts_group[3]);
76			fprintf(stdout, "ts_group[4] 0x%08x\n", blob->ts_group[4]);
77			fprintf(stdout, "ts_group[5] 0x%08x\n", blob->ts_group[5]);
78			fprintf(stdout, "ts_group[6] 0x%08x\n", blob->ts_group[6]);
79			fprintf(stdout, "ts_group[7] 0x%08x\n", blob->ts_group[7]);
80			fprintf(stdout, "ssc0 0x%08x\n", blob->ssc0);
81			fprintf(stdout, "ssc1 0x%08x\n", blob->ssc1);
82			fprintf(stdout, "sscto 0x%08x\n", blob->sscto);
83			fprintf(stdout, "sspsp 0x%08x\n", blob->sspsp);
84			fprintf(stdout, "sstsa 0x%08x\n", blob->sstsa);
85			fprintf(stdout, "ssrsa 0x%08x\n", blob->ssrsa);
86			fprintf(stdout, "ssc2 0x%08x\n", blob->ssc2);
87			fprintf(stdout, "sspsp2 0x%08x\n", blob->sspsp2);
88			fprintf(stdout, "ssc3 0x%08x\n", blob->ssc3);
89			fprintf(stdout, "ssioc 0x%08x\n", blob->ssioc);
90			fprintf(stdout, "mdivc 0x%08x\n", blob->mdivc);
91			fprintf(stdout, "mdivr 0x%08x\n", blob->mdivr);
92		}
93		blob_aux = (struct ssp_aux_blob *)&(ssp->ssp_blob_ext[ssp_index][i]);
94		fprintf(stdout, "aux_blob size  %u\n", blob_aux->size);
95		for (j = 0; j < blob_aux->size; j += 4) {
96			ptr = (uint32_t *)&(blob_aux->aux_blob[j]);
97			fprintf(stdout, "aux_blob %d 0x%08x\n", j, *ptr);
98		}
99
100		fprintf(stdout, "\n");
101	}
102
103	fprintf(stdout, "\n");
104}
105
106void ssp_print_internal(struct intel_ssp_params *ssp)
107{
108	struct ssp_aux_config_link *link;
109	struct ssp_aux_config_sync *sync;
110	struct ssp_aux_config_ext *ext;
111	struct ssp_aux_config_run *run;
112	struct ssp_aux_config_clk *clk;
113	struct ssp_aux_config_mn *mn;
114	struct ssp_aux_config_tr *tr;
115	struct ssp_config_dai *dai;
116	struct ssp_config_hw *hw_conf;
117	uint32_t enabled;
118	int i, j;
119
120	dai = &ssp->ssp_prm[ssp->ssp_count];
121
122	fprintf(stdout, "printing ssp nhlt internal data:\n");
123
124	fprintf(stdout, "io_clk %u\n", dai->io_clk);
125	fprintf(stdout, "dai_index %u\n", dai->dai_index);
126	fprintf(stdout, "mclk_id %u\n", dai->mclk_id);
127	fprintf(stdout, "sample_valid_bits %u\n", dai->sample_valid_bits);
128	fprintf(stdout, "mclk_direction %u\n", dai->mclk_direction);
129	fprintf(stdout, "frame_pulse_width %u\n", dai->frame_pulse_width);
130	fprintf(stdout, "tdm_per_slot_padding_flag %u\n", dai->tdm_per_slot_padding_flag);
131	fprintf(stdout, "clks_control %u\n", dai->clks_control);
132	fprintf(stdout, "quirks %u\n", dai->quirks);
133	fprintf(stdout, "bclk_delay %u\n", dai->bclk_delay);
134	fprintf(stdout, "version %u\n", dai->version);
135
136	fprintf(stdout, "\n");
137
138	fprintf(stdout, "hw_config_count %u\n", ssp->ssp_hw_config_count[ssp->ssp_count]);
139
140	for (i = 0; i < ssp->ssp_hw_config_count[ssp->ssp_count]; i++) {
141		hw_conf = &dai->hw_cfg[i];
142		fprintf(stdout, "mclk_rate %u\n", hw_conf->mclk_rate);
143		fprintf(stdout, "bclk_rate %u\n", hw_conf->bclk_rate);
144		fprintf(stdout, "fsync_rate %u\n", hw_conf->fsync_rate);
145		fprintf(stdout, "tdm_slots %u\n", hw_conf->tdm_slots);
146		fprintf(stdout, "tdm_slot_width %u\n", hw_conf->tdm_slot_width);
147		fprintf(stdout, "tx_slots %u\n", hw_conf->tx_slots);
148		fprintf(stdout, "rx_slots %u\n", hw_conf->rx_slots);
149		fprintf(stdout, "format %u\n", hw_conf->format);
150
151		enabled = dai->aux_cfg[i].enabled;
152		fprintf(stdout, "aux enabled %x\n", enabled);
153		fprintf(stdout, "\n");
154
155		mn = (struct ssp_aux_config_mn *)&(dai->aux_cfg[i].mn);
156		clk = (struct ssp_aux_config_clk *)&(dai->aux_cfg[i].clk);
157		tr = (struct ssp_aux_config_tr *)&(dai->aux_cfg[i].tr_start);
158		tr = (struct ssp_aux_config_tr *)&(dai->aux_cfg[i].tr_stop);
159		run = (struct ssp_aux_config_run *)&(dai->aux_cfg[i].run);
160		sync = (struct ssp_aux_config_sync *)&(dai->aux_cfg[i].sync);
161		ext = (struct ssp_aux_config_ext *)&(dai->aux_cfg[i].ext);
162		link = (struct ssp_aux_config_link *)&(dai->aux_cfg[i].link);
163
164		if (enabled & BIT(SSP_MN_DIVIDER_CONTROLS)) {
165			fprintf(stdout, "aux mn m_div %u\n", mn->m_div);
166			fprintf(stdout, "aux mn n_div %u\n", mn->n_div);
167			fprintf(stdout, "\n");
168		}
169
170		if (enabled & BIT(SSP_DMA_CLK_CONTROLS)) {
171			fprintf(stdout, "aux clk clock_warm_up %u\n", clk->clock_warm_up);
172			fprintf(stdout, "aux clk mclk %u\n", clk->mclk);
173			fprintf(stdout, "aux clk warm_up_ovr %u\n", clk->warm_up_ovr);
174			fprintf(stdout, "aux clk clock_stop_delay %u\n", clk->clock_stop_delay);
175			fprintf(stdout, "aux clk keep_running %u\n", clk->keep_running);
176			fprintf(stdout, "aux clk keep_running %u\n", clk->clock_stop_ovr);
177			fprintf(stdout, "\n");
178		}
179
180		if (enabled & BIT(SSP_DMA_TRANSMISSION_START)) {
181			fprintf(stdout, "aux tr start sampling_frequency %u\n", tr->sampling_frequency);
182			fprintf(stdout, "aux tr start bit_depth %u\n", tr->bit_depth);
183			fprintf(stdout, "aux tr start channel_map %u\n", tr->channel_map);
184			fprintf(stdout, "aux tr start channel_config %u\n", tr->channel_config);
185			fprintf(stdout, "aux tr start interleaving_style %u\n", tr->interleaving_style);
186			fprintf(stdout, "aux tr start number_of_channels %u\n", tr->number_of_channels);
187			fprintf(stdout, "aux tr start valid_bit_depth %u\n", tr->valid_bit_depth);
188			fprintf(stdout, "aux tr start sample_types %u\n", tr->sample_type);
189			fprintf(stdout, "\n");
190		}
191
192		if (enabled & BIT(SSP_DMA_TRANSMISSION_STOP)) {
193			fprintf(stdout, "aux tr start sampling_frequency %u\n", tr->sampling_frequency);
194			fprintf(stdout, "aux tr start bit_depth %u\n", tr->bit_depth);
195			fprintf(stdout, "aux tr start channel_map %u\n", tr->channel_map);
196			fprintf(stdout, "aux tr start channel_config %u\n", tr->channel_config);
197			fprintf(stdout, "aux tr start interleaving_style %u\n", tr->interleaving_style);
198			fprintf(stdout, "aux tr start number_of_channels %u\n", tr->number_of_channels);
199			fprintf(stdout, "aux tr start valid_bit_depth %u\n", tr->valid_bit_depth);
200			fprintf(stdout, "aux tr start sample_types %u\n", tr->sample_type);
201			fprintf(stdout, "\n");
202		}
203
204		if (enabled & BIT(SSP_DMA_ALWAYS_RUNNING_MODE)) {
205			fprintf(stdout, "aux run always_run %u\n", run->always_run);
206			fprintf(stdout, "\n");
207		}
208
209		if (enabled & BIT(SSP_DMA_SYNC_DATA)) {
210			fprintf(stdout, "aux sync sync_denominator %u\n", sync->sync_denominator);
211			fprintf(stdout, "aux sync count %u\n", sync->count);
212
213			for (j = 0; j < sync->count; j++) {
214				fprintf(stdout, "aux sync node_id %u\n", sync->nodes[j].node_id);
215				fprintf(stdout, "aux sync sampling_rate %u\n", sync->nodes[j].sampling_rate);
216			}
217
218			fprintf(stdout, "\n");
219		}
220
221		if (enabled & BIT(SSP_DMA_CLK_CONTROLS_EXT)) {
222			fprintf(stdout, "aux ext mclk_policy_override %u\n", ext->mclk_policy_override);
223			fprintf(stdout, "aux ext mclk_always_running %u\n", ext->mclk_always_running);
224			fprintf(stdout, "aux ext mclk_starts_on_gtw_init %u\n", ext->mclk_starts_on_gtw_init);
225			fprintf(stdout, "aux ext mclk_starts_on_run %u\n", ext->mclk_starts_on_run);
226			fprintf(stdout, "aux ext mclk_starts_on_pause %u\n", ext->mclk_starts_on_pause);
227			fprintf(stdout, "aux ext mclk_stops_on_pause %u\n", ext->mclk_stops_on_pause);
228			fprintf(stdout, "aux ext mclk_stops_on_reset %u\n", ext->mclk_stops_on_reset);
229			fprintf(stdout, "aux ext bclk_policy_override %u\n", ext->bclk_policy_override);
230			fprintf(stdout, "aux ext bclk_always_running %u\n", ext->bclk_always_running);
231			fprintf(stdout, "aux ext bclk_starts_on_gtw_init %u\n", ext->bclk_starts_on_gtw_init);
232			fprintf(stdout, "aux ext bclk_starts_on_run %u\n", ext->bclk_starts_on_run);
233			fprintf(stdout, "aux ext bclk_starts_on_pause %u\n", ext->bclk_starts_on_pause);
234			fprintf(stdout, "aux ext bclk_stops_on_pause %u\n", ext->bclk_stops_on_pause);
235			fprintf(stdout, "aux ext bclk_stops_on_reset %u\n", ext->bclk_stops_on_reset);
236			fprintf(stdout, "aux ext sync_policy_override %u\n", ext->sync_policy_override);
237			fprintf(stdout, "aux ext sync_always_running %u\n", ext->sync_always_running);
238			fprintf(stdout, "aux ext sync_starts_on_gtw_init %u\n", ext->sync_starts_on_gtw_init);
239			fprintf(stdout, "aux ext sync_starts_on_run %u\n", ext->sync_starts_on_run);
240			fprintf(stdout, "aux ext sync_starts_on_pause %u\n", ext->sync_starts_on_pause);
241			fprintf(stdout, "aux ext sync_stops_on_pause %u\n", ext->sync_stops_on_pause);
242			fprintf(stdout, "aux ext sync_stops_on_reset %u\n", ext->sync_stops_on_reset);
243			fprintf(stdout, "\n");
244		}
245
246		if (enabled & BIT(SSP_LINK_CLK_SOURCE)) {
247			fprintf(stdout, "aux link clock_source %u\n", link->clock_source);
248			fprintf(stdout, "\n");
249		}
250	}
251
252	fprintf(stdout, "\n");
253}
254
255#else /* NHLT_DEBUG */
256void ssp_print_internal(struct intel_ssp_params *ssp ATTRIBUTE_UNUSED) {}
257void ssp_print_calculated(struct intel_ssp_params *ssp ATTRIBUTE_UNUSED) {}
258#endif
259