1// SPDX-License-Identifier: BSD-3-Clause 2// 3// Copyright(c) 2021 Intel Corporation. All rights reserved. 4// 5// Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com> 6// Jaska Uimonen <jaska.uimonen@linux.intel.com> 7 8#include "aconfig.h" 9#include <stdint.h> 10#include <errno.h> 11#include <stdio.h> 12#include <stdlib.h> 13#include <string.h> 14#include <alsa/input.h> 15#include <alsa/output.h> 16#include <alsa/conf.h> 17#include <alsa/error.h> 18#include "../intel-nhlt.h" 19#include "dmic-process.h" 20#include "dmic-internal.h" 21#include "pdm-decim-fir.h" 22#include "dmic-debug.h" 23 24/* Note 1: Higher spec filter must be before lower spec filter if there are multiple filters for a 25 * decimation factor. The first filter is skipped if the length is too much vs. overrun limit. If 26 * other order the better filter would be never selected. 27 * 28 * Note 2: The introduction order of FIR decimation factors is the selection preference order. 29 * The decimation factor 5 and 10 (2*5) cause a often less compatible output sample rate for CIC so 30 * they are not used if there other suitable nearby values. 31 * 32 * The naming scheme of coefficients set is: 33 * <type>_<decim factor>_<rel passband>_<rel stopband>_<ripple>_<attenuation> 34 */ 35struct pdm_decim *fir_list[] = { 36 &pdm_decim_int32_02_4375_5100_010_095, 37 &pdm_decim_int32_02_4323_5100_010_095, 38 &pdm_decim_int32_03_4375_5100_010_095, 39 &pdm_decim_int32_04_4318_5100_010_095, 40 &pdm_decim_int32_06_4172_5100_010_095, 41 &pdm_decim_int32_05_4325_5100_010_095, 42 &pdm_decim_int32_08_4156_5301_010_090, 43 &pdm_decim_int32_12_4156_5345_010_090, 44 &pdm_decim_int32_10_4156_5345_010_090, 45 NULL, /* This marks the end of coefficients */ 46}; 47 48/* This is a divide function that returns ceil of the quotient. E.g. ceil_divide(9, 3) returns 3, 49 * ceil_divide(10, 3) returns 4. 50 */ 51static int ceil_divide(int a, int b) 52{ 53 int c; 54 55 c = a / b; 56 57 if (!((a ^ b) & (1U << ((sizeof(int) * 8) - 1))) && c * b != a) 58 c++; 59 60 return c; 61} 62 63/* This function searches from vec[] (of length vec_length) integer values of n. The indices to 64 * equal values is returned in idx[]. The function returns the number of found matches. 65 * The max_results should be set to 0 (or negative) or vec_length to get all matches. The 66 * max_result can be set to 1 to receive only the first match in ascending order. It avoids need for 67 * an array for idx. 68 */ 69static int find_equal_int16(int16_t idx[], int16_t vec[], int n, int vec_length, 70 int max_results) 71{ 72 int nresults = 0; 73 int i; 74 75 for (i = 0; i < vec_length; i++) { 76 if (vec[i] == n) { 77 idx[nresults++] = i; 78 if (nresults == max_results) 79 break; 80 } 81 } 82 83 return nresults; 84} 85 86/* Return the largest absolute value found in the vector. Note that smallest negative value need to 87 * be saturated to preset as int32_t. 88 */ 89static int32_t find_max_abs_int32(int32_t vec[], int vec_length) 90{ 91 int i; 92 int64_t amax = (vec[0] > 0) ? vec[0] : -vec[0]; 93 94 for (i = 1; i < vec_length; i++) { 95 amax = (vec[i] > amax) ? vec[i] : amax; 96 amax = (-vec[i] > amax) ? -vec[i] : amax; 97 } 98 99 return SATP_INT32(amax); /* Amax is always a positive value */ 100} 101 102/* Count the left shift amount to normalize a 32 bit signed integer value without causing overflow. 103 * Input value 0 will result to 31. 104 */ 105static int norm_int32(int32_t val) 106{ 107 int c = 0; 108 109 /* count number of bits c that val can be right-shifted arithmetically 110 * until there is -1 (if val is negative) or 0 (if val is positive) 111 * norm of val will be 31-c 112 */ 113 for (; val != -1 && val != 0; c++) 114 val >>= 1; 115 116 return 31 - c; 117} 118 119/* This function returns a raw list of potential microphone clock and decimation modes for achieving 120 * requested sample rates. The search is constrained by decimation HW capabililies and setup 121 * parameters. The parameters such as microphone clock min/max and duty cycle requirements need be 122 * checked from used microphone component datasheet. 123 */ 124static void find_modes(struct intel_dmic_params *dmic, struct dmic_calc_decim_modes *modes, 125 uint32_t fs) 126{ 127 int di = dmic->dmic_dai_index; 128 int clkdiv_min; 129 int clkdiv_max; 130 int clkdiv; 131 int c1; 132 int du_min; 133 int du_max; 134 int pdmclk; 135 int osr; 136 int mfir; 137 int mcic; 138 unsigned int ioclk_test; 139 int osr_min = DMIC_MIN_OSR; 140 int j; 141 int i = 0; 142 143 /* Defaults, empty result */ 144 modes->num_of_modes = 0; 145 146 /* The FIFO is not requested if sample rate is set to zero. Just return in such case with 147 * num_of_modes as zero. 148 */ 149 if (fs == 0) { 150 return; 151 } 152 153 /* Override DMIC_MIN_OSR for very high sample rates, use as minimum the nominal clock for 154 * the high rates. 155 */ 156 if (fs >= DMIC_HIGH_RATE_MIN_FS) 157 osr_min = DMIC_HIGH_RATE_OSR_MIN; 158 159 /* Check for sane pdm clock, min 100 kHz, max ioclk/2 */ 160 if (dmic->dmic_prm[di].pdmclk_max < DMIC_HW_PDM_CLK_MIN || 161 dmic->dmic_prm[di].pdmclk_max > dmic->dmic_prm[di].io_clk / 2) { 162 fprintf(stderr, "find_modes(): pdm clock max not in range\n"); 163 return; 164 } 165 if (dmic->dmic_prm[di].pdmclk_min < DMIC_HW_PDM_CLK_MIN || 166 dmic->dmic_prm[di].pdmclk_min > dmic->dmic_prm[di].pdmclk_max) { 167 fprintf(stderr, "find_modes(): pdm clock min not in range\n"); 168 return; 169 } 170 171 /* Check for sane duty cycle */ 172 if (dmic->dmic_prm[di].duty_min > dmic->dmic_prm[di].duty_max) { 173 fprintf(stderr, "find_modes(): duty cycle min > max\n"); 174 return; 175 } 176 if (dmic->dmic_prm[di].duty_min < DMIC_HW_DUTY_MIN || 177 dmic->dmic_prm[di].duty_min > DMIC_HW_DUTY_MAX) { 178 fprintf(stderr, "find_modes(): pdm clock min not in range\n"); 179 return; 180 } 181 if (dmic->dmic_prm[di].duty_max < DMIC_HW_DUTY_MIN || 182 dmic->dmic_prm[di].duty_max > DMIC_HW_DUTY_MAX) { 183 fprintf(stderr, "find_modes(): pdm clock max not in range\n"); 184 return; 185 } 186 187 /* Min and max clock dividers */ 188 clkdiv_min = ceil_divide(dmic->dmic_prm[di].io_clk, dmic->dmic_prm[di].pdmclk_max); 189 clkdiv_min = MAX(clkdiv_min, DMIC_HW_CIC_DECIM_MIN); 190 clkdiv_max = dmic->dmic_prm[di].io_clk / dmic->dmic_prm[di].pdmclk_min; 191 192 /* Loop possible clock dividers and check based on resulting oversampling ratio that CIC and 193 * FIR decimation ratios are feasible. The ratios need to be integers. Also the mic clock 194 * duty cycle need to be within limits. 195 */ 196 for (clkdiv = clkdiv_min; clkdiv <= clkdiv_max; clkdiv++) { 197 /* Calculate duty cycle for this clock divider. Note that odd dividers cause non-50% 198 * duty cycle. 199 */ 200 c1 = clkdiv >> 1; 201 du_min = 100 * c1 / clkdiv; 202 du_max = 100 - du_min; 203 204 /* Calculate PDM clock rate and oversampling ratio. */ 205 pdmclk = dmic->dmic_prm[di].io_clk / clkdiv; 206 osr = pdmclk / fs; 207 208 /* Check that OSR constraints is met and clock duty cycle does not exceed microphone 209 * specification. If exceed proceed to next clkdiv. 210 */ 211 if (osr < osr_min || du_min < dmic->dmic_prm[di].duty_min || 212 du_max > dmic->dmic_prm[di].duty_max) 213 continue; 214 215 /* Loop FIR decimation factors candidates. If the integer divided decimation factors 216 * and clock dividers as multiplied with sample rate match the IO clock rate the 217 * division was exact and such decimation mode is possible. Then check that CIC 218 * decimation constraints are met. The passed decimation modes are added to array. 219 */ 220 for (j = 0; fir_list[j]; j++) { 221 mfir = fir_list[j]->decim_factor; 222 223 /* Skip if previous decimation factor was the same */ 224 if (j > 1 && fir_list[j - 1]->decim_factor == mfir) 225 continue; 226 227 mcic = osr / mfir; 228 ioclk_test = fs * mfir * mcic * clkdiv; 229 230 if (ioclk_test == dmic->dmic_prm[di].io_clk && 231 mcic >= DMIC_HW_CIC_DECIM_MIN && 232 mcic <= DMIC_HW_CIC_DECIM_MAX && 233 i < DMIC_MAX_MODES) { 234 modes->clkdiv[i] = clkdiv; 235 modes->mcic[i] = mcic; 236 modes->mfir[i] = mfir; 237 i++; 238 } 239 } 240 } 241 242 modes->num_of_modes = i; 243} 244 245/* The previous raw modes list contains sane configuration possibilities. When there is request for 246 * both FIFOs A and B operation this function returns list of compatible settings. 247 */ 248static void match_modes(struct dmic_calc_matched_modes *c, struct dmic_calc_decim_modes *a, 249 struct dmic_calc_decim_modes *b) 250{ 251 int16_t idx[DMIC_MAX_MODES]; 252 int idx_length; 253 int i; 254 int n; 255 int m; 256 257 /* Check if previous search got results. */ 258 c->num_of_modes = 0; 259 if (a->num_of_modes == 0 && b->num_of_modes == 0) { 260 /* Nothing to do */ 261 return; 262 } 263 264 /* Ensure that num_of_modes is sane. */ 265 if (a->num_of_modes > DMIC_MAX_MODES || 266 b->num_of_modes > DMIC_MAX_MODES) 267 return; 268 269 /* Check for request only for FIFO A or B. In such case pass list for A or B as such. */ 270 if (b->num_of_modes == 0) { 271 c->num_of_modes = a->num_of_modes; 272 for (i = 0; i < a->num_of_modes; i++) { 273 c->clkdiv[i] = a->clkdiv[i]; 274 c->mcic[i] = a->mcic[i]; 275 c->mfir_a[i] = a->mfir[i]; 276 c->mfir_b[i] = 0; /* Mark FIR B as non-used */ 277 } 278 return; 279 } 280 281 if (a->num_of_modes == 0) { 282 c->num_of_modes = b->num_of_modes; 283 for (i = 0; i < b->num_of_modes; i++) { 284 c->clkdiv[i] = b->clkdiv[i]; 285 c->mcic[i] = b->mcic[i]; 286 c->mfir_b[i] = b->mfir[i]; 287 c->mfir_a[i] = 0; /* Mark FIR A as non-used */ 288 } 289 return; 290 } 291 292 /* Merge a list of compatible modes */ 293 i = 0; 294 for (n = 0; n < a->num_of_modes; n++) { 295 /* Find all indices of values a->clkdiv[n] in b->clkdiv[] */ 296 idx_length = find_equal_int16(idx, b->clkdiv, a->clkdiv[n], 297 b->num_of_modes, 0); 298 for (m = 0; m < idx_length; m++) { 299 if (b->mcic[idx[m]] == a->mcic[n]) { 300 c->clkdiv[i] = a->clkdiv[n]; 301 c->mcic[i] = a->mcic[n]; 302 c->mfir_a[i] = a->mfir[n]; 303 c->mfir_b[i] = b->mfir[idx[m]]; 304 i++; 305 } 306 } 307 c->num_of_modes = i; 308 } 309} 310 311/* Finds a suitable FIR decimation filter from the included set */ 312static struct pdm_decim *get_fir(struct intel_dmic_params *dmic, 313 struct dmic_calc_configuration *cfg, int mfir) 314{ 315 int i = 0; 316 int fs; 317 int cic_fs; 318 int fir_max_length; 319 struct pdm_decim *fir = NULL; 320 int di = dmic->dmic_dai_index; 321 322 if (mfir <= 0) 323 return fir; 324 325 cic_fs = dmic->dmic_prm[di].io_clk / cfg->clkdiv / cfg->mcic; 326 fs = cic_fs / mfir; 327 /* FIR max. length depends on available cycles and coef RAM length. Exceeding this length 328 * sets HW overrun status and overwrite of other register. 329 */ 330 fir_max_length = MIN(DMIC_HW_FIR_LENGTH_MAX, 331 (int)dmic->dmic_prm[di].io_clk / fs / 2 - 332 DMIC_FIR_PIPELINE_OVERHEAD); 333 334 /* Loop until NULL */ 335 while (fir_list[i]) { 336 if (fir_list[i]->decim_factor == mfir) { 337 if (fir_list[i]->length <= fir_max_length) { 338 /* Store pointer, break from loop to avoid a possible other mode 339 * with lower FIR length. 340 */ 341 fir = fir_list[i]; 342 break; 343 } 344 } 345 i++; 346 } 347 348 return fir; 349} 350 351/* Calculate scale and shift to use for FIR coefficients. Scale is applied before write to HW coef 352 * RAM. Shift will be programmed to HW register. 353 */ 354static int fir_coef_scale(int32_t *fir_scale, int *fir_shift, int add_shift, 355 const int32_t coef[], int coef_length, int32_t gain) 356{ 357 int32_t amax; 358 int32_t new_amax; 359 int32_t fir_gain; 360 int shift; 361 362 /* Multiply gain passed from CIC with output full scale. */ 363 fir_gain = Q_MULTSR_32X32((int64_t)gain, DMIC_HW_SENS_Q28, 364 DMIC_FIR_SCALE_Q, 28, DMIC_FIR_SCALE_Q); 365 366 /* Find the largest FIR coefficient value. */ 367 amax = find_max_abs_int32((int32_t *)coef, coef_length); 368 369 /* Scale max. tap value with FIR gain. */ 370 new_amax = Q_MULTSR_32X32((int64_t)amax, fir_gain, 31, 371 DMIC_FIR_SCALE_Q, DMIC_FIR_SCALE_Q); 372 if (new_amax <= 0) 373 return -EINVAL; 374 375 /* Get left shifts count to normalize the fractional value as 32 bit. We need right shifts 376 * count for scaling so need to invert. The difference of Q31 vs. used Q format is added to 377 * get the correct normalization right shift value. 378 */ 379 shift = 31 - DMIC_FIR_SCALE_Q - norm_int32(new_amax); 380 381 /* Add to shift for coef raw Q31 format shift and store to configuration. Ensure range (fail 382 * should not happen with OK coefficient set). 383 */ 384 *fir_shift = -shift + add_shift; 385 if (*fir_shift < DMIC_HW_FIR_SHIFT_MIN || 386 *fir_shift > DMIC_HW_FIR_SHIFT_MAX) 387 return -EINVAL; 388 389 /* Compensate shift into FIR coef scaler and store as Q4.20. */ 390 if (shift < 0) 391 *fir_scale = fir_gain << -shift; 392 else 393 *fir_scale = fir_gain >> shift; 394 395 return 0; 396} 397 398/* This function selects with a simple criteria one mode to set up the decimator. For the settings 399 * chosen for FIFOs A and B output a lookup is done for FIR coefficients from the included 400 * coefficients tables. For some decimation factors there may be several length coefficient sets. It 401 * is due to possible restruction of decimation engine cycles per given sample rate. If the 402 * coefficients length is exceeded the lookup continues. Therefore the list of coefficient set must 403 * present the filters for a decimation factor in decreasing length order. 404 * 405 * Note: If there is no filter available an error is returned. The parameters should be reviewed for 406 * such case. If still a filter is missing it should be added into the included set. FIR decimation 407 * with a high factor usually needs compromizes into specifications and is not desirable. 408 */ 409static int select_mode(struct intel_dmic_params *dmic, struct dmic_calc_configuration *cfg, 410 struct dmic_calc_matched_modes *modes) 411{ 412 int32_t g_cic; 413 int32_t fir_in_max; 414 int32_t cic_out_max; 415 int32_t gain_to_fir; 416 int16_t idx[DMIC_MAX_MODES]; 417 int16_t *mfir; 418 int mcic; 419 int bits_cic; 420 int ret; 421 int n; 422 int found = 0; 423 424 /* If there are more than one possibilities select a mode with a preferred FIR decimation 425 * factor. If there are several select mode with highest ioclk divider to minimize 426 * microphone power consumption. The highest clock divisors are in the end of list so select 427 * the last of list. The minimum OSR criteria used in previous ensures that quality in the 428 * candidates should be sufficient. 429 */ 430 if (modes->num_of_modes == 0) { 431 fprintf(stderr, "select_mode(): no modes available\n"); 432 return -EINVAL; 433 } 434 435 /* Valid modes presence is indicated with non-zero decimation factor in 1st element. If FIR 436 * A is not used get decimation factors from FIR B instead. 437 */ 438 if (modes->mfir_a[0] > 0) 439 mfir = modes->mfir_a; 440 else 441 mfir = modes->mfir_b; 442 443 /* Search fir_list[] decimation factors from start towards end. The found last configuration 444 * entry with searched decimation factor will be used. 445 */ 446 for (n = 0; fir_list[n]; n++) { 447 found = find_equal_int16(idx, mfir, fir_list[n]->decim_factor, 448 modes->num_of_modes, 0); 449 if (found) 450 break; 451 } 452 453 if (!found) { 454 fprintf(stderr, "select_mode(): No filter for decimation found\n"); 455 return -EINVAL; 456 } 457 n = idx[found - 1]; /* Option with highest clock divisor and lowest mic clock rate */ 458 459 /* Get microphone clock and decimation parameters for used mode from the list. */ 460 cfg->clkdiv = modes->clkdiv[n]; 461 cfg->mfir_a = modes->mfir_a[n]; 462 cfg->mfir_b = modes->mfir_b[n]; 463 cfg->mcic = modes->mcic[n]; 464 cfg->fir_a = NULL; 465 cfg->fir_b = NULL; 466 467 /* Find raw FIR coefficients to match the decimation factors of FIR A and B. */ 468 if (cfg->mfir_a > 0) { 469 cfg->fir_a = get_fir(dmic, cfg, cfg->mfir_a); 470 if (!cfg->fir_a) { 471 fprintf(stderr, "select_mode(): can't find FIR coefficients, mfir_a = %d\n", 472 cfg->mfir_a); 473 return -EINVAL; 474 } 475 } 476 477 if (cfg->mfir_b > 0) { 478 cfg->fir_b = get_fir(dmic, cfg, cfg->mfir_b); 479 if (!cfg->fir_b) { 480 fprintf(stderr, "select_mode(): can't find FIR coefficients, mfir_b = %d\n", 481 cfg->mfir_b); 482 return -EINVAL; 483 } 484 } 485 486 /* Calculate CIC shift from the decimation factor specific gain. The gain of HW decimator 487 * equals decimation factor to power of 5. 488 */ 489 mcic = cfg->mcic; 490 g_cic = mcic * mcic * mcic * mcic * mcic; 491 if (g_cic < 0) { 492 /* Erroneous decimation factor and CIC gain */ 493 fprintf(stderr, "select_mode(): erroneous decimation factor and CIC gain\n"); 494 return -EINVAL; 495 } 496 497 bits_cic = 32 - norm_int32(g_cic); 498 cfg->cic_shift = bits_cic - DMIC_HW_BITS_FIR_INPUT; 499 500 /* Calculate remaining gain to FIR in Q format used for gain values. */ 501 fir_in_max = INT_MAX(DMIC_HW_BITS_FIR_INPUT); 502 if (cfg->cic_shift >= 0) 503 cic_out_max = g_cic >> cfg->cic_shift; 504 else 505 cic_out_max = g_cic << -cfg->cic_shift; 506 507 gain_to_fir = (int32_t)((((int64_t)fir_in_max) << DMIC_FIR_SCALE_Q) / 508 cic_out_max); 509 510 /* Calculate FIR scale and shift */ 511 if (cfg->mfir_a > 0) { 512 cfg->fir_a_length = cfg->fir_a->length; 513 ret = fir_coef_scale(&cfg->fir_a_scale, &cfg->fir_a_shift, 514 cfg->fir_a->shift, cfg->fir_a->coef, 515 cfg->fir_a->length, gain_to_fir); 516 if (ret < 0) { 517 /* Invalid coefficient set found, should not happen. */ 518 fprintf(stderr, "select_mode(): invalid coefficient set found\n"); 519 return -EINVAL; 520 } 521 } else { 522 cfg->fir_a_scale = 0; 523 cfg->fir_a_shift = 0; 524 cfg->fir_a_length = 0; 525 } 526 527 if (cfg->mfir_b > 0) { 528 cfg->fir_b_length = cfg->fir_b->length; 529 ret = fir_coef_scale(&cfg->fir_b_scale, &cfg->fir_b_shift, 530 cfg->fir_b->shift, cfg->fir_b->coef, 531 cfg->fir_b->length, gain_to_fir); 532 if (ret < 0) { 533 /* Invalid coefficient set found, should not happen. */ 534 fprintf(stderr, "select_mode(): invalid coefficient set found\n"); 535 return -EINVAL; 536 } 537 } else { 538 cfg->fir_b_scale = 0; 539 cfg->fir_b_shift = 0; 540 cfg->fir_b_length = 0; 541 } 542 543 return 0; 544} 545 546/* The FIFO input packer mode (IPM) settings are somewhat different in HW versions. This helper 547 * function returns a suitable IPM bit field value to use. 548 */ 549static void ipm_helper1(struct intel_dmic_params *dmic, int *ipm) 550{ 551 int di = dmic->dmic_dai_index; 552 int pdm[DMIC_HW_CONTROLLERS]; 553 int i; 554 555 /* Loop number of PDM controllers in the configuration. If mic A or B is enabled then a pdm 556 * controller is marked as active for this DAI. 557 */ 558 for (i = 0; i < DMIC_HW_CONTROLLERS; i++) { 559 if (dmic->dmic_prm[di].pdm[i].enable_mic_a || 560 dmic->dmic_prm[di].pdm[i].enable_mic_b) 561 pdm[i] = 1; 562 else 563 pdm[i] = 0; 564 } 565 566 /* Set IPM to match active pdm controllers. */ 567 *ipm = 0; 568 569 if (pdm[0] == 0 && pdm[1] > 0) 570 *ipm = 1; 571 572 if (pdm[0] > 0 && pdm[1] > 0) 573 *ipm = 2; 574} 575 576static void ipm_helper2(struct intel_dmic_params *dmic, int source[], int *ipm) 577{ 578 int di = dmic->dmic_dai_index; 579 int pdm[DMIC_HW_CONTROLLERS]; 580 int i; 581 int n = 0; 582 583 for (i = 0; i < OUTCONTROLX_IPM_NUMSOURCES; i++) 584 source[i] = 0; 585 586 /* Loop number of PDM controllers in the configuration. If mic A or B is enabled then a pdm 587 * controller is marked as active. The function returns in array source[] the indice of 588 * enabled pdm controllers to be used for IPM configuration. 589 */ 590 for (i = 0; i < DMIC_HW_CONTROLLERS; i++) { 591 if (dmic->dmic_prm[di].pdm[i].enable_mic_a || 592 dmic->dmic_prm[di].pdm[i].enable_mic_b) { 593 pdm[i] = 1; 594 source[n] = i; 595 n++; 596 } else { 597 pdm[i] = 0; 598 } 599 } 600 601 /* IPM bit field is set to count of active pdm controllers. */ 602 *ipm = pdm[0]; 603 for (i = 1; i < DMIC_HW_CONTROLLERS; i++) 604 *ipm += pdm[i]; 605} 606 607/* Loop number of PDM controllers in the configuration. The function checks if the controller should 608 * operate as stereo or mono left (A) or mono right (B) mode. Mono right mode is setup as channel 609 * swapped mono left. 610 */ 611static int stereo_helper(struct intel_dmic_params *dmic, int stereo[], int swap[]) 612{ 613 int cnt; 614 int i; 615 int swap_check; 616 int ret = 0; 617 618 for (i = 0; i < DMIC_HW_CONTROLLERS; i++) { 619 cnt = 0; 620 if (dmic->dmic_prm[0].pdm[i].enable_mic_a || 621 dmic->dmic_prm[1].pdm[i].enable_mic_a) 622 cnt++; 623 624 if (dmic->dmic_prm[0].pdm[i].enable_mic_b || 625 dmic->dmic_prm[1].pdm[i].enable_mic_b) 626 cnt++; 627 628 /* Set stereo mode if both mic A anc B are enabled. */ 629 cnt >>= 1; 630 stereo[i] = cnt; 631 632 /* Swap channels if only mic B is used for mono processing. */ 633 swap[i] = (dmic->dmic_prm[0].pdm[i].enable_mic_b || 634 dmic->dmic_prm[1].pdm[i].enable_mic_b) && !cnt; 635 636 /* Check that swap does not conflict with other DAI request */ 637 swap_check = (dmic->dmic_prm[1].pdm[i].enable_mic_a || 638 dmic->dmic_prm[0].pdm[i].enable_mic_a); 639 640 if (swap_check && swap[i]) { 641 ret = -EINVAL; 642 break; 643 } 644 } 645 return ret; 646} 647 648static int configure_registers(struct intel_dmic_params *dmic, struct dmic_calc_configuration *cfg) 649{ 650 int stereo[DMIC_HW_CONTROLLERS]; 651 int swap[DMIC_HW_CONTROLLERS]; 652 uint32_t val = 0; 653 int32_t ci; 654 uint32_t cu; 655 int ipm; 656 int of0; 657 int of1; 658 int fir_decim; 659 int fir_length; 660 int length; 661 int edge; 662 int soft_reset; 663 int cic_mute; 664 int fir_mute; 665 unsigned int i; 666 int j; 667 int ret; 668 int mic; 669 int chmap_bits; 670 int di = dmic->dmic_dai_index; 671 int dccomp = 1; 672 int array_a = 0; 673 int array_b = 0; 674 int bfth = 3; /* Should be 3 for 8 entries, 1 is 2 entries */ 675 int th = 3; /* Used with TIE=1 */ 676 int source[OUTCONTROLX_IPM_NUMSOURCES]; 677 678 /* 679 * ts_group value describes which audio channels in the hw fifo are enabled. A 32 bit 680 * value is divided into 8 x 4 bit nibbles corresponding to 8 audio channels. Hex value 0xF 681 * means "not in use", any other value means the channel is enabled. For example 0xFFFFFFFF 682 * means no channels are enabled, 0xFFFFFF10 means channels 1 and 2 are enabled. 683 * 684 * ts_group array index corresponds to dmic hw fifos, that gather audio samples from pdm 685 * controllers. 1 pdm controller can host 2 mono dmics and usually pdm controllers are 686 * connected to 2 hw fifos -> we can for example run the dmics simultaneously with different 687 * sampling rates. 688 * 689 * Currently there is no evidence we would ever have more than 2 hw fifos, so ts_group[2] 690 * and ts_group[3] are not used for anything. Also the nibbles could be used for channel 691 * mapping the pdm channels arbitrarely into hw fifos, however currently it is used as 692 * binary not_enabled/enabled setting. 693 * 694 * if we have 2 dmics (stereo) it means we are using 1 pdm controller with possibly 2 hw 695 * fifos: 696 * mic1 fifo0(2ch) 697 * \ / 698 * pdm0 699 * / \ 700 * mic2 fifo1(2ch) 701 * 702 * So in this case it makes only sense to control ts_group indexes 0 and 1 and their last 2 703 * nibbles (as we have only 2 channels). 704 * 705 * if we have 4 dmics, it means we are using 2 pdm controller with possibly 2 x 4 channel hw 706 * fifos: 707 * 708 * mic1 fifo0(4ch) 709 * \ / / 710 * pdm0 / 711 * / \ / 712 * mic2 \/ 713 * mic3 /\ 714 * \ / \ 715 * pdm1 \ 716 * / \ \ 717 * mic4 fifo1(4ch) 718 * 719 * So it makes sense to control ts_group indexes 0 and 1 and their last 4 nibbles. 720 * 721 * channel_pdm_mask defines which existing pdm controllers will be taken into use. So if 722 * either of mic a or b is enabled -> that particular pdm controller is in use. For example 723 * pdm0 in use/not_in_use is defined by setting bit 0 in channel_pdm_mask to 1/0. 724 * 725 * channel_ctrl_mask defines what mic channels are available in hw for a pdm controller. in 726 * theory pdm controller could have only 1 channel enabled, in practice there's always 2 727 * channels which are both enabled -> set bits 0 and 1. 728 */ 729 730 for (i = 0, mic = 0, chmap_bits = 4; i < DMIC_HW_CONTROLLERS; i++) { 731 /* enable fifo channels (ts_group) based on mic_enable in dai definition */ 732 if (dmic->dmic_prm[di].pdm[i].enable_mic_a) { 733 dmic->dmic_blob.ts_group[di] &= ~(0xF << (chmap_bits * mic)); 734 dmic->dmic_blob.ts_group[di] |= 0x0 << (chmap_bits * mic); 735 } 736 mic++; 737 if (dmic->dmic_prm[di].pdm[i].enable_mic_b) { 738 dmic->dmic_blob.ts_group[di] &= ~(0xF << (chmap_bits * mic)); 739 dmic->dmic_blob.ts_group[di] |= 0x1 << (chmap_bits * mic); 740 } 741 mic++; 742 } 743 744 /* set channel_pdm_mask to describe what pdm controllers are in use */ 745 for (i = 0; i < dmic->dmic_prm[di].num_pdm_active; i++) 746 dmic->dmic_blob.channel_pdm_mask |= 1 << i; 747 748 /* set always both mic channels enabled */ 749 dmic->dmic_blob.channel_ctrl_mask = 0x3; 750 751 /* Normal start sequence */ 752 soft_reset = 0; 753 cic_mute = 0; 754 fir_mute = 0; 755 756 /* OUTCONTROL0 and OUTCONTROL1 */ 757 of0 = (dmic->dmic_prm[0].fifo_bits == 32) ? 2 : 0; 758 of1 = (dmic->dmic_prm[1].fifo_bits == 32) ? 2 : 0; 759 760 if (dmic->dmic_prm[di].driver_version == 1) { 761 if (di == 0) { 762 ipm_helper1(dmic, &ipm); 763 val = OUTCONTROL0_TIE(0) | 764 OUTCONTROL0_SIP(0) | 765 OUTCONTROL0_FINIT(0) | 766 OUTCONTROL0_FCI(0) | 767 OUTCONTROL0_BFTH(bfth) | 768 OUTCONTROL0_OF(of0) | 769 OUTCONTROL0_IPM_VER1(ipm) | 770 OUTCONTROL0_TH(th); 771 } else { 772 ipm_helper1(dmic, &ipm); 773 val = OUTCONTROL1_TIE(0) | 774 OUTCONTROL1_SIP(0) | 775 OUTCONTROL1_FINIT(0) | 776 OUTCONTROL1_FCI(0) | 777 OUTCONTROL1_BFTH(bfth) | 778 OUTCONTROL1_OF(of1) | 779 OUTCONTROL1_IPM_VER1(ipm) | 780 OUTCONTROL1_TH(th); 781 } 782 } 783 784 if (dmic->dmic_prm[di].driver_version == 2 || dmic->dmic_prm[di].driver_version == 3) { 785 if (di == 0) { 786 ipm_helper2(dmic, source, &ipm); 787 val = OUTCONTROL0_TIE(0) | 788 OUTCONTROL0_SIP(0) | 789 OUTCONTROL0_FINIT(0) | 790 OUTCONTROL0_FCI(0) | 791 OUTCONTROL0_BFTH(bfth) | 792 OUTCONTROL0_OF(of0) | 793 OUTCONTROL0_IPM_VER2(ipm) | 794 OUTCONTROL0_IPM_SOURCE_1(source[0]) | 795 OUTCONTROL0_IPM_SOURCE_2(source[1]) | 796 OUTCONTROL0_IPM_SOURCE_3(source[2]) | 797 OUTCONTROL0_IPM_SOURCE_4(source[3]) | 798 OUTCONTROL0_IPM_SOURCE_MODE(1) | 799 OUTCONTROL0_TH(th); 800 } else { 801 ipm_helper2(dmic, source, &ipm); 802 val = OUTCONTROL1_TIE(0) | 803 OUTCONTROL1_SIP(0) | 804 OUTCONTROL1_FINIT(0) | 805 OUTCONTROL1_FCI(0) | 806 OUTCONTROL1_BFTH(bfth) | 807 OUTCONTROL1_OF(of1) | 808 OUTCONTROL1_IPM_VER2(ipm) | 809 OUTCONTROL1_IPM_SOURCE_1(source[0]) | 810 OUTCONTROL1_IPM_SOURCE_2(source[1]) | 811 OUTCONTROL1_IPM_SOURCE_3(source[2]) | 812 OUTCONTROL1_IPM_SOURCE_4(source[3]) | 813 OUTCONTROL1_IPM_SOURCE_MODE(1) | 814 OUTCONTROL1_TH(th); 815 } 816 } 817 818 dmic->dmic_blob.chan_ctrl_cfg[di] = val; 819 820 ret = stereo_helper(dmic, stereo, swap); 821 if (ret < 0) { 822 fprintf(stderr, "configure_registers(): enable conflict\n"); 823 return ret; 824 } 825 826 for (i = 0; i < DMIC_HW_CONTROLLERS; i++) { 827 /* CIC */ 828 val = CIC_CONTROL_SOFT_RESET(soft_reset) | 829 CIC_CONTROL_CIC_START_B(1) | 830 CIC_CONTROL_CIC_START_A(1) | 831 CIC_CONTROL_MIC_B_POLARITY(dmic->dmic_prm[di].pdm[i].polarity_mic_b) | 832 CIC_CONTROL_MIC_A_POLARITY(dmic->dmic_prm[di].pdm[i].polarity_mic_a) | 833 CIC_CONTROL_MIC_MUTE(cic_mute); 834 835 if (dmic->dmic_prm[di].driver_version == 1) 836 val |= CIC_CONTROL_STEREO_MODE(stereo[i]); 837 838 dmic->dmic_blob_pdm[i].cic_control = val; 839 840 val = CIC_CONFIG_CIC_SHIFT(cfg->cic_shift + 8) | 841 CIC_CONFIG_COMB_COUNT(cfg->mcic - 1); 842 dmic->dmic_blob_pdm[i].cic_config = val; 843 844 /* Mono right channel mic usage requires swap of PDM channels 845 * since the mono decimation is done with only left channel 846 * processing active. 847 */ 848 edge = dmic->dmic_prm[di].pdm[i].clk_edge; 849 if (swap[i]) 850 edge = !edge; 851 852 val = MIC_CONTROL_PDM_CLKDIV(cfg->clkdiv - 2) | 853 MIC_CONTROL_PDM_SKEW(dmic->dmic_prm[di].pdm[i].skew) | 854 MIC_CONTROL_CLK_EDGE(edge) | 855 MIC_CONTROL_PDM_EN_B(1) | 856 MIC_CONTROL_PDM_EN_A(1); 857 dmic->dmic_blob_pdm[i].mic_control = val; 858 859 /* 860 * Here we have to check the both FIRs if they are 861 * configured as the later configured DAI may have changed 862 * the configuration of the DAI configured earlier. 863 */ 864 if (cfg->mfir_a) { 865 /* FIR A */ 866 fir_decim = MAX(cfg->mfir_a - 1, 0); 867 fir_length = MAX(cfg->fir_a_length - 1, 0); 868 val = FIR_CONTROL_A_START(1) | 869 FIR_CONTROL_A_ARRAY_START_EN(array_a) | 870 FIR_CONTROL_A_DCCOMP(dccomp) | 871 FIR_CONTROL_A_MUTE(fir_mute) | 872 FIR_CONTROL_A_STEREO(stereo[i]); 873 dmic->dmic_blob_fir[i][0].fir_control = val; 874 875 val = FIR_CONFIG_A_FIR_DECIMATION(fir_decim) | 876 FIR_CONFIG_A_FIR_SHIFT(cfg->fir_a_shift) | 877 FIR_CONFIG_A_FIR_LENGTH(fir_length); 878 dmic->dmic_blob_fir[i][0].fir_config = val; 879 880 val = DC_OFFSET_LEFT_A_DC_OFFS(DCCOMP_TC0); 881 dmic->dmic_blob_fir[i][0].dc_offset_left = val; 882 883 val = DC_OFFSET_RIGHT_A_DC_OFFS(DCCOMP_TC0); 884 dmic->dmic_blob_fir[i][0].dc_offset_right = val; 885 886 val = OUT_GAIN_LEFT_A_GAIN(0); 887 dmic->dmic_blob_fir[i][0].out_gain_left = val; 888 889 val = OUT_GAIN_RIGHT_A_GAIN(0); 890 dmic->dmic_blob_fir[i][0].out_gain_right = val; 891 892 /* Write coef RAM A with scaled coefficient in reverse order */ 893 length = cfg->fir_a_length; 894 for (j = 0; j < length; j++) { 895 ci = (int32_t)Q_MULTSR_32X32((int64_t)cfg->fir_a->coef[j], 896 cfg->fir_a_scale, 31, 897 DMIC_FIR_SCALE_Q, DMIC_HW_FIR_COEF_Q); 898 cu = FIR_COEF_A(ci); 899 /* blob_pdm[i].fir_coeffs[0][j] = cu; */ 900 dmic->dmic_fir_array.fir_coeffs[i][0][j] = cu; 901 } 902 dmic->dmic_fir_array.fir_len[0] = length; 903 } else { 904 dmic->dmic_fir_array.fir_len[0] = 0; 905 } 906 907 if (cfg->mfir_b) { 908 /* FIR B */ 909 fir_decim = MAX(cfg->mfir_b - 1, 0); 910 fir_length = MAX(cfg->fir_b_length - 1, 0); 911 val = FIR_CONTROL_B_START(1) | 912 FIR_CONTROL_B_ARRAY_START_EN(array_b) | 913 FIR_CONTROL_B_DCCOMP(dccomp) | 914 FIR_CONTROL_B_MUTE(fir_mute) | 915 FIR_CONTROL_B_STEREO(stereo[i]); 916 dmic->dmic_blob_fir[i][1].fir_control = val; 917 918 val = FIR_CONFIG_B_FIR_DECIMATION(fir_decim) | 919 FIR_CONFIG_B_FIR_SHIFT(cfg->fir_b_shift) | 920 FIR_CONFIG_B_FIR_LENGTH(fir_length); 921 dmic->dmic_blob_fir[i][1].fir_config = val; 922 val = DC_OFFSET_LEFT_B_DC_OFFS(DCCOMP_TC0); 923 dmic->dmic_blob_fir[i][1].dc_offset_left = val; 924 925 val = DC_OFFSET_RIGHT_B_DC_OFFS(DCCOMP_TC0); 926 dmic->dmic_blob_fir[i][1].dc_offset_right = val; 927 928 val = OUT_GAIN_LEFT_B_GAIN(0); 929 dmic->dmic_blob_fir[i][1].out_gain_left = val; 930 931 val = OUT_GAIN_RIGHT_B_GAIN(0); 932 dmic->dmic_blob_fir[i][1].out_gain_right = val; 933 934 /* Write coef RAM B with scaled coefficient in reverse order */ 935 length = cfg->fir_b_length; 936 for (j = 0; j < length; j++) { 937 ci = (int32_t)Q_MULTSR_32X32((int64_t)cfg->fir_b->coef[j], 938 cfg->fir_b_scale, 31, 939 DMIC_FIR_SCALE_Q, DMIC_HW_FIR_COEF_Q); 940 cu = FIR_COEF_B(ci); 941 /* blob_pdm[i].fir_coeffs[1][j] = cu; */ 942 dmic->dmic_fir_array.fir_coeffs[i][1][j] = cu; 943 } 944 dmic->dmic_fir_array.fir_len[1] = length; 945 } else { 946 dmic->dmic_fir_array.fir_len[1] = 0; 947 } 948 } 949 950 return 0; 951} 952 953/* The decimation for PDM (pulse density modulation) stream is done in a programmable HW filter 954 * engine. The input to configuration algorithm is needed sample rate, channels/enabled microphones, 955 * microphone clock range, microphone clock duty cycle range, and system clock rate. 956 * 957 * The PDM bus clock divider, CIC and FIR decimation ratios are searched and configuration for 958 * optimal power consumption, filtering requirements, and HW constraints is chosen. The FIR filter 959 * for the chosen decimation is looked up from table and scaled to match the other decimation path 960 * sensitivity. 961 */ 962int dmic_calculate(struct intel_nhlt_params *nhlt) 963{ 964 struct intel_dmic_params *dmic = (struct intel_dmic_params *)nhlt->dmic_params; 965 struct dmic_calc_matched_modes modes_ab; 966 struct dmic_calc_decim_modes modes_a; 967 struct dmic_calc_decim_modes modes_b; 968 struct dmic_calc_configuration cfg; 969 int ret = 0; 970 int di; 971 972 if (!dmic) 973 return -EINVAL; 974 975 di = dmic->dmic_dai_index; 976 977 if (di >= DMIC_HW_FIFOS) { 978 fprintf(stderr, "dmic_set_config(): dai->index exceeds number of FIFOs\n"); 979 ret = -EINVAL; 980 goto out; 981 } 982 983 if (dmic->dmic_prm[di].num_pdm_active > DMIC_HW_CONTROLLERS) { 984 fprintf(stderr, "dmic_set_config():controller count exceeds platform capability\n"); 985 ret = -EINVAL; 986 goto out; 987 } 988 989 /* fifo bits 0 means fifo disabled */ 990 switch (dmic->dmic_prm[di].fifo_bits) { 991 case 0: 992 case 16: 993 case 32: 994 break; 995 default: 996 fprintf(stderr, "dmic_set_config(): fifo_bits EINVAL\n"); 997 ret = -EINVAL; 998 goto out; 999 } 1000 1001 /* Match and select optimal decimators configuration for FIFOs A and B paths. This setup 1002 * phase is still abstract. Successful completion points struct cfg to FIR coefficients and 1003 * contains the scale value to use for FIR coefficient RAM write as well as the CIC and FIR 1004 * shift values. 1005 */ 1006 find_modes(dmic, &modes_a, dmic->dmic_prm[0].fifo_fs); 1007 if (modes_a.num_of_modes == 0 && dmic->dmic_prm[0].fifo_fs > 0) { 1008 fprintf(stderr, "dmic_set_config(): No modes found for FIFO A\n"); 1009 ret = -EINVAL; 1010 goto out; 1011 } 1012 1013 find_modes(dmic, &modes_b, dmic->dmic_prm[1].fifo_fs); 1014 if (modes_b.num_of_modes == 0 && dmic->dmic_prm[1].fifo_fs > 0) { 1015 fprintf(stderr, "dmic_set_config(): No modes found for FIFO B\n"); 1016 ret = -EINVAL; 1017 goto out; 1018 } 1019 1020 match_modes(&modes_ab, &modes_a, &modes_b); 1021 ret = select_mode(dmic, &cfg, &modes_ab); 1022 if (ret < 0) { 1023 fprintf(stderr, "dmic_set_config(): select_mode() failed\n"); 1024 ret = -EINVAL; 1025 goto out; 1026 } 1027 1028 /* Struct reg contains a mirror of actual HW registers. Determine register bits 1029 * configuration from decimator configuration and the requested parameters. 1030 */ 1031 ret = configure_registers(dmic, &cfg); 1032 if (ret < 0) { 1033 fprintf(stderr, "dmic_set_config(): cannot configure registers\n"); 1034 ret = -EINVAL; 1035 goto out; 1036 } 1037 1038 dmic_print_internal(dmic); 1039 1040 dmic->dmic_count++; 1041 1042out: 1043 return ret; 1044} 1045 1046int dmic_get_params(struct intel_nhlt_params *nhlt, int index, uint32_t *sample_rate, 1047 uint16_t *channel_count, uint32_t *bits_per_sample, uint8_t *array_type, 1048 uint8_t *num_mics, uint8_t *extension, uint32_t *snr, uint32_t *sensitivity) 1049{ 1050 struct intel_dmic_params *dmic = (struct intel_dmic_params *)nhlt->dmic_params; 1051 uint32_t channels = 0; 1052 1053 if (!dmic) 1054 return -EINVAL; 1055 1056 /* check all pdm's for enabled mics */ 1057 *channel_count = 0; 1058 if (dmic->dmic_prm[index].pdm[0].enable_mic_a) 1059 channels++; 1060 1061 if (dmic->dmic_prm[index].pdm[0].enable_mic_b) 1062 channels++; 1063 1064 if (dmic->dmic_prm[index].pdm[1].enable_mic_a) 1065 channels++; 1066 1067 if (dmic->dmic_prm[index].pdm[1].enable_mic_b) 1068 channels++; 1069 1070 *sample_rate = dmic->dmic_prm[index].fifo_fs; 1071 *channel_count = channels; 1072 *bits_per_sample = dmic->dmic_prm[index].fifo_bits; 1073 *num_mics = dmic->dmic_mic_config.num_mics; 1074 *extension = dmic->dmic_mic_config.extension; 1075 *array_type = dmic->dmic_mic_config.array_type; 1076 *snr = dmic->dmic_mic_config.snr; 1077 *sensitivity = dmic->dmic_mic_config.sensitivity; 1078 1079 return 0; 1080} 1081 1082int dmic_get_mic_params(struct intel_nhlt_params *nhlt, int index, 1083 uint8_t *type, uint8_t *panel, uint32_t *speaker_position_distance, 1084 uint32_t *horizontal_offset, uint32_t *vertical_offset, 1085 uint8_t *frequency_low_band, uint8_t *frequency_high_band, 1086 uint16_t *direction_angle, uint16_t *elevation_angle, 1087 uint16_t *vertical_angle_begin, uint16_t *vertical_angle_end, 1088 uint16_t *horizontal_angle_begin, uint16_t *horizontal_angle_end) 1089{ 1090 struct intel_dmic_params *dmic = (struct intel_dmic_params *)nhlt->dmic_params; 1091 1092 if (!dmic) 1093 return -EINVAL; 1094 1095 *type = dmic->dmic_mic_config.vendor[index].type; 1096 *panel = dmic->dmic_mic_config.vendor[index].panel; 1097 *speaker_position_distance = dmic->dmic_mic_config.vendor[index].speaker_position_distance; 1098 *horizontal_offset = dmic->dmic_mic_config.vendor[index].horizontal_offset; 1099 *vertical_offset = dmic->dmic_mic_config.vendor[index].vertical_offset; 1100 *frequency_low_band = dmic->dmic_mic_config.vendor[index].frequency_low_band; 1101 *frequency_high_band = dmic->dmic_mic_config.vendor[index].frequency_high_band; 1102 *direction_angle = dmic->dmic_mic_config.vendor[index].direction_angle; 1103 *elevation_angle = dmic->dmic_mic_config.vendor[index].elevation_angle; 1104 *vertical_angle_begin = dmic->dmic_mic_config.vendor[index].vertical_angle_begin; 1105 *vertical_angle_end = dmic->dmic_mic_config.vendor[index].vertical_angle_end; 1106 *horizontal_angle_begin = dmic->dmic_mic_config.vendor[index].horizontal_angle_begin; 1107 *horizontal_angle_end = dmic->dmic_mic_config.vendor[index].horizontal_angle_end; 1108 1109 return 0; 1110} 1111 1112int dmic_get_vendor_blob_size(struct intel_nhlt_params *nhlt, size_t *size) 1113{ 1114 struct intel_dmic_params *dmic = (struct intel_dmic_params *)nhlt->dmic_params; 1115 int i, fir_index_0, fir_index_1; 1116 1117 if (!dmic || !dmic->dmic_count) 1118 return -EINVAL; 1119 1120 *size = sizeof(struct dmic_intel_config_data); 1121 1122 /* if either of the fir is 0 length, copy the existing fir twice */ 1123 fir_index_0 = 0; 1124 fir_index_1 = 1; 1125 if (dmic->dmic_fir_array.fir_len[0] == 0) { 1126 fir_index_0 = 1; 1127 fir_index_1 = 1; 1128 } 1129 if (dmic->dmic_fir_array.fir_len[1] == 0) { 1130 fir_index_0 = 0; 1131 fir_index_1 = 0; 1132 } 1133 1134 /* variable amount of pdm's */ 1135 for (i = 0; i < DMIC_HW_CONTROLLERS; i++) { 1136 /* only copy the pdm data if it is enabled */ 1137 if ((dmic->dmic_blob.channel_pdm_mask & BIT(i)) == 0) 1138 continue; 1139 1140 *size += sizeof(struct dmic_intel_pdm_ctrl_cfg); 1141 *size += sizeof(struct dmic_intel_fir_config) * DMIC_HW_FIFOS; 1142 1143 *size += dmic->dmic_fir_array.fir_len[fir_index_0] * sizeof(uint32_t); 1144 *size += dmic->dmic_fir_array.fir_len[fir_index_1] * sizeof(uint32_t); 1145 } 1146 1147 return 0; 1148} 1149 1150int dmic_get_vendor_blob_count(struct intel_nhlt_params *nhlt) 1151{ 1152 struct intel_dmic_params *dmic = (struct intel_dmic_params *)nhlt->dmic_params; 1153 1154 if (!dmic || !dmic->dmic_count) 1155 return 0; 1156 1157 return dmic->dmic_count; 1158} 1159 1160int dmic_get_vendor_blob(struct intel_nhlt_params *nhlt, uint8_t *vendor_blob) 1161{ 1162 struct intel_dmic_params *dmic = (struct intel_dmic_params *)nhlt->dmic_params; 1163 int i, fir_index_0, fir_index_1; 1164 uint8_t *orig_blob = vendor_blob; 1165 size_t blob_size; 1166 1167 if (!dmic || !dmic->dmic_count) 1168 return -EINVAL; 1169 1170 /* top level struct */ 1171 memcpy(vendor_blob, &dmic->dmic_blob, sizeof(struct dmic_intel_config_data)); 1172 vendor_blob += sizeof(struct dmic_intel_config_data); 1173 1174 /* if either of the fir is 0 length, copy the existing fir twice */ 1175 fir_index_0 = 0; 1176 fir_index_1 = 1; 1177 if (dmic->dmic_fir_array.fir_len[0] == 0) { 1178 fir_index_0 = 1; 1179 fir_index_1 = 1; 1180 } 1181 if (dmic->dmic_fir_array.fir_len[1] == 0) { 1182 fir_index_0 = 0; 1183 fir_index_1 = 0; 1184 } 1185 1186 /* variable amount of pdm's */ 1187 for (i = 0; i < DMIC_HW_CONTROLLERS; i++) { 1188 /* only copy the pdm data if it is enabled */ 1189 if ((dmic->dmic_blob.channel_pdm_mask & BIT(i)) == 0) 1190 continue; 1191 1192 /* top level struct first pdm data */ 1193 memcpy(vendor_blob, (uint8_t *)&dmic->dmic_blob_pdm[i], 1194 sizeof(struct dmic_intel_pdm_ctrl_cfg)); 1195 vendor_blob += sizeof(struct dmic_intel_pdm_ctrl_cfg); 1196 1197 /* top level struct first pdm data first fir */ 1198 memcpy(vendor_blob, (uint8_t *)&dmic->dmic_blob_fir[i][fir_index_0], 1199 sizeof(struct dmic_intel_fir_config)); 1200 vendor_blob += sizeof(struct dmic_intel_fir_config); 1201 1202 /* top level struct first pdm data second fir */ 1203 memcpy(vendor_blob, (uint8_t *)&dmic->dmic_blob_fir[i][fir_index_1], 1204 sizeof(struct dmic_intel_fir_config)); 1205 vendor_blob += sizeof(struct dmic_intel_fir_config); 1206 1207 /* fir coeffs a */ 1208 memcpy(vendor_blob, (uint8_t *)&dmic->dmic_fir_array.fir_coeffs[i][fir_index_0][0], 1209 dmic->dmic_fir_array.fir_len[fir_index_0] * sizeof(uint32_t)); 1210 vendor_blob += dmic->dmic_fir_array.fir_len[fir_index_0] * sizeof(uint32_t); 1211 1212 /* fir coeffs b */ 1213 memcpy(vendor_blob, (uint8_t *)&dmic->dmic_fir_array.fir_coeffs[i][fir_index_1][0], 1214 dmic->dmic_fir_array.fir_len[fir_index_1] * sizeof(uint32_t)); 1215 vendor_blob += dmic->dmic_fir_array.fir_len[fir_index_1] * sizeof(uint32_t); 1216 } 1217 1218 dmic_get_vendor_blob_size(nhlt, &blob_size); 1219 dmic_print_bytes_as_hex((uint8_t *)orig_blob, blob_size); 1220 dmic_print_integers_as_hex((uint32_t *)orig_blob, blob_size / 4); 1221 1222 return 0; 1223} 1224 1225int dmic_set_params(struct intel_nhlt_params *nhlt, int dai_index, int driver_version, 1226 int io_clk, int num_pdm_active, int fifo_word_length, int clk_min, int clk_max, 1227 int duty_min, int duty_max, int sample_rate, int unmute_ramp_time) 1228{ 1229 struct intel_dmic_params *dmic = (struct intel_dmic_params *)nhlt->dmic_params; 1230 1231 if (!dmic) 1232 return -EINVAL; 1233 1234 if (dai_index >= DMIC_HW_FIFOS) { 1235 fprintf(stderr, "set_dmic_data illegal dai index\n"); 1236 return -EINVAL; 1237 } 1238 1239 dmic->dmic_dai_index = dai_index; 1240 dmic->dmic_prm[dai_index].driver_version = driver_version; 1241 dmic->dmic_prm[dai_index].io_clk = io_clk; 1242 dmic->dmic_prm[dai_index].num_pdm_active = num_pdm_active; 1243 dmic->dmic_prm[dai_index].fifo_bits = fifo_word_length; 1244 dmic->dmic_prm[dai_index].pdmclk_min = clk_min; 1245 dmic->dmic_prm[dai_index].pdmclk_max = clk_max; 1246 dmic->dmic_prm[dai_index].duty_min = duty_min; 1247 dmic->dmic_prm[dai_index].duty_max = duty_max; 1248 dmic->dmic_prm[dai_index].fifo_fs = sample_rate; 1249 dmic->dmic_prm[dai_index].unmute_ramp_time = unmute_ramp_time; 1250 1251 return 0; 1252} 1253 1254int dmic_set_pdm_params(struct intel_nhlt_params *nhlt, int pdm_index, int enable_a, 1255 int enable_b, int polarity_a, int polarity_b, int clk_edge, int skew) 1256{ 1257 struct intel_dmic_params *dmic = (struct intel_dmic_params *)nhlt->dmic_params; 1258 int di; 1259 1260 if (!dmic) 1261 return -EINVAL; 1262 1263 if (pdm_index >= DMIC_HW_CONTROLLERS) { 1264 fprintf(stderr, "set_pdm_data illegal pdm_index\n"); 1265 return -EINVAL; 1266 } 1267 1268 di = dmic->dmic_dai_index; 1269 1270 dmic->dmic_prm[di].pdm[pdm_index].enable_mic_a = enable_a; 1271 dmic->dmic_prm[di].pdm[pdm_index].enable_mic_b = enable_b; 1272 dmic->dmic_prm[di].pdm[pdm_index].polarity_mic_a = polarity_a; 1273 dmic->dmic_prm[di].pdm[pdm_index].polarity_mic_b = polarity_b; 1274 dmic->dmic_prm[di].pdm[pdm_index].clk_edge = clk_edge; 1275 dmic->dmic_prm[di].pdm[pdm_index].skew = skew; 1276 1277 return 0; 1278} 1279 1280int dmic_set_ext_params(struct intel_nhlt_params *nhlt, uint32_t snr, uint32_t sensitivity) 1281{ 1282 struct intel_dmic_params *dmic = (struct intel_dmic_params *)nhlt->dmic_params; 1283 1284 if (!dmic) 1285 return -EINVAL; 1286 1287 dmic->dmic_mic_config.extension = 1; 1288 dmic->dmic_mic_config.snr = snr; 1289 dmic->dmic_mic_config.sensitivity = sensitivity; 1290 1291 return 0; 1292} 1293 1294int dmic_set_mic_params(struct intel_nhlt_params *nhlt, int index, 1295 uint8_t type, uint8_t panel, uint32_t speaker_position_distance, 1296 uint32_t horizontal_offset, uint32_t vertical_offset, 1297 uint8_t frequency_low_band, uint8_t frequency_high_band, 1298 uint16_t direction_angle, uint16_t elevation_angle, 1299 uint16_t vertical_angle_begin, uint16_t vertical_angle_end, 1300 uint16_t horizontal_angle_begin, uint16_t horizontal_angle_end) 1301{ 1302 struct intel_dmic_params *dmic = (struct intel_dmic_params *)nhlt->dmic_params; 1303 1304 if (!dmic) 1305 return -EINVAL; 1306 1307 dmic->dmic_mic_config.vendor[index].type = type; 1308 dmic->dmic_mic_config.vendor[index].panel = panel; 1309 dmic->dmic_mic_config.vendor[index].speaker_position_distance = speaker_position_distance; 1310 dmic->dmic_mic_config.vendor[index].horizontal_offset = horizontal_offset; 1311 dmic->dmic_mic_config.vendor[index].vertical_offset = vertical_offset; 1312 dmic->dmic_mic_config.vendor[index].frequency_low_band = frequency_low_band; 1313 dmic->dmic_mic_config.vendor[index].frequency_high_band = frequency_high_band; 1314 dmic->dmic_mic_config.vendor[index].direction_angle = direction_angle; 1315 dmic->dmic_mic_config.vendor[index].elevation_angle = elevation_angle; 1316 dmic->dmic_mic_config.vendor[index].vertical_angle_begin = vertical_angle_begin; 1317 dmic->dmic_mic_config.vendor[index].vertical_angle_end = vertical_angle_end; 1318 dmic->dmic_mic_config.vendor[index].horizontal_angle_begin = horizontal_angle_begin; 1319 dmic->dmic_mic_config.vendor[index].horizontal_angle_end = horizontal_angle_end; 1320 1321 dmic->dmic_mic_config.num_mics++; 1322 1323 return 0; 1324} 1325 1326/* init dmic parameters, should be called before parsing dais */ 1327int dmic_init_params(struct intel_nhlt_params *nhlt) 1328{ 1329 struct intel_dmic_params *dmic; 1330 int i; 1331 1332 dmic = calloc(1, sizeof(struct intel_dmic_params)); 1333 if (!dmic) 1334 return -ENOMEM; 1335 1336 nhlt->dmic_params = dmic; 1337 /* set always to 1, some fw variants use this for choosing memory type */ 1338 dmic->dmic_blob.gateway_attributes = 1; 1339 /* delay in ms to unmute mics after clock is started */ 1340 dmic->dmic_blob.clock_on_delay = 16; 1341 1342 for (i = 0; i < DMIC_TS_GROUP_SIZE; i++) 1343 dmic->dmic_blob.ts_group[i] = 0xFFFFFFFF; /* not enabled */ 1344 1345 dmic->dmic_count = 0; 1346 1347 dmic->dmic_mic_config.num_mics = 0; 1348 dmic->dmic_mic_config.extension = 0; 1349 dmic->dmic_mic_config.array_type = 0; 1350 dmic->dmic_mic_config.snr = 0; 1351 dmic->dmic_mic_config.sensitivity = 0; 1352 1353 return 0; 1354} 1355