1// SPDX-License-Identifier: BSD-3-Clause
2//
3// Copyright(c) 2021 Intel Corporation. All rights reserved.
4//
5// Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
6//         Jaska Uimonen <jaska.uimonen@linux.intel.com>
7
8#ifndef __DMIC_MACROS_H
9#define __DMIC_MACROS_H
10
11#include "dmic-intel.h"
12
13#define DMIC_HW_CONTROLLERS	2
14#define DMIC_HW_FIFOS		2
15#define DMIC_HW_FIR_LENGTH_MAX	250
16
17/* Get max and min signed integer values for N bits word length */
18#define INT_MAX(N)	((int64_t)((1ULL << ((N) - 1)) - 1))
19
20/* Fractional multiplication with shift and round
21 * Note that the parameters px and py must be cast to (int64_t) if other type.
22 */
23#define Q_MULTSR_32X32(px, py, qx, qy, qp) \
24	((((px) * (py) >> ((qx) + (qy) - (qp) - 1)) + 1) >> 1)
25
26/* Convert a float number to fractional Qnx.ny format. Note that there is no
27 * check for nx+ny number of bits to fit the word length of int. The parameter
28 * qy must be 31 or less.
29 */
30#define Q_CONVERT_FLOAT(f, qy) \
31	((int32_t)(((const double)f) * ((int64_t)1 << (const int)qy) + 0.5))
32
33/* Saturation */
34#define SATP_INT32(x) (((x) > INT32_MAX) ? INT32_MAX : (x))
35
36#define DMIC_MAX_MODES 50
37#define DMIC_FIR_PIPELINE_OVERHEAD 5
38
39/* Minimum OSR is always applied for 48 kHz and less sample rates */
40#define DMIC_MIN_OSR  50
41
42/* These are used as guideline for configuring > 48 kHz sample rates. The
43 * minimum OSR can be relaxed down to 40 (use 3.84 MHz clock for 96 kHz).
44 */
45#define DMIC_HIGH_RATE_MIN_FS	64000
46#define DMIC_HIGH_RATE_OSR_MIN	40
47
48/* Used for scaling FIR coefficients for HW */
49#define DMIC_HW_FIR_COEF_MAX ((1 << (DMIC_HW_BITS_FIR_COEF - 1)) - 1)
50#define DMIC_HW_FIR_COEF_Q (DMIC_HW_BITS_FIR_COEF - 1)
51
52/* Internal precision in gains computation, e.g. Q4.28 in int32_t */
53#define DMIC_FIR_SCALE_Q 28
54
55/* Parameters used in modes computation */
56#define DMIC_HW_BITS_CIC		26
57#define DMIC_HW_BITS_FIR_COEF		20
58#define DMIC_HW_BITS_FIR_GAIN		20
59#define DMIC_HW_BITS_FIR_INPUT		22
60#define DMIC_HW_BITS_FIR_OUTPUT		24
61#define DMIC_HW_BITS_FIR_INTERNAL	26
62#define DMIC_HW_BITS_GAIN_OUTPUT	22
63#define DMIC_HW_CIC_SHIFT_MIN		-8
64#define DMIC_HW_CIC_SHIFT_MAX		4
65#define DMIC_HW_FIR_SHIFT_MIN		0
66#define DMIC_HW_FIR_SHIFT_MAX		8
67#define DMIC_HW_CIC_DECIM_MIN		5
68#define DMIC_HW_CIC_DECIM_MAX		31 /* Note: Limited by BITS_CIC */
69#define DMIC_HW_FIR_DECIM_MIN		2
70#define DMIC_HW_FIR_DECIM_MAX		20 /* Note: Practical upper limit */
71#define DMIC_HW_SENS_Q28		Q_CONVERT_FLOAT(1.0, 28) /* Q1.28 */
72#define DMIC_HW_PDM_CLK_MIN		100000 /* Note: Practical min value */
73#define DMIC_HW_DUTY_MIN		20 /* Note: Practical min value */
74#define DMIC_HW_DUTY_MAX		80 /* Note: Practical max value */
75
76/* OUTCONTROL0 bits */
77#define OUTCONTROL0_TIE_BIT	BIT(27)
78#define OUTCONTROL0_SIP_BIT	BIT(26)
79#define OUTCONTROL0_FINIT_BIT	BIT(25)
80#define OUTCONTROL0_FCI_BIT	BIT(24)
81#define OUTCONTROL0_TIE(x)	SET_BIT(27, x)
82#define OUTCONTROL0_SIP(x)	SET_BIT(26, x)
83#define OUTCONTROL0_FINIT(x)	SET_BIT(25, x)
84#define OUTCONTROL0_FCI(x)	SET_BIT(24, x)
85#define OUTCONTROL0_BFTH(x)	SET_BITS(23, 20, x)
86#define OUTCONTROL0_OF(x)	SET_BITS(19, 18, x)
87#define OUTCONTROL0_TH(x)	SET_BITS(5, 0, x)
88
89/* OUTCONTROL1 bits */
90#define OUTCONTROL1_TIE_BIT	BIT(27)
91#define OUTCONTROL1_SIP_BIT	BIT(26)
92#define OUTCONTROL1_FINIT_BIT	BIT(25)
93#define OUTCONTROL1_FCI_BIT	BIT(24)
94#define OUTCONTROL1_TIE(x)	SET_BIT(27, x)
95#define OUTCONTROL1_SIP(x)	SET_BIT(26, x)
96#define OUTCONTROL1_FINIT(x)	SET_BIT(25, x)
97#define OUTCONTROL1_FCI(x)	SET_BIT(24, x)
98#define OUTCONTROL1_BFTH(x)	SET_BITS(23, 20, x)
99#define OUTCONTROL1_OF(x)	SET_BITS(19, 18, x)
100#define OUTCONTROL1_TH(x)	SET_BITS(5, 0, x)
101
102/* OUTCONTROL0 bits ver1*/
103#define OUTCONTROL0_IPM_VER1(x)	SET_BITS(17, 16, x)
104/* OUTCONTROL1 bits ver1 */
105#define OUTCONTROL1_IPM_VER1(x)	SET_BITS(17, 16, x)
106
107/* OUTCONTROL0 bits */
108#define OUTCONTROL0_IPM_VER2(x)			SET_BITS(17, 15, x)
109#define OUTCONTROL0_IPM_SOURCE_1(x)		SET_BITS(14, 13, x)
110#define OUTCONTROL0_IPM_SOURCE_2(x)		SET_BITS(12, 11, x)
111#define OUTCONTROL0_IPM_SOURCE_3(x)		SET_BITS(10, 9, x)
112#define OUTCONTROL0_IPM_SOURCE_4(x)		SET_BITS(8, 7, x)
113#define OUTCONTROL0_IPM_SOURCE_MODE(x)		SET_BIT(6, x)
114
115/* OUTCONTROL1 bits */
116#define OUTCONTROL1_IPM_VER2(x)			SET_BITS(17, 15, x)
117#define OUTCONTROL1_IPM_SOURCE_1(x)		SET_BITS(14, 13, x)
118#define OUTCONTROL1_IPM_SOURCE_2(x)		SET_BITS(12, 11, x)
119#define OUTCONTROL1_IPM_SOURCE_3(x)		SET_BITS(10, 9, x)
120#define OUTCONTROL1_IPM_SOURCE_4(x)		SET_BITS(8, 7, x)
121#define OUTCONTROL1_IPM_SOURCE_MODE(x)		SET_BIT(6, x)
122
123#define OUTCONTROLX_IPM_NUMSOURCES		4
124
125/* CIC_CONTROL bits */
126#define CIC_CONTROL_SOFT_RESET_BIT	BIT(16)
127#define CIC_CONTROL_CIC_START_B_BIT	BIT(15)
128#define CIC_CONTROL_CIC_START_A_BIT	BIT(14)
129#define CIC_CONTROL_MIC_B_POLARITY_BIT	BIT(3)
130#define CIC_CONTROL_MIC_A_POLARITY_BIT	BIT(2)
131#define CIC_CONTROL_MIC_MUTE_BIT	BIT(1)
132#define CIC_CONTROL_STEREO_MODE_BIT	BIT(0)
133
134#define CIC_CONTROL_SOFT_RESET(x)	SET_BIT(16, x)
135#define CIC_CONTROL_CIC_START_B(x)	SET_BIT(15, x)
136#define CIC_CONTROL_CIC_START_A(x)	SET_BIT(14, x)
137#define CIC_CONTROL_MIC_B_POLARITY(x)	SET_BIT(3, x)
138#define CIC_CONTROL_MIC_A_POLARITY(x)	SET_BIT(2, x)
139#define CIC_CONTROL_MIC_MUTE(x)		SET_BIT(1, x)
140#define CIC_CONTROL_STEREO_MODE(x)	SET_BIT(0, x)
141
142/* CIC_CONFIG bits */
143#define CIC_CONFIG_CIC_SHIFT(x)		SET_BITS(27, 24, x)
144#define CIC_CONFIG_COMB_COUNT(x)	SET_BITS(15, 8, x)
145
146/* CIC_CONFIG masks */
147#define CIC_CONFIG_CIC_SHIFT_MASK	MASK(27, 24)
148#define CIC_CONFIG_COMB_COUNT_MASK	MASK(15, 8)
149
150/* MIC_CONTROL bits */
151#define MIC_CONTROL_PDM_EN_B_BIT	BIT(1)
152#define MIC_CONTROL_PDM_EN_A_BIT	BIT(0)
153#define MIC_CONTROL_PDM_CLKDIV(x)	SET_BITS(15, 8, x)
154#define MIC_CONTROL_PDM_SKEW(x)		SET_BITS(7, 4, x)
155#define MIC_CONTROL_CLK_EDGE(x)		SET_BIT(3, x)
156#define MIC_CONTROL_PDM_EN_B(x)		SET_BIT(1, x)
157#define MIC_CONTROL_PDM_EN_A(x)		SET_BIT(0, x)
158
159/* MIC_CONTROL masks */
160#define MIC_CONTROL_PDM_CLKDIV_MASK	MASK(15, 8)
161
162/* FIR_CONTROL_A bits */
163#define FIR_CONTROL_A_START_BIT			BIT(7)
164#define FIR_CONTROL_A_ARRAY_START_EN_BIT	BIT(6)
165#define FIR_CONTROL_A_MUTE_BIT			BIT(1)
166#define FIR_CONTROL_A_START(x)			SET_BIT(7, x)
167#define FIR_CONTROL_A_ARRAY_START_EN(x)		SET_BIT(6, x)
168#define FIR_CONTROL_A_DCCOMP(x)			SET_BIT(4, x)
169#define FIR_CONTROL_A_MUTE(x)			SET_BIT(1, x)
170#define FIR_CONTROL_A_STEREO(x)			SET_BIT(0, x)
171
172/* FIR_CONFIG_A bits */
173#define FIR_CONFIG_A_FIR_DECIMATION(x)		SET_BITS(20, 16, x)
174#define FIR_CONFIG_A_FIR_SHIFT(x)		SET_BITS(11, 8, x)
175#define FIR_CONFIG_A_FIR_LENGTH(x)		SET_BITS(7, 0, x)
176
177/* DC offset compensation time constants */
178#define DCCOMP_TC0	0
179#define DCCOMP_TC1	1
180#define DCCOMP_TC2	2
181#define DCCOMP_TC3	3
182#define DCCOMP_TC4	4
183#define DCCOMP_TC5	5
184#define DCCOMP_TC6	6
185#define DCCOMP_TC7	7
186
187/* DC_OFFSET_LEFT_A bits */
188#define DC_OFFSET_LEFT_A_DC_OFFS(x)		SET_BITS(21, 0, x)
189
190/* DC_OFFSET_RIGHT_A bits */
191#define DC_OFFSET_RIGHT_A_DC_OFFS(x)		SET_BITS(21, 0, x)
192
193/* OUT_GAIN_LEFT_A bits */
194#define OUT_GAIN_LEFT_A_GAIN(x)			SET_BITS(19, 0, x)
195
196/* OUT_GAIN_RIGHT_A bits */
197#define OUT_GAIN_RIGHT_A_GAIN(x)		SET_BITS(19, 0, x)
198
199/* FIR_CONTROL_B bits */
200#define FIR_CONTROL_B_START_BIT			BIT(7)
201#define FIR_CONTROL_B_ARRAY_START_EN_BIT	BIT(6)
202#define FIR_CONTROL_B_MUTE_BIT			BIT(1)
203#define FIR_CONTROL_B_START(x)			SET_BIT(7, x)
204#define FIR_CONTROL_B_ARRAY_START_EN(x)		SET_BIT(6, x)
205#define FIR_CONTROL_B_DCCOMP(x)			SET_BIT(4, x)
206#define FIR_CONTROL_B_MUTE(x)			SET_BIT(1, x)
207#define FIR_CONTROL_B_STEREO(x)			SET_BIT(0, x)
208
209/* FIR_CONFIG_B bits */
210#define FIR_CONFIG_B_FIR_DECIMATION(x)		SET_BITS(20, 16, x)
211#define FIR_CONFIG_B_FIR_SHIFT(x)		SET_BITS(11, 8, x)
212#define FIR_CONFIG_B_FIR_LENGTH(x)		SET_BITS(7, 0, x)
213
214/* DC_OFFSET_LEFT_B bits */
215#define DC_OFFSET_LEFT_B_DC_OFFS(x)		SET_BITS(21, 0, x)
216
217/* DC_OFFSET_RIGHT_B bits */
218#define DC_OFFSET_RIGHT_B_DC_OFFS(x)		SET_BITS(21, 0, x)
219
220/* OUT_GAIN_LEFT_B bits */
221#define OUT_GAIN_LEFT_B_GAIN(x)			SET_BITS(19, 0, x)
222
223/* OUT_GAIN_RIGHT_B bits */
224#define OUT_GAIN_RIGHT_B_GAIN(x)		SET_BITS(19, 0, x)
225
226/* FIR coefficients */
227#define FIR_COEF_A(x)				SET_BITS(19, 0, x)
228#define FIR_COEF_B(x)				SET_BITS(19, 0, x)
229
230/* structs for dmic internal calculations */
231struct dmic_calc_decim_modes {
232	int16_t clkdiv[DMIC_MAX_MODES];
233	int16_t mcic[DMIC_MAX_MODES];
234	int16_t mfir[DMIC_MAX_MODES];
235	int num_of_modes;
236};
237
238struct dmic_calc_matched_modes {
239	int16_t clkdiv[DMIC_MAX_MODES];
240	int16_t mcic[DMIC_MAX_MODES];
241	int16_t mfir_a[DMIC_MAX_MODES];
242	int16_t mfir_b[DMIC_MAX_MODES];
243	int num_of_modes;
244};
245
246struct dmic_calc_configuration {
247	struct pdm_decim *fir_a;
248	struct pdm_decim *fir_b;
249	int clkdiv;
250	int mcic;
251	int mfir_a;
252	int mfir_b;
253	int cic_shift;
254	int fir_a_shift;
255	int fir_b_shift;
256	int fir_a_length;
257	int fir_b_length;
258	int32_t fir_a_scale;
259	int32_t fir_b_scale;
260};
261
262/* structs for gathering the parameters from topology */
263struct dmic_config_pdm {
264	uint16_t id;
265	uint16_t enable_mic_a;
266	uint16_t enable_mic_b;
267	uint16_t polarity_mic_a;
268	uint16_t polarity_mic_b;
269	uint16_t clk_edge;
270	uint16_t skew;
271};
272
273struct dmic_config_dai {
274	uint32_t driver_version;
275	uint32_t io_clk;
276	uint32_t pdmclk_min;
277	uint32_t pdmclk_max;
278	uint32_t fifo_fs;
279	uint16_t fifo_bits;
280	uint16_t fifo_bits_b;
281	uint16_t duty_min;
282	uint16_t duty_max;
283	uint32_t num_pdm_active;
284	uint32_t wake_up_time;
285	uint32_t min_clock_on_time;
286	uint32_t unmute_ramp_time;
287	struct dmic_config_pdm pdm[DMIC_HW_CONTROLLERS];
288};
289
290/* every pdm controller has separate fir filter for output fifos */
291struct dmic_calc_fir_coeffs_array {
292	uint32_t fir_len[DMIC_HW_CONTROLLERS];
293	int32_t fir_coeffs[DMIC_HW_CONTROLLERS][DMIC_HW_FIFOS][DMIC_HW_FIR_LENGTH_MAX];
294};
295
296struct dmic_config_mic_vendor {
297	uint8_t type;
298	uint8_t panel;
299	uint32_t speaker_position_distance;
300	uint32_t horizontal_offset;
301	uint32_t vertical_offset;
302	uint8_t frequency_low_band;
303	uint8_t frequency_high_band;
304	uint16_t direction_angle;
305	uint16_t elevation_angle;
306	uint16_t vertical_angle_begin;
307	uint16_t vertical_angle_end;
308	uint16_t horizontal_angle_begin;
309	uint16_t horizontal_angle_end;
310};
311
312struct dmic_config_mic {
313	uint8_t num_mics;
314	uint8_t extension;
315	int8_t array_type;
316	uint32_t snr;
317	uint32_t sensitivity;
318	struct dmic_config_mic_vendor vendor[8];
319};
320
321struct intel_dmic_params {
322	/* structs to gather dmic params before calculations */
323	struct dmic_config_dai dmic_prm[DMIC_HW_FIFOS];
324	uint32_t dmic_dai_index;
325	int dmic_count;
326
327	/* dmic vendor blob structs */
328	struct dmic_intel_config_data dmic_blob;
329	struct dmic_intel_pdm_ctrl_cfg dmic_blob_pdm[DMIC_HW_CONTROLLERS];
330	struct dmic_intel_fir_config dmic_blob_fir[DMIC_HW_CONTROLLERS][DMIC_HW_FIFOS];
331	struct dmic_calc_fir_coeffs_array dmic_fir_array;
332	struct dmic_config_mic dmic_mic_config;
333};
334
335#endif /* __DMIC_MACROS_H */
336