1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013-2014 Kevin Lo 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29#define AXE_FLAG_178A 0x10000 /* AX88178A */ 30 31#define AXGE_ACCESS_MAC 0x01 32#define AXGE_ACCESS_PHY 0x02 33#define AXGE_ACCESS_WAKEUP 0x03 34#define AXGE_ACCESS_EEPROM 0x04 35#define AXGE_ACCESS_EFUSE 0x05 36#define AXGE_RELOAD_EEPROM_EFUSE 0x06 37#define AXGE_FW_MODE 0x08 38#define AXGE_WRITE_EFUSE_EN 0x09 39#define AXGE_WRITE_EFUSE_DIS 0x0A 40#define AXGE_ACCESS_MFAB 0x10 41 42#define AXGE_FW_MODE_178A179 0x0000 43#define AXGE_FW_MODE_179A 0x0001 44 45/* Physical link status register */ 46#define AXGE_PLSR 0x02 47#define PLSR_USB_FS 0x01 48#define PLSR_USB_HS 0x02 49#define PLSR_USB_SS 0x04 50 51/* EEPROM address register */ 52#define AXGE_EAR 0x07 53 54/* EEPROM data low register */ 55#define AXGE_EDLR 0x08 56 57/* EEPROM data high register */ 58#define AXGE_EDHR 0x09 59 60/* EEPROM command register */ 61#define AXGE_ECR 0x0a 62 63/* Rx control register */ 64#define AXGE_RCR 0x0b 65#define RCR_STOP 0x0000 66#define RCR_PRO 0x0001 67#define RCR_AMALL 0x0002 68#define RCR_AB 0x0008 69#define RCR_AM 0x0010 70#define RCR_AP 0x0020 71#define RCR_SO 0x0080 72#define RCR_DROP_CRCE 0x0100 73#define RCR_IPE 0x0200 74#define RCR_TX_CRC_PAD 0x0400 75 76/* Node id register */ 77#define AXGE_NIDR 0x10 78 79/* Multicast filter array */ 80#define AXGE_MFA 0x16 81 82/* Medium status register */ 83#define AXGE_MSR 0x22 84#define MSR_GM 0x0001 85#define MSR_FD 0x0002 86#define MSR_EN_125MHZ 0x0008 87#define MSR_RFC 0x0010 88#define MSR_TFC 0x0020 89#define MSR_RE 0x0100 90#define MSR_PS 0x0200 91 92/* Monitor mode status register */ 93#define AXGE_MMSR 0x24 94#define MMSR_RWLC 0x02 95#define MMSR_RWMP 0x04 96#define MMSR_RWWF 0x08 97#define MMSR_RW_FLAG 0x10 98#define MMSR_PME_POL 0x20 99#define MMSR_PME_TYPE 0x40 100#define MMSR_PME_IND 0x80 101 102/* GPIO control/status register */ 103#define AXGE_GPIOCR 0x25 104 105/* Ethernet PHY power & reset control register */ 106#define AXGE_EPPRCR 0x26 107#define EPPRCR_BZ 0x0010 108#define EPPRCR_IPRL 0x0020 109#define EPPRCR_AUTODETACH 0x1000 110 111#define AXGE_RX_BULKIN_QCTRL 0x2e 112 113#define AXGE_CLK_SELECT 0x33 114#define AXGE_CLK_SELECT_BCS 0x01 115#define AXGE_CLK_SELECT_ACS 0x02 116#define AXGE_CLK_SELECT_ACSREQ 0x10 117#define AXGE_CLK_SELECT_ULR 0x08 118 119/* COE Rx control register */ 120#define AXGE_CRCR 0x34 121#define CRCR_IP 0x01 122#define CRCR_TCP 0x02 123#define CRCR_UDP 0x04 124#define CRCR_ICMP 0x08 125#define CRCR_IGMP 0x10 126#define CRCR_TCPV6 0x20 127#define CRCR_UDPV6 0x40 128#define CRCR_ICMPV6 0x80 129 130/* COE Tx control register */ 131#define AXGE_CTCR 0x35 132#define CTCR_IP 0x01 133#define CTCR_TCP 0x02 134#define CTCR_UDP 0x04 135#define CTCR_ICMP 0x08 136#define CTCR_IGMP 0x10 137#define CTCR_TCPV6 0x20 138#define CTCR_UDPV6 0x40 139#define CTCR_ICMPV6 0x80 140 141/* Pause water level high register */ 142#define AXGE_PWLHR 0x54 143 144/* Pause water level low register */ 145#define AXGE_PWLLR 0x55 146 147#define AXGE_CONFIG_IDX 0 /* config number 1 */ 148#define AXGE_IFACE_IDX 0 149 150#define AXGE_RXHDR_L4_TYPE_MASK 0x1c 151#define AXGE_RXHDR_L4CSUM_ERR 1 152#define AXGE_RXHDR_L3CSUM_ERR 2 153#define AXGE_RXHDR_L4_TYPE_UDP 4 154#define AXGE_RXHDR_L4_TYPE_TCP 16 155#define AXGE_RXHDR_CRC_ERR 0x20000000 156#define AXGE_RXHDR_DROP_ERR 0x80000000 157 158/* The interrupt endpoint is currently unused by the ASIX part. */ 159enum { 160 AXGE_BULK_DT_WR, 161 AXGE_BULK_DT_RD, 162 AXGE_N_TRANSFER, 163}; 164 165struct axge_softc { 166 struct usb_ether sc_ue; 167 struct mtx sc_mtx; 168 struct usb_xfer *sc_xfer[AXGE_N_TRANSFER]; 169 int sc_phyno; 170 171 int sc_flags; 172 uint8_t sc_link_status; 173#define AXE_FLAG_LINK 0x0001 174#define AXE_FLAG_STD_FRAME 0x0010 175#define AXE_FLAG_CSUM_FRAME 0x0020 176 177 uint8_t sc_ipgs[3]; 178 uint8_t sc_phyaddrs[2]; 179 uint16_t sc_pwrcfg; 180 uint16_t sc_lenmask; 181 uint8_t rx_chklink_cnt; 182#define EVENT_LINK 0x00000001 183}; 184 185#define ETHER_TYPE_LEN 2 /* length of the Ethernet type field */ 186#define ETHER_HDR_LEN (NETIF_MAX_HWADDR_LEN * 2 + ETHER_TYPE_LEN) 187 188#define IFM_1000_T 0x40 189#define IFM_100_TX 0x20 190#define IFM_10_T 0x10 191 192#define AXGE_LINK_MASK 0xf0 193 194#define AXGE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 195#define AXGE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 196#define AXGE_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t) 197