1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2010-2022 Hans Petter Selasky 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 30 * 31 * The XHCI 1.0 spec can be found at 32 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 33 * and the USB 3.0 spec at 34 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 35 */ 36 37/* 38 * A few words about the design implementation: This driver emulates 39 * the concept about TDs which is found in EHCI specification. This 40 * way we achieve that the USB controller drivers look similar to 41 * eachother which makes it easier to understand the code. 42 */ 43 44#include "implementation/global_implementation.h" 45#include "controller/xhci.h" 46#include "controller/xhcireg.h" 47 48#define XHCI_BUS2SC(bus) \ 49 ((struct xhci_softc *)(((uint8_t *)(bus)) - \ 50 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus)))) 51 52static int xhcistreams; 53 54#ifdef USB_DEBUG 55static int xhcidebug = 20; 56static int xhciroute = 0; 57static int xhcipolling = 0; 58static int xhcidma32 = 0; 59static int xhcictlstep = 0; 60#else 61#define xhciroute 0 62#define xhcidma32 0 63#define xhcictlstep 0 64#endif 65 66#undef USB_DEBUG_VAR 67#define USB_DEBUG_VAR xhcidebug 68 69#ifdef LOSCFG_USB_DEBUG 70static int xhcidebug = 0; 71#endif 72 73 74#define XHCI_INTR_ENDPT 1 75 76#define XHCI_DO_CMD_TIMEOUT 1000 77 78struct xhci_std_temp { 79 struct xhci_softc *sc; 80 struct usb_page_cache *pc; 81 struct xhci_td *td; 82 struct xhci_td *td_next; 83 uint32_t len; 84 uint32_t offset; 85 uint32_t max_packet_size; 86 uint32_t average; 87 uint16_t isoc_delta; 88 uint16_t isoc_frame; 89 uint8_t shortpkt; 90 uint8_t multishort; 91 uint8_t last_frame; 92 uint8_t trb_type; 93 uint8_t direction; 94 uint8_t tbc; 95 uint8_t tlbpc; 96 uint8_t step_td; 97 uint8_t do_isoc_sync; 98}; 99 100static void xhci_do_poll(struct usb_bus *); 101static void xhci_device_done(struct usb_xfer *, usb_error_t); 102static void xhci_root_intr(struct xhci_softc *); 103static void xhci_free_device_ext(struct usb_device *); 104static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 105 struct usb_endpoint_descriptor *); 106static usb_proc_callback_t xhci_configure_msg; 107static usb_error_t xhci_configure_device(struct usb_device *); 108static usb_error_t xhci_configure_endpoint(struct usb_device *, 109 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *, 110 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, 111 uint8_t); 112static usb_error_t xhci_configure_mask(struct usb_device *, 113 uint32_t, uint8_t); 114static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 115 uint64_t, uint8_t); 116static void xhci_endpoint_doorbell(struct usb_xfer *); 117static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val); 118static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr); 119static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val); 120#ifdef USB_DEBUG 121static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr); 122#endif 123 124extern struct usb_bus_methods xhci_bus_methods; 125 126#ifdef USB_DEBUG 127static void 128xhci_dump_trb(struct xhci_trb *trb) 129{ 130 DPRINTFN(5, "trb = %p\n", trb); 131 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 132 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 133 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 134} 135 136static void 137xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep) 138{ 139 DPRINTFN(5, "pep = %p\n", pep); 140 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0)); 141 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1)); 142 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2)); 143 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4)); 144 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5)); 145 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6)); 146 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7)); 147} 148 149static void 150xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl) 151{ 152 DPRINTFN(5, "psl = %p\n", psl); 153 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0)); 154 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1)); 155 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2)); 156 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3)); 157} 158#endif 159 160uint8_t 161xhci_use_polling(void) 162{ 163#ifdef USB_DEBUG 164 return (xhcipolling != 0); 165#else 166 return (0); 167#endif 168} 169 170static void 171xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 172{ 173 struct xhci_softc *sc = XHCI_BUS2SC(bus); 174 uint8_t i; 175 176 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 177 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 178 179 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 180 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 181 182 for (i = 0; i != sc->sc_noscratch; i++) { 183 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 184 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 185 } 186} 187 188static void 189xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val) 190{ 191 uint32_t offset; 192 if (sc->sc_ctx_is_64_byte) { 193 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 194 /* all contexts are initially 32-bytes */ 195 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 196 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 197 } 198 *ptr = htole32(val); 199} 200 201static uint32_t 202xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr) 203{ 204 uint32_t offset; 205 if (sc->sc_ctx_is_64_byte) { 206 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 207 /* all contexts are initially 32-bytes */ 208 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 209 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 210 } 211 return (le32toh(*ptr)); 212} 213 214static void 215xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val) 216{ 217 uint32_t offset; 218 if (sc->sc_ctx_is_64_byte) { 219 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 220 /* all contexts are initially 32-bytes */ 221 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 222 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 223 } 224 *ptr = htole64(val); 225} 226 227#ifdef USB_DEBUG 228static uint64_t 229xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr) 230{ 231 uint32_t offset; 232 if (sc->sc_ctx_is_64_byte) { 233 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 234 /* all contexts are initially 32-bytes */ 235 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 236 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 237 } 238 return (le64toh(*ptr)); 239} 240#endif 241 242static int 243xhci_reset_command_queue_locked(struct xhci_softc *sc) 244{ 245 struct usb_page_search buf_res; 246 struct xhci_hw_root *phwr; 247 uint64_t addr; 248 uint32_t temp; 249 250 DPRINTF("\n"); 251 252 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 253 if (temp & XHCI_CRCR_LO_CRR) { 254 DPRINTF("Command ring running\n"); 255 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA); 256 257 /* 258 * Try to abort the last command as per section 259 * 4.6.1.2 "Aborting a Command" of the XHCI 260 * specification: 261 */ 262 263 /* stop and cancel */ 264 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS); 265 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 266 267 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA); 268 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 269 270 /* wait 250ms */ 271 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4); 272 273 /* check if command ring is still running */ 274 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 275 if (temp & XHCI_CRCR_LO_CRR) { 276 DPRINTF("Comand ring still running\n"); 277 return (USB_ERR_IOERROR); 278 } 279 } 280 281 /* reset command ring */ 282 sc->sc_command_ccs = 1; 283 sc->sc_command_idx = 0; 284 285 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 286 287 /* set up command ring control base address */ 288 addr = buf_res.physaddr; 289 phwr = buf_res.buffer; 290 addr += __offsetof(struct xhci_hw_root, hwr_commands[0]); 291 292 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 293 294 (void)memset_s(phwr->hwr_commands, sizeof(phwr->hwr_commands), 0, sizeof(phwr->hwr_commands)); 295 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 296 297 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 298 299 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 300 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 301 302 return (0); 303} 304 305usb_error_t 306xhci_start_controller(struct xhci_softc *sc) 307{ 308 struct usb_page_search buf_res; 309 struct xhci_hw_root *phwr; 310 struct xhci_dev_ctx_addr *pdctxa; 311 uint64_t addr; 312 uint32_t temp; 313 uint16_t i; 314 int ret; 315 316 DPRINTF("\n"); 317 318 sc->sc_event_ccs = 1; 319 sc->sc_event_idx = 0; 320 sc->sc_command_ccs = 1; 321 sc->sc_command_idx = 0; 322 323 /* Reset controller */ 324 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 325 326 for (i = 0; i != 100; i++) { 327 usb_pause_mtx(NULL, hz / 100); 328 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) | 329 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR); 330 if (!temp) 331 break; 332 } 333 334 if (temp) { 335 device_printf(sc->sc_bus.parent, "Controller " 336 "reset timeout.\n"); 337 return (USB_ERR_IOERROR); 338 } 339 340 /* set up number of device slots */ 341 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 342 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 343 344 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 345 346 temp = XREAD4(sc, oper, XHCI_USBSTS); 347 348 /* clear interrupts */ 349 XWRITE4(sc, oper, XHCI_USBSTS, temp); 350 /* disable all device notifications */ 351 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 352 353 /* set up device context base address */ 354 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 355 pdctxa = buf_res.buffer; 356 ret = memset_s(pdctxa, USB_PAGE_SIZE, 0, sizeof(*pdctxa)); 357 if (ret != EOK) { 358 usb_err("memset_s failed, ret:%d\n", ret); 359 return (USB_ERR_BAD_BUFSIZE); 360 } 361 362 addr = buf_res.physaddr; 363 addr += __offsetof(struct xhci_dev_ctx_addr, qwSpBufPtr[0]); 364 365 /* slot 0 points to the table of scratchpad pointers */ 366 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 367 368 for (i = 0; i != sc->sc_noscratch; i++) { 369 struct usb_page_search buf_scp; 370 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 371 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 372 } 373 374 addr = buf_res.physaddr; 375 376 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 377 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 378 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 379 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 380 381 /* set up event table size */ 382 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 383 XREAD4(sc, runt, XHCI_ERSTSZ(0)), sc->sc_erst_max); 384 385 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(sc->sc_erst_max)); 386 387 /* set up interrupt rate */ 388 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default); 389 390 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 391 392 phwr = buf_res.buffer; 393 addr = buf_res.physaddr; 394 addr += __offsetof(struct xhci_hw_root, hwr_events[0]); 395 396 /* reset hardware root structure */ 397 ret = memset_s(phwr, USB_PAGE_SIZE, 0, sizeof(*phwr)); 398 if (ret != EOK) { 399 usb_err("memset_s failed, ret:%d\n", ret); 400 return (USB_ERR_BAD_BUFSIZE); 401 } 402 403 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 404 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 405 406 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 407 408 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 409 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 410 411 addr = buf_res.physaddr; 412 413 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 414 415 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 416 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 417 418 /* set up interrupter registers */ 419 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 420 temp |= XHCI_IMAN_INTR_ENA; 421 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 422 423 /* set up command ring control base address */ 424 addr = buf_res.physaddr; 425 addr += __offsetof(struct xhci_hw_root, hwr_commands[0]); 426 427 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 428 429 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 430 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 431 432 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 433 434 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 435 436 /* Go! */ 437 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 438 XHCI_CMD_INTE | XHCI_CMD_HSEE); 439 440 for (i = 0; i != 100; i++) { 441 usb_pause_mtx(NULL, hz / 100); 442 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 443 if (!temp) 444 break; 445 } 446 if (temp) { 447 XWRITE4(sc, oper, XHCI_USBCMD, 0); 448 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 449 return (USB_ERR_IOERROR); 450 } 451 452 /* catch any lost interrupts */ 453 xhci_do_poll(&sc->sc_bus); 454 455 if (sc->sc_port_route != NULL) { 456 /* Route all ports to the XHCI by default */ 457 (void)sc->sc_port_route(sc->sc_bus.parent, 458 ~xhciroute, xhciroute); 459 } 460 return (USB_ERR_NORMAL_COMPLETION); 461} 462 463usb_error_t 464xhci_halt_controller(struct xhci_softc *sc) 465{ 466 uint32_t temp; 467 uint16_t i; 468 469 DPRINTF("\n"); 470 471 sc->sc_capa_off = 0; 472 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 473 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; 474 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 475 476 /* Halt controller */ 477 XWRITE4(sc, oper, XHCI_USBCMD, 0); 478 479 for (i = 0; i != 100; i++) { 480 usb_pause_mtx(NULL, hz / 100); 481 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 482 if (temp) 483 break; 484 } 485 486 if (!temp) { 487 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 488 return (USB_ERR_IOERROR); 489 } 490 return (USB_ERR_NORMAL_COMPLETION); 491} 492 493usb_error_t 494xhci_reset_controller(struct xhci_softc *sc) 495{ 496 uint32_t temp = 0; 497 uint16_t i; 498 499 DPRINTF("\n"); 500 501 /* Reset controller */ 502 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 503 504 for (i = 0; i != 100; i++) { 505 usb_pause_mtx(NULL, hz / 100); 506 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) | 507 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR); 508 if (!temp) 509 break; 510 } 511 512 if (temp) { 513 device_printf(sc->sc_bus.parent, "Controller " 514 "reset timeout.\n"); 515 return (USB_ERR_IOERROR); 516 } 517 return (USB_ERR_NORMAL_COMPLETION); 518} 519 520usb_error_t 521xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32) 522{ 523 uint32_t temp; 524 525 DPRINTF("\n"); 526 527 /* initialize some bus fields */ 528 sc->sc_bus.parent = self; 529 530 /* set the bus revision */ 531 sc->sc_bus.usbrev = USB_REV_3_0; 532 533 /* set up the bus struct */ 534 sc->sc_bus.methods = &xhci_bus_methods; 535 536 /* set up devices array */ 537 sc->sc_bus.devices = sc->sc_devices; 538 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 539 540 /* set default cycle state in case of early interrupts */ 541 sc->sc_event_ccs = 1; 542 sc->sc_command_ccs = 1; 543 544 /* set up bus space offsets */ 545 sc->sc_capa_off = 0; 546 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 547 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 548 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 549 550 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 551 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 552 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 553 554 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 555 556 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 557 device_printf(sc->sc_bus.parent, "Controller does " 558 "not support 4K page size.\n"); 559 return (usb_error_t)(ENXIO); 560 } 561 562 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); 563 564 DPRINTF("HCS0 = 0x%08x\n", temp); 565 566 /* set up context size */ 567 if (XHCI_HCS0_CSZ(temp)) { 568 sc->sc_ctx_is_64_byte = 1; 569 } else { 570 sc->sc_ctx_is_64_byte = 0; 571 } 572 573 /* get DMA bits */ 574 sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) && 575 xhcidma32 == 0 && dma32 == 0) ? 64 : 32; 576 577 device_printf(self, "%d bytes context size, %d-bit DMA\n", 578 sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits); 579 580 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 581 582 /* get number of device slots */ 583 sc->sc_noport = XHCI_HCS1_N_PORTS(temp); 584 585 if (sc->sc_noport == 0) { 586 device_printf(sc->sc_bus.parent, "Invalid number " 587 "of ports: %u\n", sc->sc_noport); 588 return (usb_error_t)(ENXIO); 589 } 590 591 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 592 593 DPRINTF("Max slots: %u\n", sc->sc_noslot); 594 595 if (sc->sc_noslot > XHCI_MAX_DEVICES) 596 sc->sc_noslot = XHCI_MAX_DEVICES; 597 598 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 599 600 DPRINTF("HCS2=0x%08x\n", temp); 601 602 /* get number of scratchpads */ 603 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 604 605 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 606 device_printf(sc->sc_bus.parent, "XHCI request " 607 "too many scratchpads\n"); 608 return (usb_error_t)(ENOMEM); 609 } 610 611 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 612 613 /* get event table size */ 614 sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp); 615 if (sc->sc_erst_max > XHCI_MAX_RSEG) 616 sc->sc_erst_max = XHCI_MAX_RSEG; 617 618 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 619 620 /* get maximum exit latency */ 621 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 622 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 623 624 /* Check if we should use the default IMOD value. */ 625 if (sc->sc_imod_default == 0) 626 sc->sc_imod_default = XHCI_IMOD_DEFAULT; 627 628 /* get all DMA memory */ 629 if (usb_bus_mem_alloc_all(&sc->sc_bus, 630 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 631 return (usb_error_t)(ENOMEM); 632 } 633 634 /* set up command queue mutex and condition varible */ 635 cv_init(&sc->sc_cmd_cv, "CMDQ"); 636 sx_init(&sc->sc_cmd_sx, "CMDQ lock"); 637 638 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 639 sc->sc_config_msg[0].bus = &sc->sc_bus; 640 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 641 sc->sc_config_msg[1].bus = &sc->sc_bus; 642 643 return (USB_ERR_NORMAL_COMPLETION); 644} 645 646void 647xhci_uninit(struct xhci_softc *sc) 648{ 649 /* 650 * NOTE: At this point the control transfer process is gone 651 * and "xhci_configure_msg" is no longer called. Consequently 652 * waiting for the configuration messages to complete is not 653 * needed. 654 */ 655 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 656 657 cv_destroy(&sc->sc_cmd_cv); 658 sx_destroy(&sc->sc_cmd_sx); 659} 660 661static void 662xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 663{ 664 struct xhci_softc *sc = XHCI_BUS2SC(bus); 665 666 switch (state) { 667 case USB_HW_POWER_SUSPEND: 668 DPRINTF("Stopping the XHCI\n"); 669 (void)xhci_halt_controller(sc); 670 (void)xhci_reset_controller(sc); 671 break; 672 case USB_HW_POWER_SHUTDOWN: 673 DPRINTF("Stopping the XHCI\n"); 674 (void)xhci_halt_controller(sc); 675 (void)xhci_reset_controller(sc); 676 break; 677 case USB_HW_POWER_RESUME: 678 DPRINTF("Starting the XHCI\n"); 679 (void)xhci_start_controller(sc); 680 break; 681 default: 682 break; 683 } 684} 685 686static usb_error_t 687xhci_generic_done_sub(struct usb_xfer *xfer) 688{ 689 struct xhci_td *td; 690 struct xhci_td *td_alt_next; 691 uint32_t len; 692 uint8_t status; 693 694 td = xfer->td_transfer_cache; 695 td_alt_next = td->alt_next; 696 697 if (xfer->aframes != xfer->nframes) 698 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 699 700 while (1) { 701 usb_pc_cpu_invalidate(td->page_cache); 702 703 status = td->status; 704 len = td->remainder; 705 706 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 707 xfer, (unsigned int)xfer->aframes, 708 (unsigned int)xfer->nframes, 709 (unsigned int)len, (unsigned int)td->len, 710 (unsigned int)status); 711 712 /* 713 * Verify the status length and 714 * add the length to "frlengths[]": 715 */ 716 if (len > td->len) { 717 /* should not happen */ 718 DPRINTF("Invalid status length, " 719 "0x%04x/0x%04x bytes\n", len, td->len); 720 status = XHCI_TRB_ERROR_LENGTH; 721 } else if (xfer->aframes != xfer->nframes) { 722 xfer->frlengths[xfer->aframes] += td->len - len; 723 } 724 /* Check for last transfer */ 725 if (((void *)td) == xfer->td_transfer_last) { 726 td = NULL; 727 break; 728 } 729 /* Check for transfer error */ 730 if (status != XHCI_TRB_ERROR_SHORT_PKT && 731 status != XHCI_TRB_ERROR_SUCCESS) { 732 /* the transfer is finished */ 733 td = NULL; 734 break; 735 } 736 /* Check for short transfer */ 737 if (len > 0) { 738 if (xfer->flags_int.short_frames_ok || 739 xfer->flags_int.isochronous_xfr || 740 xfer->flags_int.control_xfr) { 741 /* follow alt next */ 742 td = td->alt_next; 743 } else { 744 /* the transfer is finished */ 745 td = NULL; 746 } 747 break; 748 } 749 td = td->obj_next; 750 751 if (td->alt_next != td_alt_next) { 752 /* this USB frame is complete */ 753 break; 754 } 755 } 756 757 /* update transfer cache */ 758 759 xfer->td_transfer_cache = td; 760 761 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 762 (status != XHCI_TRB_ERROR_SHORT_PKT && 763 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 764 USB_ERR_NORMAL_COMPLETION); 765} 766 767static void 768xhci_generic_done(struct usb_xfer *xfer) 769{ 770 usb_error_t err = USB_ERR_NORMAL_COMPLETION; 771 772 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 773 xfer, xfer->endpoint); 774 775 /* reset scanner */ 776 777 xfer->td_transfer_cache = xfer->td_transfer_first; 778 779 if (xfer->flags_int.control_xfr) { 780 if (xfer->flags_int.control_hdr) 781 err = xhci_generic_done_sub(xfer); 782 783 xfer->aframes = 1; 784 785 if (xfer->td_transfer_cache == NULL) 786 goto done; 787 } 788 789 while (xfer->aframes != xfer->nframes) { 790 err = xhci_generic_done_sub(xfer); 791 xfer->aframes++; 792 793 if (xfer->td_transfer_cache == NULL) 794 goto done; 795 } 796 797 if (xfer->flags_int.control_xfr && 798 !xfer->flags_int.control_act) 799 err = xhci_generic_done_sub(xfer); 800done: 801 /* transfer is complete */ 802 xhci_device_done(xfer, err); 803} 804 805static void 806xhci_activate_transfer(struct usb_xfer *xfer) 807{ 808 struct xhci_td *td; 809 810 td = xfer->td_transfer_cache; 811 812 usb_pc_cpu_invalidate(td->page_cache); 813 814 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 815 /* activate the transfer */ 816 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 817 usb_pc_cpu_flush(td->page_cache); 818 819 xhci_endpoint_doorbell(xfer); 820 } 821} 822 823static void 824xhci_skip_transfer(struct usb_xfer *xfer) 825{ 826 struct xhci_td *td; 827 struct xhci_td *td_last; 828 829 td = xfer->td_transfer_cache; 830 td_last = xfer->td_transfer_last; 831 832 td = td->alt_next; 833 834 usb_pc_cpu_invalidate(td->page_cache); 835 836 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 837 usb_pc_cpu_invalidate(td_last->page_cache); 838 839 /* copy LINK TRB to current waiting location */ 840 841 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 842 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 843 usb_pc_cpu_flush(td->page_cache); 844 845 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 846 usb_pc_cpu_flush(td->page_cache); 847 848 xhci_endpoint_doorbell(xfer); 849 } 850} 851 852/*------------------------------------------------------------------------* 853 * xhci_check_transfer 854 *------------------------------------------------------------------------*/ 855static void 856xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 857{ 858 struct xhci_endpoint_ext *pepext; 859 int64_t offset; 860 uint64_t td_event; 861 uint32_t temp; 862 uint32_t remainder; 863 uint16_t stream_id = 0; 864 uint16_t i; 865 uint8_t status; 866 uint8_t halted; 867 uint8_t epno; 868 uint8_t index; 869 870 /* decode TRB */ 871 td_event = le64toh(trb->qwTrb0); 872 temp = le32toh(trb->dwTrb2); 873 874 remainder = XHCI_TRB_2_REM_GET(temp); 875 status = XHCI_TRB_2_ERROR_GET(temp); 876 877 temp = le32toh(trb->dwTrb3); 878 epno = XHCI_TRB_3_EP_GET(temp); 879 index = XHCI_TRB_3_SLOT_GET(temp); 880 881 /* check if error means halted */ 882 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 883 status != XHCI_TRB_ERROR_SUCCESS); 884 885 DPRINTF("slot=%u epno=%u remainder=%u status=%u\n", 886 index, epno, remainder, status); 887 888 if (index > sc->sc_noslot) { 889 DPRINTF("Invalid slot.\n"); 890 return; 891 } 892 893 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 894 DPRINTF("Invalid endpoint.\n"); 895 return; 896 } 897 898 pepext = &sc->sc_hw.devs[index].endp[epno]; 899 900 /* try to find the USB transfer that generated the event */ 901 for (i = 0;; i++) { 902 struct usb_xfer *xfer; 903 struct xhci_td *td; 904 905 if (i == (XHCI_MAX_TRANSFERS - 1)) { 906 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS || 907 stream_id == (XHCI_MAX_STREAMS - 1)) 908 break; 909 stream_id++; 910 i = 0; 911 DPRINTFN(5, "stream_id=%u\n", stream_id); 912 } 913 914 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)]; 915 if (xfer == NULL) 916 continue; 917 918 td = xfer->td_transfer_cache; 919 if (td == NULL) { 920 continue; 921 } 922 923 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 924 (long long)td_event, 925 (long long)td->td_self, 926 (long long)td->td_self + sizeof(td->td_trb)); 927 928 /* 929 * NOTE: Some XHCI implementations might not trigger 930 * an event on the last LINK TRB so we need to 931 * consider both the last and second last event 932 * address as conditions for a successful transfer. 933 * 934 * NOTE: We assume that the XHCI will only trigger one 935 * event per chain of TRBs. 936 */ 937 938 offset = td_event - td->td_self; 939 940 if ((offset >= 0) && 941 (offset < (int64_t)sizeof(td->td_trb))) { 942 usb_pc_cpu_invalidate(td->page_cache); 943 944 /* compute rest of remainder, if any */ 945 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 946 temp = le32toh(td->td_trb[i].dwTrb2); 947 remainder += XHCI_TRB_2_BYTES_GET(temp); 948 } 949 950 DPRINTFN(5, "New remainder: %u\n", remainder); 951 952 /* clear isochronous transfer errors */ 953 if (xfer->flags_int.isochronous_xfr) { 954 if (halted) { 955 halted = 0; 956 status = XHCI_TRB_ERROR_SUCCESS; 957 remainder = td->len; 958 } 959 } 960 961 /* "td->remainder" is verified later */ 962 td->remainder = remainder; 963 td->status = status; 964 965 usb_pc_cpu_flush(td->page_cache); 966 967 /* 968 * 1) Last transfer descriptor makes the 969 * transfer done 970 */ 971 if (((void *)td) == xfer->td_transfer_last) { 972 DPRINTF("TD is last\n"); 973 xhci_generic_done(xfer); 974 break; 975 } 976 977 /* 978 * 2) Any kind of error makes the transfer 979 * done 980 */ 981 if (halted) { 982 DPRINTF("TD has I/O error\n"); 983 xhci_generic_done(xfer); 984 break; 985 } 986 987 /* 988 * 3) If there is no alternate next transfer, 989 * a short packet also makes the transfer done 990 */ 991 if (td->remainder > 0) { 992 if (td->alt_next == NULL) { 993 DPRINTF( 994 "short TD has no alternate next\n"); 995 xhci_generic_done(xfer); 996 break; 997 } 998 DPRINTF("TD has short pkt\n"); 999 if (xfer->flags_int.short_frames_ok || 1000 xfer->flags_int.isochronous_xfr || 1001 xfer->flags_int.control_xfr) { 1002 /* follow the alt next */ 1003 xfer->td_transfer_cache = td->alt_next; 1004 xhci_activate_transfer(xfer); 1005 break; 1006 } 1007 xhci_skip_transfer(xfer); 1008 xhci_generic_done(xfer); 1009 break; 1010 } 1011 1012 /* 1013 * 4) Transfer complete - go to next TD 1014 */ 1015 DPRINTF("Following next TD\n"); 1016 xfer->td_transfer_cache = td->obj_next; 1017 xhci_activate_transfer(xfer); 1018 break; /* there should only be one match */ 1019 } 1020 } 1021} 1022 1023static int 1024xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 1025{ 1026 if (sc->sc_cmd_addr == trb->qwTrb0) { 1027 DPRINTF("Received command event\n"); 1028 sc->sc_cmd_result[0] = trb->dwTrb2; 1029 sc->sc_cmd_result[1] = trb->dwTrb3; 1030 (void)cv_signal(&sc->sc_cmd_cv); 1031 return (1); /* command match */ 1032 } 1033 return (0); 1034} 1035 1036static int 1037xhci_interrupt_poll(struct xhci_softc *sc) 1038{ 1039 struct usb_page_search buf_res; 1040 struct xhci_hw_root *phwr; 1041 uint64_t addr; 1042 uint32_t temp; 1043 int retval = 0; 1044 uint16_t i; 1045 uint8_t event; 1046 uint8_t j; 1047 uint8_t k; 1048 uint8_t t; 1049 1050 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1051 1052 phwr = buf_res.buffer; 1053 1054 /* Receive any events */ 1055 1056 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 1057 1058 i = sc->sc_event_idx; 1059 j = sc->sc_event_ccs; 1060 t = 2; 1061 1062 while (1) { 1063 temp = le32toh(phwr->hwr_events[i].dwTrb3); 1064 1065 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1066 1067 if (j != k) 1068 break; 1069 1070 event = XHCI_TRB_3_TYPE_GET(temp); 1071 1072 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 1073 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 1074 (long)le32toh(phwr->hwr_events[i].dwTrb2), 1075 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 1076 1077 switch (event) { 1078 case XHCI_TRB_EVENT_TRANSFER: 1079 xhci_check_transfer(sc, &phwr->hwr_events[i]); 1080 break; 1081 case XHCI_TRB_EVENT_CMD_COMPLETE: 1082 retval |= xhci_check_command(sc, &phwr->hwr_events[i]); 1083 break; 1084 default: 1085 DPRINTF("Unhandled event = %u\n", event); 1086 break; 1087 } 1088 1089 i++; 1090 1091 if (i == XHCI_MAX_EVENTS) { 1092 i = 0; 1093 j ^= 1; 1094 1095 /* check for timeout */ 1096 if (!--t) 1097 break; 1098 } 1099 } 1100 1101 sc->sc_event_idx = i; 1102 sc->sc_event_ccs = j; 1103 1104 /* 1105 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 1106 * latched. That means to activate the register we need to 1107 * write both the low and high double word of the 64-bit 1108 * register. 1109 */ 1110 1111 addr = buf_res.physaddr; 1112 addr += __offsetof(struct xhci_hw_root, hwr_events[i]); 1113 1114 /* try to clear busy bit */ 1115 addr |= XHCI_ERDP_LO_BUSY; 1116 1117 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 1118 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 1119 1120 return (retval); 1121} 1122 1123static usb_error_t 1124xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 1125 uint16_t timeout_ms) 1126{ 1127 struct usb_page_search buf_res; 1128 struct xhci_hw_root *phwr; 1129 uint64_t addr; 1130 uint32_t temp; 1131 uint8_t i; 1132 uint8_t j; 1133 uint8_t timeout = 0; 1134 usb_error_t err; 1135 1136 XHCI_CMD_ASSERT_LOCKED(sc); 1137 1138 /* get hardware root structure */ 1139 1140 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1141 1142 phwr = buf_res.buffer; 1143 1144 /* Queue command */ 1145 1146 USB_BUS_LOCK(&sc->sc_bus); 1147retry: 1148 i = sc->sc_command_idx; 1149 j = sc->sc_command_ccs; 1150 1151 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1152 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1153 (long long)le64toh(trb->qwTrb0), 1154 (long)le32toh(trb->dwTrb2), 1155 (long)le32toh(trb->dwTrb3)); 1156 1157 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1158 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1159 1160 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1161 1162 temp = trb->dwTrb3; 1163 1164 if (j) 1165 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1166 else 1167 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1168 1169 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1170 1171 phwr->hwr_commands[i].dwTrb3 = temp; 1172 1173 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1174 1175 addr = buf_res.physaddr; 1176 addr += __offsetof(struct xhci_hw_root, hwr_commands[i]); 1177 1178 sc->sc_cmd_addr = htole64(addr); 1179 1180 i++; 1181 1182 if (i == (XHCI_MAX_COMMANDS - 1)) { 1183 if (j) { 1184 temp = htole32(XHCI_TRB_3_TC_BIT | 1185 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1186 XHCI_TRB_3_CYCLE_BIT); 1187 } else { 1188 temp = htole32(XHCI_TRB_3_TC_BIT | 1189 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1190 } 1191 1192 phwr->hwr_commands[i].dwTrb3 = temp; 1193 1194 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1195 1196 i = 0; 1197 j ^= 1; 1198 } 1199 1200 sc->sc_command_idx = i; 1201 sc->sc_command_ccs = j; 1202 1203 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1204 1205 err = (usb_error_t)cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx, 1206 USB_MS_TO_TICKS(timeout_ms)); 1207 1208 /* 1209 * In some error cases event interrupts are not generated. 1210 * Poll one time to see if the command has completed. 1211 */ 1212 if ((err != 0) && (xhci_interrupt_poll(sc) != 0)) { 1213 DPRINTF("Command was completed when polling\n"); 1214 err = USB_ERR_NORMAL_COMPLETION; 1215 } 1216 if (err != 0) { 1217 DPRINTF("Command timeout!\n"); 1218 /* 1219 * After some weeks of continuous operation, it has 1220 * been observed that the ASMedia Technology, ASM1042 1221 * SuperSpeed USB Host Controller can suddenly stop 1222 * accepting commands via the command queue. Try to 1223 * first reset the command queue. If that fails do a 1224 * host controller reset. 1225 */ 1226 if ((timeout == 0) && 1227 (xhci_reset_command_queue_locked(sc) == 0)) { 1228 temp = le32toh(trb->dwTrb3); 1229 1230 /* 1231 * Avoid infinite XHCI reset loops if the set 1232 * address command fails to respond due to a 1233 * non-enumerating device: 1234 */ 1235 if ((XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE) && 1236 ((temp & XHCI_TRB_3_BSR_BIT) == 0)) { 1237 DPRINTF("Set address timeout\n"); 1238 } else { 1239 timeout = 1; 1240 goto retry; 1241 } 1242 } else { 1243 DPRINTF("Controller reset!\n"); 1244 usb_bus_reset_async_locked(&sc->sc_bus); 1245 } 1246 err = USB_ERR_TIMEOUT; 1247 trb->dwTrb2 = 0; 1248 trb->dwTrb3 = 0; 1249 } else { 1250 temp = le32toh(sc->sc_cmd_result[0]); 1251 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) { 1252 if (!((XHCI_TRB_2_ERROR_GET(temp) == XHCI_TRB_ERROR_SLOT_NOT_ON) && 1253 (XHCI_TRB_3_SLOT_GET(le32toh(sc->sc_cmd_result[1]))))) { 1254 err = USB_ERR_IOERROR; 1255 } 1256 } 1257 1258 trb->dwTrb2 = sc->sc_cmd_result[0]; 1259 trb->dwTrb3 = sc->sc_cmd_result[1]; 1260 } 1261 1262 USB_BUS_UNLOCK(&sc->sc_bus); 1263 1264 return (err); 1265} 1266 1267static usb_error_t 1268xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1269{ 1270 struct xhci_trb trb; 1271 uint32_t temp; 1272 usb_error_t err; 1273 1274 DPRINTF("\n"); 1275 1276 trb.qwTrb0 = 0; 1277 trb.dwTrb2 = 0; 1278 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1279 1280 err = xhci_do_command(sc, &trb, XHCI_DO_CMD_TIMEOUT/* ms */); 1281 if (err) 1282 goto done; 1283 1284 temp = le32toh(trb.dwTrb3); 1285 1286 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1287 1288done: 1289 return (err); 1290} 1291 1292static usb_error_t 1293xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1294{ 1295 struct xhci_trb trb; 1296 uint32_t temp; 1297 1298 DPRINTF("\n"); 1299 1300 trb.qwTrb0 = 0; 1301 trb.dwTrb2 = 0; 1302 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1303 XHCI_TRB_3_SLOT_SET(slot_id); 1304 1305 trb.dwTrb3 = htole32(temp); 1306 1307 return (xhci_do_command(sc, &trb, XHCI_DO_CMD_TIMEOUT/* ms */)); 1308} 1309 1310static usb_error_t 1311xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1312 uint8_t bsr, uint8_t slot_id) 1313{ 1314 struct xhci_trb trb; 1315 uint32_t temp; 1316 1317 DPRINTF("\n"); 1318 1319 trb.qwTrb0 = htole64(input_ctx); 1320 trb.dwTrb2 = 0; 1321 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1322 XHCI_TRB_3_SLOT_SET(slot_id); 1323 1324 if (bsr) 1325 temp |= XHCI_TRB_3_BSR_BIT; 1326 1327 trb.dwTrb3 = htole32(temp); 1328 1329 return (xhci_do_command(sc, &trb, XHCI_DO_CMD_TIMEOUT/* ms */)); 1330} 1331 1332static usb_error_t 1333xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address) 1334{ 1335 struct usb_page_search buf_inp; 1336 struct usb_page_search buf_dev; 1337 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1338 struct xhci_hw_dev *hdev; 1339 struct xhci_dev_ctx *pdev; 1340 struct xhci_endpoint_ext *pepext; 1341 uint32_t temp; 1342 uint16_t mps; 1343 usb_error_t err; 1344 uint8_t index; 1345 1346 /* the root HUB case is not handled here */ 1347 if (udev->parent_hub == NULL) 1348 return (USB_ERR_INVAL); 1349 1350 index = udev->controller_slot_id; 1351 1352 hdev = &sc->sc_hw.devs[index]; 1353 1354 if (mtx != NULL) 1355 mtx_unlock(mtx); 1356 1357 XHCI_CMD_LOCK(sc); 1358 1359 switch (hdev->state) { 1360 case XHCI_ST_DEFAULT: 1361 case XHCI_ST_ENABLED: 1362 1363 hdev->state = XHCI_ST_ENABLED; 1364 1365 /* set configure mask to slot and EP0 */ 1366 (void)xhci_configure_mask(udev, 3, 0); 1367 1368 /* configure input slot context structure */ 1369 err = xhci_configure_device(udev); 1370 1371 if (err != 0) { 1372 DPRINTF("Could not configure device\n"); 1373 break; 1374 } 1375 1376 /* configure input endpoint context structure */ 1377 switch (udev->speed) { 1378 case USB_SPEED_LOW: 1379 case USB_SPEED_FULL: 1380 mps = 8; 1381 break; 1382 case USB_SPEED_HIGH: 1383 mps = 64; 1384 break; 1385 default: 1386 mps = 512; 1387 break; 1388 } 1389 1390 pepext = xhci_get_endpoint_ext(udev, 1391 &udev->ctrl_ep_desc); 1392 1393 /* ensure the control endpoint is setup again */ 1394 USB_BUS_LOCK(udev->bus); 1395 pepext->trb_halted = 1; 1396 pepext->trb_running = 0; 1397 USB_BUS_UNLOCK(udev->bus); 1398 1399 err = xhci_configure_endpoint(udev, 1400 &udev->ctrl_ep_desc, pepext, 1401 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT); 1402 1403 if (err != 0) { 1404 DPRINTF("Could not configure default endpoint\n"); 1405 break; 1406 } 1407 1408 /* execute set address command */ 1409 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1410 1411 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1412 (address == 0), index); 1413 1414 if (err != 0) { 1415 temp = le32toh(sc->sc_cmd_result[0]); 1416 if ((address == 0) && (sc->sc_port_route != NULL) && 1417 (XHCI_TRB_2_ERROR_GET(temp) == 1418 XHCI_TRB_ERROR_PARAMETER)) { 1419 /* LynxPoint XHCI - ports are not switchable */ 1420 /* Un-route all ports from the XHCI */ 1421 (void)sc->sc_port_route(sc->sc_bus.parent, 0, ~0); 1422 } 1423 DPRINTF("Could not set address " 1424 "for slot %u.\n", index); 1425 if (address != 0) 1426 break; 1427 } 1428 1429 /* update device address to new value */ 1430 1431 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1432 pdev = buf_dev.buffer; 1433 usb_pc_cpu_invalidate(&hdev->device_pc); 1434 1435 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3); 1436 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1437 1438 /* update device state to new value */ 1439 1440 if (address != 0) 1441 hdev->state = XHCI_ST_ADDRESSED; 1442 else 1443 hdev->state = XHCI_ST_DEFAULT; 1444 break; 1445 1446 default: 1447 DPRINTF("Wrong state for set address.\n"); 1448 err = USB_ERR_IOERROR; 1449 break; 1450 } 1451 XHCI_CMD_UNLOCK(sc); 1452 1453 if (mtx != NULL) 1454 mtx_lock(mtx); 1455 1456 return (err); 1457} 1458 1459static usb_error_t 1460xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1461 uint8_t deconfigure, uint8_t slot_id) 1462{ 1463 struct xhci_trb trb; 1464 uint32_t temp; 1465 1466 DPRINTF("\n"); 1467 1468 trb.qwTrb0 = htole64(input_ctx); 1469 trb.dwTrb2 = 0; 1470 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1471 XHCI_TRB_3_SLOT_SET(slot_id); 1472 1473 if (deconfigure) 1474 temp |= XHCI_TRB_3_DCEP_BIT; 1475 1476 trb.dwTrb3 = htole32(temp); 1477 1478 return (xhci_do_command(sc, &trb, XHCI_DO_CMD_TIMEOUT/* ms */)); 1479} 1480 1481static usb_error_t 1482xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1483 uint8_t slot_id) 1484{ 1485 struct xhci_trb trb; 1486 uint32_t temp; 1487 1488 DPRINTF("\n"); 1489 1490 trb.qwTrb0 = htole64(input_ctx); 1491 trb.dwTrb2 = 0; 1492 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1493 XHCI_TRB_3_SLOT_SET(slot_id); 1494 trb.dwTrb3 = htole32(temp); 1495 1496 return (xhci_do_command(sc, &trb, XHCI_DO_CMD_TIMEOUT/* ms */)); 1497} 1498 1499static usb_error_t 1500xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1501 uint8_t ep_id, uint8_t slot_id) 1502{ 1503 struct xhci_trb trb; 1504 uint32_t temp; 1505 1506 DPRINTF("\n"); 1507 1508 trb.qwTrb0 = 0; 1509 trb.dwTrb2 = 0; 1510 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1511 XHCI_TRB_3_SLOT_SET(slot_id) | 1512 XHCI_TRB_3_EP_SET(ep_id); 1513 1514 if (preserve) 1515 temp |= XHCI_TRB_3_PRSV_BIT; 1516 1517 trb.dwTrb3 = htole32(temp); 1518 1519 return (xhci_do_command(sc, &trb, XHCI_DO_CMD_TIMEOUT/* ms */)); 1520} 1521 1522static usb_error_t 1523xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1524 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1525{ 1526 struct xhci_trb trb; 1527 uint32_t temp; 1528 1529 DPRINTF("\n"); 1530 1531 trb.qwTrb0 = htole64(dequeue_ptr); 1532 1533 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1534 trb.dwTrb2 = htole32(temp); 1535 1536 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1537 XHCI_TRB_3_SLOT_SET(slot_id) | 1538 XHCI_TRB_3_EP_SET(ep_id); 1539 trb.dwTrb3 = htole32(temp); 1540 1541 return (xhci_do_command(sc, &trb, XHCI_DO_CMD_TIMEOUT/* ms */)); 1542} 1543 1544static usb_error_t 1545xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1546 uint8_t ep_id, uint8_t slot_id) 1547{ 1548 struct xhci_trb trb; 1549 uint32_t temp; 1550 1551 DPRINTF("\n"); 1552 1553 trb.qwTrb0 = 0; 1554 trb.dwTrb2 = 0; 1555 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1556 XHCI_TRB_3_SLOT_SET(slot_id) | 1557 XHCI_TRB_3_EP_SET(ep_id); 1558 1559 if (suspend) 1560 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1561 1562 trb.dwTrb3 = htole32(temp); 1563 1564 return (xhci_do_command(sc, &trb, XHCI_DO_CMD_TIMEOUT/* ms */)); 1565} 1566 1567static usb_error_t 1568xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1569{ 1570 struct xhci_trb trb; 1571 uint32_t temp; 1572 1573 DPRINTF("\n"); 1574 1575 trb.qwTrb0 = 0; 1576 trb.dwTrb2 = 0; 1577 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1578 XHCI_TRB_3_SLOT_SET(slot_id); 1579 1580 trb.dwTrb3 = htole32(temp); 1581 1582 return (xhci_do_command(sc, &trb, XHCI_DO_CMD_TIMEOUT/* ms */)); 1583} 1584 1585/*------------------------------------------------------------------------* 1586 * xhci_interrupt - XHCI interrupt handler 1587 *------------------------------------------------------------------------*/ 1588void 1589xhci_interrupt(unsigned int irq, struct xhci_softc *sc) 1590{ 1591 uint32_t status; 1592 uint32_t temp; 1593 1594 USB_BUS_LOCK(&sc->sc_bus); 1595 1596 status = XREAD4(sc, oper, XHCI_USBSTS); 1597 1598 /* acknowledge interrupts, if any */ 1599 if (status != 0) { 1600 XWRITE4(sc, oper, XHCI_USBSTS, status); 1601 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status); 1602 } 1603 1604 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 1605 1606 /* force clearing of pending interrupts */ 1607 if (temp & XHCI_IMAN_INTR_PEND) 1608 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 1609 1610 /* check for event(s) */ 1611 (void)xhci_interrupt_poll(sc); 1612 1613 if (status & (XHCI_STS_PCD | XHCI_STS_HCH | 1614 XHCI_STS_HSE | XHCI_STS_HCE)) { 1615 if (status & XHCI_STS_PCD) { 1616 xhci_root_intr(sc); 1617 } 1618 1619 if (status & XHCI_STS_HCH) { 1620 PRINTK("%s: host controller halted\n", 1621 __FUNCTION__); 1622 } 1623 1624 if (status & XHCI_STS_HSE) { 1625 PRINTK("%s: host system error\n", 1626 __FUNCTION__); 1627 } 1628 1629 if (status & XHCI_STS_HCE) { 1630 PRINTK("%s: host controller error\n", 1631 __FUNCTION__); 1632 } 1633 } 1634 USB_BUS_UNLOCK(&sc->sc_bus); 1635} 1636 1637/*------------------------------------------------------------------------* 1638 * xhci_timeout - XHCI timeout handler 1639 *------------------------------------------------------------------------*/ 1640static void 1641xhci_timeout(void *arg) 1642{ 1643 struct usb_xfer *xfer = arg; 1644 1645 DPRINTF("xfer=%p\n", xfer); 1646 1647 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1648 1649 /* transfer is transferred */ 1650 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1651} 1652 1653static void 1654xhci_do_poll(struct usb_bus *bus) 1655{ 1656 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1657 1658 USB_BUS_LOCK(&sc->sc_bus); 1659 (void)xhci_interrupt_poll(sc); 1660 USB_BUS_UNLOCK(&sc->sc_bus); 1661} 1662 1663static void 1664xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) 1665{ 1666 struct usb_page_search buf_res; 1667 struct xhci_td *td; 1668 struct xhci_td *td_next; 1669 struct xhci_td *td_alt_next; 1670 struct xhci_td *td_first; 1671 uint32_t buf_offset; 1672 uint32_t average; 1673 uint32_t len_old; 1674 uint32_t npkt_off; 1675 uint32_t dword; 1676 uint8_t shortpkt_old; 1677 uint8_t precompute; 1678 uint8_t x; 1679 1680 td_alt_next = NULL; 1681 buf_offset = 0; 1682 shortpkt_old = temp->shortpkt; 1683 len_old = temp->len; 1684 npkt_off = 0; 1685 precompute = 1; 1686 1687restart: 1688 1689 td = temp->td; 1690 td_next = td_first = temp->td_next; 1691 1692 while (1) { 1693 if (temp->len == 0) { 1694 if (temp->shortpkt) 1695 break; 1696 1697 /* send a Zero Length Packet, ZLP, last */ 1698 1699 temp->shortpkt = 1; 1700 average = 0; 1701 1702 } else { 1703 average = temp->average; 1704 1705 if (temp->len < average) { 1706 if (temp->len % temp->max_packet_size) { 1707 temp->shortpkt = 1; 1708 } 1709 average = temp->len; 1710 } 1711 } 1712 1713 if (td_next == NULL) 1714 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__); 1715 1716 /* get next TD */ 1717 1718 td = td_next; 1719 td_next = td->obj_next; 1720 1721 /* check if we are pre-computing */ 1722 1723 if (precompute) { 1724 /* update remaining length */ 1725 1726 temp->len -= average; 1727 1728 continue; 1729 } 1730 /* fill out current TD */ 1731 1732 td->len = average; 1733 td->remainder = 0; 1734 td->status = 0; 1735 1736 /* update remaining length */ 1737 1738 temp->len -= average; 1739 1740 /* reset TRB index */ 1741 1742 x = 0; 1743 1744 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { 1745 /* immediate data */ 1746 1747 if (average > 8) 1748 average = 8; 1749 1750 td->td_trb[0].qwTrb0 = 0; 1751 1752 usbd_copy_out(temp->pc, temp->offset + buf_offset, 1753 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, 1754 average); 1755 1756 dword = XHCI_TRB_2_BYTES_SET(8) | 1757 XHCI_TRB_2_TDSZ_SET(0) | 1758 XHCI_TRB_2_IRQ_SET(0); 1759 1760 td->td_trb[0].dwTrb2 = htole32(dword); 1761 1762 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 1763 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; 1764 1765 /* check wLength */ 1766 if (td->td_trb[0].qwTrb0 & 1767 htole64(XHCI_TRB_0_WLENGTH_MASK)) { 1768 if (td->td_trb[0].qwTrb0 & 1769 htole64(XHCI_TRB_0_DIR_IN_MASK)) 1770 dword |= XHCI_TRB_3_TRT_IN; 1771 else 1772 dword |= XHCI_TRB_3_TRT_OUT; 1773 } 1774 1775 td->td_trb[0].dwTrb3 = htole32(dword); 1776#ifdef USB_DEBUG 1777 xhci_dump_trb(&td->td_trb[x]); 1778#endif 1779 x++; 1780 1781 } else do { 1782 uint32_t npkt; 1783 1784 /* fill out buffer pointers */ 1785 1786 if (average == 0) { 1787 (void)memset_s(&buf_res, sizeof(buf_res), 0, sizeof(buf_res)); 1788 } else { 1789 usbd_get_page(temp->pc, temp->offset + 1790 buf_offset, &buf_res); 1791 1792 /* get length to end of page */ 1793 if (buf_res.length > average) 1794 buf_res.length = average; 1795 1796 /* check for maximum length */ 1797 if (buf_res.length > XHCI_TD_PAGE_SIZE) 1798 buf_res.length = XHCI_TD_PAGE_SIZE; 1799 1800 npkt_off += buf_res.length; 1801 } 1802 1803 /* set up npkt */ 1804 npkt = (len_old - npkt_off + temp->max_packet_size - 1) / 1805 temp->max_packet_size; 1806 1807 if (npkt == 0) 1808 npkt = 1; 1809 else if (npkt > 31) 1810 npkt = 31; 1811 1812 /* fill out TRB's */ 1813 td->td_trb[x].qwTrb0 = 1814 htole64((uint64_t)buf_res.physaddr); 1815 1816 dword = 1817 XHCI_TRB_2_BYTES_SET(buf_res.length) | 1818 XHCI_TRB_2_TDSZ_SET(npkt) | 1819 XHCI_TRB_2_IRQ_SET(0); 1820 1821 td->td_trb[x].dwTrb2 = htole32(dword); 1822 1823 switch (temp->trb_type) { 1824 case XHCI_TRB_TYPE_ISOCH: 1825 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1826 XHCI_TRB_3_TBC_SET(temp->tbc) | 1827 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1828 if (td != td_first) { 1829 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1830 } else if (temp->do_isoc_sync != 0) { 1831 temp->do_isoc_sync = 0; 1832 /* wait until "isoc_frame" */ 1833 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1834 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8); 1835 } else { 1836 /* start data transfer at next interval */ 1837 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1838 XHCI_TRB_3_ISO_SIA_BIT; 1839 } 1840 if (temp->direction == UE_DIR_IN) 1841 dword |= XHCI_TRB_3_ISP_BIT; 1842 break; 1843 case XHCI_TRB_TYPE_DATA_STAGE: 1844 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1845 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE); 1846 if (temp->direction == UE_DIR_IN) 1847 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1848 /* 1849 * Section 3.2.9 in the XHCI 1850 * specification about control 1851 * transfers says that we should use a 1852 * normal-TRB if there are more TRBs 1853 * extending the data-stage 1854 * TRB. Update the "trb_type". 1855 */ 1856 temp->trb_type = XHCI_TRB_TYPE_NORMAL; 1857 break; 1858 case XHCI_TRB_TYPE_STATUS_STAGE: 1859 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1860 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE); 1861 if (temp->direction == UE_DIR_IN) 1862 dword |= XHCI_TRB_3_DIR_IN; 1863 break; 1864 default: /* XHCI_TRB_TYPE_NORMAL */ 1865 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1866 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1867 if (temp->direction == UE_DIR_IN) 1868 dword |= XHCI_TRB_3_ISP_BIT; 1869 break; 1870 } 1871 td->td_trb[x].dwTrb3 = htole32(dword); 1872 1873 average -= buf_res.length; 1874 buf_offset += buf_res.length; 1875#ifdef USB_DEBUG 1876 xhci_dump_trb(&td->td_trb[x]); 1877#endif 1878 x++; 1879 1880 } while (average != 0); 1881 1882 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1883 1884 /* store number of data TRB's */ 1885 1886 td->ntrb = x; 1887 1888 DPRINTF("NTRB=%u\n", x); 1889 1890 /* fill out link TRB */ 1891 1892 if (td_next != NULL) { 1893 /* link the current TD with the next one */ 1894 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); 1895 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); 1896 } else { 1897 /* this field will get updated later */ 1898 DPRINTF("NOLINK\n"); 1899 } 1900 1901 dword = XHCI_TRB_2_IRQ_SET(0); 1902 1903 td->td_trb[x].dwTrb2 = htole32(dword); 1904 1905 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1906 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT | 1907 /* 1908 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint 1909 * frame only receives a single short packet event 1910 * by setting the CHAIN bit in the LINK field. In 1911 * addition some XHCI controllers have problems 1912 * sending a ZLP unless the CHAIN-BIT is set in 1913 * the LINK TRB. 1914 */ 1915 XHCI_TRB_3_CHAIN_BIT; 1916 1917 td->td_trb[x].dwTrb3 = htole32(dword); 1918 1919 td->alt_next = td_alt_next; 1920#ifdef USB_DEBUG 1921 xhci_dump_trb(&td->td_trb[x]); 1922#endif 1923 usb_pc_cpu_flush(td->page_cache); 1924 } 1925 1926 if (precompute) { 1927 precompute = 0; 1928 1929 /* set up alt next pointer, if any */ 1930 if (temp->last_frame) { 1931 td_alt_next = NULL; 1932 } else { 1933 /* we use this field internally */ 1934 td_alt_next = td_next; 1935 } 1936 1937 /* restore */ 1938 temp->shortpkt = shortpkt_old; 1939 temp->len = len_old; 1940 goto restart; 1941 } 1942 1943 /* 1944 * Remove cycle bit from the first TRB if we are 1945 * stepping them: 1946 */ 1947 if (temp->step_td != 0) { 1948 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1949 usb_pc_cpu_flush(td_first->page_cache); 1950 } 1951 1952 /* clear TD SIZE to zero, hence this is the last TRB */ 1953 /* remove chain bit because this is the last data TRB in the chain */ 1954 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15)); 1955 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1956 /* remove CHAIN-BIT from last LINK TRB */ 1957 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1958 1959 usb_pc_cpu_flush(td->page_cache); 1960 1961 temp->td = td; 1962 temp->td_next = td_next; 1963} 1964 1965static void 1966xhci_setup_generic_chain(struct usb_xfer *xfer) 1967{ 1968 struct xhci_std_temp temp; 1969 struct xhci_td *td; 1970 uint32_t x; 1971 uint32_t y; 1972 uint8_t mult; 1973 1974 temp.do_isoc_sync = 0; 1975 temp.step_td = 0; 1976 temp.tbc = 0; 1977 temp.tlbpc = 0; 1978 temp.average = xfer->max_hc_frame_size; 1979 temp.max_packet_size = xfer->max_packet_size; 1980 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); 1981 temp.pc = NULL; 1982 temp.last_frame = 0; 1983 temp.offset = 0; 1984 temp.multishort = xfer->flags_int.isochronous_xfr || 1985 xfer->flags_int.control_xfr || 1986 xfer->flags_int.short_frames_ok; 1987 1988 /* toggle the DMA set we are using */ 1989 xfer->flags_int.curr_dma_set ^= 1; 1990 1991 /* get next DMA set */ 1992 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1993 1994 temp.td = NULL; 1995 temp.td_next = td; 1996 1997 xfer->td_transfer_first = td; 1998 xfer->td_transfer_cache = td; 1999 2000 if (xfer->flags_int.isochronous_xfr) { 2001 uint8_t shift; 2002 2003 /* compute multiplier for ISOCHRONOUS transfers */ 2004 mult = xfer->endpoint->ecomp ? 2005 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes) 2006 : 0; 2007 /* check for USB 2.0 multiplier */ 2008 if (mult == 0) { 2009 mult = (xfer->endpoint->edesc-> 2010 wMaxPacketSize[1] >> 3) & 3; 2011 } 2012 /* range check */ 2013 if (mult > 2) 2014 mult = 3; 2015 else 2016 mult++; 2017 2018 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); 2019 2020 DPRINTF("MFINDEX=0x%08x\n", x); 2021 2022 switch (usbd_get_speed(xfer->xroot->udev)) { 2023 case USB_SPEED_FULL: 2024 shift = 3; 2025 temp.isoc_delta = 8; /* 1ms */ 2026 x += temp.isoc_delta - 1; 2027 x &= ~(temp.isoc_delta - 1); 2028 break; 2029 default: 2030 shift = usbd_xfer_get_fps_shift(xfer); 2031 temp.isoc_delta = 1U << shift; 2032 x += temp.isoc_delta - 1; 2033 x &= ~(temp.isoc_delta - 1); 2034 /* simple frame load balancing */ 2035 x += xfer->endpoint->usb_uframe; 2036 break; 2037 } 2038 2039 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next); 2040 2041 if ((xfer->endpoint->is_synced == 0) || 2042 (y < (xfer->nframes << shift)) || 2043 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) { 2044 /* 2045 * If there is data underflow or the pipe 2046 * queue is empty we schedule the transfer a 2047 * few frames ahead of the current frame 2048 * position. Else two isochronous transfers 2049 * might overlap. 2050 */ 2051 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8)); 2052 xfer->endpoint->is_synced = 1; 2053 temp.do_isoc_sync = 1; 2054 2055 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2056 } 2057 2058 /* compute isochronous completion time */ 2059 2060 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7)); 2061 2062 xfer->isoc_time_complete = 2063 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) + 2064 (y / 8) + (((xfer->nframes << shift) + 7) / 8); 2065 2066 x = 0; 2067 temp.isoc_frame = xfer->endpoint->isoc_next; 2068 temp.trb_type = XHCI_TRB_TYPE_ISOCH; 2069 2070 xfer->endpoint->isoc_next += xfer->nframes << shift; 2071 2072 } else if (xfer->flags_int.control_xfr) { 2073 /* check if we should prepend a setup message */ 2074 2075 if (xfer->flags_int.control_hdr) { 2076 temp.len = xfer->frlengths[0]; 2077 temp.pc = xfer->frbuffers + 0; 2078 temp.shortpkt = temp.len ? 1 : 0; 2079 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; 2080 temp.direction = 0; 2081 2082 /* check for last frame */ 2083 if (xfer->nframes == 1) { 2084 /* no STATUS stage yet, SETUP is last */ 2085 if (xfer->flags_int.control_act) 2086 temp.last_frame = 1; 2087 } 2088 2089 xhci_setup_generic_chain_sub(&temp); 2090 } 2091 x = 1; 2092 mult = 1; 2093 temp.isoc_delta = 0; 2094 temp.isoc_frame = 0; 2095 temp.trb_type = xfer->flags_int.control_did_data ? 2096 XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE; 2097 } else { 2098 x = 0; 2099 mult = 1; 2100 temp.isoc_delta = 0; 2101 temp.isoc_frame = 0; 2102 temp.trb_type = XHCI_TRB_TYPE_NORMAL; 2103 } 2104 2105 if (x != xfer->nframes) { 2106 /* set up page_cache pointer */ 2107 temp.pc = xfer->frbuffers + x; 2108 /* set endpoint direction */ 2109 temp.direction = UE_GET_DIR(xfer->endpointno); 2110 } 2111 2112 while (x != xfer->nframes) { 2113 /* DATA0 / DATA1 message */ 2114 2115 temp.len = xfer->frlengths[x]; 2116 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && 2117 x != 0 && temp.multishort == 0); 2118 2119 x++; 2120 2121 if (x == xfer->nframes) { 2122 if (xfer->flags_int.control_xfr) { 2123 /* no STATUS stage yet, DATA is last */ 2124 if (xfer->flags_int.control_act) 2125 temp.last_frame = 1; 2126 } else { 2127 temp.last_frame = 1; 2128 } 2129 } 2130 if (temp.len == 0) { 2131 /* make sure that we send an USB packet */ 2132 2133 temp.shortpkt = 0; 2134 2135 temp.tbc = 0; 2136 temp.tlbpc = mult - 1; 2137 2138 } else if (xfer->flags_int.isochronous_xfr) { 2139 uint8_t tdpc; 2140 2141 /* 2142 * Isochronous transfers don't have short 2143 * packet termination: 2144 */ 2145 2146 temp.shortpkt = 1; 2147 2148 /* isochronous transfers have a transfer limit */ 2149 2150 if (temp.len > xfer->max_frame_size) 2151 temp.len = xfer->max_frame_size; 2152 2153 /* compute TD packet count */ 2154 tdpc = (temp.len + xfer->max_packet_size - 1) / 2155 xfer->max_packet_size; 2156 2157 temp.tbc = ((tdpc + mult - 1) / mult) - 1; 2158 temp.tlbpc = (tdpc % mult); 2159 2160 if (temp.tlbpc == 0) 2161 temp.tlbpc = mult - 1; 2162 else 2163 temp.tlbpc--; 2164 } else { 2165 /* regular data transfer */ 2166 2167 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; 2168 } 2169 2170 xhci_setup_generic_chain_sub(&temp); 2171 2172 if (xfer->flags_int.isochronous_xfr) { 2173 temp.offset += xfer->frlengths[x - 1]; 2174 temp.isoc_frame += temp.isoc_delta; 2175 } else { 2176 /* get next Page Cache pointer */ 2177 temp.pc = xfer->frbuffers + x; 2178 } 2179 } 2180 2181 /* check if we should append a status stage */ 2182 2183 if (xfer->flags_int.control_xfr && 2184 !xfer->flags_int.control_act) { 2185 /* 2186 * Send a DATA1 message and invert the current 2187 * endpoint direction. 2188 */ 2189 if (xhcictlstep || temp.sc->sc_ctlstep) { 2190 /* 2191 * Some XHCI controllers will not delay the 2192 * status stage until the next SOF. Force this 2193 * behaviour to avoid failed control 2194 * transfers. 2195 */ 2196 temp.step_td = (xfer->nframes != 0); 2197 } else { 2198 temp.step_td = 0; 2199 } 2200 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; 2201 temp.len = 0; 2202 temp.pc = NULL; 2203 temp.shortpkt = 0; 2204 temp.last_frame = 1; 2205 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; 2206 2207 xhci_setup_generic_chain_sub(&temp); 2208 } 2209 2210 td = temp.td; 2211 2212 /* must have at least one frame! */ 2213 2214 xfer->td_transfer_last = td; 2215 2216 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 2217} 2218 2219static void 2220xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2221{ 2222 struct usb_page_search buf_res; 2223 struct xhci_dev_ctx_addr *pdctxa; 2224 2225 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2226 2227 pdctxa = buf_res.buffer; 2228 2229 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2230 2231 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2232 2233 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2234} 2235 2236static usb_error_t 2237xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2238{ 2239 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2240 struct usb_page_search buf_inp; 2241 struct xhci_input_dev_ctx *pinp; 2242 uint32_t temp; 2243 uint8_t index; 2244 uint8_t x; 2245 2246 index = udev->controller_slot_id; 2247 2248 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2249 2250 pinp = buf_inp.buffer; 2251 2252 if (drop) { 2253 mask &= XHCI_INCTX_NON_CTRL_MASK; 2254 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask); 2255 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0); 2256 } else { 2257 /* 2258 * Some hardware requires that we drop the endpoint 2259 * context before adding it again: 2260 */ 2261 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 2262 mask & XHCI_INCTX_NON_CTRL_MASK); 2263 2264 /* Add new endpoint context */ 2265 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask); 2266 2267 /* find most significant set bit */ 2268 for (x = 31; x != 1; x--) { 2269 if (mask & (1 << x)) 2270 break; 2271 } 2272 2273 /* adjust */ 2274 x--; 2275 2276 /* figure out the maximum number of contexts */ 2277 if (x > sc->sc_hw.devs[index].context_num) 2278 sc->sc_hw.devs[index].context_num = x; 2279 else 2280 x = sc->sc_hw.devs[index].context_num; 2281 2282 /* update number of contexts */ 2283 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0); 2284 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); 2285 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); 2286 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2287 } 2288 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2289 return (USB_ERR_NORMAL_COMPLETION); 2290} 2291 2292static usb_error_t 2293xhci_configure_endpoint(struct usb_device *udev, 2294 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext, 2295 uint16_t interval, uint8_t max_packet_count, 2296 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size, 2297 uint16_t max_frame_size, uint8_t ep_mode) 2298{ 2299 struct usb_page_search buf_inp; 2300 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2301 struct xhci_input_dev_ctx *pinp; 2302 uint64_t ring_addr = pepext->physaddr; 2303 uint32_t temp; 2304 uint8_t index; 2305 uint8_t epno; 2306 uint8_t type; 2307 2308 index = udev->controller_slot_id; 2309 2310 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2311 2312 pinp = buf_inp.buffer; 2313 2314 epno = edesc->bEndpointAddress; 2315 type = edesc->bmAttributes & UE_XFERTYPE; 2316 2317 if (type == UE_CONTROL) 2318 epno |= UE_DIR_IN; 2319 2320 epno = XHCI_EPNO2EPID(epno); 2321 2322 if (epno == 0) 2323 return (USB_ERR_NO_PIPE); /* invalid */ 2324 2325 if (max_packet_count == 0) 2326 return (USB_ERR_BAD_BUFSIZE); 2327 2328 max_packet_count--; 2329 2330 if (mult == 0) 2331 return (USB_ERR_BAD_BUFSIZE); 2332 2333 /* store endpoint mode */ 2334 pepext->trb_ep_mode = ep_mode; 2335 /* store bMaxPacketSize for control endpoints */ 2336 pepext->trb_ep_maxp = edesc->wMaxPacketSize[0]; 2337 usb_pc_cpu_flush(pepext->page_cache); 2338 2339 if (ep_mode == USB_EP_MODE_STREAMS) { 2340 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2341 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) | 2342 XHCI_EPCTX_0_LSA_SET(1); 2343 2344 ring_addr += sizeof(struct xhci_trb) * 2345 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS; 2346 } else { 2347 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2348 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2349 XHCI_EPCTX_0_LSA_SET(0); 2350 2351 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2352 } 2353 2354 switch (udev->speed) { 2355 case USB_SPEED_FULL: 2356 case USB_SPEED_LOW: 2357 /* 1ms -> 125us */ 2358 fps_shift += 3; 2359 break; 2360 default: 2361 break; 2362 } 2363 2364 switch (type) { 2365 case UE_INTERRUPT: 2366 if (fps_shift > 3) 2367 fps_shift--; 2368 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2369 break; 2370 case UE_ISOCHRONOUS: 2371 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2372 2373 switch (udev->speed) { 2374 case USB_SPEED_SUPER: 2375 if (mult > 3) 2376 mult = 3; 2377 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2378 max_packet_count /= mult; 2379 break; 2380 default: 2381 break; 2382 } 2383 break; 2384 default: 2385 break; 2386 } 2387 2388 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp); 2389 2390 temp = 2391 XHCI_EPCTX_1_HID_SET(0) | 2392 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2393 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2394 2395 /* 2396 * Always enable the "three strikes and you are gone" feature 2397 * except for ISOCHRONOUS endpoints. This is suggested by 2398 * section 4.3.3 in the XHCI specification about device slot 2399 * initialisation. 2400 */ 2401 if (type != UE_ISOCHRONOUS) 2402 temp |= XHCI_EPCTX_1_CERR_SET(3); 2403 2404 switch (type) { 2405 case UE_CONTROL: 2406 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2407 break; 2408 case UE_ISOCHRONOUS: 2409 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2410 break; 2411 case UE_BULK: 2412 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2413 break; 2414 default: 2415 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2416 break; 2417 } 2418 2419 /* check for IN direction */ 2420 if (epno & 1) 2421 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2422 2423 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp); 2424 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr); 2425 2426 switch (edesc->bmAttributes & UE_XFERTYPE) { 2427 case UE_INTERRUPT: 2428 case UE_ISOCHRONOUS: 2429 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2430 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2431 max_frame_size)); 2432 break; 2433 case UE_CONTROL: 2434 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2435 break; 2436 default: 2437 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2438 break; 2439 } 2440 2441 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp); 2442 2443#ifdef USB_DEBUG 2444 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]); 2445#endif 2446 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2447 2448 return (USB_ERR_NORMAL_COMPLETION); /* success */ 2449} 2450 2451static usb_error_t 2452xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2453{ 2454 struct xhci_endpoint_ext *pepext; 2455 struct usb_endpoint_ss_comp_descriptor *ecomp; 2456 usb_stream_t x; 2457 2458 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2459 xfer->endpoint->edesc); 2460 2461 ecomp = xfer->endpoint->ecomp; 2462 2463 for (x = 0; x != XHCI_MAX_STREAMS; x++) { 2464 uint64_t temp; 2465 2466 /* halt any transfers */ 2467 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0; 2468 2469 /* compute start of TRB ring for stream "x" */ 2470 temp = pepext->physaddr + 2471 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) + 2472 XHCI_SCTX_0_SCT_SEC_TR_RING; 2473 2474 /* make tree structure */ 2475 pepext->trb[(XHCI_MAX_TRANSFERS * 2476 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); 2477 2478 /* reserved fields */ 2479 pepext->trb[(XHCI_MAX_TRANSFERS * 2480 XHCI_MAX_STREAMS) + x].dwTrb2 = 0; 2481 pepext->trb[(XHCI_MAX_TRANSFERS * 2482 XHCI_MAX_STREAMS) + x].dwTrb3 = 0; 2483 } 2484 usb_pc_cpu_flush(pepext->page_cache); 2485 2486 return (xhci_configure_endpoint(xfer->xroot->udev, 2487 xfer->endpoint->edesc, pepext, 2488 xfer->interval, xfer->max_packet_count, 2489 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1, 2490 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2491 xfer->max_frame_size, xfer->endpoint->ep_mode)); 2492} 2493 2494static usb_error_t 2495xhci_configure_device(struct usb_device *udev) 2496{ 2497 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2498 struct usb_page_search buf_inp; 2499 struct usb_page_cache *pcinp; 2500 struct xhci_input_dev_ctx *pinp; 2501 struct usb_device *hubdev; 2502 uint32_t temp; 2503 uint32_t route; 2504 uint32_t rh_port; 2505 uint8_t is_hub; 2506 uint8_t index; 2507 uint8_t depth; 2508 2509 index = udev->controller_slot_id; 2510 2511 DPRINTF("index=%u\n", index); 2512 2513 pcinp = &sc->sc_hw.devs[index].input_pc; 2514 2515 usbd_get_page(pcinp, 0, &buf_inp); 2516 2517 pinp = buf_inp.buffer; 2518 2519 rh_port = 0; 2520 route = 0; 2521 2522 /* figure out route string and root HUB port number */ 2523 2524 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2525 if (hubdev->parent_hub == NULL) 2526 break; 2527 2528 depth = hubdev->parent_hub->depth; 2529 2530 /* 2531 * NOTE: HS/FS/LS devices and the SS root HUB can have 2532 * more than 15 ports 2533 */ 2534 2535 rh_port = hubdev->port_no; 2536 2537 if (depth == 0) 2538 break; 2539 2540 if (rh_port > 15) 2541 rh_port = 15; 2542 2543 if (depth < 6) 2544 route |= rh_port << (4 * (depth - 1)); 2545 } 2546 2547 DPRINTF("Route=0x%08x\n", route); 2548 2549 temp = XHCI_SCTX_0_ROUTE_SET(route) | 2550 XHCI_SCTX_0_CTX_NUM_SET( 2551 sc->sc_hw.devs[index].context_num + 1); 2552 2553 switch (udev->speed) { 2554 case USB_SPEED_LOW: 2555 temp |= XHCI_SCTX_0_SPEED_SET(2); 2556 if ((udev->parent_hs_hub != NULL) && 2557 (udev->parent_hs_hub->ddesc.bDeviceProtocol == 2558 UDPROTO_HSHUBMTT)) { 2559 DPRINTF("Device inherits MTT\n"); 2560 temp |= XHCI_SCTX_0_MTT_SET(1); 2561 } 2562 break; 2563 case USB_SPEED_HIGH: 2564 temp |= XHCI_SCTX_0_SPEED_SET(3); 2565 if ((sc->sc_hw.devs[index].nports != 0) && 2566 (udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT)) { 2567 DPRINTF("HUB supports MTT\n"); 2568 temp |= XHCI_SCTX_0_MTT_SET(1); 2569 } 2570 break; 2571 case USB_SPEED_FULL: 2572 temp |= XHCI_SCTX_0_SPEED_SET(1); 2573 if ((udev->parent_hs_hub != NULL) && 2574 (udev->parent_hs_hub->ddesc.bDeviceProtocol == 2575 UDPROTO_HSHUBMTT)) { 2576 DPRINTF("Device inherits MTT\n"); 2577 temp |= XHCI_SCTX_0_MTT_SET(1); 2578 } 2579 break; 2580 default: 2581 temp |= XHCI_SCTX_0_SPEED_SET(4); 2582 break; 2583 } 2584 2585 is_hub = sc->sc_hw.devs[index].nports != 0 && 2586 (udev->speed == USB_SPEED_SUPER || 2587 udev->speed == USB_SPEED_HIGH); 2588 2589 if (is_hub) 2590 temp |= XHCI_SCTX_0_HUB_SET(1); 2591 2592 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2593 2594 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2595 2596 if (is_hub) { 2597 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2598 sc->sc_hw.devs[index].nports); 2599 } 2600 2601 switch (udev->speed) { 2602 case USB_SPEED_SUPER: 2603 switch (sc->sc_hw.devs[index].state) { 2604 case XHCI_ST_ADDRESSED: 2605 case XHCI_ST_CONFIGURED: 2606 /* enable power save */ 2607 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max); 2608 break; 2609 default: 2610 /* disable power save */ 2611 break; 2612 } 2613 break; 2614 default: 2615 break; 2616 } 2617 2618 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp); 2619 2620 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2621 2622 if (is_hub) { 2623 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( 2624 sc->sc_hw.devs[index].tt); 2625 } 2626 2627 hubdev = udev->parent_hs_hub; 2628 2629 /* check if we should activate the transaction translator */ 2630 switch (udev->speed) { 2631 case USB_SPEED_FULL: 2632 case USB_SPEED_LOW: 2633 if (hubdev != NULL) { 2634 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2635 hubdev->controller_slot_id); 2636 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2637 udev->hs_port_no); 2638 } 2639 break; 2640 default: 2641 break; 2642 } 2643 2644 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp); 2645 2646 /* 2647 * These fields should be initialized to zero, according to 2648 * XHCI section 6.2.2 - slot context: 2649 */ 2650 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) | 2651 XHCI_SCTX_3_SLOT_STATE_SET(0); 2652 2653 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp); 2654 2655#ifdef USB_DEBUG 2656 xhci_dump_device(sc, &pinp->ctx_slot); 2657#endif 2658 usb_pc_cpu_flush(pcinp); 2659 2660 return (USB_ERR_NORMAL_COMPLETION); /* success */ 2661} 2662 2663static usb_error_t 2664xhci_alloc_device_ext(struct usb_device *udev) 2665{ 2666 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2667 struct usb_page_search buf_dev; 2668 struct usb_page_search buf_ep; 2669 struct xhci_trb *trb; 2670 struct usb_page_cache *pc; 2671 struct usb_page *pg; 2672 uint64_t addr; 2673 uint8_t index; 2674 uint8_t i; 2675 2676 index = udev->controller_slot_id; 2677 2678 pc = &sc->sc_hw.devs[index].device_pc; 2679 pg = &sc->sc_hw.devs[index].device_pg; 2680 2681 /* need to initialize the page cache */ 2682 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2683 2684 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2685 (2 * sizeof(struct xhci_dev_ctx)) : 2686 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2687 goto error; 2688 2689 usbd_get_page(pc, 0, &buf_dev); 2690 2691 pc = &sc->sc_hw.devs[index].input_pc; 2692 pg = &sc->sc_hw.devs[index].input_pg; 2693 2694 /* need to initialize the page cache */ 2695 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2696 2697 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2698 (2 * sizeof(struct xhci_input_dev_ctx)) : 2699 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) { 2700 goto error; 2701 } 2702 2703 /* initialize all endpoint LINK TRBs */ 2704 2705 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2706 pc = &sc->sc_hw.devs[index].endpoint_pc[i]; 2707 pg = &sc->sc_hw.devs[index].endpoint_pg[i]; 2708 2709 /* need to initialize the page cache */ 2710 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2711 2712 if (usb_pc_alloc_mem(pc, pg, 2713 sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) { 2714 goto error; 2715 } 2716 2717 /* lookup endpoint TRB ring */ 2718 usbd_get_page(pc, 0, &buf_ep); 2719 2720 /* get TRB pointer */ 2721 trb = buf_ep.buffer; 2722 trb += XHCI_MAX_TRANSFERS - 1; 2723 2724 /* get TRB start address */ 2725 addr = buf_ep.physaddr; 2726 2727 /* create LINK TRB */ 2728 trb->qwTrb0 = htole64(addr); 2729 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2730 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2731 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2732 2733 usb_pc_cpu_flush(pc); 2734 } 2735 2736 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2737 2738 return (USB_ERR_NORMAL_COMPLETION); 2739 2740error: 2741 xhci_free_device_ext(udev); 2742 2743 return (USB_ERR_NOMEM); 2744} 2745 2746static void 2747xhci_free_device_ext(struct usb_device *udev) 2748{ 2749 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2750 uint8_t index; 2751 uint8_t i; 2752 2753 index = udev->controller_slot_id; 2754 xhci_set_slot_pointer(sc, index, 0); 2755 2756 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2757 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2758 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) 2759 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]); 2760} 2761 2762static struct xhci_endpoint_ext * 2763xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2764{ 2765 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2766 struct xhci_endpoint_ext *pepext; 2767 struct usb_page_cache *pc; 2768 struct usb_page_search buf_ep; 2769 uint8_t epno; 2770 uint8_t index; 2771 2772 epno = edesc->bEndpointAddress; 2773 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2774 epno |= UE_DIR_IN; 2775 2776 epno = XHCI_EPNO2EPID(epno); 2777 2778 index = udev->controller_slot_id; 2779 2780 pc = &sc->sc_hw.devs[index].endpoint_pc[epno]; 2781 2782 usbd_get_page(pc, 0, &buf_ep); 2783 2784 pepext = &sc->sc_hw.devs[index].endp[epno]; 2785 pepext->page_cache = pc; 2786 pepext->trb = buf_ep.buffer; 2787 pepext->physaddr = buf_ep.physaddr; 2788 2789 return (pepext); 2790} 2791 2792static void 2793xhci_endpoint_doorbell(struct usb_xfer *xfer) 2794{ 2795 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2796 uint8_t epno; 2797 uint8_t index; 2798 2799 epno = xfer->endpointno; 2800 if (xfer->flags_int.control_xfr) 2801 epno |= UE_DIR_IN; 2802 2803 epno = XHCI_EPNO2EPID(epno); 2804 index = xfer->xroot->udev->controller_slot_id; 2805 2806 if (xfer->xroot->udev->flags.self_suspended == 0) { 2807 XWRITE4(sc, door, XHCI_DOORBELL(index), 2808 epno | XHCI_DB_SID_SET(xfer->stream_id)); 2809 } 2810} 2811 2812static void 2813xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2814{ 2815 struct xhci_endpoint_ext *pepext; 2816 2817 if (xfer->flags_int.bandwidth_reclaimed) { 2818 xfer->flags_int.bandwidth_reclaimed = 0; 2819 2820 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2821 xfer->endpoint->edesc); 2822 2823 pepext->trb_used[xfer->stream_id]--; 2824 2825 pepext->xfer[xfer->qh_pos] = NULL; 2826 2827 if (error && (pepext->trb_running != 0)) { 2828 pepext->trb_halted = 1; 2829 pepext->trb_running = 0; 2830 } 2831 } 2832} 2833 2834static usb_error_t 2835xhci_transfer_insert(struct usb_xfer *xfer) 2836{ 2837 struct xhci_td *td_first; 2838 struct xhci_td *td_last; 2839 struct xhci_trb *trb_link; 2840 struct xhci_endpoint_ext *pepext; 2841 uint64_t addr; 2842 usb_stream_t id; 2843 uint8_t i; 2844 uint8_t inext; 2845 uint8_t trb_limit; 2846 2847 DPRINTFN(8, "\n"); 2848 2849 id = xfer->stream_id; 2850 2851 /* check if already inserted */ 2852 if (xfer->flags_int.bandwidth_reclaimed) { 2853 DPRINTFN(8, "Already in schedule\n"); 2854 return (USB_ERR_NORMAL_COMPLETION); 2855 } 2856 2857 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2858 xfer->endpoint->edesc); 2859 2860 td_first = xfer->td_transfer_first; 2861 td_last = xfer->td_transfer_last; 2862 addr = pepext->physaddr; 2863 2864 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 2865 case UE_CONTROL: 2866 case UE_INTERRUPT: 2867 /* single buffered */ 2868 trb_limit = 1; 2869 break; 2870 default: 2871 /* multi buffered */ 2872 trb_limit = (XHCI_MAX_TRANSFERS - 2); 2873 break; 2874 } 2875 2876 if (pepext->trb_used[id] >= trb_limit) { 2877 DPRINTFN(8, "Too many TDs queued.\n"); 2878 return (USB_ERR_NOMEM); 2879 } 2880 2881 /* check if bMaxPacketSize changed */ 2882 if (xfer->flags_int.control_xfr != 0 && 2883 pepext->trb_ep_maxp != xfer->endpoint->edesc->wMaxPacketSize[0]) { 2884 DPRINTFN(8, "Reconfigure control endpoint\n"); 2885 2886 /* force driver to reconfigure endpoint */ 2887 pepext->trb_halted = 1; 2888 pepext->trb_running = 0; 2889 } 2890 2891 /* check for stopped condition, after putting transfer on interrupt queue */ 2892 if (pepext->trb_running == 0) { 2893 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2894 2895 DPRINTFN(8, "Not running\n"); 2896 2897 /* start configuration */ 2898 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 2899 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 2900 return (USB_ERR_NORMAL_COMPLETION); 2901 } 2902 2903 pepext->trb_used[id]++; 2904 2905 /* get current TRB index */ 2906 i = pepext->trb_index[id]; 2907 2908 /* get next TRB index */ 2909 inext = (i + 1); 2910 2911 /* the last entry of the ring is a hardcoded link TRB */ 2912 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 2913 inext = 0; 2914 2915 /* store next TRB index, before stream ID offset is added */ 2916 pepext->trb_index[id] = inext; 2917 2918 /* offset for stream */ 2919 i += id * XHCI_MAX_TRANSFERS; 2920 inext += id * XHCI_MAX_TRANSFERS; 2921 2922 /* compute terminating return address */ 2923 addr += (inext * sizeof(struct xhci_trb)); 2924 2925 /* compute link TRB pointer */ 2926 trb_link = td_last->td_trb + td_last->ntrb; 2927 2928 /* update next pointer of last link TRB */ 2929 trb_link->qwTrb0 = htole64(addr); 2930 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2931 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 2932 XHCI_TRB_3_CYCLE_BIT | 2933 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2934 2935#ifdef USB_DEBUG 2936 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 2937#endif 2938 usb_pc_cpu_flush(td_last->page_cache); 2939 2940 /* write ahead chain end marker */ 2941 2942 pepext->trb[inext].qwTrb0 = 0; 2943 pepext->trb[inext].dwTrb2 = 0; 2944 pepext->trb[inext].dwTrb3 = 0; 2945 2946 /* update next pointer of link TRB */ 2947 2948 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 2949 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2950 2951#ifdef USB_DEBUG 2952 xhci_dump_trb(&pepext->trb[i]); 2953#endif 2954 usb_pc_cpu_flush(pepext->page_cache); 2955 2956 /* toggle cycle bit which activates the transfer chain */ 2957 2958 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2959 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2960 2961 usb_pc_cpu_flush(pepext->page_cache); 2962 2963 DPRINTF("qh_pos = %u\n", i); 2964 2965 pepext->xfer[i] = xfer; 2966 2967 xfer->qh_pos = i; 2968 2969 xfer->flags_int.bandwidth_reclaimed = 1; 2970 2971 xhci_endpoint_doorbell(xfer); 2972 2973 return (USB_ERR_NORMAL_COMPLETION); 2974} 2975 2976static void 2977xhci_root_intr(struct xhci_softc *sc) 2978{ 2979 uint16_t i; 2980 2981 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2982 2983 /* clear any old interrupt data */ 2984 (void)memset_s(sc->sc_hub_idata, sizeof(sc->sc_hub_idata), 0, sizeof(sc->sc_hub_idata)); 2985 2986 for (i = 1; i <= sc->sc_noport; i++) { 2987 /* pick out CHANGE bits from the status register */ 2988 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 2989 XHCI_PS_CSC | XHCI_PS_PEC | 2990 XHCI_PS_OCC | XHCI_PS_WRC | 2991 XHCI_PS_PRC | XHCI_PS_PLC | 2992 XHCI_PS_CEC)) { 2993 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2994 DPRINTF("port %d changed\n", i); 2995 } 2996 } 2997 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2998 sizeof(sc->sc_hub_idata)); 2999} 3000 3001/*------------------------------------------------------------------------* 3002 * xhci_device_done - XHCI done handler 3003 * 3004 * NOTE: This function can be called two times in a row on 3005 * the same USB transfer. From close and from interrupt. 3006 *------------------------------------------------------------------------*/ 3007static void 3008xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 3009{ 3010 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 3011 xfer, xfer->endpoint, error); 3012 3013 /* remove transfer from HW queue */ 3014 xhci_transfer_remove(xfer, error); 3015 3016 /* dequeue transfer and start next transfer */ 3017 usbd_transfer_done(xfer, error); 3018} 3019 3020/*------------------------------------------------------------------------* 3021 * XHCI data transfer support (generic type) 3022 *------------------------------------------------------------------------*/ 3023static void 3024xhci_device_generic_open(struct usb_xfer *xfer) 3025{ 3026 if (xfer->flags_int.isochronous_xfr) { 3027 switch (xfer->xroot->udev->speed) { 3028 case USB_SPEED_FULL: 3029 break; 3030 default: 3031 usb_hs_bandwidth_alloc(xfer); 3032 break; 3033 } 3034 } 3035} 3036 3037static void 3038xhci_device_generic_close(struct usb_xfer *xfer) 3039{ 3040 DPRINTF("\n"); 3041 3042 xhci_device_done(xfer, USB_ERR_CANCELLED); 3043 if (xfer->flags_int.isochronous_xfr) { 3044 switch (xfer->xroot->udev->speed) { 3045 case USB_SPEED_FULL: 3046 break; 3047 default: 3048 usb_hs_bandwidth_free(xfer); 3049 break; 3050 } 3051 } 3052} 3053 3054static void 3055xhci_device_generic_multi_enter(struct usb_endpoint *ep, 3056 usb_stream_t stream_id, struct usb_xfer *enter_xfer) 3057{ 3058 struct usb_xfer *xfer; 3059 3060 /* check if there is a current transfer */ 3061 xfer = ep->endpoint_q[stream_id].curr; 3062 if (xfer == NULL) 3063 return; 3064 3065 /* 3066 * Check if the current transfer is started and then pickup 3067 * the next one, if any. Else wait for next start event due to 3068 * block on failure feature. 3069 */ 3070 if (!xfer->flags_int.bandwidth_reclaimed) 3071 return; 3072 3073 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head); 3074 if (xfer == NULL) { 3075 /* 3076 * In case of enter we have to consider that the 3077 * transfer is queued by the USB core after the enter 3078 * method is called. 3079 */ 3080 xfer = enter_xfer; 3081 3082 if (xfer == NULL) 3083 return; 3084 } 3085 3086 /* try to multi buffer */ 3087 (void)xhci_transfer_insert(xfer); 3088} 3089 3090static void 3091xhci_device_generic_enter(struct usb_xfer *xfer) 3092{ 3093 DPRINTF("\n"); 3094 3095 /* set up TD's and QH */ 3096 xhci_setup_generic_chain(xfer); 3097 3098 xhci_device_generic_multi_enter(xfer->endpoint, 3099 xfer->stream_id, xfer); 3100} 3101 3102static void 3103xhci_device_generic_start(struct usb_xfer *xfer) 3104{ 3105 DPRINTF("\n"); 3106 3107 /* try to insert xfer on HW queue */ 3108 (void)xhci_transfer_insert(xfer); 3109 3110 /* try to multi buffer */ 3111 xhci_device_generic_multi_enter(xfer->endpoint, 3112 xfer->stream_id, NULL); 3113 3114 /* add transfer last on interrupt queue */ 3115 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3116 3117 /* start timeout, if any */ 3118 if (xfer->timeout != 0) 3119 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 3120} 3121 3122struct usb_pipe_methods xhci_device_generic_methods = { 3123 .open = xhci_device_generic_open, 3124 .close = xhci_device_generic_close, 3125 .enter = xhci_device_generic_enter, 3126 .start = xhci_device_generic_start, 3127}; 3128 3129/*------------------------------------------------------------------------* 3130 * xhci root HUB support 3131 *------------------------------------------------------------------------* 3132 * Simulate a hardware HUB by handling all the necessary requests. 3133 *------------------------------------------------------------------------*/ 3134#define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3135 3136static const 3137struct usb_device_descriptor xhci_devd = { 3138 .bLength = sizeof(xhci_devd), 3139 .bDescriptorType = UDESC_DEVICE, /* type */ 3140 HSETW(.bcdUSB, 0x0300), /* USB version */ 3141 .bDeviceClass = UDCLASS_HUB, /* class */ 3142 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 3143 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 3144 .bMaxPacketSize = 9, /* max packet size */ 3145 HSETW(.idVendor, 0x0000), /* vendor */ 3146 HSETW(.idProduct, 0x0000), /* product */ 3147 HSETW(.bcdDevice, 0x0100), /* device version */ 3148 .iManufacturer = 1, 3149 .iProduct = 2, 3150 .iSerialNumber = 0, 3151 .bNumConfigurations = 1, /* # of configurations */ 3152}; 3153 3154static const 3155struct xhci_bos_desc xhci_bosd = { 3156 .bosd = { 3157 .bLength = sizeof(xhci_bosd.bosd), 3158 .bDescriptorType = UDESC_BOS, 3159 HSETW(.wTotalLength, sizeof(xhci_bosd)), 3160 .bNumDeviceCaps = 3, 3161 }, 3162 .usb2extd = { 3163 .bLength = sizeof(xhci_bosd.usb2extd), 3164 .bDescriptorType = 1, 3165 .bDevCapabilityType = 2, 3166 .bmAttributes[0] = 2, 3167 }, 3168 .usbdcd = { 3169 .bLength = sizeof(xhci_bosd.usbdcd), 3170 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 3171 .bDevCapabilityType = 3, 3172 .bmAttributes = 0, 3173 HSETW(.wSpeedsSupported, 0x000C), 3174 .bFunctionalitySupport = 8, 3175 .bU1DevExitLat = 255, /* dummy - not used */ 3176 .wU2DevExitLat = { 0x00, 0x08 }, 3177 }, 3178 .cidd = { 3179 .bLength = sizeof(xhci_bosd.cidd), 3180 .bDescriptorType = 1, 3181 .bDevCapabilityType = 4, 3182 .bReserved = 0, 3183 .bContainerID = 0, 3184 }, 3185}; 3186 3187static const 3188struct xhci_config_desc xhci_confd = { 3189 .confd = { 3190 .bLength = sizeof(xhci_confd.confd), 3191 .bDescriptorType = UDESC_CONFIG, 3192 .wTotalLength[0] = sizeof(xhci_confd), 3193 .bNumInterface = 1, 3194 .bConfigurationValue = 1, 3195 .iConfiguration = 0, 3196 .bmAttributes = UC_SELF_POWERED, 3197 .bMaxPower = 0 /* max power */ 3198 }, 3199 .ifcd = { 3200 .bLength = sizeof(xhci_confd.ifcd), 3201 .bDescriptorType = UDESC_INTERFACE, 3202 .bNumEndpoints = 1, 3203 .bInterfaceClass = UICLASS_HUB, 3204 .bInterfaceSubClass = UISUBCLASS_HUB, 3205 .bInterfaceProtocol = 0, 3206 }, 3207 .endpd = { 3208 .bLength = sizeof(xhci_confd.endpd), 3209 .bDescriptorType = UDESC_ENDPOINT, 3210 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 3211 .bmAttributes = UE_INTERRUPT, 3212 .wMaxPacketSize[0] = 2, /* max 15 ports */ 3213 .bInterval = 255, 3214 }, 3215 .endpcd = { 3216 .bLength = sizeof(xhci_confd.endpcd), 3217 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 3218 .bMaxBurst = 0, 3219 .bmAttributes = 0, 3220 }, 3221}; 3222 3223static const 3224struct usb_hub_ss_descriptor xhci_hubd = { 3225 .bLength = sizeof(xhci_hubd), 3226 .bDescriptorType = UDESC_SS_HUB, 3227}; 3228 3229static usb_error_t 3230xhci_roothub_exec(struct usb_device *udev, 3231 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3232{ 3233 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3234 const char *str_ptr; 3235 const void *ptr; 3236 uint32_t port; 3237 uint32_t v; 3238 uint16_t len; 3239 uint16_t i; 3240 uint16_t value; 3241 uint16_t index; 3242 uint8_t j; 3243 usb_error_t err; 3244 3245 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3246 3247 /* buffer reset */ 3248 ptr = (const void *)&sc->sc_hub_desc; 3249 len = 0; 3250 err = USB_ERR_NORMAL_COMPLETION; 3251 3252 value = UGETW(req->wValue); 3253 index = UGETW(req->wIndex); 3254 3255 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3256 "wValue=0x%04x wIndex=0x%04x\n", 3257 req->bmRequestType, req->bRequest, 3258 UGETW(req->wLength), value, index); 3259 3260#define C(x,y) ((x) | ((y) << 8)) 3261 switch (C(req->bRequest, req->bmRequestType)) { 3262 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3263 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3264 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3265 /* 3266 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3267 * for the integrated root hub. 3268 */ 3269 break; 3270 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3271 len = 1; 3272 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3273 break; 3274 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3275 switch (value >> 8) { 3276 case UDESC_DEVICE: 3277 if ((value & 0xff) != 0) { 3278 err = USB_ERR_IOERROR; 3279 goto done; 3280 } 3281 len = sizeof(xhci_devd); 3282 ptr = (const void *)&xhci_devd; 3283 break; 3284 3285 case UDESC_BOS: 3286 if ((value & 0xff) != 0) { 3287 err = USB_ERR_IOERROR; 3288 goto done; 3289 } 3290 len = sizeof(xhci_bosd); 3291 ptr = (const void *)&xhci_bosd; 3292 break; 3293 3294 case UDESC_CONFIG: 3295 if ((value & 0xff) != 0) { 3296 err = USB_ERR_IOERROR; 3297 goto done; 3298 } 3299 len = sizeof(xhci_confd); 3300 ptr = (const void *)&xhci_confd; 3301 break; 3302 3303 case UDESC_STRING: 3304 switch (value & 0xff) { 3305 case 0: /* Language table */ 3306 str_ptr = "\001"; 3307 break; 3308 3309 case 1: /* Vendor */ 3310 str_ptr = sc->sc_vendor; 3311 break; 3312 3313 case 2: /* Product */ 3314 str_ptr = "XHCI root HUB"; 3315 break; 3316 3317 default: 3318 str_ptr = ""; 3319 break; 3320 } 3321 3322 len = usb_make_str_desc( 3323 sc->sc_hub_desc.temp, 3324 sizeof(sc->sc_hub_desc.temp), 3325 str_ptr); 3326 break; 3327 3328 default: 3329 err = USB_ERR_IOERROR; 3330 goto done; 3331 } 3332 break; 3333 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3334 len = 1; 3335 sc->sc_hub_desc.temp[0] = 0; 3336 break; 3337 case C(UR_GET_STATUS, UT_READ_DEVICE): 3338 len = 2; 3339 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3340 break; 3341 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3342 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3343 len = 2; 3344 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3345 break; 3346 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3347 if (value >= XHCI_MAX_DEVICES) { 3348 err = USB_ERR_IOERROR; 3349 goto done; 3350 } 3351 break; 3352 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3353 if ((value != 0) && (value != 1)) { 3354 err = USB_ERR_IOERROR; 3355 goto done; 3356 } 3357 sc->sc_conf = value; 3358 break; 3359 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3360 break; 3361 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3362 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3363 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3364 err = USB_ERR_IOERROR; 3365 goto done; 3366 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3367 break; 3368 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3369 break; 3370 /* Hub requests */ 3371 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3372 break; 3373 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3374 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3375 3376 if ((index < 1) || 3377 (index > sc->sc_noport)) { 3378 err = USB_ERR_IOERROR; 3379 goto done; 3380 } 3381 port = XHCI_PORTSC(index); 3382 3383 v = XREAD4(sc, oper, port); 3384 i = XHCI_PS_PLS_GET(v); 3385 v &= ~XHCI_PS_CLEAR; 3386 3387 switch (value) { 3388 case UHF_C_BH_PORT_RESET: 3389 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3390 break; 3391 case UHF_C_PORT_CONFIG_ERROR: 3392 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3393 break; 3394 case UHF_C_PORT_SUSPEND: 3395 case UHF_C_PORT_LINK_STATE: 3396 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3397 break; 3398 case UHF_C_PORT_CONNECTION: 3399 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3400 break; 3401 case UHF_C_PORT_ENABLE: 3402 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3403 break; 3404 case UHF_C_PORT_OVER_CURRENT: 3405 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3406 break; 3407 case UHF_C_PORT_RESET: 3408 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3409 break; 3410 case UHF_PORT_ENABLE: 3411 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3412 break; 3413 case UHF_PORT_POWER: 3414 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3415 break; 3416 case UHF_PORT_INDICATOR: 3417 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3418 break; 3419 case UHF_PORT_SUSPEND: 3420 3421 /* U3 -> U15 */ 3422 if (i == 3) { 3423 XWRITE4(sc, oper, port, v | 3424 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3425 } 3426 3427 /* wait 20ms for resume sequence to complete */ 3428 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3429 3430 /* U0 */ 3431 XWRITE4(sc, oper, port, v | 3432 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3433 break; 3434 default: 3435 err = USB_ERR_IOERROR; 3436 goto done; 3437 } 3438 break; 3439 3440 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3441 if ((value & 0xff) != 0) { 3442 err = USB_ERR_IOERROR; 3443 goto done; 3444 } 3445 3446 v = XREAD4(sc, capa, XHCI_HCSPARAMS0); 3447 3448 sc->sc_hub_desc.hubd = xhci_hubd; 3449 3450 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3451 3452 if (XHCI_HCS0_PPC(v)) 3453 i = UHD_PWR_INDIVIDUAL; 3454 else 3455 i = UHD_PWR_GANGED; 3456 3457 if (XHCI_HCS0_PIND(v)) 3458 i |= UHD_PORT_IND; 3459 3460 i |= UHD_OC_INDIVIDUAL; 3461 3462 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3463 3464 /* see XHCI section 5.4.9: */ 3465 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3466 3467 for (j = 1; j <= sc->sc_noport; j++) { 3468 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3469 if (v & XHCI_PS_DR) { 3470 sc->sc_hub_desc.hubd. 3471 DeviceRemovable[j / 8] |= 1U << (j % 8); 3472 } 3473 } 3474 len = sc->sc_hub_desc.hubd.bLength; 3475 break; 3476 3477 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3478 len = 16; 3479 (void)memset_s(sc->sc_hub_desc.temp, sizeof(sc->sc_hub_desc.temp), 0, len); 3480 break; 3481 3482 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3483 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3484 3485 if ((index < 1) || 3486 (index > sc->sc_noport)) { 3487 err = USB_ERR_IOERROR; 3488 goto done; 3489 } 3490 3491 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3492 3493 DPRINTFN(9, "port status=0x%08x\n", v); 3494 3495 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3496 3497 switch (XHCI_PS_SPEED_GET(v)) { 3498 case 3: 3499 i |= UPS_HIGH_SPEED; 3500 break; 3501 case 2: 3502 i |= UPS_LOW_SPEED; 3503 break; 3504 case 1: 3505 /* FULL speed */ 3506 break; 3507 default: 3508 i |= UPS_OTHER_SPEED; 3509 break; 3510 } 3511 3512 if (v & XHCI_PS_CCS) 3513 i |= UPS_CURRENT_CONNECT_STATUS; 3514 if (v & XHCI_PS_PED) 3515 i |= UPS_PORT_ENABLED; 3516 if (v & XHCI_PS_OCA) 3517 i |= UPS_OVERCURRENT_INDICATOR; 3518 if (v & XHCI_PS_PR) 3519 i |= UPS_RESET; 3520 if (v & XHCI_PS_PP) { 3521 /* 3522 * The USB 3.0 RH is using the 3523 * USB 2.0's power bit 3524 */ 3525 i |= UPS_PORT_POWER; 3526 } 3527 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3528 3529 i = 0; 3530 if (v & XHCI_PS_CSC) 3531 i |= UPS_C_CONNECT_STATUS; 3532 if (v & XHCI_PS_PEC) 3533 i |= UPS_C_PORT_ENABLED; 3534 if (v & XHCI_PS_OCC) 3535 i |= UPS_C_OVERCURRENT_INDICATOR; 3536 if (v & XHCI_PS_WRC) 3537 i |= UPS_C_BH_PORT_RESET; 3538 if (v & XHCI_PS_PRC) 3539 i |= UPS_C_PORT_RESET; 3540 if (v & XHCI_PS_PLC) 3541 i |= UPS_C_PORT_LINK_STATE; 3542 if (v & XHCI_PS_CEC) 3543 i |= UPS_C_PORT_CONFIG_ERROR; 3544 3545 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3546 len = sizeof(sc->sc_hub_desc.ps); 3547 break; 3548 3549 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3550 err = USB_ERR_IOERROR; 3551 goto done; 3552 3553 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3554 break; 3555 3556 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3557 3558 i = index >> 8; 3559 index &= 0x00FF; 3560 3561 if ((index < 1) || 3562 (index > sc->sc_noport)) { 3563 err = USB_ERR_IOERROR; 3564 goto done; 3565 } 3566 3567 port = XHCI_PORTSC(index); 3568 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3569 3570 switch (value) { 3571 case UHF_PORT_U1_TIMEOUT: 3572 if (XHCI_PS_SPEED_GET(v) != 4) { 3573 err = USB_ERR_IOERROR; 3574 goto done; 3575 } 3576 port = XHCI_PORTPMSC(index); 3577 v = XREAD4(sc, oper, port); 3578 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3579 v |= XHCI_PM3_U1TO_SET(i); 3580 XWRITE4(sc, oper, port, v); 3581 break; 3582 case UHF_PORT_U2_TIMEOUT: 3583 if (XHCI_PS_SPEED_GET(v) != 4) { 3584 err = USB_ERR_IOERROR; 3585 goto done; 3586 } 3587 port = XHCI_PORTPMSC(index); 3588 v = XREAD4(sc, oper, port); 3589 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3590 v |= XHCI_PM3_U2TO_SET(i); 3591 XWRITE4(sc, oper, port, v); 3592 break; 3593 case UHF_BH_PORT_RESET: 3594 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3595 break; 3596 case UHF_PORT_LINK_STATE: 3597 XWRITE4(sc, oper, port, v | 3598 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3599 /* 4ms settle time */ 3600 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3601 break; 3602 case UHF_PORT_ENABLE: 3603 DPRINTFN(3, "set port enable %d\n", index); 3604 break; 3605 case UHF_PORT_SUSPEND: 3606 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3607 j = XHCI_PS_SPEED_GET(v); 3608 if ((j < 1) || (j > 3)) { 3609 /* non-supported speed */ 3610 err = USB_ERR_IOERROR; 3611 goto done; 3612 } 3613 XWRITE4(sc, oper, port, v | 3614 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3615 break; 3616 case UHF_PORT_RESET: 3617 DPRINTFN(6, "reset port %d\n", index); 3618 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3619 break; 3620 case UHF_PORT_POWER: 3621 DPRINTFN(3, "set port power %d\n", index); 3622 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3623 break; 3624 case UHF_PORT_TEST: 3625 DPRINTFN(3, "set port test %d\n", index); 3626 break; 3627 case UHF_PORT_INDICATOR: 3628 DPRINTFN(3, "set port indicator %d\n", index); 3629 3630 v &= ~XHCI_PS_PIC_SET(3); 3631 v |= XHCI_PS_PIC_SET(1); 3632 3633 XWRITE4(sc, oper, port, v); 3634 break; 3635 default: 3636 err = USB_ERR_IOERROR; 3637 goto done; 3638 } 3639 break; 3640 3641 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3642 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3643 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3644 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3645 break; 3646 default: 3647 err = USB_ERR_IOERROR; 3648 goto done; 3649 } 3650done: 3651 *plength = len; 3652 *pptr = ptr; 3653 return (err); 3654} 3655 3656static void 3657xhci_xfer_setup(struct usb_setup_params *parm) 3658{ 3659 struct usb_page_search page_info; 3660 struct usb_page_cache *pc; 3661 struct usb_xfer *xfer; 3662 void *last_obj; 3663 uint32_t ntd; 3664 uint32_t n; 3665 3666 xfer = parm->curr_xfer; 3667 3668 /* 3669 * The proof for the "ntd" formula is illustrated like this: 3670 * 3671 * +------------------------------------+ 3672 * | | 3673 * | |remainder -> | 3674 * | +-----+---+ | 3675 * | | xxx | x | frm 0 | 3676 * | +-----+---++ | 3677 * | | xxx | xx | frm 1 | 3678 * | +-----+----+ | 3679 * | ... | 3680 * +------------------------------------+ 3681 * 3682 * "xxx" means a completely full USB transfer descriptor 3683 * 3684 * "x" and "xx" means a short USB packet 3685 * 3686 * For the remainder of an USB transfer modulo 3687 * "max_data_length" we need two USB transfer descriptors. 3688 * One to transfer the remaining data and one to finalise with 3689 * a zero length packet in case the "force_short_xfer" flag is 3690 * set. We only need two USB transfer descriptors in the case 3691 * where the transfer length of the first one is a factor of 3692 * "max_frame_size". The rest of the needed USB transfer 3693 * descriptors is given by the buffer size divided by the 3694 * maximum data payload. 3695 */ 3696 parm->hc_max_packet_size = 0x400; 3697 parm->hc_max_packet_count = 16 * 3; 3698 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3699 3700 xfer->flags_int.bdma_enable = 1; 3701 3702 usbd_transfer_setup_sub(parm); 3703 3704 if (xfer->flags_int.isochronous_xfr) { 3705 ntd = ((1 * xfer->nframes) 3706 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3707 } else if (xfer->flags_int.control_xfr) { 3708 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3709 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3710 } else { 3711 ntd = ((2 * xfer->nframes) 3712 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3713 } 3714 3715alloc_dma_set: 3716 3717 if (parm->err) 3718 return; 3719 3720 /* 3721 * Allocate queue heads and transfer descriptors 3722 */ 3723 last_obj = NULL; 3724 3725 if (usbd_transfer_setup_sub_malloc( 3726 parm, &pc, sizeof(struct xhci_td), 3727 XHCI_TD_ALIGN, ntd)) { 3728 parm->err = USB_ERR_NOMEM; 3729 return; 3730 } 3731 if (parm->buf) { 3732 for (n = 0; n != ntd; n++) { 3733 struct xhci_td *td; 3734 3735 usbd_get_page(pc + n, 0, &page_info); 3736 3737 td = page_info.buffer; 3738 3739 /* init TD */ 3740 td->td_self = page_info.physaddr; 3741 td->obj_next = last_obj; 3742 td->page_cache = pc + n; 3743 3744 last_obj = td; 3745 3746 usb_pc_cpu_flush(pc + n); 3747 } 3748 } 3749 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3750 3751 if (!xfer->flags_int.curr_dma_set) { 3752 xfer->flags_int.curr_dma_set = 1; 3753 goto alloc_dma_set; 3754 } 3755} 3756 3757static usb_error_t 3758xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3759{ 3760 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3761 struct usb_page_search buf_inp; 3762 struct usb_device *udev; 3763 struct xhci_endpoint_ext *pepext; 3764 struct usb_endpoint_descriptor *edesc; 3765 struct usb_page_cache *pcinp; 3766 usb_error_t err; 3767 usb_stream_t stream_id; 3768 uint8_t index; 3769 uint8_t epno; 3770 3771 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3772 xfer->endpoint->edesc); 3773 3774 udev = xfer->xroot->udev; 3775 index = udev->controller_slot_id; 3776 3777 pcinp = &sc->sc_hw.devs[index].input_pc; 3778 3779 usbd_get_page(pcinp, 0, &buf_inp); 3780 3781 edesc = xfer->endpoint->edesc; 3782 3783 epno = edesc->bEndpointAddress; 3784 stream_id = xfer->stream_id; 3785 3786 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3787 epno |= UE_DIR_IN; 3788 3789 epno = XHCI_EPNO2EPID(epno); 3790 3791 if (epno == 0) 3792 return (USB_ERR_NO_PIPE); /* invalid */ 3793 3794 XHCI_CMD_LOCK(sc); 3795 3796 /* configure endpoint */ 3797 3798 err = xhci_configure_endpoint_by_xfer(xfer); 3799 3800 if (err != 0) { 3801 XHCI_CMD_UNLOCK(sc); 3802 return (err); 3803 } 3804 3805 /* 3806 * Get the endpoint into the stopped state according to the 3807 * endpoint context state diagram in the XHCI specification: 3808 */ 3809 3810 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3811 3812 if (err != 0) 3813 DPRINTF("Could not stop endpoint %u\n", epno); 3814 3815 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3816 3817 if (err != 0) 3818 DPRINTF("Could not reset endpoint %u\n", epno); 3819 3820 err = xhci_cmd_set_tr_dequeue_ptr(sc, 3821 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) * 3822 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1), 3823 stream_id, epno, index); 3824 3825 if (err != 0) 3826 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3827 3828 /* 3829 * Get the endpoint into the running state according to the 3830 * endpoint context state diagram in the XHCI specification: 3831 */ 3832 3833 (void)xhci_configure_mask(udev, (1U << epno) | 1U, 0); 3834 3835 if (epno > 1) 3836 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3837 else 3838 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3839 3840 if (err != 0) 3841 DPRINTF("Could not configure endpoint %u\n", epno); 3842 3843 XHCI_CMD_UNLOCK(sc); 3844 3845 return (USB_ERR_NORMAL_COMPLETION); 3846} 3847 3848static void 3849xhci_xfer_unsetup(struct usb_xfer *xfer) 3850{ 3851 return; 3852} 3853 3854static void 3855xhci_start_dma_delay(struct usb_xfer *xfer) 3856{ 3857 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3858 3859 /* put transfer on interrupt queue (again) */ 3860 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 3861 3862 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 3863 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3864} 3865 3866static void 3867xhci_configure_msg(struct usb_proc_msg *pm) 3868{ 3869 struct xhci_softc *sc; 3870 struct xhci_endpoint_ext *pepext; 3871 struct usb_xfer *xfer; 3872 3873 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 3874 3875restart: 3876 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3877 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3878 xfer->endpoint->edesc); 3879 3880 if ((pepext->trb_halted != 0) || 3881 (pepext->trb_running == 0)) { 3882 uint16_t i; 3883 3884 /* clear halted and running */ 3885 pepext->trb_halted = 0; 3886 pepext->trb_running = 0; 3887 3888 /* nuke remaining buffered transfers */ 3889 3890 for (i = 0; i != (XHCI_MAX_TRANSFERS * 3891 XHCI_MAX_STREAMS); i++) { 3892 /* 3893 * NOTE: We need to use the timeout 3894 * error code here else existing 3895 * isochronous clients can get 3896 * confused: 3897 */ 3898 if (pepext->xfer[i] != NULL) { 3899 xhci_device_done(pepext->xfer[i], 3900 USB_ERR_TIMEOUT); 3901 } 3902 } 3903 3904 /* 3905 * NOTE: The USB transfer cannot vanish in 3906 * this state! 3907 */ 3908 3909 USB_BUS_UNLOCK(&sc->sc_bus); 3910 3911 (void)xhci_configure_reset_endpoint(xfer); 3912 3913 USB_BUS_LOCK(&sc->sc_bus); 3914 3915 /* check if halted is still cleared */ 3916 if (pepext->trb_halted == 0) { 3917 pepext->trb_running = 1; 3918 (void)memset_s(pepext->trb_index, sizeof(pepext->trb_index), 3919 0, sizeof(pepext->trb_index)); 3920 } 3921 goto restart; 3922 } 3923 3924 if (xfer->flags_int.did_dma_delay) { 3925 /* remove transfer from interrupt queue (again) */ 3926 usbd_transfer_dequeue(xfer); 3927 3928 /* we are finally done */ 3929 usb_dma_delay_done_cb(xfer); 3930 3931 /* queue changed - restart */ 3932 goto restart; 3933 } 3934 } 3935 3936 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3937 /* try to insert xfer on HW queue */ 3938 (void)xhci_transfer_insert(xfer); 3939 3940 /* try to multi buffer */ 3941 xhci_device_generic_multi_enter(xfer->endpoint, 3942 xfer->stream_id, NULL); 3943 } 3944} 3945 3946static void 3947xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3948 struct usb_endpoint *ep) 3949{ 3950 struct xhci_endpoint_ext *pepext; 3951 3952 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 3953 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 3954 3955 if (udev->parent_hub == NULL) { 3956 /* root HUB has special endpoint handling */ 3957 return; 3958 } 3959 3960 ep->methods = &xhci_device_generic_methods; 3961 3962 pepext = xhci_get_endpoint_ext(udev, edesc); 3963 3964 USB_BUS_LOCK(udev->bus); 3965 pepext->trb_halted = 1; 3966 pepext->trb_running = 0; 3967 USB_BUS_UNLOCK(udev->bus); 3968} 3969 3970static void 3971xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 3972{ 3973 3974} 3975 3976static void 3977xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3978{ 3979 struct xhci_endpoint_ext *pepext; 3980 3981 DPRINTF("\n"); 3982 3983 if (udev->flags.usb_mode != USB_MODE_HOST) { 3984 /* not supported */ 3985 return; 3986 } 3987 if (udev->parent_hub == NULL) { 3988 /* root HUB has special endpoint handling */ 3989 return; 3990 } 3991 3992 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 3993 3994 USB_BUS_LOCK(udev->bus); 3995 pepext->trb_halted = 1; 3996 pepext->trb_running = 0; 3997 USB_BUS_UNLOCK(udev->bus); 3998} 3999 4000static usb_error_t 4001xhci_device_init(struct usb_device *udev) 4002{ 4003 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4004 usb_error_t err; 4005 uint8_t temp; 4006 4007 /* no init for root HUB */ 4008 if (udev->parent_hub == NULL) 4009 return (USB_ERR_NORMAL_COMPLETION); 4010 4011 XHCI_CMD_LOCK(sc); 4012 4013 /* set invalid default */ 4014 4015 udev->controller_slot_id = sc->sc_noslot + 1; 4016 4017 /* try to get a new slot ID from the XHCI */ 4018 4019 err = xhci_cmd_enable_slot(sc, &temp); 4020 4021 if (err) { 4022 XHCI_CMD_UNLOCK(sc); 4023 return (err); 4024 } 4025 4026 if (temp > sc->sc_noslot) { 4027 XHCI_CMD_UNLOCK(sc); 4028 return (USB_ERR_BAD_ADDRESS); 4029 } 4030 4031 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 4032 DPRINTF("slot %u already allocated.\n", temp); 4033 XHCI_CMD_UNLOCK(sc); 4034 return (USB_ERR_BAD_ADDRESS); 4035 } 4036 4037 /* store slot ID for later reference */ 4038 4039 udev->controller_slot_id = temp; 4040 4041 /* reset data structure */ 4042 4043 (void)memset_s(&sc->sc_hw.devs[temp], sizeof(sc->sc_hw.devs[0]), 0, sizeof(sc->sc_hw.devs[0])); 4044 4045 /* set mark slot allocated */ 4046 4047 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 4048 4049 err = xhci_alloc_device_ext(udev); 4050 4051 XHCI_CMD_UNLOCK(sc); 4052 4053 /* get device into default state */ 4054 4055 if (err == 0) 4056 err = xhci_set_address(udev, NULL, 0); 4057 4058 return (err); 4059} 4060 4061static void 4062xhci_device_uninit(struct usb_device *udev) 4063{ 4064 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4065 uint8_t index; 4066 4067 /* no init for root HUB */ 4068 if (udev->parent_hub == NULL) 4069 return; 4070 4071 XHCI_CMD_LOCK(sc); 4072 4073 index = udev->controller_slot_id; 4074 4075 if (index <= sc->sc_noslot) { 4076 (void)xhci_cmd_disable_slot(sc, index); 4077 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 4078 4079 /* free device extension */ 4080 xhci_free_device_ext(udev); 4081 } 4082 4083 XHCI_CMD_UNLOCK(sc); 4084} 4085 4086static void 4087xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4088{ 4089 /* 4090 * Wait until the hardware has finished any possible use of 4091 * the transfer descriptor(s) 4092 */ 4093 *pus = 2048; /* microseconds */ 4094} 4095 4096static void 4097xhci_device_resume(struct usb_device *udev) 4098{ 4099 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4100 uint8_t index; 4101 uint8_t n; 4102 uint8_t p; 4103 4104 DPRINTF("\n"); 4105 4106 /* check for root HUB */ 4107 if (udev->parent_hub == NULL) 4108 return; 4109 4110 index = udev->controller_slot_id; 4111 4112 XHCI_CMD_LOCK(sc); 4113 4114 /* blindly resume all endpoints */ 4115 4116 USB_BUS_LOCK(udev->bus); 4117 4118 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4119 for (p = 0; p != XHCI_MAX_STREAMS; p++) { 4120 XWRITE4(sc, door, XHCI_DOORBELL(index), 4121 n | XHCI_DB_SID_SET(p)); 4122 } 4123 } 4124 4125 USB_BUS_UNLOCK(udev->bus); 4126 4127 XHCI_CMD_UNLOCK(sc); 4128} 4129 4130static void 4131xhci_device_suspend(struct usb_device *udev) 4132{ 4133 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4134 uint8_t index; 4135 uint8_t n; 4136 usb_error_t err; 4137 4138 DPRINTF("\n"); 4139 4140 /* check for root HUB */ 4141 if (udev->parent_hub == NULL) 4142 return; 4143 4144 index = udev->controller_slot_id; 4145 4146 XHCI_CMD_LOCK(sc); 4147 4148 /* blindly suspend all endpoints */ 4149 4150 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4151 err = xhci_cmd_stop_ep(sc, 1, n, index); 4152 if (err != 0) { 4153 DPRINTF("Failed to suspend endpoint " 4154 "%u on slot %u (ignored).\n", n, index); 4155 } 4156 } 4157 4158 XHCI_CMD_UNLOCK(sc); 4159} 4160 4161static void 4162xhci_set_hw_power(struct usb_bus *bus) 4163{ 4164 DPRINTF("\n"); 4165} 4166 4167static void 4168xhci_device_state_change(struct usb_device *udev) 4169{ 4170 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4171 struct usb_page_search buf_inp; 4172 usb_error_t err; 4173 uint8_t index; 4174 4175 /* check for root HUB */ 4176 if (udev->parent_hub == NULL) 4177 return; 4178 4179 index = udev->controller_slot_id; 4180 4181 DPRINTF("\n"); 4182 4183 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 4184 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 4185 &sc->sc_hw.devs[index].tt); 4186 if (err != 0) 4187 sc->sc_hw.devs[index].nports = 0; 4188 } 4189 4190 XHCI_CMD_LOCK(sc); 4191 4192 switch (usb_get_device_state(udev)) { 4193 case USB_STATE_POWERED: 4194 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 4195 break; 4196 4197 /* set default state */ 4198 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 4199 4200 /* reset number of contexts */ 4201 sc->sc_hw.devs[index].context_num = 0; 4202 4203 err = xhci_cmd_reset_dev(sc, index); 4204 4205 if (err != 0) { 4206 DPRINTF("Device reset failed " 4207 "for slot %u.\n", index); 4208 } 4209 break; 4210 4211 case USB_STATE_ADDRESSED: 4212 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 4213 break; 4214 4215 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 4216 4217 /* set configure mask to slot only */ 4218 (void)xhci_configure_mask(udev, 1, 0); 4219 4220 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4221 4222 if (err) { 4223 DPRINTF("Failed to deconfigure " 4224 "slot %u.\n", index); 4225 } 4226 break; 4227 4228 case USB_STATE_CONFIGURED: 4229 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) 4230 break; 4231 4232 /* set configured state */ 4233 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 4234 4235 /* reset number of contexts */ 4236 sc->sc_hw.devs[index].context_num = 0; 4237 4238 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 4239 4240 (void)xhci_configure_mask(udev, 3, 0); 4241 4242 err = xhci_configure_device(udev); 4243 if (err != 0) { 4244 DPRINTF("Could not configure device " 4245 "at slot %u.\n", index); 4246 } 4247 4248 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 4249 if (err != 0) { 4250 DPRINTF("Could not evaluate device " 4251 "context at slot %u.\n", index); 4252 } 4253 break; 4254 4255 default: 4256 break; 4257 } 4258 XHCI_CMD_UNLOCK(sc); 4259} 4260 4261static usb_error_t 4262xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep, 4263 uint8_t ep_mode) 4264{ 4265 switch (ep_mode) { 4266 case USB_EP_MODE_DEFAULT: 4267 return (USB_ERR_NORMAL_COMPLETION); 4268 case USB_EP_MODE_STREAMS: 4269 if ((xhcistreams == 0) || 4270 ((ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK) || 4271 (udev->speed != USB_SPEED_SUPER)) 4272 return (USB_ERR_INVAL); 4273 return (USB_ERR_NORMAL_COMPLETION); 4274 default: 4275 return (USB_ERR_INVAL); 4276 } 4277} 4278 4279struct usb_bus_methods xhci_bus_methods = { 4280 .endpoint_init = xhci_ep_init, 4281 .endpoint_uninit = xhci_ep_uninit, 4282 .xfer_setup = xhci_xfer_setup, 4283 .xfer_unsetup = xhci_xfer_unsetup, 4284 .get_dma_delay = xhci_get_dma_delay, 4285 .device_init = xhci_device_init, 4286 .device_uninit = xhci_device_uninit, 4287 .device_resume = xhci_device_resume, 4288 .device_suspend = xhci_device_suspend, 4289 .set_hw_power = xhci_set_hw_power, 4290 .roothub_exec = xhci_roothub_exec, 4291 .xfer_poll = xhci_do_poll, 4292 .start_dma_delay = xhci_start_dma_delay, 4293 .set_address = xhci_set_address, 4294 .clear_stall = xhci_ep_clear_stall, 4295 .device_state_change = xhci_device_state_change, 4296 .set_hw_power_sleep = xhci_set_hw_power_sleep, 4297 .set_endpoint_mode = xhci_set_endpoint_mode, 4298}; 4299