1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 5 * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved. 6 * Copyright (c) 2004 Lennart Augustsson. All rights reserved. 7 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31/* 32 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 33 * 34 * The EHCI 0.96 spec can be found at 35 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf 36 * The EHCI 1.0 spec can be found at 37 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 38 * and the USB 2.0 spec at 39 * http://www.usb.org/developers/docs/usb_20.zip 40 * 41 */ 42 43#include "implementation/global_implementation.h" 44#include "controller/ehci.h" 45#include "controller/ehcireg.h" 46 47 48#define EHCI_BUS2SC(bus) \ 49 ((ehci_softc_t *)(((uint8_t *)(bus)) - \ 50 ((uint8_t *)&(((ehci_softc_t *)0)->sc_bus)))) 51 52#undef USB_DEBUG_VAR 53#define USB_DEBUG_VAR ehcidebug 54 55#ifdef LOSCFG_USB_DEBUG 56static int ehcidebug = 0; 57static int ehciiaadbug = 0; 58static int ehcilostintrbug = 0; 59 60static void ehci_dump_regs(ehci_softc_t *sc); 61static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh); 62 63void 64usb_ehci_debug_func(int level) 65{ 66 ehcidebug = level; 67 PRINTK("The level of usb ehci debug is %d\n", level); 68} 69DEBUG_MODULE(ehci, usb_ehci_debug_func); 70#endif 71 72SPIN_LOCK_INIT(g_usb_ehci_qh_spinlock); 73 74#define EHCI_INTR_ENDPT 1 75 76extern const struct usb_bus_methods ehci_bus_methods; 77extern const struct usb_pipe_methods ehci_device_bulk_methods; 78extern const struct usb_pipe_methods ehci_device_ctrl_methods; 79extern const struct usb_pipe_methods ehci_device_intr_methods; 80extern const struct usb_pipe_methods ehci_device_isoc_fs_methods; 81extern const struct usb_pipe_methods ehci_device_isoc_hs_methods; 82 83static void ehci_do_poll(struct usb_bus *); 84static void ehci_device_done(struct usb_xfer *, usb_error_t); 85static uint8_t ehci_check_transfer(struct usb_xfer *); 86static void ehci_timeout(void *); 87static void ehci_poll_timeout(void *); 88 89static void ehci_root_intr(ehci_softc_t *sc); 90 91struct ehci_std_temp { 92 ehci_softc_t *sc; 93 struct usb_page_cache *pc; 94 ehci_qtd_t *td; 95 ehci_qtd_t *td_next; 96 uint32_t average; 97 uint32_t qtd_status; 98 uint32_t len; 99 uint16_t max_frame_size; 100 uint8_t shortpkt; 101 uint8_t auto_data_toggle; 102 uint8_t setup_alt_next; 103 uint8_t last_frame; 104}; 105 106/* cb: usb_bus_mem_alloc_all_cb */ 107/* usb_bus_mem_flush_all_cb */ 108void 109ehci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 110{ 111 ehci_softc_t *sc = EHCI_BUS2SC(bus); 112 uint32_t i; 113 114 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 115 sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN); 116 117 cb(bus, &sc->sc_hw.terminate_pc, &sc->sc_hw.terminate_pg, 118 sizeof(struct ehci_qh_sub), EHCI_QH_ALIGN); 119 120 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg, 121 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 122 123 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 124 cb(bus, sc->sc_hw.intr_start_pc + i, 125 sc->sc_hw.intr_start_pg + i, 126 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 127 } 128 129 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 130 cb(bus, sc->sc_hw.isoc_hs_start_pc + i, 131 sc->sc_hw.isoc_hs_start_pg + i, 132 sizeof(ehci_itd_t), EHCI_ITD_ALIGN); 133 } 134 135 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 136 cb(bus, sc->sc_hw.isoc_fs_start_pc + i, 137 sc->sc_hw.isoc_fs_start_pg + i, 138 sizeof(ehci_sitd_t), EHCI_SITD_ALIGN); 139 } 140} 141 142usb_error_t 143ehci_reset(ehci_softc_t *sc) 144{ 145 uint32_t hcr; 146 int i; 147 148 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 149 for (i = 0; i < 100; i++) { 150 usb_pause_mtx(NULL, hz / 128); 151 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 152 if (!hcr) { 153 if (sc->sc_vendor_post_reset != NULL) 154 sc->sc_vendor_post_reset(sc); 155 return (USB_ERR_NORMAL_COMPLETION); 156 } 157 } 158 device_printf(sc->sc_bus.bdev, "Reset timeout\n"); 159 return (USB_ERR_IOERROR); 160} 161 162static usb_error_t 163ehci_hcreset(ehci_softc_t *sc) 164{ 165 uint32_t hcr = 0; 166 int i; 167 168 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 169 for (i = 0; i < 100; i++) { 170 usb_pause_mtx(NULL, hz / 128); 171 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 172 if (hcr) 173 break; 174 } 175 if (!hcr) 176 /* 177 * Fall through and try reset anyway even though 178 * Table 2-9 in the EHCI spec says this will result 179 * in undefined behavior. 180 */ 181 device_printf(sc->sc_bus.bdev, "stop timeout\n"); 182 183 return (ehci_reset(sc)); 184} 185 186static usb_error_t 187ehci_init_sub(struct ehci_softc *sc) 188{ 189 struct usb_page_search buf_res; 190 uint32_t cparams; 191 uint32_t hcr = 0; 192 uint8_t i; 193 194 cparams = EREAD4(sc, EHCI_HCCPARAMS); 195 196 DPRINTF("cparams=0x%x\n", cparams); 197 198 if (EHCI_HCC_64BIT(cparams)) { 199 DPRINTF("HCC uses 64-bit structures\n"); 200 201 /* MUST clear segment register if 64 bit capable */ 202 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 203 } 204 205 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 206 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr); 207 208 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 209 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH); 210 211 /* enable interrupts */ 212 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 213 214 /* turn on controller */ 215 EOWRITE4(sc, EHCI_USBCMD, 216 EHCI_CMD_ITC_1 | /* 1 microframes interrupt delay */ 217 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 218 EHCI_CMD_ASE | 219 EHCI_CMD_PSE | 220 EHCI_CMD_RS); 221 222 /* Take over port ownership */ 223 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 224 225 for (i = 0; i < 100; i++) { 226 usb_pause_mtx(NULL, hz / 128); 227 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 228 if (!hcr) { 229 break; 230 } 231 } 232 if (hcr) { 233 device_printf(sc->sc_bus.bdev, "run timeout\n"); 234 return (USB_ERR_IOERROR); 235 } 236 return (USB_ERR_NORMAL_COMPLETION); 237} 238 239usb_error_t 240ehci_init(ehci_softc_t *sc) 241{ 242 struct usb_page_search buf_res; 243 struct ehci_qh_sub *qh_sub; 244 ehci_qh_t *qh_t; 245 uint32_t version; 246 uint32_t sparams; 247 uint32_t *pframes; 248 uint16_t i; 249 uint16_t x; 250 uint16_t y; 251 uint16_t bit; 252 usb_error_t err = USB_ERR_NORMAL_COMPLETION; 253 254 DPRINTF("start\n"); 255 256 callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_mtx, 0); 257 callout_init_mtx(&sc->sc_tmo_poll, &sc->sc_bus.bus_mtx, 0); 258 259 sc->sc_offs = EHCI_CAPLENGTH(EREAD4(sc, EHCI_CAPLEN_HCIVERSION)); 260 261#ifdef LOSCFG_USB_DEBUG 262 if (ehciiaadbug) 263 sc->sc_flags |= EHCI_SCFLG_IAADBUG; 264 if (ehcilostintrbug) 265 sc->sc_flags |= EHCI_SCFLG_LOSTINTRBUG; 266 if (ehcidebug > 2) { 267 ehci_dump_regs(sc); 268 } 269#endif 270 271 version = EHCI_HCIVERSION(EREAD4(sc, EHCI_CAPLEN_HCIVERSION)); 272 device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n", 273 version >> 8, version & 0xff); 274 275 sparams = EREAD4(sc, EHCI_HCSPARAMS); 276 DPRINTF("sparams=0x%x\n", sparams); 277 278 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 279 sc->sc_bus.usbrev = USB_REV_2_0; 280 if (!(sc->sc_flags & EHCI_SCFLG_DONTRESET)) { 281 /* Reset the controller */ 282 DPRINTF("%s: resetting\n", 283 device_get_nameunit(sc->sc_bus.bdev)); 284 err = ehci_hcreset(sc); 285 if (err) { 286 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 287 return (err); 288 } 289 } 290 291 /* 292 * use current frame-list-size selection 0: 1024*4 bytes 1: 512*4 293 * bytes 2: 256*4 bytes 3: unknown 294 */ 295 if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) { 296 device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n"); 297 return (USB_ERR_IOERROR); 298 } 299 /* set up the bus struct */ 300 sc->sc_bus.methods = &ehci_bus_methods; 301 302 sc->sc_eintrs = EHCI_NORMAL_INTRS; 303 304 usbd_get_page(&sc->sc_hw.terminate_pc, 0, &buf_res); 305 qh_sub = (struct ehci_qh_sub *)buf_res.buffer; 306 307 sc->sc_terminate_self = htohc32(sc, buf_res.physaddr); 308 309 /* init terminate TD */ 310 qh_sub->qtd_next = 311 htohc32(sc, EHCI_LINK_TERMINATE); 312 qh_sub->qtd_altnext = 313 htohc32(sc, EHCI_LINK_TERMINATE); 314 qh_sub->qtd_status = 315 htohc32(sc, EHCI_QTD_HALTED); 316 317 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 318 usbd_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res); 319 320 qh_t = (ehci_qh_t *)buf_res.buffer; 321 322 /* initialize page cache pointer */ 323 324 qh_t->page_cache = sc->sc_hw.intr_start_pc + i; 325 326 /* store a pointer to queue head */ 327 328 sc->sc_intr_p_last[i] = qh_t; 329 330 qh_t->qh_self = 331 htohc32(sc, buf_res.physaddr) | 332 htohc32(sc, EHCI_LINK_QH); 333 334 qh_t->qh_endp = 335 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 336 qh_t->qh_endphub = 337 htohc32(sc, EHCI_QH_SET_MULT(1)); 338 qh_t->qh_curqtd = 0; 339 340 qh_t->qh_qtd.qtd_next = 341 htohc32(sc, EHCI_LINK_TERMINATE); 342 qh_t->qh_qtd.qtd_altnext = 343 htohc32(sc, EHCI_LINK_TERMINATE); 344 qh_t->qh_qtd.qtd_status = 345 htohc32(sc, EHCI_QTD_HALTED); 346 } 347 348 /* 349 * the QHs are arranged to give poll intervals that are 350 * powers of 2 times 1ms 351 */ 352 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 353 while (bit) { 354 x = bit; 355 while (x & bit) { 356 ehci_qh_t *qh_x; 357 ehci_qh_t *qh_y; 358 359 y = (x ^ bit) | (bit / 2); 360 361 qh_x = sc->sc_intr_p_last[x]; 362 qh_y = sc->sc_intr_p_last[y]; 363 364 /* 365 * the next QH has half the poll interval 366 */ 367 qh_x->qh_link = qh_y->qh_self; 368 369 x++; 370 } 371 bit >>= 1; 372 } 373 374 qh_t = sc->sc_intr_p_last[0]; 375 376 /* the last (1ms) QH terminates */ 377 qh_t->qh_link = htohc32(sc, EHCI_LINK_TERMINATE); 378 379 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 380 ehci_sitd_t *sitd; 381 ehci_itd_t *itd; 382 383 usbd_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res); 384 sitd = (ehci_sitd_t *)buf_res.buffer; 385 386 /* initialize page cache pointer */ 387 388 sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i; 389 390 /* store a pointer to the transfer descriptor */ 391 392 sc->sc_isoc_fs_p_last[i] = sitd; 393 394 /* initialize full speed isochronous */ 395 396 sitd->sitd_self = 397 htohc32(sc, buf_res.physaddr) | 398 htohc32(sc, EHCI_LINK_SITD); 399 400 sitd->sitd_back = 401 htohc32(sc, EHCI_LINK_TERMINATE); 402 403 sitd->sitd_next = 404 sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self; 405 406 usbd_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res); 407 408 itd = (ehci_itd_t *)buf_res.buffer; 409 410 /* initialize page cache pointer */ 411 412 itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i; 413 414 /* store a pointer to the transfer descriptor */ 415 416 sc->sc_isoc_hs_p_last[i] = itd; 417 418 /* initialize high speed isochronous */ 419 420 itd->itd_self = 421 htohc32(sc, buf_res.physaddr) | 422 htohc32(sc, EHCI_LINK_ITD); 423 424 itd->itd_next = 425 sitd->sitd_self; 426 } 427 428 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 429 430 pframes = (uint32_t *)buf_res.buffer; 431 432 /* 433 * execution order: 434 * pframes -> high speed isochronous -> 435 * full speed isochronous -> interrupt QH's 436 */ 437 for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) { 438 pframes[i] = sc->sc_isoc_hs_p_last 439 [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self; 440 } 441 442 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 443 444 qh_t = (ehci_qh_t *)buf_res.buffer; 445 446 /* initialize page cache pointer */ 447 448 qh_t->page_cache = &sc->sc_hw.async_start_pc; 449 450 /* store a pointer to the queue head */ 451 452 sc->sc_async_p_last = qh_t; 453 454 /* init dummy QH that starts the async list */ 455 456 qh_t->qh_self = 457 htohc32(sc, buf_res.physaddr) | 458 htohc32(sc, EHCI_LINK_QH); 459 460 /* fill the QH */ 461 qh_t->qh_endp = 462 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 463 qh_t->qh_endphub = htohc32(sc, EHCI_QH_SET_MULT(1)); 464 qh_t->qh_link = qh_t->qh_self; 465 qh_t->qh_curqtd = 0; 466 467 /* fill the overlay qTD */ 468 qh_t->qh_qtd.qtd_next = htohc32(sc, EHCI_LINK_TERMINATE); 469 qh_t->qh_qtd.qtd_altnext = htohc32(sc, EHCI_LINK_TERMINATE); 470 qh_t->qh_qtd.qtd_status = htohc32(sc, EHCI_QTD_HALTED); 471 472 /* flush all cache into memory */ 473 474 usb_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc); 475 476#ifdef LOSCFG_USB_DEBUG 477 if (ehcidebug) { 478 ehci_dump_sqh(sc, sc->sc_async_p_last); 479 } 480#endif 481 482 /* finial setup */ 483 err = ehci_init_sub(sc); 484 485 if (!err) { 486 /* catch any lost interrupts */ 487 ehci_do_poll(&sc->sc_bus); 488 } 489 return (err); 490} 491 492/* 493 * shut down the controller when the system is going down 494 */ 495void 496ehci_detach(ehci_softc_t *sc) 497{ 498 USB_BUS_LOCK(&sc->sc_bus); 499 500 callout_stop(&sc->sc_tmo_pcd); 501 callout_stop(&sc->sc_tmo_poll); 502 503 EOWRITE4(sc, EHCI_USBINTR, 0); 504 USB_BUS_UNLOCK(&sc->sc_bus); 505 506 if (ehci_hcreset(sc)) { 507 DPRINTF("reset failed!\n"); 508 } 509 510 /* XXX let stray task complete */ 511 usb_pause_mtx(NULL, hz / 20); 512 513 callout_drain(&sc->sc_tmo_pcd); 514 callout_drain(&sc->sc_tmo_poll); 515} 516 517static void 518ehci_suspend(ehci_softc_t *sc) 519{ 520 DPRINTF("stopping the HC\n"); 521 522 /* reset HC */ 523 (void)ehci_hcreset(sc); 524} 525 526static void 527ehci_resume(ehci_softc_t *sc) 528{ 529 /* reset HC */ 530 (void)ehci_hcreset(sc); 531 532 /* setup HC */ 533 (void)ehci_init_sub(sc); 534 535 /* catch any lost interrupts */ 536 ehci_do_poll(&sc->sc_bus); 537} 538 539#ifdef LOSCFG_USB_DEBUG 540static void 541ehci_dump_regs(ehci_softc_t *sc) 542{ 543 uint32_t i; 544 545 i = EOREAD4(sc, EHCI_USBCMD); 546 PRINTK("cmd=0x%08x\n", i); 547 548 if (i & EHCI_CMD_ITC_1) 549 PRINTK(" EHCI_CMD_ITC_1\n"); 550 if (i & EHCI_CMD_ITC_2) 551 PRINTK(" EHCI_CMD_ITC_2\n"); 552 if (i & EHCI_CMD_ITC_4) 553 PRINTK(" EHCI_CMD_ITC_4\n"); 554 if (i & EHCI_CMD_ITC_8) 555 PRINTK(" EHCI_CMD_ITC_8\n"); 556 if (i & EHCI_CMD_ITC_16) 557 PRINTK(" EHCI_CMD_ITC_16\n"); 558 if (i & EHCI_CMD_ITC_32) 559 PRINTK(" EHCI_CMD_ITC_32\n"); 560 if (i & EHCI_CMD_ITC_64) 561 PRINTK(" EHCI_CMD_ITC_64\n"); 562 if (i & EHCI_CMD_ASPME) 563 PRINTK(" EHCI_CMD_ASPME\n"); 564 if (i & EHCI_CMD_ASPMC) 565 PRINTK(" EHCI_CMD_ASPMC\n"); 566 if (i & EHCI_CMD_LHCR) 567 PRINTK(" EHCI_CMD_LHCR\n"); 568 if (i & EHCI_CMD_IAAD) 569 PRINTK(" EHCI_CMD_IAAD\n"); 570 if (i & EHCI_CMD_ASE) 571 PRINTK(" EHCI_CMD_ASE\n"); 572 if (i & EHCI_CMD_PSE) 573 PRINTK(" EHCI_CMD_PSE\n"); 574 if (i & EHCI_CMD_FLS_M) 575 PRINTK(" EHCI_CMD_FLS_M\n"); 576 if (i & EHCI_CMD_HCRESET) 577 PRINTK(" EHCI_CMD_HCRESET\n"); 578 if (i & EHCI_CMD_RS) 579 PRINTK(" EHCI_CMD_RS\n"); 580 581 i = EOREAD4(sc, EHCI_USBSTS); 582 583 PRINTK("sts=0x%08x\n", i); 584 585 if (i & EHCI_STS_ASS) 586 PRINTK(" EHCI_STS_ASS\n"); 587 if (i & EHCI_STS_PSS) 588 PRINTK(" EHCI_STS_PSS\n"); 589 if (i & EHCI_STS_REC) 590 PRINTK(" EHCI_STS_REC\n"); 591 if (i & EHCI_STS_HCH) 592 PRINTK(" EHCI_STS_HCH\n"); 593 if (i & EHCI_STS_IAA) 594 PRINTK(" EHCI_STS_IAA\n"); 595 if (i & EHCI_STS_HSE) 596 PRINTK(" EHCI_STS_HSE\n"); 597 if (i & EHCI_STS_FLR) 598 PRINTK(" EHCI_STS_FLR\n"); 599 if (i & EHCI_STS_PCD) 600 PRINTK(" EHCI_STS_PCD\n"); 601 if (i & EHCI_STS_ERRINT) 602 PRINTK(" EHCI_STS_ERRINT\n"); 603 if (i & EHCI_STS_INT) 604 PRINTK(" EHCI_STS_INT\n"); 605 606 PRINTK("intr=0x%08x\n", 607 EOREAD4(sc, EHCI_USBINTR)); 608 PRINTK("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 609 EOREAD4(sc, EHCI_FRINDEX), 610 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 611 EOREAD4(sc, EHCI_PERIODICLISTBASE), 612 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 613 for (i = 1; i <= sc->sc_noport; i++) { 614 PRINTK("port %d status=0x%08x\n", i, 615 EOREAD4(sc, EHCI_PORTSC(i))); 616 } 617} 618 619static void 620ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type) 621{ 622 link = hc32toh(sc, link); 623 PRINTK("0x%08x", link); 624 if (link & EHCI_LINK_TERMINATE) 625 PRINTK("<T>"); 626 else { 627 PRINTK("<"); 628 if (type) { 629 switch (EHCI_LINK_TYPE(link)) { 630 case EHCI_LINK_ITD: 631 PRINTK("ITD"); 632 break; 633 case EHCI_LINK_QH: 634 PRINTK("QH"); 635 break; 636 case EHCI_LINK_SITD: 637 PRINTK("SITD"); 638 break; 639 case EHCI_LINK_FSTN: 640 PRINTK("FSTN"); 641 break; 642 } 643 } 644 PRINTK(">"); 645 } 646} 647 648static void 649ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd) 650{ 651 uint32_t s; 652 653 PRINTK(" next="); 654 ehci_dump_link(sc, qtd->qtd_next, 0); 655 PRINTK(" altnext="); 656 ehci_dump_link(sc, qtd->qtd_altnext, 0); 657 PRINTK("\n"); 658 s = hc32toh(sc, qtd->qtd_status); 659 PRINTK(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 660 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 661 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 662 PRINTK(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n", 663 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), 664 (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE", 665 (s & EHCI_QTD_HALTED) ? "-HALTED" : "", 666 (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "", 667 (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "", 668 (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "", 669 (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "", 670 (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "", 671 (s & EHCI_QTD_PINGSTATE) ? "-PING" : ""); 672 673 for (s = 0; s < 5; s++) { 674 PRINTK(" buffer[%d]=0x%08x\n", s, 675 hc32toh(sc, qtd->qtd_buffer[s])); 676 } 677 for (s = 0; s < 5; s++) { 678 PRINTK(" buffer_hi[%d]=0x%08x\n", s, 679 hc32toh(sc, qtd->qtd_buffer_hi[s])); 680 } 681} 682 683static uint8_t 684ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd) 685{ 686 uint8_t temp; 687 688 usb_pc_cpu_invalidate(sqtd->page_cache); 689 PRINTK("QTD(%p) at 0x%08x:\n", sqtd, hc32toh(sc, sqtd->qtd_self)); 690 ehci_dump_qtd(sc, sqtd); 691 temp = (sqtd->qtd_next & htohc32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0; 692 return (temp); 693} 694 695static void 696ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd) 697{ 698 uint16_t i; 699 uint8_t stop; 700 701 stop = 0; 702 for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) { 703 stop = ehci_dump_sqtd(sc, sqtd); 704 } 705 if (sqtd) { 706 PRINTK("dump aborted, too many TDs\n"); 707 } 708} 709 710static void 711ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh) 712{ 713 uint32_t endp; 714 uint32_t endphub; 715 716 usb_pc_cpu_invalidate(qh->page_cache); 717 PRINTK("QH(%p) at 0x%08x:\n", qh, hc32toh(sc, qh->qh_self) & ~0x1F); 718 PRINTK(" link="); 719 ehci_dump_link(sc, qh->qh_link, 1); 720 PRINTK("\n"); 721 endp = hc32toh(sc, qh->qh_endp); 722 PRINTK(" endp=0x%08x\n", endp); 723 PRINTK(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 724 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 725 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 726 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 727 PRINTK(" mpl=0x%x ctl=%d nrl=%d\n", 728 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 729 EHCI_QH_GET_NRL(endp)); 730 endphub = hc32toh(sc, qh->qh_endphub); 731 PRINTK(" endphub=0x%08x\n", endphub); 732 PRINTK(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 733 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 734 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 735 EHCI_QH_GET_MULT(endphub)); 736 PRINTK(" curqtd="); 737 ehci_dump_link(sc, qh->qh_curqtd, 0); 738 PRINTK("\n"); 739 PRINTK("Overlay qTD:\n"); 740 ehci_dump_qtd(sc, (void *)&qh->qh_qtd); 741} 742 743static void 744ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd) 745{ 746 usb_pc_cpu_invalidate(sitd->page_cache); 747 PRINTK("SITD(%p) at 0x%08x\n", sitd, hc32toh(sc, sitd->sitd_self) & ~0x1F); 748 PRINTK(" next=0x%08x\n", hc32toh(sc, sitd->sitd_next)); 749 PRINTK(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n", 750 hc32toh(sc, sitd->sitd_portaddr), 751 (sitd->sitd_portaddr & htohc32(sc, EHCI_SITD_SET_DIR_IN)) 752 ? "in" : "out", 753 EHCI_SITD_GET_ADDR(hc32toh(sc, sitd->sitd_portaddr)), 754 EHCI_SITD_GET_ENDPT(hc32toh(sc, sitd->sitd_portaddr)), 755 EHCI_SITD_GET_PORT(hc32toh(sc, sitd->sitd_portaddr)), 756 EHCI_SITD_GET_HUBA(hc32toh(sc, sitd->sitd_portaddr))); 757 PRINTK(" mask=0x%08x\n", hc32toh(sc, sitd->sitd_mask)); 758 PRINTK(" status=0x%08x <%s> len=0x%x\n", hc32toh(sc, sitd->sitd_status), 759 (sitd->sitd_status & htohc32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "", 760 EHCI_SITD_GET_LEN(hc32toh(sc, sitd->sitd_status))); 761 PRINTK(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n", 762 hc32toh(sc, sitd->sitd_back), 763 hc32toh(sc, sitd->sitd_bp[0]), 764 hc32toh(sc, sitd->sitd_bp[1]), 765 hc32toh(sc, sitd->sitd_bp_hi[0]), 766 hc32toh(sc, sitd->sitd_bp_hi[1])); 767} 768 769static void 770ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd) 771{ 772 usb_pc_cpu_invalidate(itd->page_cache); 773 PRINTK("ITD(%p) at 0x%08x\n", itd, hc32toh(sc, itd->itd_self) & ~0x1F); 774 PRINTK(" next=0x%08x\n", hc32toh(sc, itd->itd_next)); 775 PRINTK(" status[0]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[0]), 776 (itd->itd_status[0] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 777 PRINTK(" status[1]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[1]), 778 (itd->itd_status[1] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 779 PRINTK(" status[2]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[2]), 780 (itd->itd_status[2] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 781 PRINTK(" status[3]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[3]), 782 (itd->itd_status[3] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 783 PRINTK(" status[4]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[4]), 784 (itd->itd_status[4] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 785 PRINTK(" status[5]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[5]), 786 (itd->itd_status[5] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 787 PRINTK(" status[6]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[6]), 788 (itd->itd_status[6] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 789 PRINTK(" status[7]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[7]), 790 (itd->itd_status[7] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 791 PRINTK(" bp[0]=0x%08x\n", hc32toh(sc, itd->itd_bp[0])); 792 PRINTK(" addr=0x%02x; endpt=0x%01x\n", 793 EHCI_ITD_GET_ADDR(hc32toh(sc, itd->itd_bp[0])), 794 EHCI_ITD_GET_ENDPT(hc32toh(sc, itd->itd_bp[0]))); 795 PRINTK(" bp[1]=0x%08x\n", hc32toh(sc, itd->itd_bp[1])); 796 PRINTK(" dir=%s; mpl=0x%02x\n", 797 (hc32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out", 798 EHCI_ITD_GET_MPL(hc32toh(sc, itd->itd_bp[1]))); 799 PRINTK(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n", 800 hc32toh(sc, itd->itd_bp[2]), 801 hc32toh(sc, itd->itd_bp[3]), 802 hc32toh(sc, itd->itd_bp[4]), 803 hc32toh(sc, itd->itd_bp[5]), 804 hc32toh(sc, itd->itd_bp[6])); 805 PRINTK(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n" 806 " 0x%08x,0x%08x,0x%08x\n", 807 hc32toh(sc, itd->itd_bp_hi[0]), 808 hc32toh(sc, itd->itd_bp_hi[1]), 809 hc32toh(sc, itd->itd_bp_hi[2]), 810 hc32toh(sc, itd->itd_bp_hi[3]), 811 hc32toh(sc, itd->itd_bp_hi[4]), 812 hc32toh(sc, itd->itd_bp_hi[5]), 813 hc32toh(sc, itd->itd_bp_hi[6])); 814} 815 816static void 817ehci_dump_isoc(ehci_softc_t *sc) 818{ 819 ehci_itd_t *itd; 820 ehci_sitd_t *sitd; 821 uint16_t max = 1000; 822 uint16_t pos; 823 824 pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) & 825 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 826 827 PRINTK("%s: isochronous dump from frame 0x%03x:\n", 828 __FUNCTION__, pos); 829 830 itd = sc->sc_isoc_hs_p_last[pos]; 831 sitd = sc->sc_isoc_fs_p_last[pos]; 832 833 while (itd && max && max--) { 834 ehci_dump_itd(sc, itd); 835 itd = itd->prev; 836 } 837 838 while (sitd && max && max--) { 839 ehci_dump_sitd(sc, sitd); 840 sitd = sitd->prev; 841 } 842} 843 844#endif 845 846static void 847ehci_transfer_intr_enqueue(struct usb_xfer *xfer) 848{ 849 /* check for early completion */ 850 if (ehci_check_transfer(xfer)) { 851 DPRINTFN(0, " ehci_check_transfer return\n"); 852 return; 853 } 854 DPRINTFN(7, " enqueue\n"); 855 /* put transfer on interrupt queue */ 856 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 857 858 /* start timeout, if any */ 859 if (xfer->timeout != 0) { 860 usbd_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout); 861 } 862} 863 864#define EHCI_APPEND_FS_TD(std, last) (last) = _ehci_append_fs_td(std, last) 865static ehci_sitd_t * 866_ehci_append_fs_td(ehci_sitd_t *ehci_std, ehci_sitd_t *last) 867{ 868 DPRINTFN(11, "%p to %p\n", ehci_std, last); 869 870 /* (sc->sc_bus.mtx) must be locked */ 871 872 ehci_std->next = last->next; 873 ehci_std->sitd_next = last->sitd_next; 874 875 ehci_std->prev = last; 876 877 usb_pc_cpu_flush(ehci_std->page_cache); 878 879 /* 880 * the last->next->prev is never followed: std->next->prev = std; 881 */ 882 last->next = ehci_std; 883 last->sitd_next = ehci_std->sitd_self; 884 885 usb_pc_cpu_flush(last->page_cache); 886 887 return (ehci_std); 888} 889 890#define EHCI_APPEND_HS_TD(std, last) (last) = _ehci_append_hs_td(std, last) 891static ehci_itd_t * 892_ehci_append_hs_td(ehci_itd_t *ehci_std, ehci_itd_t *last) 893{ 894 DPRINTFN(11, "%p to %p\n", ehci_std, last); 895 896 /* (sc->sc_bus.mtx) must be locked */ 897 898 ehci_std->next = last->next; 899 ehci_std->itd_next = last->itd_next; 900 901 ehci_std->prev = last; 902 903 usb_pc_cpu_flush(ehci_std->page_cache); 904 905 /* 906 * the last->next->prev is never followed: std->next->prev = std; 907 */ 908 last->next = ehci_std; 909 last->itd_next = ehci_std->itd_self; 910 911 usb_pc_cpu_flush(last->page_cache); 912 913 return (ehci_std); 914} 915 916#define EHCI_APPEND_QH(sqh, last) (last) = _ehci_append_qh(sqh, last) 917static ehci_qh_t * 918_ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last) 919{ 920 DPRINTFN(11, "%p to %p\n", sqh, last); 921 922 if (sqh->prev != NULL) { 923 /* should not happen */ 924 DPRINTFN(0, "QH already linked!\n"); 925 return (last); 926 } 927 /* (sc->sc_bus.mtx) must be locked */ 928 929 sqh->next = last->next; 930 sqh->qh_link = last->qh_link; 931 932 sqh->prev = last; 933 934 usb_pc_cpu_flush(sqh->page_cache); 935 936 /* 937 * the last->next->prev is never followed: sqh->next->prev = sqh; 938 */ 939 940 last->next = sqh; 941 last->qh_link = sqh->qh_self; 942 943 usb_pc_cpu_flush(last->page_cache); 944 945 return (sqh); 946} 947 948#define EHCI_REMOVE_FS_TD(std, last) (last) = _ehci_remove_fs_td(std, last) 949static ehci_sitd_t * 950_ehci_remove_fs_td(ehci_sitd_t *ehci_std, ehci_sitd_t *last) 951{ 952 DPRINTFN(11, "%p from %p\n", ehci_std, last); 953 954 /* (sc->sc_bus.mtx) must be locked */ 955 956 ehci_std->prev->next = ehci_std->next; 957 ehci_std->prev->sitd_next = ehci_std->sitd_next; 958 959 usb_pc_cpu_flush(ehci_std->prev->page_cache); 960 961 if (ehci_std->next) { 962 ehci_std->next->prev = ehci_std->prev; 963 usb_pc_cpu_flush(ehci_std->next->page_cache); 964 } 965 return ((last == ehci_std) ? ehci_std->prev : last); 966} 967 968#define EHCI_REMOVE_HS_TD(std, last) (last) = _ehci_remove_hs_td(std, last) 969static ehci_itd_t * 970_ehci_remove_hs_td(ehci_itd_t *ehci_std, ehci_itd_t *last) 971{ 972 DPRINTFN(11, "%p from %p\n", ehci_std, last); 973 974 /* (sc->sc_bus.mtx) must be locked */ 975 976 ehci_std->prev->next = ehci_std->next; 977 ehci_std->prev->itd_next = ehci_std->itd_next; 978 979 usb_pc_cpu_flush(ehci_std->prev->page_cache); 980 981 if (ehci_std->next) { 982 ehci_std->next->prev = ehci_std->prev; 983 usb_pc_cpu_flush(ehci_std->next->page_cache); 984 } 985 return ((last == ehci_std) ? ehci_std->prev : last); 986} 987 988#define EHCI_REMOVE_QH(sqh, last) (last) = _ehci_remove_qh(sqh, last) 989static ehci_qh_t * 990_ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last) 991{ 992 DPRINTFN(11, "%p from %p\n", sqh, last); 993 994 /* (sc->sc_bus.mtx) must be locked */ 995 996 /* only remove if not removed from a queue */ 997 if (sqh->prev) { 998 sqh->prev->next = sqh->next; 999 sqh->prev->qh_link = sqh->qh_link; 1000 1001 usb_pc_cpu_flush(sqh->prev->page_cache); 1002 1003 if (sqh->next) { 1004 sqh->next->prev = sqh->prev; 1005 usb_pc_cpu_flush(sqh->next->page_cache); 1006 } 1007 last = ((last == sqh) ? sqh->prev : last); 1008 1009 sqh->prev = 0; 1010 1011 usb_pc_cpu_flush(sqh->page_cache); 1012 } 1013 return (last); 1014} 1015 1016static void 1017ehci_data_toggle_update(struct usb_xfer *xfer, uint16_t actlen, uint16_t xlen) 1018{ 1019 uint16_t rem; 1020 uint8_t dt; 1021 1022 /* count number of full packets */ 1023 dt = (actlen / xfer->max_packet_size) & 1; 1024 1025 /* compute remainder */ 1026 rem = actlen % xfer->max_packet_size; 1027 1028 if (rem > 0) 1029 dt ^= 1; /* short packet at the end */ 1030 else if (actlen != xlen) 1031 dt ^= 1; /* zero length packet at the end */ 1032 else if (xlen == 0) 1033 dt ^= 1; /* zero length transfer */ 1034 1035 xfer->endpoint->toggle_next ^= dt; 1036} 1037 1038static usb_error_t 1039ehci_non_isoc_done_sub(struct usb_xfer *xfer) 1040{ 1041 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1042 ehci_qtd_t *td; 1043 ehci_qtd_t *td_alt_next; 1044 uint32_t status; 1045 uint16_t len; 1046 1047 td = (ehci_qtd_t *)xfer->td_transfer_cache; 1048 td_alt_next = td->alt_next; 1049 1050 if (xfer->aframes != xfer->nframes) { 1051 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 1052 } 1053 while (1) { 1054 usb_pc_cpu_invalidate(td->page_cache); 1055 status = hc32toh(sc, td->qtd_status); 1056 1057 len = EHCI_QTD_GET_BYTES(status); 1058 1059 /* 1060 * Verify the status length and 1061 * add the length to "frlengths[]": 1062 */ 1063 if (len > td->len) { 1064 /* should not happen */ 1065 DPRINTF("Invalid status length, " 1066 "0x%04x/0x%04x bytes\n", len, td->len); 1067 status |= EHCI_QTD_HALTED; 1068 } else if (xfer->aframes != xfer->nframes) { 1069 xfer->frlengths[xfer->aframes] += td->len - len; 1070 /* manually update data toggle */ 1071 ehci_data_toggle_update(xfer, td->len - len, td->len); 1072 } 1073 1074 /* Check for last transfer */ 1075 if (((void *)td) == xfer->td_transfer_last) { 1076 td = NULL; 1077 break; 1078 } 1079 /* Check for transfer error */ 1080 if (status & EHCI_QTD_HALTED) { 1081 /* the transfer is finished */ 1082 td = NULL; 1083 break; 1084 } 1085 /* Check for short transfer */ 1086 if (len > 0) { 1087 if (xfer->flags_int.short_frames_ok) { 1088 /* follow alt next */ 1089 td = td->alt_next; 1090 } else { 1091 /* the transfer is finished */ 1092 td = NULL; 1093 } 1094 break; 1095 } 1096 td = td->obj_next; 1097 1098 if (td->alt_next != td_alt_next) { 1099 /* this USB frame is complete */ 1100 break; 1101 } 1102 } 1103 1104 /* update transfer cache */ 1105 1106 xfer->td_transfer_cache = td; 1107 1108#ifdef LOSCFG_USB_DEBUG 1109 if (status & EHCI_QTD_STATERRS) { 1110 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x" 1111 "status=%s%s%s%s%s%s%s%s\n", 1112 xfer->address, xfer->endpointno, xfer->aframes, 1113 (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1114 (status & EHCI_QTD_HALTED) ? "[HALTED]" : "", 1115 (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "", 1116 (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "", 1117 (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "", 1118 (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "", 1119 (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "", 1120 (status & EHCI_QTD_PINGSTATE) ? "[PING]" : ""); 1121 } 1122#endif 1123 if (status & EHCI_QTD_HALTED) { 1124 if ((xfer->xroot->udev->parent_hs_hub != NULL) || 1125 (xfer->xroot->udev->address != 0)) { 1126 /* try to separate I/O errors from STALL */ 1127 if (EHCI_QTD_GET_CERR(status) == 0) 1128 return (USB_ERR_IOERROR); 1129 } 1130 return (USB_ERR_STALLED); 1131 } 1132 return (USB_ERR_NORMAL_COMPLETION); 1133} 1134 1135static void 1136ehci_non_isoc_done(struct usb_xfer *xfer) 1137{ 1138 ehci_qh_t *qh; 1139 usb_error_t err = USB_ERR_NORMAL_COMPLETION; 1140 1141 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", xfer, xfer->endpoint); 1142 1143#ifdef LOSCFG_USB_DEBUG 1144 if (ehcidebug > 10) { 1145 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1146 ehci_dump_sqtds(sc, xfer->td_transfer_first); 1147 } 1148#endif 1149 1150 /* extract data toggle directly from the QH's overlay area */ 1151 qh = (ehci_qh_t *)xfer->qh_start[xfer->flags_int.curr_dma_set]; 1152 1153 usb_pc_cpu_invalidate(qh->page_cache); 1154 1155 /* reset scanner */ 1156 xfer->td_transfer_cache = xfer->td_transfer_first; 1157 if (xfer->flags_int.control_xfr) { 1158 if (xfer->flags_int.control_hdr) { 1159 err = ehci_non_isoc_done_sub(xfer); 1160 } 1161 xfer->aframes = 1; 1162 1163 if (xfer->td_transfer_cache == NULL) { 1164 goto done; 1165 } 1166 } 1167 while (xfer->aframes != xfer->nframes) { 1168 err = ehci_non_isoc_done_sub(xfer); 1169 xfer->aframes++; 1170 1171 if (xfer->td_transfer_cache == NULL) { 1172 goto done; 1173 } 1174 } 1175 1176 if (xfer->flags_int.control_xfr && 1177 !xfer->flags_int.control_act) { 1178 err = ehci_non_isoc_done_sub(xfer); 1179 } 1180done: 1181 ehci_device_done(xfer, err); 1182} 1183 1184/*------------------------------------------------------------------------* 1185 * ehci_check_transfer 1186 * 1187 * Return values: 1188 * 0: USB transfer is not finished 1189 * Else: USB transfer is finished 1190 *------------------------------------------------------------------------*/ 1191static uint8_t 1192ehci_check_transfer(struct usb_xfer *xfer) 1193{ 1194 const struct usb_pipe_methods *methods = xfer->endpoint->methods; 1195 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1196 1197 uint32_t status; 1198 1199 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1200 1201 if (methods == &ehci_device_isoc_fs_methods) { 1202 ehci_sitd_t *td; 1203 1204 /* isochronous full speed transfer */ 1205 1206 td = (ehci_sitd_t *)xfer->td_transfer_last; 1207 usb_pc_cpu_invalidate(td->page_cache); 1208 status = hc32toh(sc, td->sitd_status); 1209 1210 /* also check if first is complete */ 1211 1212 td = (ehci_sitd_t *)xfer->td_transfer_first; 1213 usb_pc_cpu_invalidate(td->page_cache); 1214 status |= hc32toh(sc, td->sitd_status); 1215 1216 if (!(status & EHCI_SITD_ACTIVE)) { 1217 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1218 goto transferred; 1219 } 1220 } else if (methods == &ehci_device_isoc_hs_methods) { 1221 ehci_itd_t *td; 1222 1223 /* isochronous high speed transfer */ 1224 1225 /* check last transfer */ 1226 td = (ehci_itd_t *)xfer->td_transfer_last; 1227 usb_pc_cpu_invalidate(td->page_cache); 1228 status = td->itd_status[0]; 1229 status |= td->itd_status[1]; 1230 status |= td->itd_status[2]; 1231 status |= td->itd_status[3]; 1232 status |= td->itd_status[4]; 1233 status |= td->itd_status[5]; 1234 status |= td->itd_status[6]; 1235 status |= td->itd_status[7]; 1236 1237 /* also check first transfer */ 1238 td = (ehci_itd_t *)xfer->td_transfer_first; 1239 usb_pc_cpu_invalidate(td->page_cache); 1240 status |= td->itd_status[0]; 1241 status |= td->itd_status[1]; 1242 status |= td->itd_status[2]; 1243 status |= td->itd_status[3]; 1244 status |= td->itd_status[4]; 1245 status |= td->itd_status[5]; 1246 status |= td->itd_status[6]; 1247 status |= td->itd_status[7]; 1248 1249 /* if no transactions are active we continue */ 1250 if (!(status & htohc32(sc, EHCI_ITD_ACTIVE))) { 1251 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1252 goto transferred; 1253 } 1254 } else { 1255 ehci_qtd_t *td; 1256 ehci_qh_t *qh; 1257 1258 /* non-isochronous transfer */ 1259 1260 /* 1261 * check whether there is an error somewhere in the middle, 1262 * or whether there was a short packet (SPD and not ACTIVE) 1263 */ 1264 td = (ehci_qtd_t *)xfer->td_transfer_cache; 1265 1266 qh = (ehci_qh_t *)xfer->qh_start[xfer->flags_int.curr_dma_set]; 1267 1268 usb_pc_cpu_invalidate(qh->page_cache); 1269 1270 status = hc32toh(sc, qh->qh_qtd.qtd_status); 1271 if (status & EHCI_QTD_ACTIVE) { 1272 /* transfer is pending */ 1273 goto done; 1274 } 1275 1276 while (1) { 1277 usb_pc_cpu_invalidate(td->page_cache); 1278 status = hc32toh(sc, td->qtd_status); 1279 1280 /* 1281 * Check if there is an active TD which 1282 * indicates that the transfer isn't done. 1283 */ 1284 if (status & EHCI_QTD_ACTIVE) { 1285 /* update cache */ 1286 xfer->td_transfer_cache = td; 1287 goto done; 1288 } 1289 /* 1290 * last transfer descriptor makes the transfer done 1291 */ 1292 if (((void *)td) == xfer->td_transfer_last) { 1293 break; 1294 } 1295 /* 1296 * any kind of error makes the transfer done 1297 */ 1298 if (status & EHCI_QTD_HALTED) { 1299 break; 1300 } 1301 /* 1302 * if there is no alternate next transfer, a short 1303 * packet also makes the transfer done 1304 */ 1305 if (EHCI_QTD_GET_BYTES(status)) { 1306 if (xfer->flags_int.short_frames_ok) { 1307 /* follow alt next */ 1308 if (td->alt_next) { 1309 td = td->alt_next; 1310 continue; 1311 } 1312 } 1313 /* transfer is done */ 1314 break; 1315 } 1316 td = td->obj_next; 1317 } 1318 ehci_non_isoc_done(xfer); 1319 goto transferred; 1320 } 1321 1322done: 1323 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1324 return (0); 1325 1326transferred: 1327 return (1); 1328} 1329 1330static void 1331ehci_pcd_enable(ehci_softc_t *sc) 1332{ 1333 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1334 1335 sc->sc_eintrs |= EHCI_STS_PCD; 1336 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1337 1338 /* acknowledge any PCD interrupt */ 1339 EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD); 1340 1341 ehci_root_intr(sc); 1342} 1343 1344static void 1345ehci_interrupt_poll(ehci_softc_t *sc) 1346{ 1347 struct usb_xfer *xfer; 1348 1349repeat: 1350 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1351 /* 1352 * check if transfer is transferred 1353 */ 1354 if (ehci_check_transfer(xfer)) { 1355 /* queue has been modified */ 1356 goto repeat; 1357 } 1358 } 1359} 1360 1361/* 1362 * Some EHCI chips from VIA / ATI seem to trigger interrupts before 1363 * writing back the qTD status, or miss signalling occasionally under 1364 * heavy load. If the host machine is too fast, we can miss 1365 * transaction completion - when we scan the active list the 1366 * transaction still seems to be active. This generally exhibits 1367 * itself as a umass stall that never recovers. 1368 * 1369 * We work around this behaviour by setting up this callback after any 1370 * softintr that completes with transactions still pending, giving us 1371 * another chance to check for completion after the writeback has 1372 * taken place. 1373 */ 1374static void 1375ehci_poll_timeout(void *ehci_arg) 1376{ 1377 ehci_softc_t *sc = (ehci_softc_t *)ehci_arg; 1378 1379 DPRINTFN(3, "\n"); 1380 ehci_interrupt_poll(sc); 1381} 1382 1383/*------------------------------------------------------------------------* 1384 * ehci_interrupt - EHCI interrupt handler 1385 * 1386 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1387 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1388 * is present ! 1389 *------------------------------------------------------------------------*/ 1390void 1391ehci_interrupt(unsigned int irq, ehci_softc_t *sc) 1392{ 1393 uint32_t status; 1394 1395 USB_BUS_LOCK(&sc->sc_bus); 1396 DPRINTFN(16, "real interrupt\n"); 1397 1398#ifdef LOSCFG_USB_DEBUG 1399 if (ehcidebug > 15) { 1400 ehci_dump_regs(sc); 1401 } 1402#endif 1403 1404 status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1405 1406 if (status == 0) { 1407 /* the interrupt was not for us */ 1408 goto done; 1409 } 1410 if (!(status & sc->sc_eintrs)) { 1411 goto done; 1412 } 1413 EOWRITE4(sc, EHCI_USBSTS, status); /* acknowledge */ 1414 1415 status &= sc->sc_eintrs; 1416 1417#ifdef LOSCFG_USB_DEBUG 1418 if (status & EHCI_STS_HSE) { 1419 ehci_dump_regs(sc); 1420 ehci_dump_isoc(sc); 1421 } 1422#endif 1423 if (status & EHCI_STS_PCD) { 1424 /* 1425 * Disable PCD interrupt for now, because it will be 1426 * on until the port has been reset. 1427 */ 1428 sc->sc_eintrs &= ~EHCI_STS_PCD; 1429 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1430 1431 ehci_root_intr(sc); 1432 1433 /* do not allow RHSC interrupts > 1 per second */ 1434 callout_reset(&sc->sc_tmo_pcd, hz, 1435 (void *)&ehci_pcd_enable, sc); 1436 } 1437 status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA); 1438 1439 if (status != 0) { 1440 /* block unprocessed interrupts */ 1441 sc->sc_eintrs &= ~status; 1442 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1443 } 1444 /* poll all the USB transfers */ 1445 ehci_interrupt_poll(sc); 1446 1447 if (sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) { 1448 callout_reset(&sc->sc_tmo_poll, hz / 128, 1449 (void *)&ehci_poll_timeout, sc); 1450 } 1451 1452done: 1453 USB_BUS_UNLOCK(&sc->sc_bus); 1454} 1455 1456/* 1457 * called when a request does not complete 1458 */ 1459static void 1460ehci_timeout(void *ehci_arg) 1461{ 1462 struct usb_xfer *xfer = (struct usb_xfer *)ehci_arg; 1463 1464 DPRINTF("xfer=%p\n", xfer); 1465 1466 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1467 1468 /* transfer is transferred */ 1469 ehci_device_done(xfer, USB_ERR_TIMEOUT); 1470} 1471 1472static void 1473ehci_do_poll(struct usb_bus *bus) 1474{ 1475 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1476 1477 USB_BUS_LOCK(&sc->sc_bus); 1478 ehci_interrupt_poll(sc); 1479 USB_BUS_UNLOCK(&sc->sc_bus); 1480} 1481 1482static void 1483ehci_setup_standard_chain_sub(struct ehci_std_temp *temp) 1484{ 1485 struct usb_page_search buf_res; 1486 ehci_qtd_t *td; 1487 ehci_qtd_t *td_next; 1488 ehci_qtd_t *td_alt_next; 1489 uint32_t buf_offset; 1490 uint32_t average; 1491 uint32_t len_old; 1492 uint32_t terminate; 1493 uint32_t qtd_altnext; 1494 uint8_t shortpkt_old; 1495 uint8_t precompute; 1496 1497 terminate = temp->sc->sc_terminate_self; 1498 qtd_altnext = temp->sc->sc_terminate_self; 1499 td_alt_next = NULL; 1500 buf_offset = 0; 1501 shortpkt_old = temp->shortpkt; 1502 len_old = temp->len; 1503 precompute = 1; 1504 1505restart: 1506 1507 td = temp->td; 1508 td_next = temp->td_next; 1509 1510 while (1) { 1511 if (temp->len == 0) { 1512 if (temp->shortpkt) { 1513 break; 1514 } 1515 /* send a Zero Length Packet, ZLP, last */ 1516 1517 temp->shortpkt = 1; 1518 average = 0; 1519 1520 } else { 1521 average = temp->average; 1522 1523 if (temp->len < average) { 1524 if (temp->len % temp->max_frame_size) { 1525 temp->shortpkt = 1; 1526 } 1527 average = temp->len; 1528 } 1529 } 1530 1531 if (td_next == NULL) { 1532 panic("%s: out of EHCI transfer descriptors!", __FUNCTION__); 1533 } 1534 /* get next TD */ 1535 1536 td = td_next; 1537 td_next = td->obj_next; 1538 1539 /* check if we are pre-computing */ 1540 1541 if (precompute) { 1542 /* update remaining length */ 1543 1544 temp->len -= average; 1545 1546 continue; 1547 } 1548 /* fill out current TD */ 1549 1550 td->qtd_status = 1551 temp->qtd_status | 1552 htohc32(temp->sc, EHCI_QTD_IOC | 1553 EHCI_QTD_SET_BYTES(average)); 1554 1555 if (average == 0) { 1556 if (temp->auto_data_toggle == 0) { 1557 /* update data toggle, ZLP case */ 1558 1559 temp->qtd_status ^= 1560 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1561 } 1562 td->len = 0; 1563 1564 /* properly reset reserved fields */ 1565 td->qtd_buffer[0] = 0; 1566 td->qtd_buffer[1] = 0; 1567 td->qtd_buffer[2] = 0; 1568 td->qtd_buffer[3] = 0; 1569 td->qtd_buffer[4] = 0; 1570 td->qtd_buffer_hi[0] = 0; 1571 td->qtd_buffer_hi[1] = 0; 1572 td->qtd_buffer_hi[2] = 0; 1573 td->qtd_buffer_hi[3] = 0; 1574 td->qtd_buffer_hi[4] = 0; 1575 } else { 1576 uint8_t x; 1577 1578 if (temp->auto_data_toggle == 0) { 1579 /* update data toggle */ 1580 1581 if (((average + temp->max_frame_size - 1) / 1582 temp->max_frame_size) & 1) { 1583 temp->qtd_status ^= 1584 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1585 } 1586 } 1587 td->len = average; 1588 1589 /* update remaining length */ 1590 1591 temp->len -= average; 1592 1593 /* fill out buffer pointers */ 1594 1595 usbd_get_page(temp->pc, buf_offset, &buf_res); 1596 td->qtd_buffer[0] = 1597#if USB_HAVE_BUSDMA 1598 htohc32(temp->sc, buf_res.physaddr); 1599#else 1600 htohc32(temp->sc, (unsigned int)buf_res.buffer); 1601#endif 1602 td->qtd_buffer_hi[0] = 0; 1603 1604 x = 1; 1605 1606 while (average > EHCI_PAGE_SIZE) { 1607 average -= EHCI_PAGE_SIZE; 1608 buf_offset += EHCI_PAGE_SIZE; 1609 usbd_get_page(temp->pc, buf_offset, &buf_res); 1610 td->qtd_buffer[x] = 1611 htohc32(temp->sc, 1612#if USB_HAVE_BUSDMA 1613 buf_res.physaddr & (~0xFFF)); 1614#else 1615 (unsigned int)buf_res.buffer & (~0xFFF)); 1616#endif 1617 td->qtd_buffer_hi[x] = 0; 1618 x++; 1619 } 1620 1621 /* 1622 * NOTE: The "average" variable is never zero after 1623 * exiting the loop above ! 1624 * 1625 * NOTE: We have to subtract one from the offset to 1626 * ensure that we are computing the physical address 1627 * of a valid page ! 1628 */ 1629 buf_offset += average; 1630 usbd_get_page(temp->pc, buf_offset - 1, &buf_res); 1631 td->qtd_buffer[x] = 1632 htohc32(temp->sc, 1633#if USB_HAVE_BUSDMA 1634 buf_res.physaddr & (~0xFFF)); 1635#else 1636 (unsigned int)buf_res.buffer & (~0xFFF)); 1637#endif 1638 td->qtd_buffer_hi[x] = 0; 1639 1640 /* properly reset reserved fields */ 1641 while (++x < EHCI_QTD_NBUFFERS) { 1642 td->qtd_buffer[x] = 0; 1643 td->qtd_buffer_hi[x] = 0; 1644 } 1645 } 1646 1647 if (td_next) { 1648 1649 /* link the current TD with the next one */ 1650 td->qtd_next = td_next->qtd_self; 1651 } 1652 1653 td->qtd_altnext = qtd_altnext; 1654 td->alt_next = td_alt_next; 1655 1656 usb_pc_cpu_flush(td->page_cache); 1657 } 1658 1659 if (precompute) { 1660 precompute = 0; 1661 1662 /* setup alt next pointer, if any */ 1663 if (temp->last_frame) { 1664 td_alt_next = NULL; 1665 qtd_altnext = terminate; 1666 } else { 1667 /* we use this field internally */ 1668 td_alt_next = td_next; 1669 if (temp->setup_alt_next && td_next) { 1670 qtd_altnext = td_next->qtd_self; 1671 } else { 1672 qtd_altnext = terminate; 1673 } 1674 } 1675 1676 /* restore */ 1677 temp->shortpkt = shortpkt_old; 1678 temp->len = len_old; 1679 goto restart; 1680 } 1681 temp->td = td; 1682 temp->td_next = td_next; 1683} 1684 1685static void 1686ehci_setup_standard_chain(struct usb_xfer *xfer, ehci_qh_t **qh_last) 1687{ 1688 struct ehci_std_temp temp; 1689 const struct usb_pipe_methods *methods; 1690 ehci_qh_t *qh; 1691 ehci_qtd_t *td; 1692 uint32_t qh_endp; 1693 uint32_t qh_endphub; 1694 uint32_t x; 1695 uint32_t int_save; 1696 1697 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1698 xfer->address, UE_GET_ADDR(xfer->endpointno), 1699 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1700 1701 temp.average = xfer->max_hc_frame_size; 1702 temp.max_frame_size = xfer->max_frame_size; 1703 temp.sc = EHCI_BUS2SC(xfer->xroot->bus); 1704 1705 /* toggle the DMA set we are using */ 1706 xfer->flags_int.curr_dma_set ^= 1; 1707 1708 /* get next DMA set */ 1709 td = (ehci_qtd_t *)xfer->td_start[xfer->flags_int.curr_dma_set]; 1710 1711 xfer->td_transfer_first = td; 1712 xfer->td_transfer_cache = td; 1713 1714 temp.td = NULL; 1715 temp.td_next = td; 1716 temp.qtd_status = 0; 1717 temp.last_frame = 0; 1718 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1719 1720 if (xfer->flags_int.control_xfr) { 1721 if (xfer->endpoint->toggle_next) { 1722 /* DATA1 is next */ 1723 temp.qtd_status |= 1724 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1U)); 1725 } 1726 temp.auto_data_toggle = 0; 1727 } else { 1728 temp.auto_data_toggle = 1; 1729 } 1730 1731 if ((xfer->xroot->udev->parent_hs_hub != NULL) || 1732 (xfer->xroot->udev->address != 0)) { 1733 /* max 3 retries */ 1734 temp.qtd_status |= 1735 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1736 } 1737 /* check if we should prepend a setup message */ 1738 1739 if (xfer->flags_int.control_xfr) { 1740 if (xfer->flags_int.control_hdr) { 1741 xfer->endpoint->toggle_next = 0; 1742 1743 temp.qtd_status &= 1744 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1745 temp.qtd_status |= htohc32(temp.sc, 1746 EHCI_QTD_ACTIVE | 1747 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 1748 EHCI_QTD_SET_TOGGLE(0)); 1749 1750 temp.len = xfer->frlengths[0]; 1751 temp.pc = xfer->frbuffers + 0; 1752 temp.shortpkt = temp.len ? 1 : 0; 1753 /* check for last frame */ 1754 if (xfer->nframes == 1) { 1755 /* no STATUS stage yet, SETUP is last */ 1756 if (xfer->flags_int.control_act) { 1757 temp.last_frame = 1; 1758 temp.setup_alt_next = 0; 1759 } 1760 } 1761 ehci_setup_standard_chain_sub(&temp); 1762 } 1763 x = 1; 1764 } else { 1765 x = 0; 1766 } 1767 1768 while (x != xfer->nframes) { 1769 /* DATA0 / DATA1 message */ 1770 1771 temp.len = xfer->frlengths[x]; 1772 temp.pc = xfer->frbuffers + x; 1773 1774 x++; 1775 1776 if (x == xfer->nframes) { 1777 if (xfer->flags_int.control_xfr) { 1778 /* no STATUS stage yet, DATA is last */ 1779 if (xfer->flags_int.control_act) { 1780 temp.last_frame = 1; 1781 temp.setup_alt_next = 0; 1782 } 1783 } else { 1784 temp.last_frame = 1; 1785 temp.setup_alt_next = 0; 1786 } 1787 } 1788 /* keep previous data toggle and error count */ 1789 1790 temp.qtd_status &= 1791 htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1792 EHCI_QTD_SET_TOGGLE(1U)); 1793 1794 if (temp.len == 0) { 1795 /* make sure that we send an USB packet */ 1796 1797 temp.shortpkt = 0; 1798 1799 } else { 1800 /* regular data transfer */ 1801 1802 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1803 } 1804 1805 /* set endpoint direction */ 1806 1807 temp.qtd_status |= 1808 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 1809 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1810 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) : 1811 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1812 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT)); 1813 1814 ehci_setup_standard_chain_sub(&temp); 1815 } 1816 1817 /* check if we should append a status stage */ 1818 1819 if (xfer->flags_int.control_xfr && 1820 !xfer->flags_int.control_act) { 1821 /* 1822 * Send a DATA1 message and invert the current endpoint 1823 * direction. 1824 */ 1825 1826 temp.qtd_status &= htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1827 EHCI_QTD_SET_TOGGLE(1U)); 1828 temp.qtd_status |= 1829 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ? 1830 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1831 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) | 1832 EHCI_QTD_SET_TOGGLE(1U)) : 1833 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1834 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) | 1835 EHCI_QTD_SET_TOGGLE(1U)); 1836 1837 temp.len = 0; 1838 temp.pc = NULL; 1839 temp.shortpkt = 0; 1840 temp.last_frame = 1; 1841 temp.setup_alt_next = 0; 1842 1843 ehci_setup_standard_chain_sub(&temp); 1844 } 1845 td = temp.td; 1846 if (td == NULL) 1847 return; 1848 1849 /* the last TD terminates the transfer: */ 1850 td->qtd_next = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1851 td->qtd_altnext = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1852 1853 usb_pc_cpu_flush(td->page_cache); 1854 1855 /* must have at least one frame! */ 1856 1857 xfer->td_transfer_last = td; 1858 1859#ifdef LOSCFG_USB_DEBUG 1860 if (ehcidebug > 8) { 1861 DPRINTF("nexttog=%d; data before transfer:\n", 1862 xfer->endpoint->toggle_next); 1863 ehci_dump_sqtds(temp.sc, 1864 xfer->td_transfer_first); 1865 } 1866#endif 1867 1868 methods = xfer->endpoint->methods; 1869 1870 qh = (ehci_qh_t *)xfer->qh_start[xfer->flags_int.curr_dma_set]; 1871 1872 /* the "qh_link" field is filled when the QH is added */ 1873 1874 qh_endp = 1875 (EHCI_QH_SET_ADDR(xfer->address) | 1876 EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) | 1877 EHCI_QH_SET_MPL(xfer->max_packet_size)); 1878 1879 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 1880 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH); 1881 if (methods != &ehci_device_intr_methods) 1882 qh_endp |= EHCI_QH_SET_NRL(8U); 1883 } else { 1884 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) { 1885 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL); 1886 } else { 1887 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW); 1888 } 1889 1890 if (methods == &ehci_device_ctrl_methods) { 1891 qh_endp |= EHCI_QH_CTL; 1892 } 1893 if (methods != &ehci_device_intr_methods) { 1894 /* Only try one time per microframe! */ 1895 qh_endp |= EHCI_QH_SET_NRL(1); 1896 } 1897 } 1898 1899 if (temp.auto_data_toggle == 0) { 1900 /* software computes the data toggle */ 1901 qh_endp |= EHCI_QH_DTC; 1902 } 1903 1904 qh->qh_endp = htohc32(temp.sc, qh_endp); 1905 1906 qh_endphub = 1907 (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) | 1908 EHCI_QH_SET_CMASK(xfer->endpoint->usb_cmask) | 1909 EHCI_QH_SET_SMASK(xfer->endpoint->usb_smask) | 1910 EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 1911 EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no)); 1912 1913 qh->qh_endphub = htohc32(temp.sc, qh_endphub); 1914 qh->qh_curqtd = 0; 1915 1916 /* fill the overlay qTD */ 1917 1918 if (temp.auto_data_toggle && xfer->endpoint->toggle_next) { 1919 /* DATA1 is next */ 1920 qh->qh_qtd.qtd_status = htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1U)); 1921 } else { 1922 qh->qh_qtd.qtd_status = 0; 1923 } 1924 1925 td = (ehci_qtd_t *)xfer->td_transfer_first; 1926 1927 qh->qh_qtd.qtd_next = td->qtd_self; 1928 qh->qh_qtd.qtd_altnext = 1929 htohc32(temp.sc, EHCI_LINK_TERMINATE); 1930 1931 /* properly reset reserved fields */ 1932 qh->qh_qtd.qtd_buffer[0] = 0; 1933 qh->qh_qtd.qtd_buffer[1] = 0; 1934 qh->qh_qtd.qtd_buffer[2] = 0; 1935 qh->qh_qtd.qtd_buffer[3] = 0; 1936 qh->qh_qtd.qtd_buffer[4] = 0; 1937 qh->qh_qtd.qtd_buffer_hi[0] = 0; 1938 qh->qh_qtd.qtd_buffer_hi[1] = 0; 1939 qh->qh_qtd.qtd_buffer_hi[2] = 0; 1940 qh->qh_qtd.qtd_buffer_hi[3] = 0; 1941 qh->qh_qtd.qtd_buffer_hi[4] = 0; 1942 1943 usb_pc_cpu_flush(qh->page_cache); 1944 1945 if (xfer->xroot->udev->flags.self_suspended == 0) { 1946 spin_lock_irqsave(&g_usb_ehci_qh_spinlock, int_save); 1947 EHCI_APPEND_QH(qh, *qh_last); 1948 spin_unlock_irqrestore(&g_usb_ehci_qh_spinlock, int_save); 1949 } 1950} 1951 1952static void 1953ehci_root_intr(ehci_softc_t *sc) 1954{ 1955 uint16_t i; 1956 uint16_t m; 1957 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1958 1959 /* clear any old interrupt data */ 1960 (void)memset_s(sc->sc_hub_idata, sizeof(sc->sc_hub_idata), 0, sizeof(sc->sc_hub_idata)); 1961 1962 /* set bits */ 1963 m = (sc->sc_noport + 1); 1964 if (m > (8 * sizeof(sc->sc_hub_idata))) { 1965 m = (8 * sizeof(sc->sc_hub_idata)); 1966 } 1967 for (i = 1; i < m; i++) { 1968 /* pick out CHANGE bits from the status register */ 1969 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) { 1970 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 1971 DPRINTF("port %d changed\n", i); 1972 } 1973 } 1974 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 1975 sizeof(sc->sc_hub_idata)); 1976} 1977 1978static void 1979ehci_isoc_fs_done(ehci_softc_t *sc, struct usb_xfer *xfer) 1980{ 1981 uint32_t nframes = xfer->nframes; 1982 uint32_t status; 1983 uint32_t *plen = xfer->frlengths; 1984 uint16_t len = 0; 1985 ehci_sitd_t *td = (ehci_sitd_t *)xfer->td_transfer_first; 1986 ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos]; 1987 1988 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1989 xfer, xfer->endpoint); 1990 1991 while (nframes--) { 1992 if (td == NULL) { 1993 panic("%s:%d: out of TD's\n", 1994 __FUNCTION__, __LINE__); 1995 } 1996 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 1997 pp_last = &sc->sc_isoc_fs_p_last[0]; 1998 } 1999#ifdef LOSCFG_USB_DEBUG 2000 if (ehcidebug > 15) { 2001 DPRINTF("isoc FS-TD\n"); 2002 ehci_dump_sitd(sc, td); 2003 } 2004#endif 2005 usb_pc_cpu_invalidate(td->page_cache); 2006 status = hc32toh(sc, td->sitd_status); 2007 2008 len = EHCI_SITD_GET_LEN(status); 2009 2010 DPRINTFN(2, "status=0x%08x, rem=%u\n", status, len); 2011 2012 if (*plen >= len) { 2013 len = *plen - len; 2014 } else { 2015 len = 0; 2016 } 2017 2018 *plen = len; 2019 2020 /* remove FS-TD from schedule */ 2021 EHCI_REMOVE_FS_TD(td, *pp_last); 2022 2023 pp_last++; 2024 plen++; 2025 td = td->obj_next; 2026 } 2027 2028 xfer->aframes = xfer->nframes; 2029} 2030 2031static void 2032ehci_isoc_hs_done(ehci_softc_t *sc, struct usb_xfer *xfer) 2033{ 2034 uint32_t nframes = xfer->nframes; 2035 uint32_t status; 2036 uint32_t *plen = xfer->frlengths; 2037 uint16_t len = 0; 2038 uint8_t td_no = 0; 2039 ehci_itd_t *td = (ehci_itd_t *)xfer->td_transfer_first; 2040 ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos]; 2041 2042 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2043 xfer, xfer->endpoint); 2044 2045 while (nframes) { 2046 if (td == NULL) { 2047 panic("%s:%d: out of TD's\n", 2048 __FUNCTION__, __LINE__); 2049 } 2050 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2051 pp_last = &sc->sc_isoc_hs_p_last[0]; 2052 } 2053#ifdef LOSCFG_USB_DEBUG 2054 if (ehcidebug > 15) { 2055 DPRINTF("isoc HS-TD\n"); 2056 ehci_dump_itd(sc, td); 2057 } 2058#endif 2059 2060 usb_pc_cpu_invalidate(td->page_cache); 2061 status = hc32toh(sc, td->itd_status[td_no]); 2062 2063 len = EHCI_ITD_GET_LEN(status); 2064 2065 DPRINTFN(2, "status=0x%08x, len=%u\n", status, len); 2066 2067 if (xfer->endpoint->usb_smask & (1 << td_no)) { 2068 if (*plen >= len) { 2069 /* 2070 * The length is valid. NOTE: The 2071 * complete length is written back 2072 * into the status field, and not the 2073 * remainder like with other transfer 2074 * descriptor types. 2075 */ 2076 } else { 2077 /* Invalid length - truncate */ 2078 len = 0; 2079 } 2080 2081 *plen = len; 2082 plen++; 2083 nframes--; 2084 } 2085 2086 td_no++; 2087 2088 if ((td_no == 8) || (nframes == 0)) { 2089 /* remove HS-TD from schedule */ 2090 EHCI_REMOVE_HS_TD(td, *pp_last); 2091 pp_last++; 2092 2093 td_no = 0; 2094 td = td->obj_next; 2095 } 2096 } 2097 xfer->aframes = xfer->nframes; 2098} 2099 2100/* NOTE: "done" can be run two times in a row, 2101 * from close and from interrupt 2102 */ 2103static void 2104ehci_device_done(struct usb_xfer *xfer, usb_error_t error) 2105{ 2106 uintptr_t interrupt_ret; 2107 const struct usb_pipe_methods *methods = xfer->endpoint->methods; 2108 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2109 2110 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2111 2112 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2113 xfer, xfer->endpoint, error); 2114 2115 if ((methods == &ehci_device_bulk_methods) || 2116 (methods == &ehci_device_ctrl_methods)) { 2117#ifdef LOSCFG_USB_DEBUG 2118 if (ehcidebug > 8) { 2119 DPRINTF("nexttog=%d; data after transfer:\n", 2120 xfer->endpoint->toggle_next); 2121 ehci_dump_sqtds(sc, 2122 xfer->td_transfer_first); 2123 } 2124#endif 2125 2126 spin_lock_irqsave(&g_usb_ehci_qh_spinlock, interrupt_ret); 2127 EHCI_REMOVE_QH((ehci_qh_t *)xfer->qh_start[xfer->flags_int.curr_dma_set], 2128 sc->sc_async_p_last); 2129 spin_unlock_irqrestore(&g_usb_ehci_qh_spinlock, interrupt_ret); 2130 } 2131 if (methods == &ehci_device_intr_methods) { 2132 spin_lock_irqsave(&g_usb_ehci_qh_spinlock, interrupt_ret); 2133 EHCI_REMOVE_QH((ehci_qh_t *)xfer->qh_start[xfer->flags_int.curr_dma_set], 2134 sc->sc_intr_p_last[xfer->qh_pos]); 2135 spin_unlock_irqrestore(&g_usb_ehci_qh_spinlock, interrupt_ret); 2136 } 2137 /* 2138 * Only finish isochronous transfers once which will update 2139 * "xfer->frlengths". 2140 */ 2141 if (xfer->td_transfer_first && 2142 xfer->td_transfer_last) { 2143 if (methods == &ehci_device_isoc_fs_methods) { 2144 ehci_isoc_fs_done(sc, xfer); 2145 } 2146 if (methods == &ehci_device_isoc_hs_methods) { 2147 ehci_isoc_hs_done(sc, xfer); 2148 } 2149 xfer->td_transfer_first = NULL; 2150 xfer->td_transfer_last = NULL; 2151 } 2152 /* dequeue transfer and start next transfer */ 2153 usbd_transfer_done(xfer, error); 2154} 2155 2156/*------------------------------------------------------------------------* 2157 * ehci bulk support 2158 *------------------------------------------------------------------------*/ 2159static void 2160ehci_device_bulk_open(struct usb_xfer *xfer) 2161{ 2162 return; 2163} 2164 2165static void 2166ehci_device_bulk_close(struct usb_xfer *xfer) 2167{ 2168 ehci_device_done(xfer, USB_ERR_CANCELLED); 2169} 2170 2171static void 2172ehci_device_bulk_enter(struct usb_xfer *xfer) 2173{ 2174 return; 2175} 2176 2177static void 2178ehci_doorbell_async(struct ehci_softc *sc) 2179{ 2180 uint32_t temp; 2181 2182 /* 2183 * XXX Performance quirk: Some Host Controllers have a too low 2184 * interrupt rate. Issue an IAAD to stimulate the Host 2185 * Controller after queueing the BULK transfer. 2186 * 2187 * XXX Force the host controller to refresh any QH caches. 2188 */ 2189 temp = EOREAD4(sc, EHCI_USBCMD); 2190 if (!(temp & EHCI_CMD_IAAD)) 2191 EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD); 2192} 2193 2194static void 2195ehci_device_bulk_start(struct usb_xfer *xfer) 2196{ 2197 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2198 2199 /* setup TD's and QH */ 2200 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2201 2202 /* put transfer on interrupt queue */ 2203 ehci_transfer_intr_enqueue(xfer); 2204 2205 /* 2206 * XXX Certain nVidia chipsets choke when using the IAAD 2207 * feature too frequently. 2208 */ 2209 if (sc->sc_flags & EHCI_SCFLG_IAADBUG) 2210 return; 2211 2212 ehci_doorbell_async(sc); 2213} 2214 2215const struct usb_pipe_methods ehci_device_bulk_methods = 2216{ 2217 .open = ehci_device_bulk_open, 2218 .close = ehci_device_bulk_close, 2219 .enter = ehci_device_bulk_enter, 2220 .start = ehci_device_bulk_start, 2221}; 2222 2223/*------------------------------------------------------------------------* 2224 * ehci control support 2225 *------------------------------------------------------------------------*/ 2226static void 2227ehci_device_ctrl_open(struct usb_xfer *xfer) 2228{ 2229 return; 2230} 2231 2232static void 2233ehci_device_ctrl_close(struct usb_xfer *xfer) 2234{ 2235 ehci_device_done(xfer, USB_ERR_CANCELLED); 2236} 2237 2238static void 2239ehci_device_ctrl_enter(struct usb_xfer *xfer) 2240{ 2241 return; 2242} 2243 2244static void 2245ehci_device_ctrl_start(struct usb_xfer *xfer) 2246{ 2247 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2248 2249 /* setup TD's and QH */ 2250 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2251 2252 /* put transfer on interrupt queue */ 2253 ehci_transfer_intr_enqueue(xfer); 2254} 2255 2256const struct usb_pipe_methods ehci_device_ctrl_methods = 2257{ 2258 .open = ehci_device_ctrl_open, 2259 .close = ehci_device_ctrl_close, 2260 .enter = ehci_device_ctrl_enter, 2261 .start = ehci_device_ctrl_start, 2262}; 2263 2264/*------------------------------------------------------------------------* 2265 * ehci interrupt support 2266 *------------------------------------------------------------------------*/ 2267static void 2268ehci_device_intr_open(struct usb_xfer *xfer) 2269{ 2270 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2271 uint16_t best; 2272 uint16_t bit; 2273 uint16_t x; 2274 2275 usb_hs_bandwidth_alloc(xfer); 2276 2277 /* 2278 * Find the best QH position corresponding to the given interval: 2279 */ 2280 2281 best = 0; 2282 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 2283 while (bit) { 2284 if (xfer->interval >= bit) { 2285 x = bit; 2286 best = bit; 2287 while (x & bit) { 2288 if (sc->sc_intr_stat[x] < 2289 sc->sc_intr_stat[best]) { 2290 best = x; 2291 } 2292 x++; 2293 } 2294 break; 2295 } 2296 bit >>= 1; 2297 } 2298 2299 sc->sc_intr_stat[best]++; 2300 xfer->qh_pos = best; 2301 2302 DPRINTFN(3, "best=%d interval=%d\n", 2303 best, xfer->interval); 2304} 2305 2306static void 2307ehci_device_intr_close(struct usb_xfer *xfer) 2308{ 2309 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2310 2311 sc->sc_intr_stat[xfer->qh_pos]--; 2312 2313 ehci_device_done(xfer, USB_ERR_CANCELLED); 2314 2315 /* bandwidth must be freed after device done */ 2316 usb_hs_bandwidth_free(xfer); 2317} 2318 2319static void 2320ehci_device_intr_enter(struct usb_xfer *xfer) 2321{ 2322 return; 2323} 2324 2325static void 2326ehci_device_intr_start(struct usb_xfer *xfer) 2327{ 2328 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2329 2330 /* setup TD's and QH */ 2331 ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 2332 2333 /* put transfer on interrupt queue */ 2334 ehci_transfer_intr_enqueue(xfer); 2335} 2336 2337const struct usb_pipe_methods ehci_device_intr_methods = 2338{ 2339 .open = ehci_device_intr_open, 2340 .close = ehci_device_intr_close, 2341 .enter = ehci_device_intr_enter, 2342 .start = ehci_device_intr_start, 2343}; 2344 2345/*------------------------------------------------------------------------* 2346 * ehci full speed isochronous support 2347 *------------------------------------------------------------------------*/ 2348static void 2349ehci_device_isoc_fs_open(struct usb_xfer *xfer) 2350{ 2351 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2352 ehci_sitd_t *td; 2353 uint32_t sitd_portaddr; 2354 uint8_t ds; 2355 2356 sitd_portaddr = 2357 EHCI_SITD_SET_ADDR(xfer->address) | 2358 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) | 2359 EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 2360 EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no); 2361 2362 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 2363 sitd_portaddr |= EHCI_SITD_SET_DIR_IN; 2364 2365 sitd_portaddr = htohc32(sc, sitd_portaddr); 2366 2367 /* initialize all TD's */ 2368 2369 for (ds = 0; ds != 2; ds++) { 2370 for (td = (ehci_sitd_t *)xfer->td_start[ds]; td; td = td->obj_next) { 2371 td->sitd_portaddr = sitd_portaddr; 2372 2373 /* 2374 * TODO: make some kind of automatic 2375 * SMASK/CMASK selection based on micro-frame 2376 * usage 2377 * 2378 * micro-frame usage (8 microframes per 1ms) 2379 */ 2380 td->sitd_back = htohc32(sc, EHCI_LINK_TERMINATE); 2381 2382 usb_pc_cpu_flush(td->page_cache); 2383 } 2384 } 2385} 2386 2387static void 2388ehci_device_isoc_fs_close(struct usb_xfer *xfer) 2389{ 2390 ehci_device_done(xfer, USB_ERR_CANCELLED); 2391} 2392 2393static void 2394ehci_device_isoc_fs_enter(struct usb_xfer *xfer) 2395{ 2396 struct usb_page_search buf_res; 2397 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2398 ehci_sitd_t *td; 2399 ehci_sitd_t *td_last = NULL; 2400 ehci_sitd_t **pp_last; 2401 uint32_t *plen; 2402 uint32_t buf_offset; 2403 uint32_t nframes; 2404 uint32_t temp; 2405 uint32_t sitd_mask; 2406 uint16_t tlen; 2407 uint8_t sa; 2408 uint8_t sb; 2409 2410#ifdef LOSCFG_USB_DEBUG 2411 uint8_t once = 1; 2412#endif 2413 2414 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2415 xfer, xfer->endpoint->isoc_next, xfer->nframes); 2416 2417 /* get the current frame index */ 2418 2419 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2420 2421 /* 2422 * check if the frame index is within the window where the frames 2423 * will be inserted 2424 */ 2425 buf_offset = (nframes - xfer->endpoint->isoc_next) & 2426 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2427 2428 if ((xfer->endpoint->is_synced == 0) || 2429 (buf_offset < xfer->nframes)) { 2430 /* 2431 * If there is data underflow or the pipe queue is empty we 2432 * schedule the transfer a few frames ahead of the current 2433 * frame position. Else two isochronous transfers might 2434 * overlap. 2435 */ 2436 xfer->endpoint->isoc_next = (nframes + 3) & 2437 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2438 xfer->endpoint->is_synced = 1; 2439 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2440 } 2441 /* 2442 * compute how many milliseconds the insertion is ahead of the 2443 * current frame position: 2444 */ 2445 buf_offset = (xfer->endpoint->isoc_next - nframes) & 2446 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2447 2448 /* 2449 * pre-compute when the isochronous transfer will be finished: 2450 */ 2451 xfer->isoc_time_complete = 2452 usb_isoc_time_expand(&sc->sc_bus, nframes) + 2453 buf_offset + xfer->nframes; 2454 2455 /* get the real number of frames */ 2456 2457 nframes = xfer->nframes; 2458 2459 buf_offset = 0; 2460 2461 plen = xfer->frlengths; 2462 2463 /* toggle the DMA set we are using */ 2464 xfer->flags_int.curr_dma_set ^= 1; 2465 2466 /* get next DMA set */ 2467 td = (ehci_sitd_t *)xfer->td_start[xfer->flags_int.curr_dma_set]; 2468 xfer->td_transfer_first = td; 2469 2470 pp_last = &sc->sc_isoc_fs_p_last[xfer->endpoint->isoc_next]; 2471 2472 /* store starting position */ 2473 2474 xfer->qh_pos = xfer->endpoint->isoc_next; 2475 2476 while (nframes--) { 2477 if (td == NULL) { 2478 panic("%s:%d: out of TD's\n", 2479 __FUNCTION__, __LINE__); 2480 } 2481 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) 2482 pp_last = &sc->sc_isoc_fs_p_last[0]; 2483 2484 /* reuse sitd_portaddr and sitd_back from last transfer */ 2485 2486 if (*plen > xfer->max_frame_size) { 2487#ifdef LOSCFG_USB_DEBUG 2488 if (once) { 2489 once = 0; 2490 PRINTK("%s: frame length(%d) exceeds %d " 2491 "bytes (frame truncated)\n", 2492 __FUNCTION__, *plen, 2493 xfer->max_frame_size); 2494 } 2495#endif 2496 *plen = xfer->max_frame_size; 2497 } 2498 2499 /* allocate a slot */ 2500 2501 sa = usbd_fs_isoc_schedule_alloc_slot(xfer, 2502 xfer->isoc_time_complete - nframes - 1); 2503 2504 if (sa == 255) { 2505 /* 2506 * Schedule is FULL, set length to zero: 2507 */ 2508 2509 *plen = 0; 2510 sa = USB_FS_ISOC_UFRAME_MAX - 1; 2511 } 2512 if (*plen) { 2513 /* 2514 * only call "usbd_get_page()" when we have a 2515 * non-zero length 2516 */ 2517 usbd_get_page(xfer->frbuffers, buf_offset, &buf_res); 2518#if USB_HAVE_BUSDMA 2519 td->sitd_bp[0] = htohc32(sc, buf_res.physaddr); 2520#else 2521 td->sitd_bp[0] = htohc32(sc, (unsigned int)buf_res.buffer); 2522#endif 2523 buf_offset += *plen; 2524 /* 2525 * NOTE: We need to subtract one from the offset so 2526 * that we are on a valid page! 2527 */ 2528 usbd_get_page(xfer->frbuffers, buf_offset - 1, 2529 &buf_res); 2530#if USB_HAVE_BUSDMA 2531 temp = buf_res.physaddr & ~0xFFF; 2532#else 2533 temp = (unsigned int)buf_res.buffer & ~0xFFF; 2534#endif 2535 } else { 2536 td->sitd_bp[0] = 0; 2537 temp = 0; 2538 } 2539 2540 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) { 2541 tlen = *plen; 2542 if (tlen <= 188) { 2543 temp |= 1; /* T-count = 1, TP = ALL */ 2544 tlen = 1; 2545 } else { 2546 tlen += 187; 2547 tlen /= 188; 2548 temp |= (uint32_t)tlen; /* T-count = [1..6] */ 2549 temp |= 8; /* TP = Begin */ 2550 } 2551 2552 tlen += sa; 2553 2554 if (tlen >= 8) { 2555 sb = 0; 2556 } else { 2557 sb = (1 << tlen); 2558 } 2559 2560 sa = (1 << sa); 2561 sa = (sb - sa) & 0x3F; 2562 sb = 0; 2563 } else { 2564 sb = (-(4 << sa)) & 0xFE; 2565 sa = (1 << sa) & 0x3F; 2566 } 2567 2568 sitd_mask = (EHCI_SITD_SET_SMASK(sa) | 2569 EHCI_SITD_SET_CMASK(sb)); 2570 2571 td->sitd_bp[1] = htohc32(sc, temp); 2572 2573 td->sitd_mask = htohc32(sc, sitd_mask); 2574 2575 if (nframes == 0) { 2576 td->sitd_status = htohc32(sc, 2577 EHCI_SITD_IOC | 2578 EHCI_SITD_ACTIVE | 2579 EHCI_SITD_SET_LEN(*plen)); 2580 } else { 2581 td->sitd_status = htohc32(sc, 2582 EHCI_SITD_ACTIVE | 2583 EHCI_SITD_SET_LEN(*plen)); 2584 } 2585 usb_pc_cpu_flush(td->page_cache); 2586 2587#ifdef LOSCFG_USB_DEBUG 2588 if (ehcidebug > 15) { 2589 DPRINTF("FS-TD %d\n", nframes); 2590 ehci_dump_sitd(sc, td); 2591 } 2592#endif 2593 /* insert TD into schedule */ 2594 EHCI_APPEND_FS_TD(td, *pp_last); 2595 pp_last++; 2596 2597 plen++; 2598 td_last = td; 2599 td = td->obj_next; 2600 } 2601 2602 xfer->td_transfer_last = td_last; 2603 2604 /* update isoc_next */ 2605 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) & 2606 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2607 2608 /* 2609 * We don't allow cancelling of the SPLIT transaction USB FULL 2610 * speed transfer, because it disturbs the bandwidth 2611 * computation algorithm. 2612 */ 2613 xfer->flags_int.can_cancel_immed = 0; 2614} 2615 2616static void 2617ehci_device_isoc_fs_start(struct usb_xfer *xfer) 2618{ 2619 /* 2620 * We don't allow cancelling of the SPLIT transaction USB FULL 2621 * speed transfer, because it disturbs the bandwidth 2622 * computation algorithm. 2623 */ 2624 xfer->flags_int.can_cancel_immed = 0; 2625 2626 /* set a default timeout */ 2627 if (xfer->timeout == 0) 2628 xfer->timeout = 500; /* ms */ 2629 2630 /* put transfer on interrupt queue */ 2631 ehci_transfer_intr_enqueue(xfer); 2632} 2633 2634const struct usb_pipe_methods ehci_device_isoc_fs_methods = { 2635 .open = ehci_device_isoc_fs_open, 2636 .close = ehci_device_isoc_fs_close, 2637 .enter = ehci_device_isoc_fs_enter, 2638 .start = ehci_device_isoc_fs_start, 2639}; 2640 2641/*------------------------------------------------------------------------* 2642 * ehci high speed isochronous support 2643 *------------------------------------------------------------------------*/ 2644static void 2645ehci_device_isoc_hs_open(struct usb_xfer *xfer) 2646{ 2647 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2648 ehci_itd_t *td; 2649 uint32_t temp; 2650 uint8_t ds; 2651 2652 usb_hs_bandwidth_alloc(xfer); 2653 2654 /* initialize all TD's */ 2655 2656 for (ds = 0; ds != 2; ds++) { 2657 for (td = (ehci_itd_t *)xfer->td_start[ds]; td; td = td->obj_next) { 2658 /* set TD inactive */ 2659 td->itd_status[0] = 0; 2660 td->itd_status[1] = 0; 2661 td->itd_status[2] = 0; 2662 td->itd_status[3] = 0; 2663 td->itd_status[4] = 0; 2664 td->itd_status[5] = 0; 2665 td->itd_status[6] = 0; 2666 td->itd_status[7] = 0; 2667 2668 /* set endpoint and address */ 2669 td->itd_bp[0] = htohc32(sc, 2670 EHCI_ITD_SET_ADDR(xfer->address) | 2671 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno))); 2672 2673 temp = 2674 EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF); 2675 2676 /* set direction */ 2677 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 2678 temp |= EHCI_ITD_SET_DIR_IN; 2679 } 2680 /* set maximum packet size */ 2681 td->itd_bp[1] = htohc32(sc, temp); 2682 2683 /* set transfer multiplier */ 2684 td->itd_bp[2] = htohc32(sc, xfer->max_packet_count & 3); 2685 2686 usb_pc_cpu_flush(td->page_cache); 2687 } 2688 } 2689} 2690 2691static void 2692ehci_device_isoc_hs_close(struct usb_xfer *xfer) 2693{ 2694 ehci_device_done(xfer, USB_ERR_CANCELLED); 2695 2696 /* bandwidth must be freed after device done */ 2697 usb_hs_bandwidth_free(xfer); 2698} 2699 2700static void 2701ehci_device_isoc_hs_enter(struct usb_xfer *xfer) 2702{ 2703 struct usb_page_search buf_res; 2704 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2705 ehci_itd_t *td; 2706 ehci_itd_t *td_last = NULL; 2707 ehci_itd_t **pp_last; 2708 bus_size_t page_addr; 2709 uint32_t *plen; 2710 uint32_t status; 2711 uint32_t buf_offset; 2712 uint32_t nframes; 2713 uint32_t itd_offset[8 + 1]; 2714 uint8_t x; 2715 uint8_t td_no; 2716 uint8_t page_no; 2717 2718#ifdef LOSCFG_USB_DEBUG 2719 uint8_t once = 1; 2720#endif 2721 2722 DPRINTFN(6, "xfer=%p next=%d nframes=%d shift=%d\n", 2723 xfer, xfer->endpoint->isoc_next, xfer->nframes, 2724 usbd_xfer_get_fps_shift(xfer)); 2725 2726 /* get the current frame index */ 2727 2728 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2729 2730 /* 2731 * check if the frame index is within the window where the frames 2732 * will be inserted 2733 */ 2734 buf_offset = (nframes - xfer->endpoint->isoc_next) & 2735 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2736 2737 if ((xfer->endpoint->is_synced == 0) || 2738 (buf_offset < (((xfer->nframes << shift) + 7) / 8))) { 2739 /* 2740 * If there is data underflow or the pipe queue is empty we 2741 * schedule the transfer a few frames ahead of the current 2742 * frame position. Else two isochronous transfers might 2743 * overlap. 2744 */ 2745 xfer->endpoint->isoc_next = (nframes + 3) & 2746 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2747 xfer->endpoint->is_synced = 1; 2748 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2749 } 2750 /* 2751 * compute how many milliseconds the insertion is ahead of the 2752 * current frame position: 2753 */ 2754 buf_offset = (xfer->endpoint->isoc_next - nframes) & 2755 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2756 2757 /* 2758 * pre-compute when the isochronous transfer will be finished: 2759 */ 2760 xfer->isoc_time_complete = 2761 usb_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 2762 (((xfer->nframes << shift) + 7) / 8); 2763 2764 /* get the real number of frames */ 2765 2766 nframes = xfer->nframes; 2767 2768 buf_offset = 0; 2769 td_no = 0; 2770 2771 plen = xfer->frlengths; 2772 2773 /* toggle the DMA set we are using */ 2774 xfer->flags_int.curr_dma_set ^= 1; 2775 2776 /* get next DMA set */ 2777 td = (ehci_itd_t *)xfer->td_start[xfer->flags_int.curr_dma_set]; 2778 xfer->td_transfer_first = td; 2779 2780 pp_last = &sc->sc_isoc_hs_p_last[xfer->endpoint->isoc_next]; 2781 2782 /* store starting position */ 2783 2784 xfer->qh_pos = xfer->endpoint->isoc_next; 2785 2786 while (nframes) { 2787 if (td == NULL) { 2788 panic("%s:%d: out of TD's\n", 2789 __FUNCTION__, __LINE__); 2790 } 2791 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2792 pp_last = &sc->sc_isoc_hs_p_last[0]; 2793 } 2794 /* range check */ 2795 if (*plen > xfer->max_frame_size) { 2796#ifdef LOSCFG_USB_DEBUG 2797 if (once) { 2798 once = 0; 2799 PRINTK("%s: frame length(%d) exceeds %d bytes " 2800 "(frame truncated)\n", 2801 __FUNCTION__, *plen, xfer->max_frame_size); 2802 } 2803#endif 2804 *plen = xfer->max_frame_size; 2805 } 2806 2807 if (xfer->endpoint->usb_smask & (1 << td_no)) { 2808 status = (EHCI_ITD_SET_LEN(*plen) | 2809 EHCI_ITD_ACTIVE | 2810 EHCI_ITD_SET_PG(0)); 2811 td->itd_status[td_no] = htohc32(sc, status); 2812 itd_offset[td_no] = buf_offset; 2813 buf_offset += *plen; 2814 plen++; 2815 nframes --; 2816 } else { 2817 td->itd_status[td_no] = 0; /* not active */ 2818 itd_offset[td_no] = buf_offset; 2819 } 2820 2821 td_no++; 2822 2823 if ((td_no == 8) || (nframes == 0)) { 2824 /* the rest of the transfers are not active, if any */ 2825 for (x = td_no; x != 8; x++) { 2826 td->itd_status[x] = 0; /* not active */ 2827 } 2828 2829 /* check if there is any data to be transferred */ 2830 if (itd_offset[0] != buf_offset) { 2831 page_no = 0; 2832 itd_offset[td_no] = buf_offset; 2833 2834 /* get first page offset */ 2835 usbd_get_page(xfer->frbuffers, itd_offset[0], &buf_res); 2836 /* get page address */ 2837#if USB_HAVE_BUSDMA 2838 page_addr = buf_res.physaddr & ~0xFFF; 2839#else 2840 page_addr = (unsigned int)buf_res.buffer & ~0xFFF; 2841#endif 2842 /* update page address */ 2843 td->itd_bp[0] &= htohc32(sc, 0xFFF); 2844 td->itd_bp[0] |= htohc32(sc, page_addr); 2845 2846 for (x = 0; x != td_no; x++) { 2847 /* set page number and page offset */ 2848 status = (EHCI_ITD_SET_PG(page_no) | 2849#if USB_HAVE_BUSDMA 2850 (buf_res.physaddr & 0xFFF)); 2851#else 2852 ((unsigned int)buf_res.buffer & 0xFFF)); 2853#endif 2854 td->itd_status[x] |= htohc32(sc, status); 2855 2856 /* get next page offset */ 2857 if (itd_offset[x + 1] == buf_offset) { 2858 /* 2859 * We subtract one so that 2860 * we don't go off the last 2861 * page! 2862 */ 2863 usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 2864 } else { 2865 usbd_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res); 2866 } 2867#if USB_HAVE_BUSDMA 2868 /* check if we need a new page */ 2869 if ((buf_res.physaddr ^ page_addr) & ~0xFFF) { 2870 /* new page needed */ 2871 page_addr = buf_res.physaddr & ~0xFFF; 2872#else 2873 /* check if we need a new page */ 2874 if (((unsigned int)buf_res.buffer ^ page_addr) & ~0xFFF) { 2875 /* new page needed */ 2876 page_addr = (unsigned int)buf_res.buffer & ~0xFFF; 2877#endif 2878 if (page_no == 6) { 2879 panic("%s: too many pages\n", __FUNCTION__); 2880 } 2881 page_no++; 2882 page_no%= EHCI_ITD_BP_MAX; 2883 /* update page address */ 2884 td->itd_bp[page_no] &= htohc32(sc, 0xFFF); 2885 td->itd_bp[page_no] |= htohc32(sc, page_addr); 2886 } 2887 } 2888 } 2889 /* set IOC bit if we are complete */ 2890 if (nframes == 0) { 2891 td->itd_status[td_no - 1] |= htohc32(sc, EHCI_ITD_IOC); 2892 } 2893 usb_pc_cpu_flush(td->page_cache); 2894#ifdef LOSCFG_USB_DEBUG 2895 if (ehcidebug > 15) { 2896 DPRINTF("HS-TD %d\n", nframes); 2897 ehci_dump_itd(sc, td); 2898 } 2899#endif 2900 /* insert TD into schedule */ 2901 EHCI_APPEND_HS_TD(td, *pp_last); 2902 pp_last++; 2903 2904 td_no = 0; 2905 td_last = td; 2906 td = td->obj_next; 2907 } 2908 } 2909 2910 xfer->td_transfer_last = td_last; 2911 2912 /* update isoc_next */ 2913 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) & 2914 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2915} 2916 2917static void 2918ehci_device_isoc_hs_start(struct usb_xfer *xfer) 2919{ 2920 /* put transfer on interrupt queue */ 2921 ehci_transfer_intr_enqueue(xfer); 2922} 2923 2924const struct usb_pipe_methods ehci_device_isoc_hs_methods = { 2925 .open = ehci_device_isoc_hs_open, 2926 .close = ehci_device_isoc_hs_close, 2927 .enter = ehci_device_isoc_hs_enter, 2928 .start = ehci_device_isoc_hs_start, 2929}; 2930 2931/*------------------------------------------------------------------------* 2932 * ehci root control support 2933 *------------------------------------------------------------------------* 2934 * Simulate a hardware hub by handling all the necessary requests. 2935 *------------------------------------------------------------------------*/ 2936 2937static const 2938struct usb_device_descriptor ehci_devd = { 2939 sizeof(struct usb_device_descriptor), 2940 UDESC_DEVICE, /* type */ 2941 {0x00, 0x02}, /* USB version */ 2942 UDCLASS_HUB, /* class */ 2943 UDSUBCLASS_HUB, /* subclass */ 2944 UDPROTO_HSHUBSTT, /* protocol */ 2945 64, /* max packet */ 2946 {0}, {0}, {0x00, 0x01}, /* device id */ 2947 1, 2, 0, /* string indicies */ 2948 1 /* # of configurations */ 2949}; 2950 2951static const 2952struct usb_device_qualifier ehci_odevd = { 2953 sizeof(struct usb_device_qualifier), 2954 UDESC_DEVICE_QUALIFIER, /* type */ 2955 {0x00, 0x02}, /* USB version */ 2956 UDCLASS_HUB, /* class */ 2957 UDSUBCLASS_HUB, /* subclass */ 2958 UDPROTO_FSHUB, /* protocol */ 2959 0, /* max packet */ 2960 0, /* # of configurations */ 2961 0 2962}; 2963 2964static const struct ehci_config_desc ehci_confd = { 2965 .confd = { 2966 .bLength = sizeof(struct usb_config_descriptor), 2967 .bDescriptorType = UDESC_CONFIG, 2968 .wTotalLength[0] = sizeof(ehci_confd), 2969 .bNumInterface = 1, 2970 .bConfigurationValue = 1, 2971 .iConfiguration = 0, 2972 .bmAttributes = UC_SELF_POWERED, 2973 .bMaxPower = 0 /* max power */ 2974 }, 2975 .ifcd = { 2976 .bLength = sizeof(struct usb_interface_descriptor), 2977 .bDescriptorType = UDESC_INTERFACE, 2978 .bNumEndpoints = 1, 2979 .bInterfaceClass = UICLASS_HUB, 2980 .bInterfaceSubClass = UISUBCLASS_HUB, 2981 .bInterfaceProtocol = 0, 2982 }, 2983 .endpd = { 2984 .bLength = sizeof(struct usb_endpoint_descriptor), 2985 .bDescriptorType = UDESC_ENDPOINT, 2986 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT, 2987 .bmAttributes = UE_INTERRUPT, 2988 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 2989 .bInterval = 255, 2990 }, 2991}; 2992 2993static const 2994struct usb_hub_descriptor ehci_hubd = { 2995 .bDescLength = 0, /* dynamic length */ 2996 .bDescriptorType = UDESC_HUB, 2997}; 2998 2999uint16_t 3000ehci_get_port_speed_portsc(struct ehci_softc *sc, uint16_t index) 3001{ 3002 uint32_t v; 3003 3004 v = EOREAD4(sc, EHCI_PORTSC(index)); 3005 v = (v >> EHCI_PORTSC_PSPD_SHIFT) & EHCI_PORTSC_PSPD_MASK; 3006 3007 if (v == EHCI_PORT_SPEED_HIGH) 3008 return (UPS_HIGH_SPEED); 3009 if (v == EHCI_PORT_SPEED_LOW) 3010 return (UPS_LOW_SPEED); 3011 return (0); 3012} 3013 3014uint16_t 3015ehci_get_port_speed_hostc(struct ehci_softc *sc, uint16_t index) 3016{ 3017 uint32_t v; 3018 3019 v = EOREAD4(sc, EHCI_HOSTC(index)); 3020 v = (v >> EHCI_HOSTC_PSPD_SHIFT) & EHCI_HOSTC_PSPD_MASK; 3021 3022 if (v == EHCI_PORT_SPEED_HIGH) 3023 return (UPS_HIGH_SPEED); 3024 if (v == EHCI_PORT_SPEED_LOW) 3025 return (UPS_LOW_SPEED); 3026 return (0); 3027} 3028 3029static usb_error_t 3030ehci_roothub_exec(struct usb_device *udev, 3031 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3032{ 3033 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3034 const char *str_ptr; 3035 const void *ptr; 3036 uint32_t port; 3037 uint32_t v; 3038 uint16_t len; 3039 uint16_t i; 3040 uint16_t value; 3041 uint16_t index; 3042 usb_error_t err = USB_ERR_NORMAL_COMPLETION; 3043 3044 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3045 3046 /* buffer reset */ 3047 ptr = (const void *)&sc->sc_hub_desc; 3048 len = 0; 3049 3050 value = UGETW(req->wValue); 3051 index = UGETW(req->wIndex); 3052 3053 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3054 "wValue=0x%04x wIndex=0x%04x\n", 3055 req->bmRequestType, req->bRequest, 3056 UGETW(req->wLength), value, index); 3057 3058#define C(x,y) ((x) | ((y) << 8)) 3059 switch (C(req->bRequest, req->bmRequestType)) { 3060 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3061 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3062 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3063 /* 3064 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3065 * for the integrated root hub. 3066 */ 3067 break; 3068 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3069 len = 1; 3070 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3071 break; 3072 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3073 switch (value >> 8) { 3074 case UDESC_DEVICE: 3075 if ((value & 0xff) != 0) { 3076 err = USB_ERR_IOERROR; 3077 goto done; 3078 } 3079 len = sizeof(ehci_devd); 3080 ptr = (const void *)&ehci_devd; 3081 break; 3082 /* 3083 * We can't really operate at another speed, 3084 * but the specification says we need this 3085 * descriptor: 3086 */ 3087 case UDESC_DEVICE_QUALIFIER: 3088 if ((value & 0xff) != 0) { 3089 err = USB_ERR_IOERROR; 3090 goto done; 3091 } 3092 len = sizeof(ehci_odevd); 3093 ptr = (const void *)&ehci_odevd; 3094 break; 3095 3096 case UDESC_CONFIG: 3097 if ((value & 0xff) != 0) { 3098 err = USB_ERR_IOERROR; 3099 goto done; 3100 } 3101 len = sizeof(ehci_confd); 3102 ptr = (const void *)&ehci_confd; 3103 break; 3104 3105 case UDESC_STRING: 3106 switch (value & 0xff) { 3107 case 0: /* Language table */ 3108 str_ptr = "\001"; 3109 break; 3110 3111 case 1: /* Vendor */ 3112 str_ptr = sc->sc_vendor; 3113 break; 3114 3115 case 2: /* Product */ 3116 str_ptr = "EHCI root HUB"; 3117 break; 3118 3119 default: 3120 str_ptr = ""; 3121 break; 3122 } 3123 3124 len = usb_make_str_desc( 3125 sc->sc_hub_desc.temp, 3126 sizeof(sc->sc_hub_desc.temp), 3127 str_ptr); 3128 break; 3129 default: 3130 err = USB_ERR_IOERROR; 3131 goto done; 3132 } 3133 break; 3134 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3135 len = 1; 3136 sc->sc_hub_desc.temp[0] = 0; 3137 break; 3138 case C(UR_GET_STATUS, UT_READ_DEVICE): 3139 len = 2; 3140 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3141 break; 3142 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3143 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3144 len = 2; 3145 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3146 break; 3147 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3148 if (value >= EHCI_MAX_DEVICES) { 3149 err = USB_ERR_IOERROR; 3150 goto done; 3151 } 3152 sc->sc_addr = value; 3153 break; 3154 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3155 if ((value != 0) && (value != 1)) { 3156 err = USB_ERR_IOERROR; 3157 goto done; 3158 } 3159 sc->sc_conf = value; 3160 break; 3161 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3162 break; 3163 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3164 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3165 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3166 err = USB_ERR_IOERROR; 3167 goto done; 3168 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3169 break; 3170 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3171 break; 3172 /* Hub requests */ 3173 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3174 break; 3175 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3176 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3177 3178 if ((index < 1) || 3179 (index > sc->sc_noport)) { 3180 err = USB_ERR_IOERROR; 3181 goto done; 3182 } 3183 port = EHCI_PORTSC(index); 3184 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3185 switch (value) { 3186 case UHF_PORT_ENABLE: 3187 EOWRITE4(sc, port, v & ~EHCI_PS_PE); 3188 break; 3189 case UHF_PORT_SUSPEND: 3190 if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) { 3191 /* 3192 * waking up a High Speed device is rather 3193 * complicated if 3194 */ 3195 EOWRITE4(sc, port, v | EHCI_PS_FPR); 3196 } 3197 /* wait 20ms for resume sequence to complete */ 3198 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3199 3200 EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP | 3201 EHCI_PS_FPR | (3 << 10) /* High Speed */ )); 3202 3203 /* 4ms settle time */ 3204 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3205 break; 3206 case UHF_PORT_POWER: 3207 EOWRITE4(sc, port, v & ~EHCI_PS_PP); 3208 break; 3209 case UHF_PORT_TEST: 3210 DPRINTFN(3, "clear port test " 3211 "%d\n", index); 3212 break; 3213 case UHF_PORT_INDICATOR: 3214 DPRINTFN(3, "clear port ind " 3215 "%d\n", index); 3216 EOWRITE4(sc, port, v & ~EHCI_PS_PIC); 3217 break; 3218 case UHF_C_PORT_CONNECTION: 3219 EOWRITE4(sc, port, v | EHCI_PS_CSC); 3220 break; 3221 case UHF_C_PORT_ENABLE: 3222 EOWRITE4(sc, port, v | EHCI_PS_PEC); 3223 break; 3224 case UHF_C_PORT_SUSPEND: 3225 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3226 break; 3227 case UHF_C_PORT_OVER_CURRENT: 3228 EOWRITE4(sc, port, v | EHCI_PS_OCC); 3229 break; 3230 case UHF_C_PORT_RESET: 3231 sc->sc_isreset = 0; 3232 break; 3233 default: 3234 err = USB_ERR_IOERROR; 3235 goto done; 3236 } 3237 break; 3238 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3239 if ((value & 0xff) != 0) { 3240 err = USB_ERR_IOERROR; 3241 goto done; 3242 } 3243 v = EREAD4(sc, EHCI_HCSPARAMS); 3244 3245 sc->sc_hub_desc.hubd = ehci_hubd; 3246 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3247 3248 if (EHCI_HCS_PPC(v)) 3249 i = UHD_PWR_INDIVIDUAL; 3250 else 3251 i = UHD_PWR_NO_SWITCH; 3252 3253 if (EHCI_HCS_P_INDICATOR(v)) 3254 i |= UHD_PORT_IND; 3255 3256 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3257 /* XXX can't find out? */ 3258 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200; 3259 /* XXX don't know if ports are removable or not */ 3260 sc->sc_hub_desc.hubd.bDescLength = 3261 8 + ((sc->sc_noport + 7) / 8); 3262 len = sc->sc_hub_desc.hubd.bDescLength; 3263 break; 3264 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3265 len = 16; 3266 (void)memset_s(sc->sc_hub_desc.temp, sizeof(sc->sc_hub_desc.temp), 0, len); 3267 break; 3268 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3269 DPRINTFN(9, "get port status i=%d\n", 3270 index); 3271 if ((index < 1) || 3272 (index > sc->sc_noport)) { 3273 err = USB_ERR_IOERROR; 3274 goto done; 3275 } 3276 v = EOREAD4(sc, EHCI_PORTSC(index)); 3277 DPRINTFN(1, "port status=0x%04x\n", v); 3278 if (sc->sc_flags & EHCI_SCFLG_TT) { 3279 if (sc->sc_vendor_get_port_speed != NULL) { 3280 i = sc->sc_vendor_get_port_speed(sc, index); 3281 } else { 3282 device_printf(sc->sc_bus.bdev, 3283 "EHCI_SCFLG_TT quirk is set but " 3284 "sc_vendor_get_hub_speed() is NULL\n"); 3285 i = UPS_HIGH_SPEED; 3286 } 3287 } else { 3288 i = UPS_HIGH_SPEED; 3289 } 3290 if (v & EHCI_PS_CS) 3291 i |= UPS_CURRENT_CONNECT_STATUS; 3292 if (v & EHCI_PS_PE) 3293 i |= UPS_PORT_ENABLED; 3294 if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR)) 3295 i |= UPS_SUSPEND; 3296 if (v & EHCI_PS_OCA) 3297 i |= UPS_OVERCURRENT_INDICATOR; 3298 if (v & EHCI_PS_PR) 3299 i |= UPS_RESET; 3300 if (v & EHCI_PS_PP) 3301 i |= UPS_PORT_POWER; 3302 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3303 i = 0; 3304 if (v & EHCI_PS_CSC) 3305 i |= UPS_C_CONNECT_STATUS; 3306 if (v & EHCI_PS_PEC) 3307 i |= UPS_C_PORT_ENABLED; 3308 if (v & EHCI_PS_OCC) 3309 i |= UPS_C_OVERCURRENT_INDICATOR; 3310 if (v & EHCI_PS_FPR) 3311 i |= UPS_C_SUSPEND; 3312 if (sc->sc_isreset) 3313 i |= UPS_C_PORT_RESET; 3314 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3315 len = sizeof(sc->sc_hub_desc.ps); 3316 break; 3317 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3318 err = USB_ERR_IOERROR; 3319 goto done; 3320 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3321 break; 3322 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3323 if ((index < 1) || 3324 (index > sc->sc_noport)) { 3325 err = USB_ERR_IOERROR; 3326 goto done; 3327 } 3328 port = EHCI_PORTSC(index); 3329 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3330 switch (value) { 3331 case UHF_PORT_ENABLE: 3332 EOWRITE4(sc, port, v | EHCI_PS_PE); 3333 break; 3334 case UHF_PORT_SUSPEND: 3335 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3336 break; 3337 case UHF_PORT_RESET: 3338 DPRINTFN(6, "reset port %d\n", index); 3339 if (EHCI_PS_IS_LOWSPEED(v) && 3340 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3341 /* Low speed device, give up ownership. */ 3342 DPRINTFN(6, "Low speed device is not support!!!!\n"); 3343 err = USB_ERR_INVAL; 3344 goto done; 3345 } 3346 /* Start reset sequence. */ 3347 v &= ~(EHCI_PS_PE | EHCI_PS_PR); 3348 EOWRITE4(sc, port, v | EHCI_PS_PR); 3349 3350 /* Wait for reset to complete. */ 3351 usb_pause_mtx(&sc->sc_bus.bus_mtx, 3352 USB_MS_TO_TICKS(usb_port_root_reset_delay)); 3353 3354 /* Terminate reset sequence. */ 3355 if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM)) 3356 EOWRITE4(sc, port, v); 3357 3358 /* Wait for HC to complete reset. */ 3359 usb_pause_mtx(&sc->sc_bus.bus_mtx, 3360 USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE)); 3361 3362 v = EOREAD4(sc, port); 3363 DPRINTF("ehci after reset, status=0x%08x\n", v); 3364 if (v & EHCI_PS_PR) { 3365 device_printf(sc->sc_bus.bdev, 3366 "port reset timeout\n"); 3367 err = USB_ERR_TIMEOUT; 3368 goto done; 3369 } 3370 if (!(v & EHCI_PS_PE) && 3371 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3372 /* Not a high speed device, give up ownership.*/ 3373 DPRINTFN(6, "Full speed device is not support!!!!\n"); 3374 err = USB_ERR_INVAL; 3375 goto done; 3376 } 3377 sc->sc_isreset = 1; 3378 DPRINTF("ehci port %d reset, status = 0x%08x\n", 3379 index, v); 3380 break; 3381 3382 case UHF_PORT_POWER: 3383 DPRINTFN(3, "set port power %d\n", index); 3384 EOWRITE4(sc, port, v | EHCI_PS_PP); 3385 break; 3386 3387 case UHF_PORT_TEST: 3388 DPRINTFN(3, "set port test %d\n", index); 3389 break; 3390 3391 case UHF_PORT_INDICATOR: 3392 DPRINTFN(3, "set port ind %d\n", index); 3393 EOWRITE4(sc, port, v | EHCI_PS_PIC); 3394 break; 3395 3396 default: 3397 err = USB_ERR_IOERROR; 3398 goto done; 3399 } 3400 break; 3401 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3402 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3403 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3404 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3405 break; 3406 default: 3407 err = USB_ERR_IOERROR; 3408 goto done; 3409 } 3410done: 3411 *plength = len; 3412 *pptr = ptr; 3413 return (err); 3414} 3415 3416static void 3417ehci_xfer_setup(struct usb_setup_params *parm) 3418{ 3419 struct usb_page_search page_info; 3420 struct usb_page_cache *pc; 3421 ehci_softc_t *sc; 3422 struct usb_xfer *xfer; 3423 void *last_obj; 3424 uint32_t nqtd; 3425 uint32_t nqh; 3426 uint32_t nsitd; 3427 uint32_t nitd; 3428 uint32_t n; 3429 3430 sc = EHCI_BUS2SC(parm->udev->bus); 3431 xfer = parm->curr_xfer; 3432 3433 nqtd = 0; 3434 nqh = 0; 3435 nsitd = 0; 3436 nitd = 0; 3437 3438 /* 3439 * compute maximum number of some structures 3440 */ 3441 if (parm->methods == &ehci_device_ctrl_methods) { 3442 /* 3443 * The proof for the "nqtd" formula is illustrated like 3444 * this: 3445 * 3446 * +------------------------------------+ 3447 * | | 3448 * | |remainder -> | 3449 * | +-----+---+ | 3450 * | | xxx | x | frm 0 | 3451 * | +-----+---++ | 3452 * | | xxx | xx | frm 1 | 3453 * | +-----+----+ | 3454 * | ... | 3455 * +------------------------------------+ 3456 * 3457 * "xxx" means a completely full USB transfer descriptor 3458 * 3459 * "x" and "xx" means a short USB packet 3460 * 3461 * For the remainder of an USB transfer modulo 3462 * "max_data_length" we need two USB transfer descriptors. 3463 * One to transfer the remaining data and one to finalise 3464 * with a zero length packet in case the "force_short_xfer" 3465 * flag is set. We only need two USB transfer descriptors in 3466 * the case where the transfer length of the first one is a 3467 * factor of "max_frame_size". The rest of the needed USB 3468 * transfer descriptors is given by the buffer size divided 3469 * by the maximum data payload. 3470 */ 3471 parm->hc_max_packet_size = 0x400; 3472 parm->hc_max_packet_count = 1; 3473 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3474#if USB_HAVE_BUSDMA 3475 xfer->flags_int.bdma_enable = 1; 3476#endif 3477 usbd_transfer_setup_sub(parm); 3478 3479 nqh = 1; 3480 nqtd = ((2 * xfer->nframes) + 1 /* STATUS */ 3481 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3482 3483 } else if (parm->methods == &ehci_device_bulk_methods) { 3484 parm->hc_max_packet_size = 0x400; 3485 parm->hc_max_packet_count = 1; 3486 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3487#if USB_HAVE_BUSDMA 3488 xfer->flags_int.bdma_enable = 1; 3489#endif 3490 3491 usbd_transfer_setup_sub(parm); 3492 3493 nqh = 1; 3494 nqtd = ((2 * xfer->nframes) 3495 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3496 3497 } else if (parm->methods == &ehci_device_intr_methods) { 3498 if (parm->speed == USB_SPEED_HIGH) { 3499 parm->hc_max_packet_size = 0x400; 3500 parm->hc_max_packet_count = 3; 3501 } else if (parm->speed == USB_SPEED_FULL) { 3502 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME; 3503 parm->hc_max_packet_count = 1; 3504 } else { 3505 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8; 3506 parm->hc_max_packet_count = 1; 3507 } 3508 3509 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3510#if USB_HAVE_BUSDMA 3511 xfer->flags_int.bdma_enable = 1; 3512#endif 3513 3514 usbd_transfer_setup_sub(parm); 3515 3516 nqh = 1; 3517 nqtd = ((2 * xfer->nframes) 3518 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3519 3520 } else if (parm->methods == &ehci_device_isoc_fs_methods) { 3521 parm->hc_max_packet_size = 0x3FF; 3522 parm->hc_max_packet_count = 1; 3523 parm->hc_max_frame_size = 0x3FF; 3524#if USB_HAVE_BUSDMA 3525 xfer->flags_int.bdma_enable = 1; 3526#endif 3527 3528 usbd_transfer_setup_sub(parm); 3529 3530 nsitd = xfer->nframes; 3531 3532 } else if (parm->methods == &ehci_device_isoc_hs_methods) { 3533 parm->hc_max_packet_size = 0x400; 3534 parm->hc_max_packet_count = 3; 3535 parm->hc_max_frame_size = 0xC00; 3536#if USB_HAVE_BUSDMA 3537 xfer->flags_int.bdma_enable = 1; 3538#endif 3539 3540 usbd_transfer_setup_sub(parm); 3541 3542 nitd = ((xfer->nframes + 7) / 8) << 3543 usbd_xfer_get_fps_shift(xfer); 3544 3545 } else { 3546 parm->hc_max_packet_size = 0x400; 3547 parm->hc_max_packet_count = 1; 3548 parm->hc_max_frame_size = 0x400; 3549 3550 usbd_transfer_setup_sub(parm); 3551 } 3552 3553alloc_dma_set: 3554 3555 if (parm->err) { 3556 return; 3557 } 3558 /* 3559 * Allocate queue heads and transfer descriptors 3560 */ 3561 last_obj = NULL; 3562 3563 if (usbd_transfer_setup_sub_malloc( 3564 parm, &pc, sizeof(ehci_itd_t), 3565 EHCI_ITD_ALIGN, nitd)) { 3566 parm->err = USB_ERR_NOMEM; 3567 return; 3568 } 3569 if (parm->buf) { 3570 for (n = 0; n != nitd; n++) { 3571 ehci_itd_t *td; 3572 3573 usbd_get_page(pc + n, 0, &page_info); 3574 3575 td = (ehci_itd_t *)page_info.buffer; 3576 3577 /* init TD */ 3578#if USB_HAVE_BUSDMA 3579 td->itd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_ITD); 3580#else 3581 td->itd_self = htohc32(sc, (unsigned int)page_info.buffer | EHCI_LINK_ITD); 3582#endif 3583 td->obj_next = (ehci_itd_t *)last_obj; 3584 td->page_cache = pc + n; 3585 3586 last_obj = td; 3587 3588 usb_pc_cpu_flush(pc + n); 3589 } 3590 } 3591 if (usbd_transfer_setup_sub_malloc( 3592 parm, &pc, sizeof(ehci_sitd_t), 3593 EHCI_SITD_ALIGN, nsitd)) { 3594 parm->err = USB_ERR_NOMEM; 3595 return; 3596 } 3597 if (parm->buf) { 3598 for (n = 0; n != nsitd; n++) { 3599 ehci_sitd_t *td; 3600 3601 usbd_get_page(pc + n, 0, &page_info); 3602 3603 td = (ehci_sitd_t *)page_info.buffer; 3604 3605 /* init TD */ 3606#if USB_HAVE_BUSDMA 3607 td->sitd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_SITD); 3608#else 3609 td->sitd_self = htohc32(sc, (unsigned int)page_info.buffer | EHCI_LINK_SITD); 3610#endif 3611 td->obj_next = (ehci_sitd_t *)last_obj; 3612 td->page_cache = pc + n; 3613 3614 last_obj = td; 3615 3616 usb_pc_cpu_flush(pc + n); 3617 } 3618 } 3619 if (usbd_transfer_setup_sub_malloc( 3620 parm, &pc, sizeof(ehci_qtd_t), 3621 EHCI_QTD_ALIGN, nqtd)) { 3622 parm->err = USB_ERR_NOMEM; 3623 return; 3624 } 3625 if (parm->buf) { 3626 for (n = 0; n != nqtd; n++) { 3627 ehci_qtd_t *qtd; 3628 3629 usbd_get_page(pc + n, 0, &page_info); 3630 3631 qtd = (ehci_qtd_t *)page_info.buffer; 3632 3633 /* init TD */ 3634#if USB_HAVE_BUSDMA 3635 qtd->qtd_self = htohc32(sc, page_info.physaddr); 3636#else 3637 qtd->qtd_self = htohc32(sc, (unsigned int)page_info.buffer); 3638#endif 3639 qtd->obj_next = (ehci_qtd_t *)last_obj; 3640 qtd->page_cache = pc + n; 3641 3642 last_obj = qtd; 3643 3644 usb_pc_cpu_flush(pc + n); 3645 } 3646 } 3647 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3648 3649 last_obj = NULL; 3650 3651 if (usbd_transfer_setup_sub_malloc( 3652 parm, &pc, sizeof(ehci_qh_t), 3653 EHCI_QH_ALIGN, nqh)) { 3654 parm->err = USB_ERR_NOMEM; 3655 return; 3656 } 3657 if (parm->buf) { 3658 for (n = 0; n != nqh; n++) { 3659 ehci_qh_t *qh; 3660 3661 usbd_get_page(pc + n, 0, &page_info); 3662 3663 qh = (ehci_qh_t *)page_info.buffer; 3664 3665 /* init QH */ 3666#if USB_HAVE_BUSDMA 3667 qh->qh_self = htohc32(sc, page_info.physaddr | EHCI_LINK_QH); 3668#else 3669 qh->qh_self = htohc32(sc, (unsigned int)page_info.buffer | EHCI_LINK_QH); 3670#endif 3671 qh->obj_next = (ehci_qh_t *)last_obj; 3672 qh->page_cache = pc + n; 3673 3674 last_obj = qh; 3675 3676 usb_pc_cpu_flush(pc + n); 3677 } 3678 } 3679 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3680 3681 if (!xfer->flags_int.curr_dma_set) { 3682 xfer->flags_int.curr_dma_set = 1; 3683 goto alloc_dma_set; 3684 } 3685} 3686 3687static void 3688ehci_xfer_unsetup(struct usb_xfer *xfer) 3689{ 3690 return; 3691} 3692 3693static void 3694ehci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3695 struct usb_endpoint *ep) 3696{ 3697 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3698 3699 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3700 ep, udev->address, 3701 edesc->bEndpointAddress, udev->flags.usb_mode, 3702 sc->sc_addr); 3703 3704 if (udev->device_index != sc->sc_addr) { 3705 if ((udev->speed != USB_SPEED_HIGH) && 3706 ((udev->hs_hub_addr == 0) || 3707 (udev->hs_port_no == 0) || 3708 (udev->parent_hs_hub == NULL) || 3709 (udev->parent_hs_hub->hub == NULL))) { 3710 /* We need a transaction translator */ 3711 DPRINTFN(2, "no hub or no port\n"); 3712 goto done; 3713 } 3714 switch (edesc->bmAttributes & UE_XFERTYPE) { 3715 case UE_CONTROL: 3716 ep->methods = &ehci_device_ctrl_methods; 3717 DPRINTFN(2, "UE_CONTROL\n"); 3718 break; 3719 case UE_INTERRUPT: 3720 ep->methods = &ehci_device_intr_methods; 3721 DPRINTFN(2, "UE_INTERRUPT\n"); 3722 break; 3723 case UE_ISOCHRONOUS: 3724 if (udev->speed == USB_SPEED_HIGH) { 3725 ep->methods = &ehci_device_isoc_hs_methods; 3726 } else if (udev->speed == USB_SPEED_FULL) { 3727 ep->methods = &ehci_device_isoc_fs_methods; 3728 } 3729 DPRINTFN(2, "UE_ISOCHRONOUS\n"); 3730 break; 3731 case UE_BULK: 3732 ep->methods = &ehci_device_bulk_methods; 3733 DPRINTFN(2, "UE_BULK\n"); 3734 break; 3735 default: 3736 /* do nothing */ 3737 break; 3738 } 3739 } 3740done: 3741 return; 3742} 3743 3744static void 3745ehci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3746{ 3747 /* 3748 * Wait until the hardware has finished any possible use of 3749 * the transfer descriptor(s) and QH 3750 */ 3751 *pus = (1125); /* microseconds */ 3752} 3753 3754static void 3755ehci_device_resume(struct usb_device *udev) 3756{ 3757 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3758 struct usb_xfer *xfer; 3759 const struct usb_pipe_methods *methods; 3760 3761 DPRINTF("\n"); 3762 3763 USB_BUS_LOCK(udev->bus); 3764 3765 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3766 if (xfer->xroot->udev == udev) { 3767 methods = xfer->endpoint->methods; 3768 3769 if ((methods == &ehci_device_bulk_methods) || 3770 (methods == &ehci_device_ctrl_methods)) { 3771 EHCI_APPEND_QH((ehci_qh_t *)xfer->qh_start[xfer->flags_int.curr_dma_set], 3772 sc->sc_async_p_last); 3773 } 3774 if (methods == &ehci_device_intr_methods) { 3775 EHCI_APPEND_QH((ehci_qh_t *)xfer->qh_start[xfer->flags_int.curr_dma_set], 3776 sc->sc_intr_p_last[xfer->qh_pos]); 3777 } 3778 } 3779 } 3780 3781 USB_BUS_UNLOCK(udev->bus); 3782 3783 return; 3784} 3785 3786static void 3787ehci_device_suspend(struct usb_device *udev) 3788{ 3789 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3790 struct usb_xfer *xfer; 3791 const struct usb_pipe_methods *methods; 3792 3793 DPRINTF("\n"); 3794 3795 USB_BUS_LOCK(udev->bus); 3796 3797 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3798 3799 if (xfer->xroot->udev == udev) { 3800 3801 methods = xfer->endpoint->methods; 3802 3803 if ((methods == &ehci_device_bulk_methods) || 3804 (methods == &ehci_device_ctrl_methods)) { 3805 EHCI_REMOVE_QH((ehci_qh_t *)xfer->qh_start[xfer->flags_int.curr_dma_set], 3806 sc->sc_async_p_last); 3807 } 3808 if (methods == &ehci_device_intr_methods) { 3809 EHCI_REMOVE_QH((ehci_qh_t *)xfer->qh_start[xfer->flags_int.curr_dma_set], 3810 sc->sc_intr_p_last[xfer->qh_pos]); 3811 } 3812 } 3813 } 3814 3815 USB_BUS_UNLOCK(udev->bus); 3816} 3817 3818static void 3819ehci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 3820{ 3821 struct ehci_softc *sc = EHCI_BUS2SC(bus); 3822 3823 switch (state) { 3824 case USB_HW_POWER_SUSPEND: 3825 case USB_HW_POWER_SHUTDOWN: 3826 ehci_suspend(sc); 3827 break; 3828 case USB_HW_POWER_RESUME: 3829 ehci_resume(sc); 3830 break; 3831 default: 3832 break; 3833 } 3834} 3835 3836static void 3837ehci_set_hw_power(struct usb_bus *bus) 3838{ 3839 ehci_softc_t *sc = EHCI_BUS2SC(bus); 3840 uint32_t temp; 3841 uint32_t flags; 3842 3843 DPRINTF("\n"); 3844 3845 USB_BUS_LOCK(bus); 3846 3847 flags = bus->hw_power_state; 3848 3849 temp = EOREAD4(sc, EHCI_USBCMD); 3850 3851 temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 3852 3853 if (flags & (USB_HW_POWER_CONTROL | 3854 USB_HW_POWER_BULK)) { 3855 DPRINTF("Async is active\n"); 3856 temp |= EHCI_CMD_ASE; 3857 } 3858 if (flags & (USB_HW_POWER_INTERRUPT | 3859 USB_HW_POWER_ISOC)) { 3860 DPRINTF("Periodic is active\n"); 3861 temp |= EHCI_CMD_PSE; 3862 } 3863 EOWRITE4(sc, EHCI_USBCMD, temp); 3864 3865 USB_BUS_UNLOCK(bus); 3866 3867 return; 3868} 3869 3870static void 3871ehci_start_dma_delay_second(struct usb_xfer *xfer) 3872{ 3873 struct ehci_softc *sc = EHCI_BUS2SC(xfer->xroot->bus); 3874 3875 DPRINTF("\n"); 3876 3877 /* trigger doorbell */ 3878 ehci_doorbell_async(sc); 3879 3880 /* give the doorbell 4ms */ 3881 usbd_transfer_timeout_ms(xfer, 3882 (void (*)(void *))&usb_dma_delay_done_cb, 4); 3883} 3884 3885/* 3886 * Ring the doorbell twice before freeing any DMA descriptors. Some host 3887 * controllers apparently cache the QH descriptors and need a message 3888 * that the cache needs to be discarded. 3889 */ 3890static void 3891ehci_start_dma_delay(struct usb_xfer *xfer) 3892{ 3893 struct ehci_softc *sc = EHCI_BUS2SC(xfer->xroot->bus); 3894 3895 DPRINTF("\n"); 3896 3897 /* trigger doorbell */ 3898 ehci_doorbell_async(sc); 3899 3900 /* give the doorbell 4ms */ 3901 usbd_transfer_timeout_ms(xfer, 3902 (void (*)(void *))&ehci_start_dma_delay_second, 4); 3903} 3904 3905const struct usb_bus_methods ehci_bus_methods = { 3906 .endpoint_init = ehci_ep_init, 3907 .xfer_setup = ehci_xfer_setup, 3908 .xfer_unsetup = ehci_xfer_unsetup, 3909 .get_dma_delay = ehci_get_dma_delay, 3910 .device_resume = ehci_device_resume, 3911 .device_suspend = ehci_device_suspend, 3912 .set_hw_power = ehci_set_hw_power, 3913 .set_hw_power_sleep = ehci_set_hw_power_sleep, 3914 .roothub_exec = ehci_roothub_exec, 3915 .xfer_poll = ehci_do_poll, 3916 .start_dma_delay = ehci_start_dma_delay, 3917}; 3918#undef USB_DEBUG_VAR 3919