1/*
2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without modification,
6 * are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this list of
9 *    conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice, this list
12 *    of conditions and the following disclaimer in the documentation and/or other materials
13 *    provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its contributors may be used
16 *    to endorse or promote products derived from this software without specific prior written
17 *    permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#ifndef _LOS_ARCH_MACRO_H
33#define _LOS_ARCH_MACRO_H
34
35#ifdef __cplusplus
36#if __cplusplus
37extern "C" {
38#endif /* __cplusplus */
39#endif /* __cplusplus */
40
41.macro POP_ALL_REG SP PC PState
42#if (defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))
43    l16ui  a3, \SP, CONTEXT_OFF_CPENABLE
44    wsr    a3, CPENABLE
45    rsync
46    l16ui  a3, \SP, CONTEXT_OFF_CPSTORED
47    bbci.l a3, 0, 2f
48
49    l32i   a3, \SP, CONTEXT_OFF_FCR
50    wur.FCR a3
51    l32i   a3, \SP, CONTEXT_OFF_FSR
52    wur.FSR a3
53
54    lsi f0, \SP, CONTEXT_OFF_F0
55    lsi f1, \SP, CONTEXT_OFF_F1
56    lsi f2, \SP, CONTEXT_OFF_F2
57    lsi f3, \SP, CONTEXT_OFF_F3
58    lsi f4, \SP, CONTEXT_OFF_F4
59    lsi f5, \SP, CONTEXT_OFF_F5
60    lsi f6, \SP, CONTEXT_OFF_F6
61    lsi f7, \SP, CONTEXT_OFF_F7
62    lsi f8, \SP, CONTEXT_OFF_F8
63    lsi f9, \SP, CONTEXT_OFF_F9
64    lsi f10, \SP, CONTEXT_OFF_F10
65    lsi f11, \SP, CONTEXT_OFF_F11
66    lsi f12, \SP, CONTEXT_OFF_F12
67    lsi f13, \SP, CONTEXT_OFF_F13
68    lsi f14, \SP, CONTEXT_OFF_F14
69    lsi f15, \SP, CONTEXT_OFF_F15
70
712:
72    movi   a4, 0
73    s16i   a4, \SP, CONTEXT_OFF_CPSTORED
74#endif
75    l32i    a3,  \SP, CONTEXT_OFF_LBEG
76    l32i    a4,  \SP, CONTEXT_OFF_LEND
77    wsr     a3,  LBEG
78    l32i    a3,  \SP, CONTEXT_OFF_LCOUNT
79    wsr     a4,  LEND
80    wsr     a3,  LCOUNT
81    l32i    a3,  \SP, CONTEXT_OFF_SAR
82    l32i    a1,  \SP, CONTEXT_OFF_A1
83    wsr     a3,  SAR
84    l32i    a3,  \SP, CONTEXT_OFF_A3
85    l32i    a4,  \SP, CONTEXT_OFF_A4
86    l32i    a5,  \SP, CONTEXT_OFF_A5
87    l32i    a6,  \SP, CONTEXT_OFF_A6
88    l32i    a7,  \SP, CONTEXT_OFF_A7
89    l32i    a8,  \SP, CONTEXT_OFF_A8
90    l32i    a9,  \SP, CONTEXT_OFF_A9
91    l32i    a10, \SP, CONTEXT_OFF_A10
92    l32i    a11, \SP, CONTEXT_OFF_A11
93    l32i    a12, \SP, CONTEXT_OFF_A12
94    l32i    a13, \SP, CONTEXT_OFF_A13
95    l32i    a14, \SP, CONTEXT_OFF_A14
96    l32i    a15, \SP, CONTEXT_OFF_A15
97    l32i    a0,  \SP, CONTEXT_OFF_PS
98    wsr     a0,  \PState
99    l32i    a0,  \SP, CONTEXT_OFF_PC
100    wsr     a0,  \PC
101    l32i    a0,  \SP, CONTEXT_OFF_A0
102    l32i    a2,  \SP, CONTEXT_OFF_A2
103.endm
104
105.macro PUSH_ALL_REG SP
106    s32i    a0,  \SP, CONTEXT_OFF_A0
107    s32i    a1,  \SP, CONTEXT_OFF_A1
108    s32i    a2,  \SP, CONTEXT_OFF_A2
109    s32i    a3,  \SP, CONTEXT_OFF_A3
110    s32i    a4,  \SP, CONTEXT_OFF_A4
111    s32i    a5,  \SP, CONTEXT_OFF_A5
112    s32i    a6,  \SP, CONTEXT_OFF_A6
113    s32i    a7,  \SP, CONTEXT_OFF_A7
114    s32i    a8,  \SP, CONTEXT_OFF_A8
115    s32i    a9,  \SP, CONTEXT_OFF_A9
116    s32i    a10, \SP, CONTEXT_OFF_A10
117    s32i    a11, \SP, CONTEXT_OFF_A11
118    s32i    a12, \SP, CONTEXT_OFF_A12
119    s32i    a13, \SP, CONTEXT_OFF_A13
120    s32i    a14, \SP, CONTEXT_OFF_A14
121    s32i    a15, \SP, CONTEXT_OFF_A15
122    rsr     a3,  SAR
123    s32i    a3,  \SP, CONTEXT_OFF_SAR
124    rsr     a3,  LBEG
125    s32i    a3,  \SP, CONTEXT_OFF_LBEG
126    rsr     a3,  LEND
127    s32i    a3,  \SP, CONTEXT_OFF_LEND
128    rsr     a3,  LCOUNT
129    s32i    a3,  \SP, CONTEXT_OFF_LCOUNT
130    rsr     a3,  PS
131    s32i    a3,  \SP, CONTEXT_OFF_PS
132#if (defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))
133    rsr     a3, CPENABLE
134    beqz    a3, 1f
135    s16i    a3, \SP, CONTEXT_OFF_CPSTORED
136    s16i    a3, \SP, CONTEXT_OFF_CPENABLE
137
138    bbci.l  a3, 0, 1f
139    rur.FCR a3
140    s32i    a3, \SP, CONTEXT_OFF_FCR
141    rur.FSR a3
142    s32i    a3, \SP, CONTEXT_OFF_FSR
143
144    ssi f0, \SP, CONTEXT_OFF_F0
145    ssi f1, \SP, CONTEXT_OFF_F1
146    ssi f2, \SP, CONTEXT_OFF_F2
147    ssi f3, \SP, CONTEXT_OFF_F3
148    ssi f4, \SP, CONTEXT_OFF_F4
149    ssi f5, \SP, CONTEXT_OFF_F5
150    ssi f6, \SP, CONTEXT_OFF_F6
151    ssi f7, \SP, CONTEXT_OFF_F7
152    ssi f8, \SP, CONTEXT_OFF_F8
153    ssi f9, \SP, CONTEXT_OFF_F9
154    ssi f10, \SP, CONTEXT_OFF_F10
155    ssi f11, \SP, CONTEXT_OFF_F11
156    ssi f12, \SP, CONTEXT_OFF_F12
157    ssi f13, \SP, CONTEXT_OFF_F13
158    ssi f14, \SP, CONTEXT_OFF_F14
159    ssi f15, \SP, CONTEXT_OFF_F15
1601:
161#endif
162.endm
163
164#ifdef __cplusplus
165#if __cplusplus
166}
167#endif /* __cplusplus */
168#endif /* __cplusplus */
169
170#endif /* _LOS_ARCH_MACRO_H */
171
172