1/*
2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2023 Huawei Device Co., Ltd. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without modification,
6 * are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this list of
9 *    conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice, this list
12 *    of conditions and the following disclaimer in the documentation and/or other materials
13 *    provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its contributors may be used
16 *    to endorse or promote products derived from this software without specific prior written
17 *    permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#ifndef _LOS_ARCH_INTERRUPT_H
33#define _LOS_ARCH_INTERRUPT_H
34
35#include "los_common_interrupt.h"
36
37#ifdef __cplusplus
38#if __cplusplus
39extern "C" {
40#endif /* __cplusplus */
41#endif /* __cplusplus */
42
43/* *
44 * @ingroup los_arch_interrupt
45 * Highest priority of a hardware interrupt.
46 */
47#ifndef OS_HWI_PRIO_HIGHEST
48#define OS_HWI_PRIO_HIGHEST                   0
49#endif
50
51/* *
52 * @ingroup los_arch_interrupt
53 * Lowest priority of a hardware interrupt.
54 */
55#ifndef OS_HWI_PRIO_LOWEST
56#define OS_HWI_PRIO_LOWEST                    7
57#endif
58
59/* *
60 * @ingroup los_arch_interrupt
61 * Count of arm9 system interrupt vector.
62 */
63#define OS_SYS_VECTOR_CNT                     0
64
65/* *
66 * @ingroup los_arch_interrupt
67 * Count of arm9 interrupt vector.
68 */
69#define OS_VECTOR_CNT                         (OS_SYS_VECTOR_CNT + OS_HWI_MAX_NUM)
70
71/* *
72 * @ingroup los_arch_interrupt
73 * Hardware interrupt error code: Invalid interrupt number.
74 *
75 * Value: 0x02000900
76 *
77 * Solution: Ensure that the interrupt number is valid.
78 * The value range of the interrupt number applicable for a arm9 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
79 */
80#define OS_ERRNO_HWI_NUM_INVALID              LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00)
81
82/* *
83 * @ingroup los_arch_interrupt
84 * Hardware interrupt error code: Null hardware interrupt handling function.
85 *
86 * Value: 0x02000901
87 *
88 * Solution: Pass in a valid non-null hardware interrupt handling function.
89 */
90#define OS_ERRNO_HWI_PROC_FUNC_NULL           LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x01)
91
92/* *
93 * @ingroup los_arch_interrupt
94 * Hardware interrupt error code: Insufficient interrupt resources for hardware interrupt creation.
95 *
96 * Value: 0x02000902
97 *
98 * Solution: Increase the configured maximum number of supported hardware interrupts.
99 */
100#define OS_ERRNO_HWI_CB_UNAVAILABLE           LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x02)
101
102/* *
103 * @ingroup los_arch_interrupt
104 * Hardware interrupt error code: Insufficient memory for hardware interrupt initialization.
105 *
106 * Value: 0x02000903
107 *
108 * Solution: Expand the configured memory.
109 */
110#define OS_ERRNO_HWI_NO_MEMORY                LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x03)
111
112/* *
113 * @ingroup los_arch_interrupt
114 * Hardware interrupt error code: The interrupt has already been created.
115 *
116 * Value: 0x02000904
117 *
118 * Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
119 */
120#define OS_ERRNO_HWI_ALREADY_CREATED          LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x04)
121
122/* *
123 * @ingroup los_arch_interrupt
124 * Hardware interrupt error code: Invalid interrupt priority.
125 *
126 * Value: 0x02000905
127 *
128 * Solution: Ensure that the interrupt priority is valid.
129 * The value range of the interrupt priority applicable for a arm9 platform is [0,15].
130 */
131#define OS_ERRNO_HWI_PRIO_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05)
132
133/* *
134 * @ingroup los_arch_interrupt
135 * Hardware interrupt error code: Incorrect interrupt creation mode.
136 *
137 * Value: 0x02000906
138 *
139 * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or
140 * OS_HWI_MODE_FAST of which the value can be 0 or 1.
141 */
142#define OS_ERRNO_HWI_MODE_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06)
143
144/* *
145 * @ingroup los_arch_interrupt
146 * Hardware interrupt error code: The interrupt has already been created as a fast interrupt.
147 *
148 * Value: 0x02000907
149 *
150 * Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
151 */
152#define OS_ERRNO_HWI_FASTMODE_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x07)
153
154/* *
155 * @ingroup los_arch_interrupt
156 * Hardware interrupt error code: Invalid interrupt operation function.
157 *
158 * Value: 0x0200090c
159 *
160 * Solution: Set a valid interrupt operation function
161 */
162#define OS_ERRNO_HWI_OPS_FUNC_NULL            LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x0c)
163
164/* *
165 * @ingroup  los_arch_interrupt
166 * @brief: Hardware interrupt entry function.
167 *
168 * @par Description:
169 * This API is used as all hardware interrupt handling function entry.
170 *
171 * @attention:
172 * <ul><li>None.</li></ul>
173 *
174 * @param:None.
175 *
176 * @retval:None.
177 * @par Dependency:
178 * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
179 * @see None.
180 */
181extern VOID HalInterrupt(VOID);
182
183/**
184 * @ingroup los_exc
185 * the struct of register files
186 *
187 * description: the register files that saved when exception triggered
188 *
189 * notes:the following register with prefix 'uw'  correspond to the registers in the cpu  data sheet.
190 */
191typedef struct TagExcContext {
192    UINT32 spsr;
193    UINT32 r0;
194    UINT32 r1;
195    UINT32 r2;
196    UINT32 r3;
197    UINT32 r4;
198    UINT32 r5;
199    UINT32 r6;
200    UINT32 r7;
201    UINT32 r8;
202    UINT32 r9;
203    UINT32 r10;
204    UINT32 r11;
205    UINT32 r12;
206    UINT32 sp;
207    UINT32 lr;
208    UINT32 pc;
209} EXC_CONTEXT_S;
210
211typedef VOID (*EXC_PROC_FUNC)(UINT32, EXC_CONTEXT_S *);
212VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr);
213VOID HalHwiInit(VOID);
214
215/**
216 * @ingroup los_exc
217 * exception types: undefined instruction exception.
218 */
219#define OS_EXCEPT_UNDEF_INSTR           1
220
221/**
222 * @ingroup los_exc
223 * exception types: software interrupt.
224 */
225#define OS_EXCEPT_SWI                   2
226
227/**
228 * @ingroup los_exc
229 * exception types: prefetch abort exception.
230 */
231#define OS_EXCEPT_PREFETCH_ABORT        3
232
233/**
234 * @ingroup los_exc
235 * exception types: data abort exception.
236 */
237#define OS_EXCEPT_DATA_ABORT            4
238
239/**
240 * @ingroup los_exc
241 * exception types: FIQ exception.
242 */
243#define OS_EXCEPT_FIQ                   5
244
245/**
246 * @ingroup los_exc
247 * Exception information structure
248 *
249 * Description: Exception information saved when an exception is triggered on the Cortex-M4 platform.
250 *
251 */
252typedef struct TagExcInfo {
253    /**< Exception occurrence phase: 0 means that an exception occurs in initialization,
254     * 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
255    UINT16 phase;
256    /**< Exception type. When exceptions occur, check the numbers 1 - 19 listed above */
257    UINT16 type;
258    /**< If the exact address access error indicates the wrong access address when the exception occurred */
259    UINT32 faultAddr;
260    /**< An exception occurs in an interrupt, indicating the interrupt number.
261     * An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
262    UINT32 thrdPid;
263    /**< Number of nested exceptions. Currently only registered hook functions are supported
264     * when an exception is entered for the first time */
265    UINT16 nestCnt;
266    /**< reserve */
267    UINT16 reserved;
268    /**< Hardware context at the time an exception to the automatic stack floating-point register occurs */
269    EXC_CONTEXT_S *context;
270} ExcInfo;
271
272extern ExcInfo g_excInfo;
273
274#ifdef __cplusplus
275#if __cplusplus
276}
277#endif /* __cplusplus */
278#endif /* __cplusplus */
279
280#endif /* _LOS_ARCH_INTERRUPT_H */
281