1/* 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without modification, 6 * are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, this list of 9 * conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, this list 12 * of conditions and the following disclaimer in the documentation and/or other materials 13 * provided with the distribution. 14 * 15 * 3. Neither the name of the copyright holder nor the names of its contributors may be used 16 * to endorse or promote products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#ifndef _GIC_COMMON_H 33#define _GIC_COMMON_H 34 35#include "stdint.h" 36#include "target_config.h" 37#include "los_config.h" 38 39/* gic arch revision */ 40enum { 41 GICV1 = 1, 42 GICV2, 43 GICV3, 44 GICV4 45}; 46 47#define GIC_REV_MASK 0xF0 48#define GIC_REV_OFFSET 0x4 49 50#ifdef LOSCFG_ARCH_GIC_V2 51#define GICC_CTLR (GICC_OFFSET + 0x00) /* CPU Interface Control Register */ 52#define GICC_PMR (GICC_OFFSET + 0x04) /* Interrupt Priority Mask Register */ 53#define GICC_BPR (GICC_OFFSET + 0x08) /* Binary Point Register */ 54#define GICC_IAR (GICC_OFFSET + 0x0c) /* Interrupt Acknowledge Register */ 55#define GICC_EOIR (GICC_OFFSET + 0x10) /* End of Interrupt Register */ 56#define GICC_RPR (GICC_OFFSET + 0x14) /* Running Priority Register */ 57#define GICC_HPPIR (GICC_OFFSET + 0x18) /* Highest Priority Pending Interrupt Register */ 58#endif 59 60#define GICD_CTLR (GICD_OFFSET + 0x000) /* Distributor Control Register */ 61#define GICD_TYPER (GICD_OFFSET + 0x004) /* Interrupt Controller Type Register */ 62#define GICD_IIDR (GICD_OFFSET + 0x008) /* Distributor Implementer Identification Register */ 63#define GICD_IGROUPR(n) (GICD_OFFSET + 0x080 + (n) * 4) /* Interrupt Group Registers */ 64#define GICD_ISENABLER(n) (GICD_OFFSET + 0x100 + (n) * 4) /* Interrupt Set-Enable Registers */ 65#define GICD_ICENABLER(n) (GICD_OFFSET + 0x180 + (n) * 4) /* Interrupt Clear-Enable Registers */ 66#define GICD_ISPENDR(n) (GICD_OFFSET + 0x200 + (n) * 4) /* Interrupt Set-Pending Registers */ 67#define GICD_ICPENDR(n) (GICD_OFFSET + 0x280 + (n) * 4) /* Interrupt Clear-Pending Registers */ 68#define GICD_ISACTIVER(n) (GICD_OFFSET + 0x300 + (n) * 4) /* GICv2 Interrupt Set-Active Registers */ 69#define GICD_ICACTIVER(n) (GICD_OFFSET + 0x380 + (n) * 4) /* Interrupt Clear-Active Registers */ 70#define GICD_IPRIORITYR(n) (GICD_OFFSET + 0x400 + (n) * 4) /* Interrupt Priority Registers */ 71#define GICD_ITARGETSR(n) (GICD_OFFSET + 0x800 + (n) * 4) /* Interrupt Processor Targets Registers */ 72#define GICD_ICFGR(n) (GICD_OFFSET + 0xc00 + (n) * 4) /* Interrupt Configuration Registers */ 73#define GICD_SGIR (GICD_OFFSET + 0xf00) /* Software Generated Interrupt Register */ 74#define GICD_CPENDSGIR(n) (GICD_OFFSET + 0xf10 + (n) * 4) /* SGI Clear-Pending Registers; NOT available on cortex-a9 */ 75#define GICD_SPENDSGIR(n) (GICD_OFFSET + 0xf20 + (n) * 4) /* SGI Set-Pending Registers; NOT available on cortex-a9 */ 76#define GICD_PIDR2V2 (GICD_OFFSET + 0xfe8) 77#define GICD_PIDR2V3 (GICD_OFFSET + 0xffe8) 78 79#ifdef LOSCFG_ARCH_GIC_V3 80#define GICD_IGRPMODR(n) (GICD_OFFSET + 0x0d00 + (n) * 4) /* Interrupt Group Mode Registers */ 81#define GICD_IROUTER(n) (GICD_OFFSET + 0x6000 + (n) * 8) /* Interrupt Rounter Registers */ 82#endif 83 84#define GIC_REG_8(reg) (*(volatile UINT8 *)((UINTPTR)(GIC_BASE_ADDR + (reg)))) 85#define GIC_REG_32(reg) (*(volatile UINT32 *)((UINTPTR)(GIC_BASE_ADDR + (reg)))) 86#define GIC_REG_64(reg) (*(volatile UINT64 *)((UINTPTR)(GIC_BASE_ADDR + (reg)))) 87 88#define GICD_INT_DEF_PRI 0xa0U 89#define GICD_INT_DEF_PRI_X4 (((UINT32)GICD_INT_DEF_PRI << 24) | \ 90 ((UINT32)GICD_INT_DEF_PRI << 16) | \ 91 ((UINT32)GICD_INT_DEF_PRI << 8) | \ 92 (UINT32)GICD_INT_DEF_PRI) 93 94#define GIC_MIN_SPI_NUM 32 95 96/* Interrupt preemption config */ 97#define GIC_PRIORITY_MASK 0xFFU 98#define GIC_PRIORITY_OFFSET 8 99 100/* 101 * The number of bits to shift for an interrupt priority is dependent 102 * on the number of bits implemented by the interrupt controller. 103 * If the MAX_BINARY_POINT_VALUE is 7, 104 * it means that interrupt preemption is not supported. 105 */ 106#ifndef LOSCFG_ARCH_INTERRUPT_PREEMPTION 107#define MAX_BINARY_POINT_VALUE 7 108#define PRIORITY_SHIFT 0 109#define GIC_MAX_INTERRUPT_PREEMPTION_LEVEL 0U 110#else 111#define PRIORITY_SHIFT ((MAX_BINARY_POINT_VALUE + 1) % GIC_PRIORITY_OFFSET) 112#define GIC_MAX_INTERRUPT_PREEMPTION_LEVEL ((UINT8)((GIC_PRIORITY_MASK + 1) >> PRIORITY_SHIFT)) 113#endif 114 115#define GIC_INTR_PRIO_MASK ((UINT8)(0xFFFFFFFFU << PRIORITY_SHIFT)) 116 117/* 118 * The preemption level is up to 128, and the maximum value corresponding to the interrupt priority is 254 [7:1]. 119 * If the GIC_MAX_INTERRUPT_PREEMPTION_LEVEL is 0, the minimum priority is 0xff. 120 */ 121#define MIN_INTERRUPT_PRIORITY ((UINT8)((GIC_MAX_INTERRUPT_PREEMPTION_LEVEL - 1) << PRIORITY_SHIFT)) 122 123#endif 124