1/****************************************************************************
2 ****************************************************************************
3 ***
4 ***   This header was automatically generated from a Linux kernel header
5 ***   of the same name, to make information necessary for userspace to
6 ***   call into the kernel available to libc.  It contains only constants,
7 ***   structures, and macros generated from the original header, and thus,
8 ***   contains no copyrightable information.
9 ***
10 ***   To edit the content of this header, modify the corresponding
11 ***   source file (e.g. under external/kernel-headers/original/) then
12 ***   run bionic/libc/kernel/tools/update_all.py
13 ***
14 ***   Any manual change here will be lost the next time this script will
15 ***   be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __HDA_TPLG_INTERFACE_H__
20#define __HDA_TPLG_INTERFACE_H__
21#include <linux/types.h>
22#define SKL_CONTROL_TYPE_BYTE_TLV 0x100
23#define SKL_CONTROL_TYPE_MIC_SELECT 0x102
24#define SKL_CONTROL_TYPE_MULTI_IO_SELECT 0x103
25#define SKL_CONTROL_TYPE_MULTI_IO_SELECT_DMIC 0x104
26#define HDA_SST_CFG_MAX 900
27#define MAX_IN_QUEUE 8
28#define MAX_OUT_QUEUE 8
29#define SKL_UUID_STR_SZ 40
30enum skl_event_types {
31  SKL_EVENT_NONE = 0,
32  SKL_MIXER_EVENT,
33  SKL_MUX_EVENT,
34  SKL_VMIXER_EVENT,
35  SKL_PGA_EVENT
36};
37enum skl_ch_cfg {
38  SKL_CH_CFG_MONO = 0,
39  SKL_CH_CFG_STEREO = 1,
40  SKL_CH_CFG_2_1 = 2,
41  SKL_CH_CFG_3_0 = 3,
42  SKL_CH_CFG_3_1 = 4,
43  SKL_CH_CFG_QUATRO = 5,
44  SKL_CH_CFG_4_0 = 6,
45  SKL_CH_CFG_5_0 = 7,
46  SKL_CH_CFG_5_1 = 8,
47  SKL_CH_CFG_DUAL_MONO = 9,
48  SKL_CH_CFG_I2S_DUAL_STEREO_0 = 10,
49  SKL_CH_CFG_I2S_DUAL_STEREO_1 = 11,
50  SKL_CH_CFG_4_CHANNEL = 12,
51  SKL_CH_CFG_INVALID
52};
53enum skl_module_type {
54  SKL_MODULE_TYPE_MIXER = 0,
55  SKL_MODULE_TYPE_COPIER,
56  SKL_MODULE_TYPE_UPDWMIX,
57  SKL_MODULE_TYPE_SRCINT,
58  SKL_MODULE_TYPE_ALGO,
59  SKL_MODULE_TYPE_BASE_OUTFMT,
60  SKL_MODULE_TYPE_KPB,
61  SKL_MODULE_TYPE_MIC_SELECT,
62};
63enum skl_core_affinity {
64  SKL_AFFINITY_CORE_0 = 0,
65  SKL_AFFINITY_CORE_1,
66  SKL_AFFINITY_CORE_MAX
67};
68enum skl_pipe_conn_type {
69  SKL_PIPE_CONN_TYPE_NONE = 0,
70  SKL_PIPE_CONN_TYPE_FE,
71  SKL_PIPE_CONN_TYPE_BE
72};
73enum skl_hw_conn_type {
74  SKL_CONN_NONE = 0,
75  SKL_CONN_SOURCE = 1,
76  SKL_CONN_SINK = 2
77};
78enum skl_dev_type {
79  SKL_DEVICE_BT = 0x0,
80  SKL_DEVICE_DMIC = 0x1,
81  SKL_DEVICE_I2S = 0x2,
82  SKL_DEVICE_SLIMBUS = 0x3,
83  SKL_DEVICE_HDALINK = 0x4,
84  SKL_DEVICE_HDAHOST = 0x5,
85  SKL_DEVICE_NONE
86};
87enum skl_interleaving {
88  SKL_INTERLEAVING_PER_CHANNEL = 0,
89  SKL_INTERLEAVING_PER_SAMPLE = 1,
90};
91enum skl_sample_type {
92  SKL_SAMPLE_TYPE_INT_MSB = 0,
93  SKL_SAMPLE_TYPE_INT_LSB = 1,
94  SKL_SAMPLE_TYPE_INT_SIGNED = 2,
95  SKL_SAMPLE_TYPE_INT_UNSIGNED = 3,
96  SKL_SAMPLE_TYPE_FLOAT = 4
97};
98enum module_pin_type {
99  SKL_PIN_TYPE_HOMOGENEOUS,
100  SKL_PIN_TYPE_HETEROGENEOUS,
101};
102enum skl_module_param_type {
103  SKL_PARAM_DEFAULT = 0,
104  SKL_PARAM_INIT,
105  SKL_PARAM_SET,
106  SKL_PARAM_BIND
107};
108struct skl_dfw_algo_data {
109  __u32 set_params : 2;
110  __u32 rsvd : 30;
111  __u32 param_id;
112  __u32 max;
113  char params[0];
114} __packed;
115enum skl_tkn_dir {
116  SKL_DIR_IN,
117  SKL_DIR_OUT
118};
119enum skl_tuple_type {
120  SKL_TYPE_TUPLE,
121  SKL_TYPE_DATA
122};
123struct skl_dfw_v4_module_pin {
124  __u16 module_id;
125  __u16 instance_id;
126} __packed;
127struct skl_dfw_v4_module_fmt {
128  __u32 channels;
129  __u32 freq;
130  __u32 bit_depth;
131  __u32 valid_bit_depth;
132  __u32 ch_cfg;
133  __u32 interleaving_style;
134  __u32 sample_type;
135  __u32 ch_map;
136} __packed;
137struct skl_dfw_v4_module_caps {
138  __u32 set_params : 2;
139  __u32 rsvd : 30;
140  __u32 param_id;
141  __u32 caps_size;
142  __u32 caps[HDA_SST_CFG_MAX];
143} __packed;
144struct skl_dfw_v4_pipe {
145  __u8 pipe_id;
146  __u8 pipe_priority;
147  __u16 conn_type : 4;
148  __u16 rsvd : 4;
149  __u16 memory_pages : 8;
150} __packed;
151struct skl_dfw_v4_module {
152  char uuid[SKL_UUID_STR_SZ];
153  __u16 module_id;
154  __u16 instance_id;
155  __u32 max_mcps;
156  __u32 mem_pages;
157  __u32 obs;
158  __u32 ibs;
159  __u32 vbus_id;
160  __u32 max_in_queue : 8;
161  __u32 max_out_queue : 8;
162  __u32 time_slot : 8;
163  __u32 core_id : 4;
164  __u32 rsvd1 : 4;
165  __u32 module_type : 8;
166  __u32 conn_type : 4;
167  __u32 dev_type : 4;
168  __u32 hw_conn_type : 4;
169  __u32 rsvd2 : 12;
170  __u32 params_fixup : 8;
171  __u32 converter : 8;
172  __u32 input_pin_type : 1;
173  __u32 output_pin_type : 1;
174  __u32 is_dynamic_in_pin : 1;
175  __u32 is_dynamic_out_pin : 1;
176  __u32 is_loadable : 1;
177  __u32 rsvd3 : 11;
178  struct skl_dfw_v4_pipe pipe;
179  struct skl_dfw_v4_module_fmt in_fmt[MAX_IN_QUEUE];
180  struct skl_dfw_v4_module_fmt out_fmt[MAX_OUT_QUEUE];
181  struct skl_dfw_v4_module_pin in_pin[MAX_IN_QUEUE];
182  struct skl_dfw_v4_module_pin out_pin[MAX_OUT_QUEUE];
183  struct skl_dfw_v4_module_caps caps;
184} __packed;
185#endif
186