1/****************************************************************************
2 ****************************************************************************
3 ***
4 ***   This header was automatically generated from a Linux kernel header
5 ***   of the same name, to make information necessary for userspace to
6 ***   call into the kernel available to libc.  It contains only constants,
7 ***   structures, and macros generated from the original header, and thus,
8 ***   contains no copyrightable information.
9 ***
10 ***   To edit the content of this header, modify the corresponding
11 ***   source file (e.g. under external/kernel-headers/original/) then
12 ***   run bionic/libc/kernel/tools/update_all.py
13 ***
14 ***   Any manual change here will be lost the next time this script will
15 ***   be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _UAPI__SOUND_EMU10K1_H
20#define _UAPI__SOUND_EMU10K1_H
21#ifdef __linux__
22#include <linux/types.h>
23#endif
24#define EMU10K1_CARD_CREATIVE 0x00000000
25#define EMU10K1_CARD_EMUAPS 0x00000001
26#define EMU10K1_FX8010_PCM_COUNT 8
27#define __EMU10K1_DECLARE_BITMAP(name,bits) unsigned long name[(bits) / (sizeof(unsigned long) * 8)]
28#define iMAC0 0x00
29#define iMAC1 0x01
30#define iMAC2 0x02
31#define iMAC3 0x03
32#define iMACINT0 0x04
33#define iMACINT1 0x05
34#define iACC3 0x06
35#define iMACMV 0x07
36#define iANDXOR 0x08
37#define iTSTNEG 0x09
38#define iLIMITGE 0x0a
39#define iLIMITLT 0x0b
40#define iLOG 0x0c
41#define iEXP 0x0d
42#define iINTERP 0x0e
43#define iSKIP 0x0f
44#define FXBUS(x) (0x00 + (x))
45#define EXTIN(x) (0x10 + (x))
46#define EXTOUT(x) (0x20 + (x))
47#define FXBUS2(x) (0x30 + (x))
48#define C_00000000 0x40
49#define C_00000001 0x41
50#define C_00000002 0x42
51#define C_00000003 0x43
52#define C_00000004 0x44
53#define C_00000008 0x45
54#define C_00000010 0x46
55#define C_00000020 0x47
56#define C_00000100 0x48
57#define C_00010000 0x49
58#define C_00080000 0x4a
59#define C_10000000 0x4b
60#define C_20000000 0x4c
61#define C_40000000 0x4d
62#define C_80000000 0x4e
63#define C_7fffffff 0x4f
64#define C_ffffffff 0x50
65#define C_fffffffe 0x51
66#define C_c0000000 0x52
67#define C_4f1bbcdc 0x53
68#define C_5a7ef9db 0x54
69#define C_00100000 0x55
70#define GPR_ACCU 0x56
71#define GPR_COND 0x57
72#define GPR_NOISE0 0x58
73#define GPR_NOISE1 0x59
74#define GPR_IRQ 0x5a
75#define GPR_DBAC 0x5b
76#define GPR(x) (FXGPREGBASE + (x))
77#define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x))
78#define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x))
79#define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x))
80#define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x))
81#define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x))
82#define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x))
83#define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x))
84#define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x))
85#define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x))
86#define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x))
87#define A_FXBUS(x) (0x00 + (x))
88#define A_EXTIN(x) (0x40 + (x))
89#define A_P16VIN(x) (0x50 + (x))
90#define A_EXTOUT(x) (0x60 + (x))
91#define A_FXBUS2(x) (0x80 + (x))
92#define A_EMU32OUTH(x) (0xa0 + (x))
93#define A_EMU32OUTL(x) (0xb0 + (x))
94#define A3_EMU32IN(x) (0x160 + (x))
95#define A3_EMU32OUT(x) (0x1E0 + (x))
96#define A_GPR(x) (A_FXGPREGBASE + (x))
97#define CC_REG_NORMALIZED C_00000001
98#define CC_REG_BORROW C_00000002
99#define CC_REG_MINUS C_00000004
100#define CC_REG_ZERO C_00000008
101#define CC_REG_SATURATE C_00000010
102#define CC_REG_NONZERO C_00000100
103#define FXBUS_PCM_LEFT 0x00
104#define FXBUS_PCM_RIGHT 0x01
105#define FXBUS_PCM_LEFT_REAR 0x02
106#define FXBUS_PCM_RIGHT_REAR 0x03
107#define FXBUS_MIDI_LEFT 0x04
108#define FXBUS_MIDI_RIGHT 0x05
109#define FXBUS_PCM_CENTER 0x06
110#define FXBUS_PCM_LFE 0x07
111#define FXBUS_PCM_LEFT_FRONT 0x08
112#define FXBUS_PCM_RIGHT_FRONT 0x09
113#define FXBUS_MIDI_REVERB 0x0c
114#define FXBUS_MIDI_CHORUS 0x0d
115#define FXBUS_PCM_LEFT_SIDE 0x0e
116#define FXBUS_PCM_RIGHT_SIDE 0x0f
117#define FXBUS_PT_LEFT 0x14
118#define FXBUS_PT_RIGHT 0x15
119#define EXTIN_AC97_L 0x00
120#define EXTIN_AC97_R 0x01
121#define EXTIN_SPDIF_CD_L 0x02
122#define EXTIN_SPDIF_CD_R 0x03
123#define EXTIN_ZOOM_L 0x04
124#define EXTIN_ZOOM_R 0x05
125#define EXTIN_TOSLINK_L 0x06
126#define EXTIN_TOSLINK_R 0x07
127#define EXTIN_LINE1_L 0x08
128#define EXTIN_LINE1_R 0x09
129#define EXTIN_COAX_SPDIF_L 0x0a
130#define EXTIN_COAX_SPDIF_R 0x0b
131#define EXTIN_LINE2_L 0x0c
132#define EXTIN_LINE2_R 0x0d
133#define EXTOUT_AC97_L 0x00
134#define EXTOUT_AC97_R 0x01
135#define EXTOUT_TOSLINK_L 0x02
136#define EXTOUT_TOSLINK_R 0x03
137#define EXTOUT_AC97_CENTER 0x04
138#define EXTOUT_AC97_LFE 0x05
139#define EXTOUT_HEADPHONE_L 0x06
140#define EXTOUT_HEADPHONE_R 0x07
141#define EXTOUT_REAR_L 0x08
142#define EXTOUT_REAR_R 0x09
143#define EXTOUT_ADC_CAP_L 0x0a
144#define EXTOUT_ADC_CAP_R 0x0b
145#define EXTOUT_MIC_CAP 0x0c
146#define EXTOUT_AC97_REAR_L 0x0d
147#define EXTOUT_AC97_REAR_R 0x0e
148#define EXTOUT_ACENTER 0x11
149#define EXTOUT_ALFE 0x12
150#define A_EXTIN_AC97_L 0x00
151#define A_EXTIN_AC97_R 0x01
152#define A_EXTIN_SPDIF_CD_L 0x02
153#define A_EXTIN_SPDIF_CD_R 0x03
154#define A_EXTIN_OPT_SPDIF_L 0x04
155#define A_EXTIN_OPT_SPDIF_R 0x05
156#define A_EXTIN_LINE2_L 0x08
157#define A_EXTIN_LINE2_R 0x09
158#define A_EXTIN_ADC_L 0x0a
159#define A_EXTIN_ADC_R 0x0b
160#define A_EXTIN_AUX2_L 0x0c
161#define A_EXTIN_AUX2_R 0x0d
162#define A_EXTOUT_FRONT_L 0x00
163#define A_EXTOUT_FRONT_R 0x01
164#define A_EXTOUT_CENTER 0x02
165#define A_EXTOUT_LFE 0x03
166#define A_EXTOUT_HEADPHONE_L 0x04
167#define A_EXTOUT_HEADPHONE_R 0x05
168#define A_EXTOUT_REAR_L 0x06
169#define A_EXTOUT_REAR_R 0x07
170#define A_EXTOUT_AFRONT_L 0x08
171#define A_EXTOUT_AFRONT_R 0x09
172#define A_EXTOUT_ACENTER 0x0a
173#define A_EXTOUT_ALFE 0x0b
174#define A_EXTOUT_ASIDE_L 0x0c
175#define A_EXTOUT_ASIDE_R 0x0d
176#define A_EXTOUT_AREAR_L 0x0e
177#define A_EXTOUT_AREAR_R 0x0f
178#define A_EXTOUT_AC97_L 0x10
179#define A_EXTOUT_AC97_R 0x11
180#define A_EXTOUT_ADC_CAP_L 0x16
181#define A_EXTOUT_ADC_CAP_R 0x17
182#define A_EXTOUT_MIC_CAP 0x18
183#define A_C_00000000 0xc0
184#define A_C_00000001 0xc1
185#define A_C_00000002 0xc2
186#define A_C_00000003 0xc3
187#define A_C_00000004 0xc4
188#define A_C_00000008 0xc5
189#define A_C_00000010 0xc6
190#define A_C_00000020 0xc7
191#define A_C_00000100 0xc8
192#define A_C_00010000 0xc9
193#define A_C_00000800 0xca
194#define A_C_10000000 0xcb
195#define A_C_20000000 0xcc
196#define A_C_40000000 0xcd
197#define A_C_80000000 0xce
198#define A_C_7fffffff 0xcf
199#define A_C_ffffffff 0xd0
200#define A_C_fffffffe 0xd1
201#define A_C_c0000000 0xd2
202#define A_C_4f1bbcdc 0xd3
203#define A_C_5a7ef9db 0xd4
204#define A_C_00100000 0xd5
205#define A_GPR_ACCU 0xd6
206#define A_GPR_COND 0xd7
207#define A_GPR_NOISE0 0xd8
208#define A_GPR_NOISE1 0xd9
209#define A_GPR_IRQ 0xda
210#define A_GPR_DBAC 0xdb
211#define A_GPR_DBACE 0xde
212#define EMU10K1_DBG_ZC 0x80000000
213#define EMU10K1_DBG_SATURATION_OCCURED 0x02000000
214#define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000
215#define EMU10K1_DBG_SINGLE_STEP 0x00008000
216#define EMU10K1_DBG_STEP 0x00004000
217#define EMU10K1_DBG_CONDITION_CODE 0x00003e00
218#define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff
219#define TANKMEMADDRREG_ADDR_MASK 0x000fffff
220#define TANKMEMADDRREG_CLEAR 0x00800000
221#define TANKMEMADDRREG_ALIGN 0x00400000
222#define TANKMEMADDRREG_WRITE 0x00200000
223#define TANKMEMADDRREG_READ 0x00100000
224struct snd_emu10k1_fx8010_info {
225  unsigned int internal_tram_size;
226  unsigned int external_tram_size;
227  char fxbus_names[16][32];
228  char extin_names[16][32];
229  char extout_names[32][32];
230  unsigned int gpr_controls;
231};
232#define EMU10K1_GPR_TRANSLATION_NONE 0
233#define EMU10K1_GPR_TRANSLATION_TABLE100 1
234#define EMU10K1_GPR_TRANSLATION_BASS 2
235#define EMU10K1_GPR_TRANSLATION_TREBLE 3
236#define EMU10K1_GPR_TRANSLATION_ONOFF 4
237enum emu10k1_ctl_elem_iface {
238  EMU10K1_CTL_ELEM_IFACE_MIXER = 2,
239  EMU10K1_CTL_ELEM_IFACE_PCM = 3,
240};
241struct emu10k1_ctl_elem_id {
242  unsigned int pad;
243  int iface;
244  unsigned int device;
245  unsigned int subdevice;
246  unsigned char name[44];
247  unsigned int index;
248};
249struct snd_emu10k1_fx8010_control_gpr {
250  struct emu10k1_ctl_elem_id id;
251  unsigned int vcount;
252  unsigned int count;
253  unsigned short gpr[32];
254  unsigned int value[32];
255  unsigned int min;
256  unsigned int max;
257  unsigned int translation;
258  const unsigned int * tlv;
259};
260struct snd_emu10k1_fx8010_control_old_gpr {
261  struct emu10k1_ctl_elem_id id;
262  unsigned int vcount;
263  unsigned int count;
264  unsigned short gpr[32];
265  unsigned int value[32];
266  unsigned int min;
267  unsigned int max;
268  unsigned int translation;
269};
270struct snd_emu10k1_fx8010_code {
271  char name[128];
272  __EMU10K1_DECLARE_BITMAP(gpr_valid, 0x200);
273  __u32 * gpr_map;
274  unsigned int gpr_add_control_count;
275  struct snd_emu10k1_fx8010_control_gpr * gpr_add_controls;
276  unsigned int gpr_del_control_count;
277  struct emu10k1_ctl_elem_id * gpr_del_controls;
278  unsigned int gpr_list_control_count;
279  unsigned int gpr_list_control_total;
280  struct snd_emu10k1_fx8010_control_gpr * gpr_list_controls;
281  __EMU10K1_DECLARE_BITMAP(tram_valid, 0x100);
282  __u32 * tram_data_map;
283  __u32 * tram_addr_map;
284  __EMU10K1_DECLARE_BITMAP(code_valid, 1024);
285  __u32 * code;
286};
287struct snd_emu10k1_fx8010_tram {
288  unsigned int address;
289  unsigned int size;
290  unsigned int * samples;
291};
292struct snd_emu10k1_fx8010_pcm_rec {
293  unsigned int substream;
294  unsigned int res1;
295  unsigned int channels;
296  unsigned int tram_start;
297  unsigned int buffer_size;
298  unsigned short gpr_size;
299  unsigned short gpr_ptr;
300  unsigned short gpr_count;
301  unsigned short gpr_tmpcount;
302  unsigned short gpr_trigger;
303  unsigned short gpr_running;
304  unsigned char pad;
305  unsigned char etram[32];
306  unsigned int res2;
307};
308#define SNDRV_EMU10K1_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1)
309#define SNDRV_EMU10K1_IOCTL_INFO _IOR('H', 0x10, struct snd_emu10k1_fx8010_info)
310#define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW('H', 0x11, struct snd_emu10k1_fx8010_code)
311#define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR('H', 0x12, struct snd_emu10k1_fx8010_code)
312#define SNDRV_EMU10K1_IOCTL_TRAM_SETUP _IOW('H', 0x20, int)
313#define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW('H', 0x21, struct snd_emu10k1_fx8010_tram)
314#define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR('H', 0x22, struct snd_emu10k1_fx8010_tram)
315#define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW('H', 0x30, struct snd_emu10k1_fx8010_pcm_rec)
316#define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, struct snd_emu10k1_fx8010_pcm_rec)
317#define SNDRV_EMU10K1_IOCTL_PVERSION _IOR('H', 0x40, int)
318#define SNDRV_EMU10K1_IOCTL_STOP _IO('H', 0x80)
319#define SNDRV_EMU10K1_IOCTL_CONTINUE _IO('H', 0x81)
320#define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO('H', 0x82)
321#define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW('H', 0x83, int)
322#define SNDRV_EMU10K1_IOCTL_DBG_READ _IOR('H', 0x84, int)
323#endif
324