1/****************************************************************************
2 ****************************************************************************
3 ***
4 ***   This header was automatically generated from a Linux kernel header
5 ***   of the same name, to make information necessary for userspace to
6 ***   call into the kernel available to libc.  It contains only constants,
7 ***   structures, and macros generated from the original header, and thus,
8 ***   contains no copyrightable information.
9 ***
10 ***   To edit the content of this header, modify the corresponding
11 ***   source file (e.g. under external/kernel-headers/original/) then
12 ***   run bionic/libc/kernel/tools/update_all.py
13 ***
14 ***   Any manual change here will be lost the next time this script will
15 ***   be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef MLX4_ABI_USER_H
20#define MLX4_ABI_USER_H
21#include <linux/types.h>
22#define MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION 3
23#define MLX4_IB_UVERBS_ABI_VERSION 4
24struct mlx4_ib_alloc_ucontext_resp_v3 {
25  __u32 qp_tab_size;
26  __u16 bf_reg_size;
27  __u16 bf_regs_per_page;
28};
29enum {
30  MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0,
31};
32struct mlx4_ib_alloc_ucontext_resp {
33  __u32 dev_caps;
34  __u32 qp_tab_size;
35  __u16 bf_reg_size;
36  __u16 bf_regs_per_page;
37  __u32 cqe_size;
38};
39struct mlx4_ib_alloc_pd_resp {
40  __u32 pdn;
41  __u32 reserved;
42};
43struct mlx4_ib_create_cq {
44  __aligned_u64 buf_addr;
45  __aligned_u64 db_addr;
46};
47struct mlx4_ib_create_cq_resp {
48  __u32 cqn;
49  __u32 reserved;
50};
51struct mlx4_ib_resize_cq {
52  __aligned_u64 buf_addr;
53};
54struct mlx4_ib_create_srq {
55  __aligned_u64 buf_addr;
56  __aligned_u64 db_addr;
57};
58struct mlx4_ib_create_srq_resp {
59  __u32 srqn;
60  __u32 reserved;
61};
62struct mlx4_ib_create_qp_rss {
63  __aligned_u64 rx_hash_fields_mask;
64  __u8 rx_hash_function;
65  __u8 reserved[7];
66  __u8 rx_hash_key[40];
67  __u32 comp_mask;
68  __u32 reserved1;
69};
70struct mlx4_ib_create_qp {
71  __aligned_u64 buf_addr;
72  __aligned_u64 db_addr;
73  __u8 log_sq_bb_count;
74  __u8 log_sq_stride;
75  __u8 sq_no_prefetch;
76  __u8 reserved;
77  __u32 inl_recv_sz;
78};
79struct mlx4_ib_create_wq {
80  __aligned_u64 buf_addr;
81  __aligned_u64 db_addr;
82  __u8 log_range_size;
83  __u8 reserved[3];
84  __u32 comp_mask;
85};
86struct mlx4_ib_modify_wq {
87  __u32 comp_mask;
88  __u32 reserved;
89};
90struct mlx4_ib_create_rwq_ind_tbl_resp {
91  __u32 response_length;
92  __u32 reserved;
93};
94enum mlx4_ib_rx_hash_function_flags {
95  MLX4_IB_RX_HASH_FUNC_TOEPLITZ = 1 << 0,
96};
97enum mlx4_ib_rx_hash_fields {
98  MLX4_IB_RX_HASH_SRC_IPV4 = 1 << 0,
99  MLX4_IB_RX_HASH_DST_IPV4 = 1 << 1,
100  MLX4_IB_RX_HASH_SRC_IPV6 = 1 << 2,
101  MLX4_IB_RX_HASH_DST_IPV6 = 1 << 3,
102  MLX4_IB_RX_HASH_SRC_PORT_TCP = 1 << 4,
103  MLX4_IB_RX_HASH_DST_PORT_TCP = 1 << 5,
104  MLX4_IB_RX_HASH_SRC_PORT_UDP = 1 << 6,
105  MLX4_IB_RX_HASH_DST_PORT_UDP = 1 << 7,
106  MLX4_IB_RX_HASH_INNER = 1ULL << 31,
107};
108struct mlx4_ib_rss_caps {
109  __aligned_u64 rx_hash_fields_mask;
110  __u8 rx_hash_function;
111  __u8 reserved[7];
112};
113enum query_device_resp_mask {
114  MLX4_IB_QUERY_DEV_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
115};
116struct mlx4_ib_tso_caps {
117  __u32 max_tso;
118  __u32 supported_qpts;
119};
120struct mlx4_uverbs_ex_query_device_resp {
121  __u32 comp_mask;
122  __u32 response_length;
123  __aligned_u64 hca_core_clock_offset;
124  __u32 max_inl_recv_sz;
125  __u32 reserved;
126  struct mlx4_ib_rss_caps rss_caps;
127  struct mlx4_ib_tso_caps tso_caps;
128};
129#endif
130