1/****************************************************************************
2 ****************************************************************************
3 ***
4 ***   This header was automatically generated from a Linux kernel header
5 ***   of the same name, to make information necessary for userspace to
6 ***   call into the kernel available to libc.  It contains only constants,
7 ***   structures, and macros generated from the original header, and thus,
8 ***   contains no copyrightable information.
9 ***
10 ***   To edit the content of this header, modify the corresponding
11 ***   source file (e.g. under external/kernel-headers/original/) then
12 ***   run bionic/libc/kernel/tools/update_all.py
13 ***
14 ***   Any manual change here will be lost the next time this script will
15 ***   be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef HABANALABS_H_
20#define HABANALABS_H_
21#include <linux/types.h>
22#include <linux/ioctl.h>
23#define GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START 0x8000
24#define GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START 0x80
25#define GAUDI_FIRST_AVAILABLE_W_S_SYNC_OBJECT 48
26#define GAUDI_FIRST_AVAILABLE_W_S_MONITOR 24
27enum goya_queue_id {
28  GOYA_QUEUE_ID_DMA_0 = 0,
29  GOYA_QUEUE_ID_DMA_1 = 1,
30  GOYA_QUEUE_ID_DMA_2 = 2,
31  GOYA_QUEUE_ID_DMA_3 = 3,
32  GOYA_QUEUE_ID_DMA_4 = 4,
33  GOYA_QUEUE_ID_CPU_PQ = 5,
34  GOYA_QUEUE_ID_MME = 6,
35  GOYA_QUEUE_ID_TPC0 = 7,
36  GOYA_QUEUE_ID_TPC1 = 8,
37  GOYA_QUEUE_ID_TPC2 = 9,
38  GOYA_QUEUE_ID_TPC3 = 10,
39  GOYA_QUEUE_ID_TPC4 = 11,
40  GOYA_QUEUE_ID_TPC5 = 12,
41  GOYA_QUEUE_ID_TPC6 = 13,
42  GOYA_QUEUE_ID_TPC7 = 14,
43  GOYA_QUEUE_ID_SIZE
44};
45enum gaudi_queue_id {
46  GAUDI_QUEUE_ID_DMA_0_0 = 0,
47  GAUDI_QUEUE_ID_DMA_0_1 = 1,
48  GAUDI_QUEUE_ID_DMA_0_2 = 2,
49  GAUDI_QUEUE_ID_DMA_0_3 = 3,
50  GAUDI_QUEUE_ID_DMA_1_0 = 4,
51  GAUDI_QUEUE_ID_DMA_1_1 = 5,
52  GAUDI_QUEUE_ID_DMA_1_2 = 6,
53  GAUDI_QUEUE_ID_DMA_1_3 = 7,
54  GAUDI_QUEUE_ID_CPU_PQ = 8,
55  GAUDI_QUEUE_ID_DMA_2_0 = 9,
56  GAUDI_QUEUE_ID_DMA_2_1 = 10,
57  GAUDI_QUEUE_ID_DMA_2_2 = 11,
58  GAUDI_QUEUE_ID_DMA_2_3 = 12,
59  GAUDI_QUEUE_ID_DMA_3_0 = 13,
60  GAUDI_QUEUE_ID_DMA_3_1 = 14,
61  GAUDI_QUEUE_ID_DMA_3_2 = 15,
62  GAUDI_QUEUE_ID_DMA_3_3 = 16,
63  GAUDI_QUEUE_ID_DMA_4_0 = 17,
64  GAUDI_QUEUE_ID_DMA_4_1 = 18,
65  GAUDI_QUEUE_ID_DMA_4_2 = 19,
66  GAUDI_QUEUE_ID_DMA_4_3 = 20,
67  GAUDI_QUEUE_ID_DMA_5_0 = 21,
68  GAUDI_QUEUE_ID_DMA_5_1 = 22,
69  GAUDI_QUEUE_ID_DMA_5_2 = 23,
70  GAUDI_QUEUE_ID_DMA_5_3 = 24,
71  GAUDI_QUEUE_ID_DMA_6_0 = 25,
72  GAUDI_QUEUE_ID_DMA_6_1 = 26,
73  GAUDI_QUEUE_ID_DMA_6_2 = 27,
74  GAUDI_QUEUE_ID_DMA_6_3 = 28,
75  GAUDI_QUEUE_ID_DMA_7_0 = 29,
76  GAUDI_QUEUE_ID_DMA_7_1 = 30,
77  GAUDI_QUEUE_ID_DMA_7_2 = 31,
78  GAUDI_QUEUE_ID_DMA_7_3 = 32,
79  GAUDI_QUEUE_ID_MME_0_0 = 33,
80  GAUDI_QUEUE_ID_MME_0_1 = 34,
81  GAUDI_QUEUE_ID_MME_0_2 = 35,
82  GAUDI_QUEUE_ID_MME_0_3 = 36,
83  GAUDI_QUEUE_ID_MME_1_0 = 37,
84  GAUDI_QUEUE_ID_MME_1_1 = 38,
85  GAUDI_QUEUE_ID_MME_1_2 = 39,
86  GAUDI_QUEUE_ID_MME_1_3 = 40,
87  GAUDI_QUEUE_ID_TPC_0_0 = 41,
88  GAUDI_QUEUE_ID_TPC_0_1 = 42,
89  GAUDI_QUEUE_ID_TPC_0_2 = 43,
90  GAUDI_QUEUE_ID_TPC_0_3 = 44,
91  GAUDI_QUEUE_ID_TPC_1_0 = 45,
92  GAUDI_QUEUE_ID_TPC_1_1 = 46,
93  GAUDI_QUEUE_ID_TPC_1_2 = 47,
94  GAUDI_QUEUE_ID_TPC_1_3 = 48,
95  GAUDI_QUEUE_ID_TPC_2_0 = 49,
96  GAUDI_QUEUE_ID_TPC_2_1 = 50,
97  GAUDI_QUEUE_ID_TPC_2_2 = 51,
98  GAUDI_QUEUE_ID_TPC_2_3 = 52,
99  GAUDI_QUEUE_ID_TPC_3_0 = 53,
100  GAUDI_QUEUE_ID_TPC_3_1 = 54,
101  GAUDI_QUEUE_ID_TPC_3_2 = 55,
102  GAUDI_QUEUE_ID_TPC_3_3 = 56,
103  GAUDI_QUEUE_ID_TPC_4_0 = 57,
104  GAUDI_QUEUE_ID_TPC_4_1 = 58,
105  GAUDI_QUEUE_ID_TPC_4_2 = 59,
106  GAUDI_QUEUE_ID_TPC_4_3 = 60,
107  GAUDI_QUEUE_ID_TPC_5_0 = 61,
108  GAUDI_QUEUE_ID_TPC_5_1 = 62,
109  GAUDI_QUEUE_ID_TPC_5_2 = 63,
110  GAUDI_QUEUE_ID_TPC_5_3 = 64,
111  GAUDI_QUEUE_ID_TPC_6_0 = 65,
112  GAUDI_QUEUE_ID_TPC_6_1 = 66,
113  GAUDI_QUEUE_ID_TPC_6_2 = 67,
114  GAUDI_QUEUE_ID_TPC_6_3 = 68,
115  GAUDI_QUEUE_ID_TPC_7_0 = 69,
116  GAUDI_QUEUE_ID_TPC_7_1 = 70,
117  GAUDI_QUEUE_ID_TPC_7_2 = 71,
118  GAUDI_QUEUE_ID_TPC_7_3 = 72,
119  GAUDI_QUEUE_ID_NIC_0_0 = 73,
120  GAUDI_QUEUE_ID_NIC_0_1 = 74,
121  GAUDI_QUEUE_ID_NIC_0_2 = 75,
122  GAUDI_QUEUE_ID_NIC_0_3 = 76,
123  GAUDI_QUEUE_ID_NIC_1_0 = 77,
124  GAUDI_QUEUE_ID_NIC_1_1 = 78,
125  GAUDI_QUEUE_ID_NIC_1_2 = 79,
126  GAUDI_QUEUE_ID_NIC_1_3 = 80,
127  GAUDI_QUEUE_ID_NIC_2_0 = 81,
128  GAUDI_QUEUE_ID_NIC_2_1 = 82,
129  GAUDI_QUEUE_ID_NIC_2_2 = 83,
130  GAUDI_QUEUE_ID_NIC_2_3 = 84,
131  GAUDI_QUEUE_ID_NIC_3_0 = 85,
132  GAUDI_QUEUE_ID_NIC_3_1 = 86,
133  GAUDI_QUEUE_ID_NIC_3_2 = 87,
134  GAUDI_QUEUE_ID_NIC_3_3 = 88,
135  GAUDI_QUEUE_ID_NIC_4_0 = 89,
136  GAUDI_QUEUE_ID_NIC_4_1 = 90,
137  GAUDI_QUEUE_ID_NIC_4_2 = 91,
138  GAUDI_QUEUE_ID_NIC_4_3 = 92,
139  GAUDI_QUEUE_ID_NIC_5_0 = 93,
140  GAUDI_QUEUE_ID_NIC_5_1 = 94,
141  GAUDI_QUEUE_ID_NIC_5_2 = 95,
142  GAUDI_QUEUE_ID_NIC_5_3 = 96,
143  GAUDI_QUEUE_ID_NIC_6_0 = 97,
144  GAUDI_QUEUE_ID_NIC_6_1 = 98,
145  GAUDI_QUEUE_ID_NIC_6_2 = 99,
146  GAUDI_QUEUE_ID_NIC_6_3 = 100,
147  GAUDI_QUEUE_ID_NIC_7_0 = 101,
148  GAUDI_QUEUE_ID_NIC_7_1 = 102,
149  GAUDI_QUEUE_ID_NIC_7_2 = 103,
150  GAUDI_QUEUE_ID_NIC_7_3 = 104,
151  GAUDI_QUEUE_ID_NIC_8_0 = 105,
152  GAUDI_QUEUE_ID_NIC_8_1 = 106,
153  GAUDI_QUEUE_ID_NIC_8_2 = 107,
154  GAUDI_QUEUE_ID_NIC_8_3 = 108,
155  GAUDI_QUEUE_ID_NIC_9_0 = 109,
156  GAUDI_QUEUE_ID_NIC_9_1 = 110,
157  GAUDI_QUEUE_ID_NIC_9_2 = 111,
158  GAUDI_QUEUE_ID_NIC_9_3 = 112,
159  GAUDI_QUEUE_ID_SIZE
160};
161enum goya_engine_id {
162  GOYA_ENGINE_ID_DMA_0 = 0,
163  GOYA_ENGINE_ID_DMA_1,
164  GOYA_ENGINE_ID_DMA_2,
165  GOYA_ENGINE_ID_DMA_3,
166  GOYA_ENGINE_ID_DMA_4,
167  GOYA_ENGINE_ID_MME_0,
168  GOYA_ENGINE_ID_TPC_0,
169  GOYA_ENGINE_ID_TPC_1,
170  GOYA_ENGINE_ID_TPC_2,
171  GOYA_ENGINE_ID_TPC_3,
172  GOYA_ENGINE_ID_TPC_4,
173  GOYA_ENGINE_ID_TPC_5,
174  GOYA_ENGINE_ID_TPC_6,
175  GOYA_ENGINE_ID_TPC_7,
176  GOYA_ENGINE_ID_SIZE
177};
178enum gaudi_engine_id {
179  GAUDI_ENGINE_ID_DMA_0 = 0,
180  GAUDI_ENGINE_ID_DMA_1,
181  GAUDI_ENGINE_ID_DMA_2,
182  GAUDI_ENGINE_ID_DMA_3,
183  GAUDI_ENGINE_ID_DMA_4,
184  GAUDI_ENGINE_ID_DMA_5,
185  GAUDI_ENGINE_ID_DMA_6,
186  GAUDI_ENGINE_ID_DMA_7,
187  GAUDI_ENGINE_ID_MME_0,
188  GAUDI_ENGINE_ID_MME_1,
189  GAUDI_ENGINE_ID_MME_2,
190  GAUDI_ENGINE_ID_MME_3,
191  GAUDI_ENGINE_ID_TPC_0,
192  GAUDI_ENGINE_ID_TPC_1,
193  GAUDI_ENGINE_ID_TPC_2,
194  GAUDI_ENGINE_ID_TPC_3,
195  GAUDI_ENGINE_ID_TPC_4,
196  GAUDI_ENGINE_ID_TPC_5,
197  GAUDI_ENGINE_ID_TPC_6,
198  GAUDI_ENGINE_ID_TPC_7,
199  GAUDI_ENGINE_ID_NIC_0,
200  GAUDI_ENGINE_ID_NIC_1,
201  GAUDI_ENGINE_ID_NIC_2,
202  GAUDI_ENGINE_ID_NIC_3,
203  GAUDI_ENGINE_ID_NIC_4,
204  GAUDI_ENGINE_ID_NIC_5,
205  GAUDI_ENGINE_ID_NIC_6,
206  GAUDI_ENGINE_ID_NIC_7,
207  GAUDI_ENGINE_ID_NIC_8,
208  GAUDI_ENGINE_ID_NIC_9,
209  GAUDI_ENGINE_ID_SIZE
210};
211enum hl_device_status {
212  HL_DEVICE_STATUS_OPERATIONAL,
213  HL_DEVICE_STATUS_IN_RESET,
214  HL_DEVICE_STATUS_MALFUNCTION
215};
216#define HL_INFO_HW_IP_INFO 0
217#define HL_INFO_HW_EVENTS 1
218#define HL_INFO_DRAM_USAGE 2
219#define HL_INFO_HW_IDLE 3
220#define HL_INFO_DEVICE_STATUS 4
221#define HL_INFO_DEVICE_UTILIZATION 6
222#define HL_INFO_HW_EVENTS_AGGREGATE 7
223#define HL_INFO_CLK_RATE 8
224#define HL_INFO_RESET_COUNT 9
225#define HL_INFO_TIME_SYNC 10
226#define HL_INFO_CS_COUNTERS 11
227#define HL_INFO_PCI_COUNTERS 12
228#define HL_INFO_CLK_THROTTLE_REASON 13
229#define HL_INFO_SYNC_MANAGER 14
230#define HL_INFO_TOTAL_ENERGY 15
231#define HL_INFO_VERSION_MAX_LEN 128
232#define HL_INFO_CARD_NAME_MAX_LEN 16
233struct hl_info_hw_ip_info {
234  __u64 sram_base_address;
235  __u64 dram_base_address;
236  __u64 dram_size;
237  __u32 sram_size;
238  __u32 num_of_events;
239  __u32 device_id;
240  __u32 module_id;
241  __u32 reserved[2];
242  __u32 cpld_version;
243  __u32 psoc_pci_pll_nr;
244  __u32 psoc_pci_pll_nf;
245  __u32 psoc_pci_pll_od;
246  __u32 psoc_pci_pll_div_factor;
247  __u8 tpc_enabled_mask;
248  __u8 dram_enabled;
249  __u8 pad[2];
250  __u8 cpucp_version[HL_INFO_VERSION_MAX_LEN];
251  __u8 card_name[HL_INFO_CARD_NAME_MAX_LEN];
252};
253struct hl_info_dram_usage {
254  __u64 dram_free_mem;
255  __u64 ctx_dram_mem;
256};
257struct hl_info_hw_idle {
258  __u32 is_idle;
259  __u32 busy_engines_mask;
260  __u64 busy_engines_mask_ext;
261};
262struct hl_info_device_status {
263  __u32 status;
264  __u32 pad;
265};
266struct hl_info_device_utilization {
267  __u32 utilization;
268  __u32 pad;
269};
270struct hl_info_clk_rate {
271  __u32 cur_clk_rate_mhz;
272  __u32 max_clk_rate_mhz;
273};
274struct hl_info_reset_count {
275  __u32 hard_reset_cnt;
276  __u32 soft_reset_cnt;
277};
278struct hl_info_time_sync {
279  __u64 device_time;
280  __u64 host_time;
281};
282struct hl_info_pci_counters {
283  __u64 rx_throughput;
284  __u64 tx_throughput;
285  __u64 replay_cnt;
286};
287#define HL_CLK_THROTTLE_POWER 0x1
288#define HL_CLK_THROTTLE_THERMAL 0x2
289struct hl_info_clk_throttle {
290  __u32 clk_throttling_reason;
291};
292struct hl_info_energy {
293  __u64 total_energy_consumption;
294};
295struct hl_info_sync_manager {
296  __u32 first_available_sync_object;
297  __u32 first_available_monitor;
298};
299struct hl_cs_counters {
300  __u64 out_of_mem_drop_cnt;
301  __u64 parsing_drop_cnt;
302  __u64 queue_full_drop_cnt;
303  __u64 device_in_reset_drop_cnt;
304  __u64 max_cs_in_flight_drop_cnt;
305};
306struct hl_info_cs_counters {
307  struct hl_cs_counters cs_counters;
308  struct hl_cs_counters ctx_cs_counters;
309};
310enum gaudi_dcores {
311  HL_GAUDI_WS_DCORE,
312  HL_GAUDI_WN_DCORE,
313  HL_GAUDI_EN_DCORE,
314  HL_GAUDI_ES_DCORE
315};
316struct hl_info_args {
317  __u64 return_pointer;
318  __u32 return_size;
319  __u32 op;
320  union {
321    __u32 dcore_id;
322    __u32 ctx_id;
323    __u32 period_ms;
324  };
325  __u32 pad;
326};
327#define HL_CB_OP_CREATE 0
328#define HL_CB_OP_DESTROY 1
329#define HL_MAX_CB_SIZE (0x200000 - 32)
330#define HL_CB_FLAGS_MAP 0x1
331struct hl_cb_in {
332  __u64 cb_handle;
333  __u32 op;
334  __u32 cb_size;
335  __u32 ctx_id;
336  __u32 flags;
337};
338struct hl_cb_out {
339  __u64 cb_handle;
340};
341union hl_cb_args {
342  struct hl_cb_in in;
343  struct hl_cb_out out;
344};
345struct hl_cs_chunk {
346  union {
347    __u64 cb_handle;
348    __u64 signal_seq_arr;
349  };
350  __u32 queue_index;
351  union {
352    __u32 cb_size;
353    __u32 num_signal_seq_arr;
354  };
355  __u32 cs_chunk_flags;
356  __u32 pad[11];
357};
358#define HL_CS_FLAGS_FORCE_RESTORE 0x1
359#define HL_CS_FLAGS_SIGNAL 0x2
360#define HL_CS_FLAGS_WAIT 0x4
361#define HL_CS_STATUS_SUCCESS 0
362#define HL_MAX_JOBS_PER_CS 512
363struct hl_cs_in {
364  __u64 chunks_restore;
365  __u64 chunks_execute;
366  __u64 chunks_store;
367  __u32 num_chunks_restore;
368  __u32 num_chunks_execute;
369  __u32 num_chunks_store;
370  __u32 cs_flags;
371  __u32 ctx_id;
372};
373struct hl_cs_out {
374  __u64 seq;
375  __u32 status;
376  __u32 pad;
377};
378union hl_cs_args {
379  struct hl_cs_in in;
380  struct hl_cs_out out;
381};
382struct hl_wait_cs_in {
383  __u64 seq;
384  __u64 timeout_us;
385  __u32 ctx_id;
386  __u32 pad;
387};
388#define HL_WAIT_CS_STATUS_COMPLETED 0
389#define HL_WAIT_CS_STATUS_BUSY 1
390#define HL_WAIT_CS_STATUS_TIMEDOUT 2
391#define HL_WAIT_CS_STATUS_ABORTED 3
392#define HL_WAIT_CS_STATUS_INTERRUPTED 4
393struct hl_wait_cs_out {
394  __u32 status;
395  __u32 pad;
396};
397union hl_wait_cs_args {
398  struct hl_wait_cs_in in;
399  struct hl_wait_cs_out out;
400};
401#define HL_MEM_OP_ALLOC 0
402#define HL_MEM_OP_FREE 1
403#define HL_MEM_OP_MAP 2
404#define HL_MEM_OP_UNMAP 3
405#define HL_MEM_CONTIGUOUS 0x1
406#define HL_MEM_SHARED 0x2
407#define HL_MEM_USERPTR 0x4
408struct hl_mem_in {
409  union {
410    struct {
411      __u64 mem_size;
412    } alloc;
413    struct {
414      __u64 handle;
415    } free;
416    struct {
417      __u64 hint_addr;
418      __u64 handle;
419    } map_device;
420    struct {
421      __u64 host_virt_addr;
422      __u64 hint_addr;
423      __u64 mem_size;
424    } map_host;
425    struct {
426      __u64 device_virt_addr;
427    } unmap;
428  };
429  __u32 op;
430  __u32 flags;
431  __u32 ctx_id;
432  __u32 pad;
433};
434struct hl_mem_out {
435  union {
436    __u64 device_virt_addr;
437    __u64 handle;
438  };
439};
440union hl_mem_args {
441  struct hl_mem_in in;
442  struct hl_mem_out out;
443};
444#define HL_DEBUG_MAX_AUX_VALUES 10
445struct hl_debug_params_etr {
446  __u64 buffer_address;
447  __u64 buffer_size;
448  __u32 sink_mode;
449  __u32 pad;
450};
451struct hl_debug_params_etf {
452  __u64 buffer_address;
453  __u64 buffer_size;
454  __u32 sink_mode;
455  __u32 pad;
456};
457struct hl_debug_params_stm {
458  __u64 he_mask;
459  __u64 sp_mask;
460  __u32 id;
461  __u32 frequency;
462};
463struct hl_debug_params_bmon {
464  __u64 start_addr0;
465  __u64 addr_mask0;
466  __u64 start_addr1;
467  __u64 addr_mask1;
468  __u32 bw_win;
469  __u32 win_capture;
470  __u32 id;
471  __u32 pad;
472};
473struct hl_debug_params_spmu {
474  __u64 event_types[HL_DEBUG_MAX_AUX_VALUES];
475  __u32 event_types_num;
476  __u32 pad;
477};
478#define HL_DEBUG_OP_ETR 0
479#define HL_DEBUG_OP_ETF 1
480#define HL_DEBUG_OP_STM 2
481#define HL_DEBUG_OP_FUNNEL 3
482#define HL_DEBUG_OP_BMON 4
483#define HL_DEBUG_OP_SPMU 5
484#define HL_DEBUG_OP_TIMESTAMP 6
485#define HL_DEBUG_OP_SET_MODE 7
486struct hl_debug_args {
487  __u64 input_ptr;
488  __u64 output_ptr;
489  __u32 input_size;
490  __u32 output_size;
491  __u32 op;
492  __u32 reg_idx;
493  __u32 enable;
494  __u32 ctx_id;
495};
496#define HL_IOCTL_INFO _IOWR('H', 0x01, struct hl_info_args)
497#define HL_IOCTL_CB _IOWR('H', 0x02, union hl_cb_args)
498#define HL_IOCTL_CS _IOWR('H', 0x03, union hl_cs_args)
499#define HL_IOCTL_WAIT_CS _IOWR('H', 0x04, union hl_wait_cs_args)
500#define HL_IOCTL_MEMORY _IOWR('H', 0x05, union hl_mem_args)
501#define HL_IOCTL_DEBUG _IOWR('H', 0x06, struct hl_debug_args)
502#define HL_COMMAND_START 0x01
503#define HL_COMMAND_END 0x07
504#endif
505