1/****************************************************************************
2 ****************************************************************************
3 ***
4 ***   This header was automatically generated from a Linux kernel header
5 ***   of the same name, to make information necessary for userspace to
6 ***   call into the kernel available to libc.  It contains only constants,
7 ***   structures, and macros generated from the original header, and thus,
8 ***   contains no copyrightable information.
9 ***
10 ***   To edit the content of this header, modify the corresponding
11 ***   source file (e.g. under external/kernel-headers/original/) then
12 ***   run bionic/libc/kernel/tools/update_all.py
13 ***
14 ***   Any manual change here will be lost the next time this script will
15 ***   be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _USR_IDXD_H_
20#define _USR_IDXD_H_
21#include <stdint.h>
22#define IDXD_OP_FLAG_FENCE 0x0001
23#define IDXD_OP_FLAG_BOF 0x0002
24#define IDXD_OP_FLAG_CRAV 0x0004
25#define IDXD_OP_FLAG_RCR 0x0008
26#define IDXD_OP_FLAG_RCI 0x0010
27#define IDXD_OP_FLAG_CRSTS 0x0020
28#define IDXD_OP_FLAG_CR 0x0080
29#define IDXD_OP_FLAG_CC 0x0100
30#define IDXD_OP_FLAG_ADDR1_TCS 0x0200
31#define IDXD_OP_FLAG_ADDR2_TCS 0x0400
32#define IDXD_OP_FLAG_ADDR3_TCS 0x0800
33#define IDXD_OP_FLAG_CR_TCS 0x1000
34#define IDXD_OP_FLAG_STORD 0x2000
35#define IDXD_OP_FLAG_DRDBK 0x4000
36#define IDXD_OP_FLAG_DSTS 0x8000
37enum dsa_opcode {
38  DSA_OPCODE_NOOP = 0,
39  DSA_OPCODE_BATCH,
40  DSA_OPCODE_DRAIN,
41  DSA_OPCODE_MEMMOVE,
42  DSA_OPCODE_MEMFILL,
43  DSA_OPCODE_COMPARE,
44  DSA_OPCODE_COMPVAL,
45  DSA_OPCODE_CR_DELTA,
46  DSA_OPCODE_AP_DELTA,
47  DSA_OPCODE_DUALCAST,
48  DSA_OPCODE_CRCGEN = 0x10,
49  DSA_OPCODE_COPY_CRC,
50  DSA_OPCODE_DIF_CHECK,
51  DSA_OPCODE_DIF_INS,
52  DSA_OPCODE_DIF_STRP,
53  DSA_OPCODE_DIF_UPDT,
54  DSA_OPCODE_CFLUSH = 0x20,
55};
56enum dsa_completion_status {
57  DSA_COMP_NONE = 0,
58  DSA_COMP_SUCCESS,
59  DSA_COMP_SUCCESS_PRED,
60  DSA_COMP_PAGE_FAULT_NOBOF,
61  DSA_COMP_PAGE_FAULT_IR,
62  DSA_COMP_BATCH_FAIL,
63  DSA_COMP_BATCH_PAGE_FAULT,
64  DSA_COMP_DR_OFFSET_NOINC,
65  DSA_COMP_DR_OFFSET_ERANGE,
66  DSA_COMP_DIF_ERR,
67  DSA_COMP_BAD_OPCODE = 0x10,
68  DSA_COMP_INVALID_FLAGS,
69  DSA_COMP_NOZERO_RESERVE,
70  DSA_COMP_XFER_ERANGE,
71  DSA_COMP_DESC_CNT_ERANGE,
72  DSA_COMP_DR_ERANGE,
73  DSA_COMP_OVERLAP_BUFFERS,
74  DSA_COMP_DCAST_ERR,
75  DSA_COMP_DESCLIST_ALIGN,
76  DSA_COMP_INT_HANDLE_INVAL,
77  DSA_COMP_CRA_XLAT,
78  DSA_COMP_CRA_ALIGN,
79  DSA_COMP_ADDR_ALIGN,
80  DSA_COMP_PRIV_BAD,
81  DSA_COMP_TRAFFIC_CLASS_CONF,
82  DSA_COMP_PFAULT_RDBA,
83  DSA_COMP_HW_ERR1,
84  DSA_COMP_HW_ERR_DRB,
85  DSA_COMP_TRANSLATION_FAIL,
86};
87#define DSA_COMP_STATUS_MASK 0x7f
88#define DSA_COMP_STATUS_WRITE 0x80
89struct dsa_hw_desc {
90  uint32_t pasid : 20;
91  uint32_t rsvd : 11;
92  uint32_t priv : 1;
93  uint32_t flags : 24;
94  uint32_t opcode : 8;
95  uint64_t completion_addr;
96  union {
97    uint64_t src_addr;
98    uint64_t rdback_addr;
99    uint64_t pattern;
100    uint64_t desc_list_addr;
101  };
102  union {
103    uint64_t dst_addr;
104    uint64_t rdback_addr2;
105    uint64_t src2_addr;
106    uint64_t comp_pattern;
107  };
108  union {
109    uint32_t xfer_size;
110    uint32_t desc_count;
111  };
112  uint16_t int_handle;
113  uint16_t rsvd1;
114  union {
115    uint8_t expected_res;
116    struct {
117      uint64_t delta_addr;
118      uint32_t max_delta_size;
119      uint32_t delt_rsvd;
120      uint8_t expected_res_mask;
121    };
122    uint32_t delta_rec_size;
123    uint64_t dest2;
124    struct {
125      uint32_t crc_seed;
126      uint32_t crc_rsvd;
127      uint64_t seed_addr;
128    };
129    struct {
130      uint8_t src_dif_flags;
131      uint8_t dif_chk_res;
132      uint8_t dif_chk_flags;
133      uint8_t dif_chk_res2[5];
134      uint32_t chk_ref_tag_seed;
135      uint16_t chk_app_tag_mask;
136      uint16_t chk_app_tag_seed;
137    };
138    struct {
139      uint8_t dif_ins_res;
140      uint8_t dest_dif_flag;
141      uint8_t dif_ins_flags;
142      uint8_t dif_ins_res2[13];
143      uint32_t ins_ref_tag_seed;
144      uint16_t ins_app_tag_mask;
145      uint16_t ins_app_tag_seed;
146    };
147    struct {
148      uint8_t src_upd_flags;
149      uint8_t upd_dest_flags;
150      uint8_t dif_upd_flags;
151      uint8_t dif_upd_res[5];
152      uint32_t src_ref_tag_seed;
153      uint16_t src_app_tag_mask;
154      uint16_t src_app_tag_seed;
155      uint32_t dest_ref_tag_seed;
156      uint16_t dest_app_tag_mask;
157      uint16_t dest_app_tag_seed;
158    };
159    uint8_t op_specific[24];
160  };
161} __attribute__((packed));
162struct dsa_raw_desc {
163  uint64_t field[8];
164} __attribute__((packed));
165struct dsa_completion_record {
166  volatile uint8_t status;
167  union {
168    uint8_t result;
169    uint8_t dif_status;
170  };
171  uint16_t rsvd;
172  uint32_t bytes_completed;
173  uint64_t fault_addr;
174  union {
175    struct {
176      uint32_t invalid_flags : 24;
177      uint32_t rsvd2 : 8;
178    };
179    uint16_t delta_rec_size;
180    uint16_t crc_val;
181    struct {
182      uint32_t dif_chk_ref_tag;
183      uint16_t dif_chk_app_tag_mask;
184      uint16_t dif_chk_app_tag;
185    };
186    struct {
187      uint64_t dif_ins_res;
188      uint32_t dif_ins_ref_tag;
189      uint16_t dif_ins_app_tag_mask;
190      uint16_t dif_ins_app_tag;
191    };
192    struct {
193      uint32_t dif_upd_src_ref_tag;
194      uint16_t dif_upd_src_app_tag_mask;
195      uint16_t dif_upd_src_app_tag;
196      uint32_t dif_upd_dest_ref_tag;
197      uint16_t dif_upd_dest_app_tag_mask;
198      uint16_t dif_upd_dest_app_tag;
199    };
200    uint8_t op_specific[16];
201  };
202} __attribute__((packed));
203struct dsa_raw_completion_record {
204  uint64_t field[4];
205} __attribute__((packed));
206#endif
207