1/****************************************************************************
2 ****************************************************************************
3 ***
4 ***   This header was automatically generated from a Linux kernel header
5 ***   of the same name, to make information necessary for userspace to
6 ***   call into the kernel available to libc.  It contains only constants,
7 ***   structures, and macros generated from the original header, and thus,
8 ***   contains no copyrightable information.
9 ***
10 ***   To edit the content of this header, modify the corresponding
11 ***   source file (e.g. under external/kernel-headers/original/) then
12 ***   run bionic/libc/kernel/tools/update_all.py
13 ***
14 ***   Any manual change here will be lost the next time this script will
15 ***   be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __VMWGFX_DRM_H__
20#define __VMWGFX_DRM_H__
21#include "drm.h"
22#ifdef __cplusplus
23extern "C" {
24#endif
25#define DRM_VMW_MAX_SURFACE_FACES 6
26#define DRM_VMW_MAX_MIP_LEVELS 24
27#define DRM_VMW_GET_PARAM 0
28#define DRM_VMW_ALLOC_DMABUF 1
29#define DRM_VMW_ALLOC_BO 1
30#define DRM_VMW_UNREF_DMABUF 2
31#define DRM_VMW_HANDLE_CLOSE 2
32#define DRM_VMW_CURSOR_BYPASS 3
33#define DRM_VMW_CONTROL_STREAM 4
34#define DRM_VMW_CLAIM_STREAM 5
35#define DRM_VMW_UNREF_STREAM 6
36#define DRM_VMW_CREATE_CONTEXT 7
37#define DRM_VMW_UNREF_CONTEXT 8
38#define DRM_VMW_CREATE_SURFACE 9
39#define DRM_VMW_UNREF_SURFACE 10
40#define DRM_VMW_REF_SURFACE 11
41#define DRM_VMW_EXECBUF 12
42#define DRM_VMW_GET_3D_CAP 13
43#define DRM_VMW_FENCE_WAIT 14
44#define DRM_VMW_FENCE_SIGNALED 15
45#define DRM_VMW_FENCE_UNREF 16
46#define DRM_VMW_FENCE_EVENT 17
47#define DRM_VMW_PRESENT 18
48#define DRM_VMW_PRESENT_READBACK 19
49#define DRM_VMW_UPDATE_LAYOUT 20
50#define DRM_VMW_CREATE_SHADER 21
51#define DRM_VMW_UNREF_SHADER 22
52#define DRM_VMW_GB_SURFACE_CREATE 23
53#define DRM_VMW_GB_SURFACE_REF 24
54#define DRM_VMW_SYNCCPU 25
55#define DRM_VMW_CREATE_EXTENDED_CONTEXT 26
56#define DRM_VMW_GB_SURFACE_CREATE_EXT 27
57#define DRM_VMW_GB_SURFACE_REF_EXT 28
58#define DRM_VMW_MSG 29
59#define DRM_VMW_PARAM_NUM_STREAMS 0
60#define DRM_VMW_PARAM_NUM_FREE_STREAMS 1
61#define DRM_VMW_PARAM_3D 2
62#define DRM_VMW_PARAM_HW_CAPS 3
63#define DRM_VMW_PARAM_FIFO_CAPS 4
64#define DRM_VMW_PARAM_MAX_FB_SIZE 5
65#define DRM_VMW_PARAM_FIFO_HW_VERSION 6
66#define DRM_VMW_PARAM_MAX_SURF_MEMORY 7
67#define DRM_VMW_PARAM_3D_CAPS_SIZE 8
68#define DRM_VMW_PARAM_MAX_MOB_MEMORY 9
69#define DRM_VMW_PARAM_MAX_MOB_SIZE 10
70#define DRM_VMW_PARAM_SCREEN_TARGET 11
71#define DRM_VMW_PARAM_DX 12
72#define DRM_VMW_PARAM_HW_CAPS2 13
73#define DRM_VMW_PARAM_SM4_1 14
74#define DRM_VMW_PARAM_SM5 15
75enum drm_vmw_handle_type {
76  DRM_VMW_HANDLE_LEGACY = 0,
77  DRM_VMW_HANDLE_PRIME = 1
78};
79struct drm_vmw_getparam_arg {
80  __u64 value;
81  __u32 param;
82  __u32 pad64;
83};
84struct drm_vmw_context_arg {
85  __s32 cid;
86  __u32 pad64;
87};
88struct drm_vmw_surface_create_req {
89  __u32 flags;
90  __u32 format;
91  __u32 mip_levels[DRM_VMW_MAX_SURFACE_FACES];
92  __u64 size_addr;
93  __s32 shareable;
94  __s32 scanout;
95};
96struct drm_vmw_surface_arg {
97  __s32 sid;
98  enum drm_vmw_handle_type handle_type;
99};
100struct drm_vmw_size {
101  __u32 width;
102  __u32 height;
103  __u32 depth;
104  __u32 pad64;
105};
106union drm_vmw_surface_create_arg {
107  struct drm_vmw_surface_arg rep;
108  struct drm_vmw_surface_create_req req;
109};
110union drm_vmw_surface_reference_arg {
111  struct drm_vmw_surface_create_req rep;
112  struct drm_vmw_surface_arg req;
113};
114#define DRM_VMW_EXECBUF_VERSION 2
115#define DRM_VMW_EXECBUF_FLAG_IMPORT_FENCE_FD (1 << 0)
116#define DRM_VMW_EXECBUF_FLAG_EXPORT_FENCE_FD (1 << 1)
117struct drm_vmw_execbuf_arg {
118  __u64 commands;
119  __u32 command_size;
120  __u32 throttle_us;
121  __u64 fence_rep;
122  __u32 version;
123  __u32 flags;
124  __u32 context_handle;
125  __s32 imported_fence_fd;
126};
127struct drm_vmw_fence_rep {
128  __u32 handle;
129  __u32 mask;
130  __u32 seqno;
131  __u32 passed_seqno;
132  __s32 fd;
133  __s32 error;
134};
135struct drm_vmw_alloc_bo_req {
136  __u32 size;
137  __u32 pad64;
138};
139#define drm_vmw_alloc_dmabuf_req drm_vmw_alloc_bo_req
140struct drm_vmw_bo_rep {
141  __u64 map_handle;
142  __u32 handle;
143  __u32 cur_gmr_id;
144  __u32 cur_gmr_offset;
145  __u32 pad64;
146};
147#define drm_vmw_dmabuf_rep drm_vmw_bo_rep
148union drm_vmw_alloc_bo_arg {
149  struct drm_vmw_alloc_bo_req req;
150  struct drm_vmw_bo_rep rep;
151};
152#define drm_vmw_alloc_dmabuf_arg drm_vmw_alloc_bo_arg
153struct drm_vmw_rect {
154  __s32 x;
155  __s32 y;
156  __u32 w;
157  __u32 h;
158};
159struct drm_vmw_control_stream_arg {
160  __u32 stream_id;
161  __u32 enabled;
162  __u32 flags;
163  __u32 color_key;
164  __u32 handle;
165  __u32 offset;
166  __s32 format;
167  __u32 size;
168  __u32 width;
169  __u32 height;
170  __u32 pitch[3];
171  __u32 pad64;
172  struct drm_vmw_rect src;
173  struct drm_vmw_rect dst;
174};
175#define DRM_VMW_CURSOR_BYPASS_ALL (1 << 0)
176#define DRM_VMW_CURSOR_BYPASS_FLAGS (1)
177struct drm_vmw_cursor_bypass_arg {
178  __u32 flags;
179  __u32 crtc_id;
180  __s32 xpos;
181  __s32 ypos;
182  __s32 xhot;
183  __s32 yhot;
184};
185struct drm_vmw_stream_arg {
186  __u32 stream_id;
187  __u32 pad64;
188};
189struct drm_vmw_get_3d_cap_arg {
190  __u64 buffer;
191  __u32 max_size;
192  __u32 pad64;
193};
194#define DRM_VMW_FENCE_FLAG_EXEC (1 << 0)
195#define DRM_VMW_FENCE_FLAG_QUERY (1 << 1)
196#define DRM_VMW_WAIT_OPTION_UNREF (1 << 0)
197struct drm_vmw_fence_wait_arg {
198  __u32 handle;
199  __s32 cookie_valid;
200  __u64 kernel_cookie;
201  __u64 timeout_us;
202  __s32 lazy;
203  __s32 flags;
204  __s32 wait_options;
205  __s32 pad64;
206};
207struct drm_vmw_fence_signaled_arg {
208  __u32 handle;
209  __u32 flags;
210  __s32 signaled;
211  __u32 passed_seqno;
212  __u32 signaled_flags;
213  __u32 pad64;
214};
215struct drm_vmw_fence_arg {
216  __u32 handle;
217  __u32 pad64;
218};
219#define DRM_VMW_EVENT_FENCE_SIGNALED 0x80000000
220struct drm_vmw_event_fence {
221  struct drm_event base;
222  __u64 user_data;
223  __u32 tv_sec;
224  __u32 tv_usec;
225};
226#define DRM_VMW_FE_FLAG_REQ_TIME (1 << 0)
227struct drm_vmw_fence_event_arg {
228  __u64 fence_rep;
229  __u64 user_data;
230  __u32 handle;
231  __u32 flags;
232};
233struct drm_vmw_present_arg {
234  __u32 fb_id;
235  __u32 sid;
236  __s32 dest_x;
237  __s32 dest_y;
238  __u64 clips_ptr;
239  __u32 num_clips;
240  __u32 pad64;
241};
242struct drm_vmw_present_readback_arg {
243  __u32 fb_id;
244  __u32 num_clips;
245  __u64 clips_ptr;
246  __u64 fence_rep;
247};
248struct drm_vmw_update_layout_arg {
249  __u32 num_outputs;
250  __u32 pad64;
251  __u64 rects;
252};
253enum drm_vmw_shader_type {
254  drm_vmw_shader_type_vs = 0,
255  drm_vmw_shader_type_ps,
256};
257struct drm_vmw_shader_create_arg {
258  enum drm_vmw_shader_type shader_type;
259  __u32 size;
260  __u32 buffer_handle;
261  __u32 shader_handle;
262  __u64 offset;
263};
264struct drm_vmw_shader_arg {
265  __u32 handle;
266  __u32 pad64;
267};
268enum drm_vmw_surface_flags {
269  drm_vmw_surface_flag_shareable = (1 << 0),
270  drm_vmw_surface_flag_scanout = (1 << 1),
271  drm_vmw_surface_flag_create_buffer = (1 << 2),
272  drm_vmw_surface_flag_coherent = (1 << 3),
273};
274struct drm_vmw_gb_surface_create_req {
275  __u32 svga3d_flags;
276  __u32 format;
277  __u32 mip_levels;
278  enum drm_vmw_surface_flags drm_surface_flags;
279  __u32 multisample_count;
280  __u32 autogen_filter;
281  __u32 buffer_handle;
282  __u32 array_size;
283  struct drm_vmw_size base_size;
284};
285struct drm_vmw_gb_surface_create_rep {
286  __u32 handle;
287  __u32 backup_size;
288  __u32 buffer_handle;
289  __u32 buffer_size;
290  __u64 buffer_map_handle;
291};
292union drm_vmw_gb_surface_create_arg {
293  struct drm_vmw_gb_surface_create_rep rep;
294  struct drm_vmw_gb_surface_create_req req;
295};
296struct drm_vmw_gb_surface_ref_rep {
297  struct drm_vmw_gb_surface_create_req creq;
298  struct drm_vmw_gb_surface_create_rep crep;
299};
300union drm_vmw_gb_surface_reference_arg {
301  struct drm_vmw_gb_surface_ref_rep rep;
302  struct drm_vmw_surface_arg req;
303};
304enum drm_vmw_synccpu_flags {
305  drm_vmw_synccpu_read = (1 << 0),
306  drm_vmw_synccpu_write = (1 << 1),
307  drm_vmw_synccpu_dontblock = (1 << 2),
308  drm_vmw_synccpu_allow_cs = (1 << 3)
309};
310enum drm_vmw_synccpu_op {
311  drm_vmw_synccpu_grab,
312  drm_vmw_synccpu_release
313};
314struct drm_vmw_synccpu_arg {
315  enum drm_vmw_synccpu_op op;
316  enum drm_vmw_synccpu_flags flags;
317  __u32 handle;
318  __u32 pad64;
319};
320enum drm_vmw_extended_context {
321  drm_vmw_context_legacy,
322  drm_vmw_context_dx
323};
324union drm_vmw_extended_context_arg {
325  enum drm_vmw_extended_context req;
326  struct drm_vmw_context_arg rep;
327};
328struct drm_vmw_handle_close_arg {
329  __u32 handle;
330  __u32 pad64;
331};
332#define drm_vmw_unref_dmabuf_arg drm_vmw_handle_close_arg
333enum drm_vmw_surface_version {
334  drm_vmw_gb_surface_v1,
335};
336struct drm_vmw_gb_surface_create_ext_req {
337  struct drm_vmw_gb_surface_create_req base;
338  enum drm_vmw_surface_version version;
339  __u32 svga3d_flags_upper_32_bits;
340  __u32 multisample_pattern;
341  __u32 quality_level;
342  __u32 buffer_byte_stride;
343  __u32 must_be_zero;
344};
345union drm_vmw_gb_surface_create_ext_arg {
346  struct drm_vmw_gb_surface_create_rep rep;
347  struct drm_vmw_gb_surface_create_ext_req req;
348};
349struct drm_vmw_gb_surface_ref_ext_rep {
350  struct drm_vmw_gb_surface_create_ext_req creq;
351  struct drm_vmw_gb_surface_create_rep crep;
352};
353union drm_vmw_gb_surface_reference_ext_arg {
354  struct drm_vmw_gb_surface_ref_ext_rep rep;
355  struct drm_vmw_surface_arg req;
356};
357struct drm_vmw_msg_arg {
358  __u64 send;
359  __u64 receive;
360  __s32 send_only;
361  __u32 receive_len;
362};
363#ifdef __cplusplus
364}
365#endif
366#endif
367