1/****************************************************************************
2 ****************************************************************************
3 ***
4 ***   This header was automatically generated from a Linux kernel header
5 ***   of the same name, to make information necessary for userspace to
6 ***   call into the kernel available to libc.  It contains only constants,
7 ***   structures, and macros generated from the original header, and thus,
8 ***   contains no copyrightable information.
9 ***
10 ***   To edit the content of this header, modify the corresponding
11 ***   source file (e.g. under external/kernel-headers/original/) then
12 ***   run bionic/libc/kernel/tools/update_all.py
13 ***
14 ***   Any manual change here will be lost the next time this script will
15 ***   be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __ETNAVIV_DRM_H__
20#define __ETNAVIV_DRM_H__
21#include "drm.h"
22#ifdef __cplusplus
23extern "C" {
24#endif
25struct drm_etnaviv_timespec {
26  __s64 tv_sec;
27  __s64 tv_nsec;
28};
29#define ETNAVIV_PARAM_GPU_MODEL 0x01
30#define ETNAVIV_PARAM_GPU_REVISION 0x02
31#define ETNAVIV_PARAM_GPU_FEATURES_0 0x03
32#define ETNAVIV_PARAM_GPU_FEATURES_1 0x04
33#define ETNAVIV_PARAM_GPU_FEATURES_2 0x05
34#define ETNAVIV_PARAM_GPU_FEATURES_3 0x06
35#define ETNAVIV_PARAM_GPU_FEATURES_4 0x07
36#define ETNAVIV_PARAM_GPU_FEATURES_5 0x08
37#define ETNAVIV_PARAM_GPU_FEATURES_6 0x09
38#define ETNAVIV_PARAM_GPU_FEATURES_7 0x0a
39#define ETNAVIV_PARAM_GPU_FEATURES_8 0x0b
40#define ETNAVIV_PARAM_GPU_FEATURES_9 0x0c
41#define ETNAVIV_PARAM_GPU_FEATURES_10 0x0d
42#define ETNAVIV_PARAM_GPU_FEATURES_11 0x0e
43#define ETNAVIV_PARAM_GPU_FEATURES_12 0x0f
44#define ETNAVIV_PARAM_GPU_STREAM_COUNT 0x10
45#define ETNAVIV_PARAM_GPU_REGISTER_MAX 0x11
46#define ETNAVIV_PARAM_GPU_THREAD_COUNT 0x12
47#define ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE 0x13
48#define ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT 0x14
49#define ETNAVIV_PARAM_GPU_PIXEL_PIPES 0x15
50#define ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE 0x16
51#define ETNAVIV_PARAM_GPU_BUFFER_SIZE 0x17
52#define ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT 0x18
53#define ETNAVIV_PARAM_GPU_NUM_CONSTANTS 0x19
54#define ETNAVIV_PARAM_GPU_NUM_VARYINGS 0x1a
55#define ETNAVIV_PARAM_SOFTPIN_START_ADDR 0x1b
56#define ETNA_MAX_PIPES 4
57struct drm_etnaviv_param {
58  __u32 pipe;
59  __u32 param;
60  __u64 value;
61};
62#define ETNA_BO_CACHE_MASK 0x000f0000
63#define ETNA_BO_CACHED 0x00010000
64#define ETNA_BO_WC 0x00020000
65#define ETNA_BO_UNCACHED 0x00040000
66#define ETNA_BO_FORCE_MMU 0x00100000
67struct drm_etnaviv_gem_new {
68  __u64 size;
69  __u32 flags;
70  __u32 handle;
71};
72struct drm_etnaviv_gem_info {
73  __u32 handle;
74  __u32 pad;
75  __u64 offset;
76};
77#define ETNA_PREP_READ 0x01
78#define ETNA_PREP_WRITE 0x02
79#define ETNA_PREP_NOSYNC 0x04
80struct drm_etnaviv_gem_cpu_prep {
81  __u32 handle;
82  __u32 op;
83  struct drm_etnaviv_timespec timeout;
84};
85struct drm_etnaviv_gem_cpu_fini {
86  __u32 handle;
87  __u32 flags;
88};
89struct drm_etnaviv_gem_submit_reloc {
90  __u32 submit_offset;
91  __u32 reloc_idx;
92  __u64 reloc_offset;
93  __u32 flags;
94};
95#define ETNA_SUBMIT_BO_READ 0x0001
96#define ETNA_SUBMIT_BO_WRITE 0x0002
97struct drm_etnaviv_gem_submit_bo {
98  __u32 flags;
99  __u32 handle;
100  __u64 presumed;
101};
102#define ETNA_PM_PROCESS_PRE 0x0001
103#define ETNA_PM_PROCESS_POST 0x0002
104struct drm_etnaviv_gem_submit_pmr {
105  __u32 flags;
106  __u8 domain;
107  __u8 pad;
108  __u16 signal;
109  __u32 sequence;
110  __u32 read_offset;
111  __u32 read_idx;
112};
113#define ETNA_SUBMIT_NO_IMPLICIT 0x0001
114#define ETNA_SUBMIT_FENCE_FD_IN 0x0002
115#define ETNA_SUBMIT_FENCE_FD_OUT 0x0004
116#define ETNA_SUBMIT_SOFTPIN 0x0008
117#define ETNA_SUBMIT_FLAGS (ETNA_SUBMIT_NO_IMPLICIT | ETNA_SUBMIT_FENCE_FD_IN | ETNA_SUBMIT_FENCE_FD_OUT | ETNA_SUBMIT_SOFTPIN)
118#define ETNA_PIPE_3D 0x00
119#define ETNA_PIPE_2D 0x01
120#define ETNA_PIPE_VG 0x02
121struct drm_etnaviv_gem_submit {
122  __u32 fence;
123  __u32 pipe;
124  __u32 exec_state;
125  __u32 nr_bos;
126  __u32 nr_relocs;
127  __u32 stream_size;
128  __u64 bos;
129  __u64 relocs;
130  __u64 stream;
131  __u32 flags;
132  __s32 fence_fd;
133  __u64 pmrs;
134  __u32 nr_pmrs;
135  __u32 pad;
136};
137#define ETNA_WAIT_NONBLOCK 0x01
138struct drm_etnaviv_wait_fence {
139  __u32 pipe;
140  __u32 fence;
141  __u32 flags;
142  __u32 pad;
143  struct drm_etnaviv_timespec timeout;
144};
145#define ETNA_USERPTR_READ 0x01
146#define ETNA_USERPTR_WRITE 0x02
147struct drm_etnaviv_gem_userptr {
148  __u64 user_ptr;
149  __u64 user_size;
150  __u32 flags;
151  __u32 handle;
152};
153struct drm_etnaviv_gem_wait {
154  __u32 pipe;
155  __u32 handle;
156  __u32 flags;
157  __u32 pad;
158  struct drm_etnaviv_timespec timeout;
159};
160struct drm_etnaviv_pm_domain {
161  __u32 pipe;
162  __u8 iter;
163  __u8 id;
164  __u16 nr_signals;
165  char name[64];
166};
167struct drm_etnaviv_pm_signal {
168  __u32 pipe;
169  __u8 domain;
170  __u8 pad;
171  __u16 iter;
172  __u16 id;
173  char name[64];
174};
175#define DRM_ETNAVIV_GET_PARAM 0x00
176#define DRM_ETNAVIV_GEM_NEW 0x02
177#define DRM_ETNAVIV_GEM_INFO 0x03
178#define DRM_ETNAVIV_GEM_CPU_PREP 0x04
179#define DRM_ETNAVIV_GEM_CPU_FINI 0x05
180#define DRM_ETNAVIV_GEM_SUBMIT 0x06
181#define DRM_ETNAVIV_WAIT_FENCE 0x07
182#define DRM_ETNAVIV_GEM_USERPTR 0x08
183#define DRM_ETNAVIV_GEM_WAIT 0x09
184#define DRM_ETNAVIV_PM_QUERY_DOM 0x0a
185#define DRM_ETNAVIV_PM_QUERY_SIG 0x0b
186#define DRM_ETNAVIV_NUM_IOCTLS 0x0c
187#define DRM_IOCTL_ETNAVIV_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param)
188#define DRM_IOCTL_ETNAVIV_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new)
189#define DRM_IOCTL_ETNAVIV_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_INFO, struct drm_etnaviv_gem_info)
190#define DRM_IOCTL_ETNAVIV_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_PREP, struct drm_etnaviv_gem_cpu_prep)
191#define DRM_IOCTL_ETNAVIV_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_FINI, struct drm_etnaviv_gem_cpu_fini)
192#define DRM_IOCTL_ETNAVIV_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_SUBMIT, struct drm_etnaviv_gem_submit)
193#define DRM_IOCTL_ETNAVIV_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence)
194#define DRM_IOCTL_ETNAVIV_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr)
195#define DRM_IOCTL_ETNAVIV_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait)
196#define DRM_IOCTL_ETNAVIV_PM_QUERY_DOM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_DOM, struct drm_etnaviv_pm_domain)
197#define DRM_IOCTL_ETNAVIV_PM_QUERY_SIG DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_SIG, struct drm_etnaviv_pm_signal)
198#ifdef __cplusplus
199}
200#endif
201#endif
202