1/****************************************************************************
2 ****************************************************************************
3 ***
4 ***   This header was automatically generated from a Linux kernel header
5 ***   of the same name, to make information necessary for userspace to
6 ***   call into the kernel available to libc.  It contains only constants,
7 ***   structures, and macros generated from the original header, and thus,
8 ***   contains no copyrightable information.
9 ***
10 ***   To edit the content of this header, modify the corresponding
11 ***   source file (e.g. under external/kernel-headers/original/) then
12 ***   run bionic/libc/kernel/tools/update_all.py
13 ***
14 ***   Any manual change here will be lost the next time this script will
15 ***   be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _DRM_MODE_H
20#define _DRM_MODE_H
21#include "drm.h"
22#ifdef __cplusplus
23extern "C" {
24#endif
25#define DRM_CONNECTOR_NAME_LEN 32
26#define DRM_DISPLAY_MODE_LEN 32
27#define DRM_PROP_NAME_LEN 32
28#define DRM_MODE_TYPE_BUILTIN (1 << 0)
29#define DRM_MODE_TYPE_CLOCK_C ((1 << 1) | DRM_MODE_TYPE_BUILTIN)
30#define DRM_MODE_TYPE_CRTC_C ((1 << 2) | DRM_MODE_TYPE_BUILTIN)
31#define DRM_MODE_TYPE_PREFERRED (1 << 3)
32#define DRM_MODE_TYPE_DEFAULT (1 << 4)
33#define DRM_MODE_TYPE_USERDEF (1 << 5)
34#define DRM_MODE_TYPE_DRIVER (1 << 6)
35#define DRM_MODE_TYPE_ALL (DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_USERDEF | DRM_MODE_TYPE_DRIVER)
36#define DRM_MODE_FLAG_PHSYNC (1 << 0)
37#define DRM_MODE_FLAG_NHSYNC (1 << 1)
38#define DRM_MODE_FLAG_PVSYNC (1 << 2)
39#define DRM_MODE_FLAG_NVSYNC (1 << 3)
40#define DRM_MODE_FLAG_INTERLACE (1 << 4)
41#define DRM_MODE_FLAG_DBLSCAN (1 << 5)
42#define DRM_MODE_FLAG_CSYNC (1 << 6)
43#define DRM_MODE_FLAG_PCSYNC (1 << 7)
44#define DRM_MODE_FLAG_NCSYNC (1 << 8)
45#define DRM_MODE_FLAG_HSKEW (1 << 9)
46#define DRM_MODE_FLAG_BCAST (1 << 10)
47#define DRM_MODE_FLAG_PIXMUX (1 << 11)
48#define DRM_MODE_FLAG_DBLCLK (1 << 12)
49#define DRM_MODE_FLAG_CLKDIV2 (1 << 13)
50#define DRM_MODE_FLAG_3D_MASK (0x1f << 14)
51#define DRM_MODE_FLAG_3D_NONE (0 << 14)
52#define DRM_MODE_FLAG_3D_FRAME_PACKING (1 << 14)
53#define DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE (2 << 14)
54#define DRM_MODE_FLAG_3D_LINE_ALTERNATIVE (3 << 14)
55#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL (4 << 14)
56#define DRM_MODE_FLAG_3D_L_DEPTH (5 << 14)
57#define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6 << 14)
58#define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7 << 14)
59#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8 << 14)
60#define DRM_MODE_PICTURE_ASPECT_NONE 0
61#define DRM_MODE_PICTURE_ASPECT_4_3 1
62#define DRM_MODE_PICTURE_ASPECT_16_9 2
63#define DRM_MODE_PICTURE_ASPECT_64_27 3
64#define DRM_MODE_PICTURE_ASPECT_256_135 4
65#define DRM_MODE_CONTENT_TYPE_NO_DATA 0
66#define DRM_MODE_CONTENT_TYPE_GRAPHICS 1
67#define DRM_MODE_CONTENT_TYPE_PHOTO 2
68#define DRM_MODE_CONTENT_TYPE_CINEMA 3
69#define DRM_MODE_CONTENT_TYPE_GAME 4
70#define DRM_MODE_FLAG_PIC_AR_MASK (0x0F << 19)
71#define DRM_MODE_FLAG_PIC_AR_NONE (DRM_MODE_PICTURE_ASPECT_NONE << 19)
72#define DRM_MODE_FLAG_PIC_AR_4_3 (DRM_MODE_PICTURE_ASPECT_4_3 << 19)
73#define DRM_MODE_FLAG_PIC_AR_16_9 (DRM_MODE_PICTURE_ASPECT_16_9 << 19)
74#define DRM_MODE_FLAG_PIC_AR_64_27 (DRM_MODE_PICTURE_ASPECT_64_27 << 19)
75#define DRM_MODE_FLAG_PIC_AR_256_135 (DRM_MODE_PICTURE_ASPECT_256_135 << 19)
76#define DRM_MODE_FLAG_ALL (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLSCAN | DRM_MODE_FLAG_CSYNC | DRM_MODE_FLAG_PCSYNC | DRM_MODE_FLAG_NCSYNC | DRM_MODE_FLAG_HSKEW | DRM_MODE_FLAG_DBLCLK | DRM_MODE_FLAG_CLKDIV2 | DRM_MODE_FLAG_3D_MASK)
77#define DRM_MODE_DPMS_ON 0
78#define DRM_MODE_DPMS_STANDBY 1
79#define DRM_MODE_DPMS_SUSPEND 2
80#define DRM_MODE_DPMS_OFF 3
81#define DRM_MODE_SCALE_NONE 0
82#define DRM_MODE_SCALE_FULLSCREEN 1
83#define DRM_MODE_SCALE_CENTER 2
84#define DRM_MODE_SCALE_ASPECT 3
85#define DRM_MODE_DITHERING_OFF 0
86#define DRM_MODE_DITHERING_ON 1
87#define DRM_MODE_DITHERING_AUTO 2
88#define DRM_MODE_DIRTY_OFF 0
89#define DRM_MODE_DIRTY_ON 1
90#define DRM_MODE_DIRTY_ANNOTATE 2
91#define DRM_MODE_LINK_STATUS_GOOD 0
92#define DRM_MODE_LINK_STATUS_BAD 1
93#define DRM_MODE_ROTATE_0 (1 << 0)
94#define DRM_MODE_ROTATE_90 (1 << 1)
95#define DRM_MODE_ROTATE_180 (1 << 2)
96#define DRM_MODE_ROTATE_270 (1 << 3)
97#define DRM_MODE_ROTATE_MASK (DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270)
98#define DRM_MODE_REFLECT_X (1 << 4)
99#define DRM_MODE_REFLECT_Y (1 << 5)
100#define DRM_MODE_REFLECT_MASK (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y)
101#define DRM_MODE_CONTENT_PROTECTION_UNDESIRED 0
102#define DRM_MODE_CONTENT_PROTECTION_DESIRED 1
103#define DRM_MODE_CONTENT_PROTECTION_ENABLED 2
104struct drm_mode_modeinfo {
105  __u32 clock;
106  __u16 hdisplay;
107  __u16 hsync_start;
108  __u16 hsync_end;
109  __u16 htotal;
110  __u16 hskew;
111  __u16 vdisplay;
112  __u16 vsync_start;
113  __u16 vsync_end;
114  __u16 vtotal;
115  __u16 vscan;
116  __u32 vrefresh;
117  __u32 flags;
118  __u32 type;
119  char name[DRM_DISPLAY_MODE_LEN];
120};
121struct drm_mode_card_res {
122  __u64 fb_id_ptr;
123  __u64 crtc_id_ptr;
124  __u64 connector_id_ptr;
125  __u64 encoder_id_ptr;
126  __u32 count_fbs;
127  __u32 count_crtcs;
128  __u32 count_connectors;
129  __u32 count_encoders;
130  __u32 min_width;
131  __u32 max_width;
132  __u32 min_height;
133  __u32 max_height;
134};
135struct drm_mode_crtc {
136  __u64 set_connectors_ptr;
137  __u32 count_connectors;
138  __u32 crtc_id;
139  __u32 fb_id;
140  __u32 x;
141  __u32 y;
142  __u32 gamma_size;
143  __u32 mode_valid;
144  struct drm_mode_modeinfo mode;
145};
146#define DRM_MODE_PRESENT_TOP_FIELD (1 << 0)
147#define DRM_MODE_PRESENT_BOTTOM_FIELD (1 << 1)
148struct drm_mode_set_plane {
149  __u32 plane_id;
150  __u32 crtc_id;
151  __u32 fb_id;
152  __u32 flags;
153  __s32 crtc_x;
154  __s32 crtc_y;
155  __u32 crtc_w;
156  __u32 crtc_h;
157  __u32 src_x;
158  __u32 src_y;
159  __u32 src_h;
160  __u32 src_w;
161};
162struct drm_mode_get_plane {
163  __u32 plane_id;
164  __u32 crtc_id;
165  __u32 fb_id;
166  __u32 possible_crtcs;
167  __u32 gamma_size;
168  __u32 count_format_types;
169  __u64 format_type_ptr;
170};
171struct drm_mode_get_plane_res {
172  __u64 plane_id_ptr;
173  __u32 count_planes;
174};
175#define DRM_MODE_ENCODER_NONE 0
176#define DRM_MODE_ENCODER_DAC 1
177#define DRM_MODE_ENCODER_TMDS 2
178#define DRM_MODE_ENCODER_LVDS 3
179#define DRM_MODE_ENCODER_TVDAC 4
180#define DRM_MODE_ENCODER_VIRTUAL 5
181#define DRM_MODE_ENCODER_DSI 6
182#define DRM_MODE_ENCODER_DPMST 7
183#define DRM_MODE_ENCODER_DPI 8
184struct drm_mode_get_encoder {
185  __u32 encoder_id;
186  __u32 encoder_type;
187  __u32 crtc_id;
188  __u32 possible_crtcs;
189  __u32 possible_clones;
190};
191enum drm_mode_subconnector {
192  DRM_MODE_SUBCONNECTOR_Automatic = 0,
193  DRM_MODE_SUBCONNECTOR_Unknown = 0,
194  DRM_MODE_SUBCONNECTOR_VGA = 1,
195  DRM_MODE_SUBCONNECTOR_DVID = 3,
196  DRM_MODE_SUBCONNECTOR_DVIA = 4,
197  DRM_MODE_SUBCONNECTOR_Composite = 5,
198  DRM_MODE_SUBCONNECTOR_SVIDEO = 6,
199  DRM_MODE_SUBCONNECTOR_Component = 8,
200  DRM_MODE_SUBCONNECTOR_SCART = 9,
201  DRM_MODE_SUBCONNECTOR_DisplayPort = 10,
202  DRM_MODE_SUBCONNECTOR_HDMIA = 11,
203  DRM_MODE_SUBCONNECTOR_Native = 15,
204  DRM_MODE_SUBCONNECTOR_Wireless = 18,
205};
206#define DRM_MODE_CONNECTOR_Unknown 0
207#define DRM_MODE_CONNECTOR_VGA 1
208#define DRM_MODE_CONNECTOR_DVII 2
209#define DRM_MODE_CONNECTOR_DVID 3
210#define DRM_MODE_CONNECTOR_DVIA 4
211#define DRM_MODE_CONNECTOR_Composite 5
212#define DRM_MODE_CONNECTOR_SVIDEO 6
213#define DRM_MODE_CONNECTOR_LVDS 7
214#define DRM_MODE_CONNECTOR_Component 8
215#define DRM_MODE_CONNECTOR_9PinDIN 9
216#define DRM_MODE_CONNECTOR_DisplayPort 10
217#define DRM_MODE_CONNECTOR_HDMIA 11
218#define DRM_MODE_CONNECTOR_HDMIB 12
219#define DRM_MODE_CONNECTOR_TV 13
220#define DRM_MODE_CONNECTOR_eDP 14
221#define DRM_MODE_CONNECTOR_VIRTUAL 15
222#define DRM_MODE_CONNECTOR_DSI 16
223#define DRM_MODE_CONNECTOR_DPI 17
224#define DRM_MODE_CONNECTOR_WRITEBACK 18
225#define DRM_MODE_CONNECTOR_SPI 19
226struct drm_mode_get_connector {
227  __u64 encoders_ptr;
228  __u64 modes_ptr;
229  __u64 props_ptr;
230  __u64 prop_values_ptr;
231  __u32 count_modes;
232  __u32 count_props;
233  __u32 count_encoders;
234  __u32 encoder_id;
235  __u32 connector_id;
236  __u32 connector_type;
237  __u32 connector_type_id;
238  __u32 connection;
239  __u32 mm_width;
240  __u32 mm_height;
241  __u32 subpixel;
242  __u32 pad;
243};
244#define DRM_MODE_PROP_PENDING (1 << 0)
245#define DRM_MODE_PROP_RANGE (1 << 1)
246#define DRM_MODE_PROP_IMMUTABLE (1 << 2)
247#define DRM_MODE_PROP_ENUM (1 << 3)
248#define DRM_MODE_PROP_BLOB (1 << 4)
249#define DRM_MODE_PROP_BITMASK (1 << 5)
250#define DRM_MODE_PROP_LEGACY_TYPE (DRM_MODE_PROP_RANGE | DRM_MODE_PROP_ENUM | DRM_MODE_PROP_BLOB | DRM_MODE_PROP_BITMASK)
251#define DRM_MODE_PROP_EXTENDED_TYPE 0x0000ffc0
252#define DRM_MODE_PROP_TYPE(n) ((n) << 6)
253#define DRM_MODE_PROP_OBJECT DRM_MODE_PROP_TYPE(1)
254#define DRM_MODE_PROP_SIGNED_RANGE DRM_MODE_PROP_TYPE(2)
255#define DRM_MODE_PROP_ATOMIC 0x80000000
256struct drm_mode_property_enum {
257  __u64 value;
258  char name[DRM_PROP_NAME_LEN];
259};
260struct drm_mode_get_property {
261  __u64 values_ptr;
262  __u64 enum_blob_ptr;
263  __u32 prop_id;
264  __u32 flags;
265  char name[DRM_PROP_NAME_LEN];
266  __u32 count_values;
267  __u32 count_enum_blobs;
268};
269struct drm_mode_connector_set_property {
270  __u64 value;
271  __u32 prop_id;
272  __u32 connector_id;
273};
274#define DRM_MODE_OBJECT_CRTC 0xcccccccc
275#define DRM_MODE_OBJECT_CONNECTOR 0xc0c0c0c0
276#define DRM_MODE_OBJECT_ENCODER 0xe0e0e0e0
277#define DRM_MODE_OBJECT_MODE 0xdededede
278#define DRM_MODE_OBJECT_PROPERTY 0xb0b0b0b0
279#define DRM_MODE_OBJECT_FB 0xfbfbfbfb
280#define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb
281#define DRM_MODE_OBJECT_PLANE 0xeeeeeeee
282#define DRM_MODE_OBJECT_ANY 0
283struct drm_mode_obj_get_properties {
284  __u64 props_ptr;
285  __u64 prop_values_ptr;
286  __u32 count_props;
287  __u32 obj_id;
288  __u32 obj_type;
289};
290struct drm_mode_obj_set_property {
291  __u64 value;
292  __u32 prop_id;
293  __u32 obj_id;
294  __u32 obj_type;
295};
296struct drm_mode_get_blob {
297  __u32 blob_id;
298  __u32 length;
299  __u64 data;
300};
301struct drm_mode_fb_cmd {
302  __u32 fb_id;
303  __u32 width;
304  __u32 height;
305  __u32 pitch;
306  __u32 bpp;
307  __u32 depth;
308  __u32 handle;
309};
310#define DRM_MODE_FB_INTERLACED (1 << 0)
311#define DRM_MODE_FB_MODIFIERS (1 << 1)
312struct drm_mode_fb_cmd2 {
313  __u32 fb_id;
314  __u32 width;
315  __u32 height;
316  __u32 pixel_format;
317  __u32 flags;
318  __u32 handles[4];
319  __u32 pitches[4];
320  __u32 offsets[4];
321  __u64 modifier[4];
322};
323#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
324#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
325#define DRM_MODE_FB_DIRTY_FLAGS 0x03
326#define DRM_MODE_FB_DIRTY_MAX_CLIPS 256
327struct drm_mode_fb_dirty_cmd {
328  __u32 fb_id;
329  __u32 flags;
330  __u32 color;
331  __u32 num_clips;
332  __u64 clips_ptr;
333};
334struct drm_mode_mode_cmd {
335  __u32 connector_id;
336  struct drm_mode_modeinfo mode;
337};
338#define DRM_MODE_CURSOR_BO 0x01
339#define DRM_MODE_CURSOR_MOVE 0x02
340#define DRM_MODE_CURSOR_FLAGS 0x03
341struct drm_mode_cursor {
342  __u32 flags;
343  __u32 crtc_id;
344  __s32 x;
345  __s32 y;
346  __u32 width;
347  __u32 height;
348  __u32 handle;
349};
350struct drm_mode_cursor2 {
351  __u32 flags;
352  __u32 crtc_id;
353  __s32 x;
354  __s32 y;
355  __u32 width;
356  __u32 height;
357  __u32 handle;
358  __s32 hot_x;
359  __s32 hot_y;
360};
361struct drm_mode_crtc_lut {
362  __u32 crtc_id;
363  __u32 gamma_size;
364  __u64 red;
365  __u64 green;
366  __u64 blue;
367};
368struct drm_color_ctm {
369  __u64 matrix[9];
370};
371struct drm_color_lut {
372  __u16 red;
373  __u16 green;
374  __u16 blue;
375  __u16 reserved;
376};
377struct hdr_metadata_infoframe {
378  __u8 eotf;
379  __u8 metadata_type;
380  struct {
381    __u16 x, y;
382  } display_primaries[3];
383  struct {
384    __u16 x, y;
385  } white_point;
386  __u16 max_display_mastering_luminance;
387  __u16 min_display_mastering_luminance;
388  __u16 max_cll;
389  __u16 max_fall;
390};
391struct hdr_output_metadata {
392  __u32 metadata_type;
393  union {
394    struct hdr_metadata_infoframe hdmi_metadata_type1;
395  };
396};
397#define DRM_MODE_PAGE_FLIP_EVENT 0x01
398#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
399#define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
400#define DRM_MODE_PAGE_FLIP_TARGET_RELATIVE 0x8
401#define DRM_MODE_PAGE_FLIP_TARGET (DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE | DRM_MODE_PAGE_FLIP_TARGET_RELATIVE)
402#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_PAGE_FLIP_ASYNC | DRM_MODE_PAGE_FLIP_TARGET)
403struct drm_mode_crtc_page_flip {
404  __u32 crtc_id;
405  __u32 fb_id;
406  __u32 flags;
407  __u32 reserved;
408  __u64 user_data;
409};
410struct drm_mode_crtc_page_flip_target {
411  __u32 crtc_id;
412  __u32 fb_id;
413  __u32 flags;
414  __u32 sequence;
415  __u64 user_data;
416};
417struct drm_mode_create_dumb {
418  __u32 height;
419  __u32 width;
420  __u32 bpp;
421  __u32 flags;
422  __u32 handle;
423  __u32 pitch;
424  __u64 size;
425};
426struct drm_mode_map_dumb {
427  __u32 handle;
428  __u32 pad;
429  __u64 offset;
430};
431struct drm_mode_destroy_dumb {
432  __u32 handle;
433};
434#define DRM_MODE_ATOMIC_TEST_ONLY 0x0100
435#define DRM_MODE_ATOMIC_NONBLOCK 0x0200
436#define DRM_MODE_ATOMIC_ALLOW_MODESET 0x0400
437#define DRM_MODE_ATOMIC_FLAGS (DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_PAGE_FLIP_ASYNC | DRM_MODE_ATOMIC_TEST_ONLY | DRM_MODE_ATOMIC_NONBLOCK | DRM_MODE_ATOMIC_ALLOW_MODESET)
438struct drm_mode_atomic {
439  __u32 flags;
440  __u32 count_objs;
441  __u64 objs_ptr;
442  __u64 count_props_ptr;
443  __u64 props_ptr;
444  __u64 prop_values_ptr;
445  __u64 reserved;
446  __u64 user_data;
447};
448struct drm_format_modifier_blob {
449#define FORMAT_BLOB_CURRENT 1
450  __u32 version;
451  __u32 flags;
452  __u32 count_formats;
453  __u32 formats_offset;
454  __u32 count_modifiers;
455  __u32 modifiers_offset;
456};
457struct drm_format_modifier {
458  __u64 formats;
459  __u32 offset;
460  __u32 pad;
461  __u64 modifier;
462};
463struct drm_mode_create_blob {
464  __u64 data;
465  __u32 length;
466  __u32 blob_id;
467};
468struct drm_mode_destroy_blob {
469  __u32 blob_id;
470};
471struct drm_mode_create_lease {
472  __u64 object_ids;
473  __u32 object_count;
474  __u32 flags;
475  __u32 lessee_id;
476  __u32 fd;
477};
478struct drm_mode_list_lessees {
479  __u32 count_lessees;
480  __u32 pad;
481  __u64 lessees_ptr;
482};
483struct drm_mode_get_lease {
484  __u32 count_objects;
485  __u32 pad;
486  __u64 objects_ptr;
487};
488struct drm_mode_revoke_lease {
489  __u32 lessee_id;
490};
491struct drm_mode_rect {
492  __s32 x1;
493  __s32 y1;
494  __s32 x2;
495  __s32 y2;
496};
497#ifdef __cplusplus
498}
499#endif
500#endif
501