1/****************************************************************************
2 ****************************************************************************
3 ***
4 ***   This header was automatically generated from a Linux kernel header
5 ***   of the same name, to make information necessary for userspace to
6 ***   call into the kernel available to libc.  It contains only constants,
7 ***   structures, and macros generated from the original header, and thus,
8 ***   contains no copyrightable information.
9 ***
10 ***   To edit the content of this header, modify the corresponding
11 ***   source file (e.g. under external/kernel-headers/original/) then
12 ***   run bionic/libc/kernel/tools/update_all.py
13 ***
14 ***   Any manual change here will be lost the next time this script will
15 ***   be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __AMDGPU_DRM_H__
20#define __AMDGPU_DRM_H__
21#include "drm.h"
22#ifdef __cplusplus
23extern "C" {
24#endif
25#define DRM_AMDGPU_GEM_CREATE 0x00
26#define DRM_AMDGPU_GEM_MMAP 0x01
27#define DRM_AMDGPU_CTX 0x02
28#define DRM_AMDGPU_BO_LIST 0x03
29#define DRM_AMDGPU_CS 0x04
30#define DRM_AMDGPU_INFO 0x05
31#define DRM_AMDGPU_GEM_METADATA 0x06
32#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07
33#define DRM_AMDGPU_GEM_VA 0x08
34#define DRM_AMDGPU_WAIT_CS 0x09
35#define DRM_AMDGPU_GEM_OP 0x10
36#define DRM_AMDGPU_GEM_USERPTR 0x11
37#define DRM_AMDGPU_WAIT_FENCES 0x12
38#define DRM_AMDGPU_VM 0x13
39#define DRM_AMDGPU_FENCE_TO_HANDLE 0x14
40#define DRM_AMDGPU_SCHED 0x15
41#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
42#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
43#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
44#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
45#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
46#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
47#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
48#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
49#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
50#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
51#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
52#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
53#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
54#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
55#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
56#define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
57#define AMDGPU_GEM_DOMAIN_CPU 0x1
58#define AMDGPU_GEM_DOMAIN_GTT 0x2
59#define AMDGPU_GEM_DOMAIN_VRAM 0x4
60#define AMDGPU_GEM_DOMAIN_GDS 0x8
61#define AMDGPU_GEM_DOMAIN_GWS 0x10
62#define AMDGPU_GEM_DOMAIN_OA 0x20
63#define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)
64#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
65#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)
66#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
67#define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)
68#define AMDGPU_GEM_CREATE_SHADOW (1 << 4)
69#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
70#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
71#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7)
72#define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8)
73#define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9)
74#define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10)
75struct drm_amdgpu_gem_create_in {
76  __u64 bo_size;
77  __u64 alignment;
78  __u64 domains;
79  __u64 domain_flags;
80};
81struct drm_amdgpu_gem_create_out {
82  __u32 handle;
83  __u32 _pad;
84};
85union drm_amdgpu_gem_create {
86  struct drm_amdgpu_gem_create_in in;
87  struct drm_amdgpu_gem_create_out out;
88};
89#define AMDGPU_BO_LIST_OP_CREATE 0
90#define AMDGPU_BO_LIST_OP_DESTROY 1
91#define AMDGPU_BO_LIST_OP_UPDATE 2
92struct drm_amdgpu_bo_list_in {
93  __u32 operation;
94  __u32 list_handle;
95  __u32 bo_number;
96  __u32 bo_info_size;
97  __u64 bo_info_ptr;
98};
99struct drm_amdgpu_bo_list_entry {
100  __u32 bo_handle;
101  __u32 bo_priority;
102};
103struct drm_amdgpu_bo_list_out {
104  __u32 list_handle;
105  __u32 _pad;
106};
107union drm_amdgpu_bo_list {
108  struct drm_amdgpu_bo_list_in in;
109  struct drm_amdgpu_bo_list_out out;
110};
111#define AMDGPU_CTX_OP_ALLOC_CTX 1
112#define AMDGPU_CTX_OP_FREE_CTX 2
113#define AMDGPU_CTX_OP_QUERY_STATE 3
114#define AMDGPU_CTX_OP_QUERY_STATE2 4
115#define AMDGPU_CTX_NO_RESET 0
116#define AMDGPU_CTX_GUILTY_RESET 1
117#define AMDGPU_CTX_INNOCENT_RESET 2
118#define AMDGPU_CTX_UNKNOWN_RESET 3
119#define AMDGPU_CTX_QUERY2_FLAGS_RESET (1 << 0)
120#define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1 << 1)
121#define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1 << 2)
122#define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1 << 3)
123#define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1 << 4)
124#define AMDGPU_CTX_PRIORITY_UNSET - 2048
125#define AMDGPU_CTX_PRIORITY_VERY_LOW - 1023
126#define AMDGPU_CTX_PRIORITY_LOW - 512
127#define AMDGPU_CTX_PRIORITY_NORMAL 0
128#define AMDGPU_CTX_PRIORITY_HIGH 512
129#define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023
130struct drm_amdgpu_ctx_in {
131  __u32 op;
132  __u32 flags;
133  __u32 ctx_id;
134  __s32 priority;
135};
136union drm_amdgpu_ctx_out {
137  struct {
138    __u32 ctx_id;
139    __u32 _pad;
140  } alloc;
141  struct {
142    __u64 flags;
143    __u32 hangs;
144    __u32 reset_status;
145  } state;
146};
147union drm_amdgpu_ctx {
148  struct drm_amdgpu_ctx_in in;
149  union drm_amdgpu_ctx_out out;
150};
151#define AMDGPU_VM_OP_RESERVE_VMID 1
152#define AMDGPU_VM_OP_UNRESERVE_VMID 2
153struct drm_amdgpu_vm_in {
154  __u32 op;
155  __u32 flags;
156};
157struct drm_amdgpu_vm_out {
158  __u64 flags;
159};
160union drm_amdgpu_vm {
161  struct drm_amdgpu_vm_in in;
162  struct drm_amdgpu_vm_out out;
163};
164#define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1
165#define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2
166struct drm_amdgpu_sched_in {
167  __u32 op;
168  __u32 fd;
169  __s32 priority;
170  __u32 ctx_id;
171};
172union drm_amdgpu_sched {
173  struct drm_amdgpu_sched_in in;
174};
175#define AMDGPU_GEM_USERPTR_READONLY (1 << 0)
176#define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1)
177#define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2)
178#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3)
179struct drm_amdgpu_gem_userptr {
180  __u64 addr;
181  __u64 size;
182  __u32 flags;
183  __u32 handle;
184};
185#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0
186#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf
187#define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4
188#define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f
189#define AMDGPU_TILING_TILE_SPLIT_SHIFT 9
190#define AMDGPU_TILING_TILE_SPLIT_MASK 0x7
191#define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12
192#define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7
193#define AMDGPU_TILING_BANK_WIDTH_SHIFT 15
194#define AMDGPU_TILING_BANK_WIDTH_MASK 0x3
195#define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17
196#define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3
197#define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19
198#define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3
199#define AMDGPU_TILING_NUM_BANKS_SHIFT 21
200#define AMDGPU_TILING_NUM_BANKS_MASK 0x3
201#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0
202#define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f
203#define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5
204#define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF
205#define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29
206#define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF
207#define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43
208#define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1
209#define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44
210#define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1
211#define AMDGPU_TILING_SCANOUT_SHIFT 63
212#define AMDGPU_TILING_SCANOUT_MASK 0x1
213#define AMDGPU_TILING_SET(field,value) (((__u64) (value) & AMDGPU_TILING_ ##field ##_MASK) << AMDGPU_TILING_ ##field ##_SHIFT)
214#define AMDGPU_TILING_GET(value,field) (((__u64) (value) >> AMDGPU_TILING_ ##field ##_SHIFT) & AMDGPU_TILING_ ##field ##_MASK)
215#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1
216#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2
217struct drm_amdgpu_gem_metadata {
218  __u32 handle;
219  __u32 op;
220  struct {
221    __u64 flags;
222    __u64 tiling_info;
223    __u32 data_size_bytes;
224    __u32 data[64];
225  } data;
226};
227struct drm_amdgpu_gem_mmap_in {
228  __u32 handle;
229  __u32 _pad;
230};
231struct drm_amdgpu_gem_mmap_out {
232  __u64 addr_ptr;
233};
234union drm_amdgpu_gem_mmap {
235  struct drm_amdgpu_gem_mmap_in in;
236  struct drm_amdgpu_gem_mmap_out out;
237};
238struct drm_amdgpu_gem_wait_idle_in {
239  __u32 handle;
240  __u32 flags;
241  __u64 timeout;
242};
243struct drm_amdgpu_gem_wait_idle_out {
244  __u32 status;
245  __u32 domain;
246};
247union drm_amdgpu_gem_wait_idle {
248  struct drm_amdgpu_gem_wait_idle_in in;
249  struct drm_amdgpu_gem_wait_idle_out out;
250};
251struct drm_amdgpu_wait_cs_in {
252  __u64 handle;
253  __u64 timeout;
254  __u32 ip_type;
255  __u32 ip_instance;
256  __u32 ring;
257  __u32 ctx_id;
258};
259struct drm_amdgpu_wait_cs_out {
260  __u64 status;
261};
262union drm_amdgpu_wait_cs {
263  struct drm_amdgpu_wait_cs_in in;
264  struct drm_amdgpu_wait_cs_out out;
265};
266struct drm_amdgpu_fence {
267  __u32 ctx_id;
268  __u32 ip_type;
269  __u32 ip_instance;
270  __u32 ring;
271  __u64 seq_no;
272};
273struct drm_amdgpu_wait_fences_in {
274  __u64 fences;
275  __u32 fence_count;
276  __u32 wait_all;
277  __u64 timeout_ns;
278};
279struct drm_amdgpu_wait_fences_out {
280  __u32 status;
281  __u32 first_signaled;
282};
283union drm_amdgpu_wait_fences {
284  struct drm_amdgpu_wait_fences_in in;
285  struct drm_amdgpu_wait_fences_out out;
286};
287#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
288#define AMDGPU_GEM_OP_SET_PLACEMENT 1
289struct drm_amdgpu_gem_op {
290  __u32 handle;
291  __u32 op;
292  __u64 value;
293};
294#define AMDGPU_VA_OP_MAP 1
295#define AMDGPU_VA_OP_UNMAP 2
296#define AMDGPU_VA_OP_CLEAR 3
297#define AMDGPU_VA_OP_REPLACE 4
298#define AMDGPU_VM_DELAY_UPDATE (1 << 0)
299#define AMDGPU_VM_PAGE_READABLE (1 << 1)
300#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2)
301#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)
302#define AMDGPU_VM_PAGE_PRT (1 << 4)
303#define AMDGPU_VM_MTYPE_MASK (0xf << 5)
304#define AMDGPU_VM_MTYPE_DEFAULT (0 << 5)
305#define AMDGPU_VM_MTYPE_NC (1 << 5)
306#define AMDGPU_VM_MTYPE_WC (2 << 5)
307#define AMDGPU_VM_MTYPE_CC (3 << 5)
308#define AMDGPU_VM_MTYPE_UC (4 << 5)
309#define AMDGPU_VM_MTYPE_RW (5 << 5)
310struct drm_amdgpu_gem_va {
311  __u32 handle;
312  __u32 _pad;
313  __u32 operation;
314  __u32 flags;
315  __u64 va_address;
316  __u64 offset_in_bo;
317  __u64 map_size;
318};
319#define AMDGPU_HW_IP_GFX 0
320#define AMDGPU_HW_IP_COMPUTE 1
321#define AMDGPU_HW_IP_DMA 2
322#define AMDGPU_HW_IP_UVD 3
323#define AMDGPU_HW_IP_VCE 4
324#define AMDGPU_HW_IP_UVD_ENC 5
325#define AMDGPU_HW_IP_VCN_DEC 6
326#define AMDGPU_HW_IP_VCN_ENC 7
327#define AMDGPU_HW_IP_VCN_JPEG 8
328#define AMDGPU_HW_IP_NUM 9
329#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
330#define AMDGPU_CHUNK_ID_IB 0x01
331#define AMDGPU_CHUNK_ID_FENCE 0x02
332#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
333#define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04
334#define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05
335#define AMDGPU_CHUNK_ID_BO_HANDLES 0x06
336#define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07
337#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08
338#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09
339struct drm_amdgpu_cs_chunk {
340  __u32 chunk_id;
341  __u32 length_dw;
342  __u64 chunk_data;
343};
344struct drm_amdgpu_cs_in {
345  __u32 ctx_id;
346  __u32 bo_list_handle;
347  __u32 num_chunks;
348  __u32 flags;
349  __u64 chunks;
350};
351struct drm_amdgpu_cs_out {
352  __u64 handle;
353};
354union drm_amdgpu_cs {
355  struct drm_amdgpu_cs_in in;
356  struct drm_amdgpu_cs_out out;
357};
358#define AMDGPU_IB_FLAG_CE (1 << 0)
359#define AMDGPU_IB_FLAG_PREAMBLE (1 << 1)
360#define AMDGPU_IB_FLAG_PREEMPT (1 << 2)
361#define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
362#define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4)
363#define AMDGPU_IB_FLAGS_SECURE (1 << 5)
364#define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6)
365struct drm_amdgpu_cs_chunk_ib {
366  __u32 _pad;
367  __u32 flags;
368  __u64 va_start;
369  __u32 ib_bytes;
370  __u32 ip_type;
371  __u32 ip_instance;
372  __u32 ring;
373};
374struct drm_amdgpu_cs_chunk_dep {
375  __u32 ip_type;
376  __u32 ip_instance;
377  __u32 ring;
378  __u32 ctx_id;
379  __u64 handle;
380};
381struct drm_amdgpu_cs_chunk_fence {
382  __u32 handle;
383  __u32 offset;
384};
385struct drm_amdgpu_cs_chunk_sem {
386  __u32 handle;
387};
388struct drm_amdgpu_cs_chunk_syncobj {
389  __u32 handle;
390  __u32 flags;
391  __u64 point;
392};
393#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0
394#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1
395#define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2
396union drm_amdgpu_fence_to_handle {
397  struct {
398    struct drm_amdgpu_fence fence;
399    __u32 what;
400    __u32 pad;
401  } in;
402  struct {
403    __u32 handle;
404  } out;
405};
406struct drm_amdgpu_cs_chunk_data {
407  union {
408    struct drm_amdgpu_cs_chunk_ib ib_data;
409    struct drm_amdgpu_cs_chunk_fence fence_data;
410  };
411};
412#define AMDGPU_IDS_FLAGS_FUSION 0x1
413#define AMDGPU_IDS_FLAGS_PREEMPTION 0x2
414#define AMDGPU_IDS_FLAGS_TMZ 0x4
415#define AMDGPU_INFO_ACCEL_WORKING 0x00
416#define AMDGPU_INFO_CRTC_FROM_ID 0x01
417#define AMDGPU_INFO_HW_IP_INFO 0x02
418#define AMDGPU_INFO_HW_IP_COUNT 0x03
419#define AMDGPU_INFO_TIMESTAMP 0x05
420#define AMDGPU_INFO_FW_VERSION 0x0e
421#define AMDGPU_INFO_FW_VCE 0x1
422#define AMDGPU_INFO_FW_UVD 0x2
423#define AMDGPU_INFO_FW_GMC 0x03
424#define AMDGPU_INFO_FW_GFX_ME 0x04
425#define AMDGPU_INFO_FW_GFX_PFP 0x05
426#define AMDGPU_INFO_FW_GFX_CE 0x06
427#define AMDGPU_INFO_FW_GFX_RLC 0x07
428#define AMDGPU_INFO_FW_GFX_MEC 0x08
429#define AMDGPU_INFO_FW_SMC 0x0a
430#define AMDGPU_INFO_FW_SDMA 0x0b
431#define AMDGPU_INFO_FW_SOS 0x0c
432#define AMDGPU_INFO_FW_ASD 0x0d
433#define AMDGPU_INFO_FW_VCN 0x0e
434#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f
435#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10
436#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11
437#define AMDGPU_INFO_FW_DMCU 0x12
438#define AMDGPU_INFO_FW_TA 0x13
439#define AMDGPU_INFO_FW_DMCUB 0x14
440#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
441#define AMDGPU_INFO_VRAM_USAGE 0x10
442#define AMDGPU_INFO_GTT_USAGE 0x11
443#define AMDGPU_INFO_GDS_CONFIG 0x13
444#define AMDGPU_INFO_VRAM_GTT 0x14
445#define AMDGPU_INFO_READ_MMR_REG 0x15
446#define AMDGPU_INFO_DEV_INFO 0x16
447#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17
448#define AMDGPU_INFO_NUM_EVICTIONS 0x18
449#define AMDGPU_INFO_MEMORY 0x19
450#define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A
451#define AMDGPU_INFO_VBIOS 0x1B
452#define AMDGPU_INFO_VBIOS_SIZE 0x1
453#define AMDGPU_INFO_VBIOS_IMAGE 0x2
454#define AMDGPU_INFO_NUM_HANDLES 0x1C
455#define AMDGPU_INFO_SENSOR 0x1D
456#define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1
457#define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2
458#define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3
459#define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4
460#define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5
461#define AMDGPU_INFO_SENSOR_VDDNB 0x6
462#define AMDGPU_INFO_SENSOR_VDDGFX 0x7
463#define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8
464#define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9
465#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
466#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
467#define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20
468#define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0)
469#define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1)
470#define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2)
471#define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3)
472#define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4)
473#define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5)
474#define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6)
475#define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7)
476#define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8)
477#define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9)
478#define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10)
479#define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11)
480#define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12)
481#define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13)
482#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
483#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
484#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8
485#define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff
486struct drm_amdgpu_query_fw {
487  __u32 fw_type;
488  __u32 ip_instance;
489  __u32 index;
490  __u32 _pad;
491};
492struct drm_amdgpu_info {
493  __u64 return_pointer;
494  __u32 return_size;
495  __u32 query;
496  union {
497    struct {
498      __u32 id;
499      __u32 _pad;
500    } mode_crtc;
501    struct {
502      __u32 type;
503      __u32 ip_instance;
504    } query_hw_ip;
505    struct {
506      __u32 dword_offset;
507      __u32 count;
508      __u32 instance;
509      __u32 flags;
510    } read_mmr_reg;
511    struct drm_amdgpu_query_fw query_fw;
512    struct {
513      __u32 type;
514      __u32 offset;
515    } vbios_info;
516    struct {
517      __u32 type;
518    } sensor_info;
519  };
520};
521struct drm_amdgpu_info_gds {
522  __u32 gds_gfx_partition_size;
523  __u32 compute_partition_size;
524  __u32 gds_total_size;
525  __u32 gws_per_gfx_partition;
526  __u32 gws_per_compute_partition;
527  __u32 oa_per_gfx_partition;
528  __u32 oa_per_compute_partition;
529  __u32 _pad;
530};
531struct drm_amdgpu_info_vram_gtt {
532  __u64 vram_size;
533  __u64 vram_cpu_accessible_size;
534  __u64 gtt_size;
535};
536struct drm_amdgpu_heap_info {
537  __u64 total_heap_size;
538  __u64 usable_heap_size;
539  __u64 heap_usage;
540  __u64 max_allocation;
541};
542struct drm_amdgpu_memory_info {
543  struct drm_amdgpu_heap_info vram;
544  struct drm_amdgpu_heap_info cpu_accessible_vram;
545  struct drm_amdgpu_heap_info gtt;
546};
547struct drm_amdgpu_info_firmware {
548  __u32 ver;
549  __u32 feature;
550};
551#define AMDGPU_VRAM_TYPE_UNKNOWN 0
552#define AMDGPU_VRAM_TYPE_GDDR1 1
553#define AMDGPU_VRAM_TYPE_DDR2 2
554#define AMDGPU_VRAM_TYPE_GDDR3 3
555#define AMDGPU_VRAM_TYPE_GDDR4 4
556#define AMDGPU_VRAM_TYPE_GDDR5 5
557#define AMDGPU_VRAM_TYPE_HBM 6
558#define AMDGPU_VRAM_TYPE_DDR3 7
559#define AMDGPU_VRAM_TYPE_DDR4 8
560#define AMDGPU_VRAM_TYPE_GDDR6 9
561struct drm_amdgpu_info_device {
562  __u32 device_id;
563  __u32 chip_rev;
564  __u32 external_rev;
565  __u32 pci_rev;
566  __u32 family;
567  __u32 num_shader_engines;
568  __u32 num_shader_arrays_per_engine;
569  __u32 gpu_counter_freq;
570  __u64 max_engine_clock;
571  __u64 max_memory_clock;
572  __u32 cu_active_number;
573  __u32 cu_ao_mask;
574  __u32 cu_bitmap[4][4];
575  __u32 enabled_rb_pipes_mask;
576  __u32 num_rb_pipes;
577  __u32 num_hw_gfx_contexts;
578  __u32 _pad;
579  __u64 ids_flags;
580  __u64 virtual_address_offset;
581  __u64 virtual_address_max;
582  __u32 virtual_address_alignment;
583  __u32 pte_fragment_size;
584  __u32 gart_page_size;
585  __u32 ce_ram_size;
586  __u32 vram_type;
587  __u32 vram_bit_width;
588  __u32 vce_harvest_config;
589  __u32 gc_double_offchip_lds_buf;
590  __u64 prim_buf_gpu_addr;
591  __u64 pos_buf_gpu_addr;
592  __u64 cntl_sb_buf_gpu_addr;
593  __u64 param_buf_gpu_addr;
594  __u32 prim_buf_size;
595  __u32 pos_buf_size;
596  __u32 cntl_sb_buf_size;
597  __u32 param_buf_size;
598  __u32 wave_front_size;
599  __u32 num_shader_visible_vgprs;
600  __u32 num_cu_per_sh;
601  __u32 num_tcc_blocks;
602  __u32 gs_vgt_table_depth;
603  __u32 gs_prim_buffer_depth;
604  __u32 max_gs_waves_per_vgt;
605  __u32 _pad1;
606  __u32 cu_ao_bitmap[4][4];
607  __u64 high_va_offset;
608  __u64 high_va_max;
609  __u32 pa_sc_tile_steering_override;
610  __u64 tcc_disabled_mask;
611};
612struct drm_amdgpu_info_hw_ip {
613  __u32 hw_ip_version_major;
614  __u32 hw_ip_version_minor;
615  __u64 capabilities_flags;
616  __u32 ib_start_alignment;
617  __u32 ib_size_alignment;
618  __u32 available_rings;
619  __u32 _pad;
620};
621struct drm_amdgpu_info_num_handles {
622  __u32 uvd_max_handles;
623  __u32 uvd_used_handles;
624};
625#define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6
626struct drm_amdgpu_info_vce_clock_table_entry {
627  __u32 sclk;
628  __u32 mclk;
629  __u32 eclk;
630  __u32 pad;
631};
632struct drm_amdgpu_info_vce_clock_table {
633  struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES];
634  __u32 num_valid_entries;
635  __u32 pad;
636};
637#define AMDGPU_FAMILY_UNKNOWN 0
638#define AMDGPU_FAMILY_SI 110
639#define AMDGPU_FAMILY_CI 120
640#define AMDGPU_FAMILY_KV 125
641#define AMDGPU_FAMILY_VI 130
642#define AMDGPU_FAMILY_CZ 135
643#define AMDGPU_FAMILY_AI 141
644#define AMDGPU_FAMILY_RV 142
645#define AMDGPU_FAMILY_NV 143
646#ifdef __cplusplus
647}
648#endif
649#endif
650