1/* 2 * This header was generated from the Linux kernel headers by update_headers.py, 3 * to provide necessary information from kernel to userspace, such as constants, 4 * structures, and macros, and thus, contains no copyrightable information. 5 */ 6#ifndef _UAPI__SOUND_EMU10K1_H 7#define _UAPI__SOUND_EMU10K1_H 8#include <linux/types.h> 9#include <sound/asound.h> 10#define EMU10K1_CARD_CREATIVE 0x00000000 11#define EMU10K1_CARD_EMUAPS 0x00000001 12#define EMU10K1_FX8010_PCM_COUNT 8 13#define __EMU10K1_DECLARE_BITMAP(name,bits) \ 14 unsigned long name[(bits) / (sizeof(unsigned long) * 8)] 15#define iMAC0 0x00 16#define iMAC1 0x01 17#define iMAC2 0x02 18#define iMAC3 0x03 19#define iMACINT0 0x04 20#define iMACINT1 0x05 21#define iACC3 0x06 22#define iMACMV 0x07 23#define iANDXOR 0x08 24#define iTSTNEG 0x09 25#define iLIMITGE 0x0a 26#define iLIMITLT 0x0b 27#define iLOG 0x0c 28#define iEXP 0x0d 29#define iINTERP 0x0e 30#define iSKIP 0x0f 31#define FXBUS(x) (0x00 + (x)) 32#define EXTIN(x) (0x10 + (x)) 33#define EXTOUT(x) (0x20 + (x)) 34#define FXBUS2(x) (0x30 + (x)) 35 36#define C_00000000 0x40 37#define C_00000001 0x41 38#define C_00000002 0x42 39#define C_00000003 0x43 40#define C_00000004 0x44 41#define C_00000008 0x45 42#define C_00000010 0x46 43#define C_00000020 0x47 44#define C_00000100 0x48 45#define C_00010000 0x49 46#define C_00080000 0x4a 47#define C_10000000 0x4b 48#define C_20000000 0x4c 49#define C_40000000 0x4d 50#define C_80000000 0x4e 51#define C_7fffffff 0x4f 52#define C_ffffffff 0x50 53#define C_fffffffe 0x51 54#define C_c0000000 0x52 55#define C_4f1bbcdc 0x53 56#define C_5a7ef9db 0x54 57#define C_00100000 0x55 58#define GPR_ACCU 0x56 59#define GPR_COND 0x57 60#define GPR_NOISE0 0x58 61#define GPR_NOISE1 0x59 62#define GPR_IRQ 0x5a 63#define GPR_DBAC 0x5b 64#define GPR(x) (FXGPREGBASE + (x)) 65#define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) 66#define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x)) 67#define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) 68#define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x)) 69#define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) 70#define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x)) 71#define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) 72#define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x)) 73#define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x)) 74#define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x)) 75#define A_FXBUS(x) (0x00 + (x)) 76#define A_EXTIN(x) (0x40 + (x)) 77#define A_P16VIN(x) (0x50 + (x)) 78#define A_EXTOUT(x) (0x60 + (x)) 79#define A_FXBUS2(x) (0x80 + (x)) 80#define A_EMU32OUTH(x) (0xa0 + (x)) 81#define A_EMU32OUTL(x) (0xb0 + (x)) 82#define A3_EMU32IN(x) (0x160 + (x)) 83#define A3_EMU32OUT(x) (0x1E0 + (x)) 84#define A_GPR(x) (A_FXGPREGBASE + (x)) 85#define CC_REG_NORMALIZED C_00000001 86#define CC_REG_BORROW C_00000002 87#define CC_REG_MINUS C_00000004 88#define CC_REG_ZERO C_00000008 89#define CC_REG_SATURATE C_00000010 90#define CC_REG_NONZERO C_00000100 91#define FXBUS_PCM_LEFT 0x00 92#define FXBUS_PCM_RIGHT 0x01 93#define FXBUS_PCM_LEFT_REAR 0x02 94#define FXBUS_PCM_RIGHT_REAR 0x03 95#define FXBUS_MIDI_LEFT 0x04 96#define FXBUS_MIDI_RIGHT 0x05 97#define FXBUS_PCM_CENTER 0x06 98#define FXBUS_PCM_LFE 0x07 99#define FXBUS_PCM_LEFT_FRONT 0x08 100#define FXBUS_PCM_RIGHT_FRONT 0x09 101#define FXBUS_MIDI_REVERB 0x0c 102#define FXBUS_MIDI_CHORUS 0x0d 103#define FXBUS_PCM_LEFT_SIDE 0x0e 104#define FXBUS_PCM_RIGHT_SIDE 0x0f 105#define FXBUS_PT_LEFT 0x14 106#define FXBUS_PT_RIGHT 0x15 107#define EXTIN_AC97_L 0x00 108#define EXTIN_AC97_R 0x01 109#define EXTIN_SPDIF_CD_L 0x02 110#define EXTIN_SPDIF_CD_R 0x03 111#define EXTIN_ZOOM_L 0x04 112#define EXTIN_ZOOM_R 0x05 113#define EXTIN_TOSLINK_L 0x06 114#define EXTIN_TOSLINK_R 0x07 115#define EXTIN_LINE1_L 0x08 116#define EXTIN_LINE1_R 0x09 117#define EXTIN_COAX_SPDIF_L 0x0a 118#define EXTIN_COAX_SPDIF_R 0x0b 119#define EXTIN_LINE2_L 0x0c 120#define EXTIN_LINE2_R 0x0d 121#define EXTOUT_AC97_L 0x00 122#define EXTOUT_AC97_R 0x01 123#define EXTOUT_TOSLINK_L 0x02 124#define EXTOUT_TOSLINK_R 0x03 125#define EXTOUT_AC97_CENTER 0x04 126#define EXTOUT_AC97_LFE 0x05 127#define EXTOUT_HEADPHONE_L 0x06 128#define EXTOUT_HEADPHONE_R 0x07 129#define EXTOUT_REAR_L 0x08 130#define EXTOUT_REAR_R 0x09 131#define EXTOUT_ADC_CAP_L 0x0a 132#define EXTOUT_ADC_CAP_R 0x0b 133#define EXTOUT_MIC_CAP 0x0c 134#define EXTOUT_AC97_REAR_L 0x0d 135#define EXTOUT_AC97_REAR_R 0x0e 136#define EXTOUT_ACENTER 0x11 137#define EXTOUT_ALFE 0x12 138#define A_EXTIN_AC97_L 0x00 139#define A_EXTIN_AC97_R 0x01 140#define A_EXTIN_SPDIF_CD_L 0x02 141#define A_EXTIN_SPDIF_CD_R 0x03 142#define A_EXTIN_OPT_SPDIF_L 0x04 143#define A_EXTIN_OPT_SPDIF_R 0x05 144#define A_EXTIN_LINE2_L 0x08 145#define A_EXTIN_LINE2_R 0x09 146#define A_EXTIN_ADC_L 0x0a 147#define A_EXTIN_ADC_R 0x0b 148#define A_EXTIN_AUX2_L 0x0c 149#define A_EXTIN_AUX2_R 0x0d 150#define A_EXTOUT_FRONT_L 0x00 151#define A_EXTOUT_FRONT_R 0x01 152#define A_EXTOUT_CENTER 0x02 153#define A_EXTOUT_LFE 0x03 154#define A_EXTOUT_HEADPHONE_L 0x04 155#define A_EXTOUT_HEADPHONE_R 0x05 156#define A_EXTOUT_REAR_L 0x06 157#define A_EXTOUT_REAR_R 0x07 158#define A_EXTOUT_AFRONT_L 0x08 159#define A_EXTOUT_AFRONT_R 0x09 160#define A_EXTOUT_ACENTER 0x0a 161#define A_EXTOUT_ALFE 0x0b 162#define A_EXTOUT_ASIDE_L 0x0c 163#define A_EXTOUT_ASIDE_R 0x0d 164#define A_EXTOUT_AREAR_L 0x0e 165#define A_EXTOUT_AREAR_R 0x0f 166#define A_EXTOUT_AC97_L 0x10 167#define A_EXTOUT_AC97_R 0x11 168#define A_EXTOUT_ADC_CAP_L 0x16 169#define A_EXTOUT_ADC_CAP_R 0x17 170#define A_EXTOUT_MIC_CAP 0x18 171#define A_C_00000000 0xc0 172#define A_C_00000001 0xc1 173#define A_C_00000002 0xc2 174#define A_C_00000003 0xc3 175#define A_C_00000004 0xc4 176#define A_C_00000008 0xc5 177#define A_C_00000010 0xc6 178#define A_C_00000020 0xc7 179#define A_C_00000100 0xc8 180#define A_C_00010000 0xc9 181#define A_C_00000800 0xca 182#define A_C_10000000 0xcb 183#define A_C_20000000 0xcc 184#define A_C_40000000 0xcd 185#define A_C_80000000 0xce 186#define A_C_7fffffff 0xcf 187#define A_C_ffffffff 0xd0 188#define A_C_fffffffe 0xd1 189#define A_C_c0000000 0xd2 190#define A_C_4f1bbcdc 0xd3 191#define A_C_5a7ef9db 0xd4 192#define A_C_00100000 0xd5 193#define A_GPR_ACCU 0xd6 194#define A_GPR_COND 0xd7 195#define A_GPR_NOISE0 0xd8 196#define A_GPR_NOISE1 0xd9 197#define A_GPR_IRQ 0xda 198#define A_GPR_DBAC 0xdb 199#define A_GPR_DBACE 0xde 200#define EMU10K1_DBG_ZC 0x80000000 201#define EMU10K1_DBG_SATURATION_OCCURED 0x02000000 202#define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000 203#define EMU10K1_DBG_SINGLE_STEP 0x00008000 204#define EMU10K1_DBG_STEP 0x00004000 205#define EMU10K1_DBG_CONDITION_CODE 0x00003e00 206#define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff 207#ifndef __KERNEL__ 208#define TANKMEMADDRREG_ADDR_MASK 0x000fffff 209#define TANKMEMADDRREG_CLEAR 0x00800000 210#define TANKMEMADDRREG_ALIGN 0x00400000 211#define TANKMEMADDRREG_WRITE 0x00200000 212#define TANKMEMADDRREG_READ 0x00100000 213#endif 214struct snd_emu10k1_fx8010_info { 215 unsigned int internal_tram_size; 216 unsigned int external_tram_size; 217 char fxbus_names[16][32]; 218 char extin_names[16][32]; 219 char extout_names[32][32]; 220 unsigned int gpr_controls; 221}; 222#define EMU10K1_GPR_TRANSLATION_NONE 0 223#define EMU10K1_GPR_TRANSLATION_TABLE100 1 224#define EMU10K1_GPR_TRANSLATION_BASS 2 225#define EMU10K1_GPR_TRANSLATION_TREBLE 3 226#define EMU10K1_GPR_TRANSLATION_ONOFF 4 227struct snd_emu10k1_fx8010_control_gpr { 228 struct snd_ctl_elem_id id; 229 unsigned int vcount; 230 unsigned int count; 231 unsigned short gpr[32]; 232 unsigned int value[32]; 233 unsigned int min; 234 unsigned int max; 235 unsigned int translation; 236 const unsigned int *tlv; 237}; 238struct snd_emu10k1_fx8010_control_old_gpr { 239 struct snd_ctl_elem_id id; 240 unsigned int vcount; 241 unsigned int count; 242 unsigned short gpr[32]; 243 unsigned int value[32]; 244 unsigned int min; 245 unsigned int max; 246 unsigned int translation; 247}; 248struct snd_emu10k1_fx8010_code { 249 char name[128]; 250 __EMU10K1_DECLARE_BITMAP(gpr_valid, 0x200); 251 __u32 __user *gpr_map; 252 unsigned int gpr_add_control_count; 253 struct snd_emu10k1_fx8010_control_gpr __user *gpr_add_controls; 254 unsigned int gpr_del_control_count; 255 struct snd_ctl_elem_id __user *gpr_del_controls; 256 unsigned int gpr_list_control_count; 257 unsigned int gpr_list_control_total; 258 struct snd_emu10k1_fx8010_control_gpr __user *gpr_list_controls; 259 __EMU10K1_DECLARE_BITMAP(tram_valid, 0x100); 260 __u32 __user *tram_data_map; 261 __u32 __user *tram_addr_map; 262 __EMU10K1_DECLARE_BITMAP(code_valid, 1024); 263 __u32 __user *code; 264}; 265struct snd_emu10k1_fx8010_tram { 266 unsigned int address; 267 unsigned int size; 268 unsigned int *samples; 269 270}; 271struct snd_emu10k1_fx8010_pcm_rec { 272 unsigned int substream; 273 unsigned int res1; 274 unsigned int channels; 275 unsigned int tram_start; 276 unsigned int buffer_size; 277 unsigned short gpr_size; 278 unsigned short gpr_ptr; 279 unsigned short gpr_count; 280 unsigned short gpr_tmpcount; 281 unsigned short gpr_trigger; 282 unsigned short gpr_running; 283 unsigned char pad; 284 unsigned char etram[32]; 285 unsigned int res2; 286}; 287#define SNDRV_EMU10K1_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1) 288#define SNDRV_EMU10K1_IOCTL_INFO _IOR ('H', 0x10, struct snd_emu10k1_fx8010_info) 289#define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW ('H', 0x11, struct snd_emu10k1_fx8010_code) 290#define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR('H', 0x12, struct snd_emu10k1_fx8010_code) 291#define SNDRV_EMU10K1_IOCTL_TRAM_SETUP _IOW ('H', 0x20, int) 292#define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW ('H', 0x21, struct snd_emu10k1_fx8010_tram) 293#define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR('H', 0x22, struct snd_emu10k1_fx8010_tram) 294#define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW ('H', 0x30, struct snd_emu10k1_fx8010_pcm_rec) 295#define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, struct snd_emu10k1_fx8010_pcm_rec) 296#define SNDRV_EMU10K1_IOCTL_PVERSION _IOR ('H', 0x40, int) 297#define SNDRV_EMU10K1_IOCTL_STOP _IO ('H', 0x80) 298#define SNDRV_EMU10K1_IOCTL_CONTINUE _IO ('H', 0x81) 299#define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO ('H', 0x82) 300#define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW ('H', 0x83, int) 301#define SNDRV_EMU10K1_IOCTL_DBG_READ _IOR ('H', 0x84, int) 302typedef struct snd_emu10k1_fx8010_info emu10k1_fx8010_info_t; 303typedef struct snd_emu10k1_fx8010_control_gpr emu10k1_fx8010_control_gpr_t; 304typedef struct snd_emu10k1_fx8010_code emu10k1_fx8010_code_t; 305typedef struct snd_emu10k1_fx8010_tram emu10k1_fx8010_tram_t; 306typedef struct snd_emu10k1_fx8010_pcm_rec emu10k1_fx8010_pcm_t; 307#endif 308