1/* 2 * This header was generated from the Linux kernel headers by update_headers.py, 3 * to provide necessary information from kernel to userspace, such as constants, 4 * structures, and macros, and thus, contains no copyrightable information. 5 */ 6#ifndef _UAPI__SOUND_ASOUND_H 7#define _UAPI__SOUND_ASOUND_H 8#if defined(__KERNEL__) || defined(__linux__) 9#include <linux/types.h> 10#else 11#include <sys/ioctl.h> 12#endif 13#ifndef __KERNEL__ 14#include <stdlib.h> 15#endif 16#define SNDRV_PROTOCOL_VERSION(major, minor, subminor) (((major)<<16)|((minor)<<8)|(subminor)) 17#define SNDRV_PROTOCOL_MAJOR(version) (((version)>>16)&0xffff) 18#define SNDRV_PROTOCOL_MINOR(version) (((version)>>8)&0xff) 19#define SNDRV_PROTOCOL_MICRO(version) ((version)&0xff) 20#define SNDRV_PROTOCOL_INCOMPATIBLE(kversion, uversion) \ 21 (SNDRV_PROTOCOL_MAJOR(kversion) != SNDRV_PROTOCOL_MAJOR(uversion) || \ 22 (SNDRV_PROTOCOL_MAJOR(kversion) == SNDRV_PROTOCOL_MAJOR(uversion) && \ 23 SNDRV_PROTOCOL_MINOR(kversion) != SNDRV_PROTOCOL_MINOR(uversion))) 24struct snd_aes_iec958 { 25 unsigned char status[24]; 26 unsigned char subcode[147]; 27 unsigned char pad; 28 unsigned char dig_subframe[4]; 29}; 30struct snd_cea_861_aud_if { 31 unsigned char db1_ct_cc; 32 unsigned char db2_sf_ss; 33 unsigned char db3; 34 unsigned char db4_ca; 35 unsigned char db5_dminh_lsv; 36}; 37#define SNDRV_HWDEP_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1) 38enum { 39 SNDRV_HWDEP_IFACE_OPL2 = 0, 40 SNDRV_HWDEP_IFACE_OPL3, 41 SNDRV_HWDEP_IFACE_OPL4, 42 SNDRV_HWDEP_IFACE_SB16CSP, 43 SNDRV_HWDEP_IFACE_EMU10K1, 44 SNDRV_HWDEP_IFACE_YSS225, 45 SNDRV_HWDEP_IFACE_ICS2115, 46 SNDRV_HWDEP_IFACE_SSCAPE, 47 SNDRV_HWDEP_IFACE_VX, 48 SNDRV_HWDEP_IFACE_MIXART, 49 SNDRV_HWDEP_IFACE_USX2Y, 50 SNDRV_HWDEP_IFACE_EMUX_WAVETABLE, 51 SNDRV_HWDEP_IFACE_BLUETOOTH, 52 SNDRV_HWDEP_IFACE_USX2Y_PCM, 53 SNDRV_HWDEP_IFACE_PCXHR, 54 SNDRV_HWDEP_IFACE_SB_RC, 55 SNDRV_HWDEP_IFACE_HDA, 56 SNDRV_HWDEP_IFACE_USB_STREAM, 57 SNDRV_HWDEP_IFACE_FW_DICE, 58 SNDRV_HWDEP_IFACE_FW_FIREWORKS, 59 SNDRV_HWDEP_IFACE_FW_BEBOB, 60 SNDRV_HWDEP_IFACE_FW_OXFW, 61 SNDRV_HWDEP_IFACE_FW_DIGI00X, 62 SNDRV_HWDEP_IFACE_FW_TASCAM, 63 SNDRV_HWDEP_IFACE_LINE6, 64 SNDRV_HWDEP_IFACE_FW_MOTU, 65 SNDRV_HWDEP_IFACE_FW_FIREFACE, 66 67 SNDRV_HWDEP_IFACE_LAST = SNDRV_HWDEP_IFACE_FW_FIREFACE 68}; 69struct snd_hwdep_info { 70 unsigned int device; 71 int card; 72 unsigned char id[64]; 73 unsigned char name[80]; 74 int iface; 75 unsigned char reserved[64]; 76}; 77struct snd_hwdep_dsp_status { 78 unsigned int version; 79 unsigned char id[32]; 80 unsigned int num_dsps; 81 unsigned int dsp_loaded; 82 unsigned int chip_ready; 83 unsigned char reserved[16]; 84}; 85struct snd_hwdep_dsp_image { 86 unsigned int index; 87 unsigned char name[64]; 88 unsigned char __user *image; 89 size_t length; 90 unsigned long driver_data; 91}; 92#define SNDRV_HWDEP_IOCTL_PVERSION _IOR ('H', 0x00, int) 93#define SNDRV_HWDEP_IOCTL_INFO _IOR ('H', 0x01, struct snd_hwdep_info) 94#define SNDRV_HWDEP_IOCTL_DSP_STATUS _IOR('H', 0x02, struct snd_hwdep_dsp_status) 95#define SNDRV_HWDEP_IOCTL_DSP_LOAD _IOW('H', 0x03, struct snd_hwdep_dsp_image) 96#define SNDRV_PCM_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 14) 97typedef unsigned long snd_pcm_uframes_t; 98typedef signed long snd_pcm_sframes_t; 99enum { 100 SNDRV_PCM_CLASS_GENERIC = 0, 101 SNDRV_PCM_CLASS_MULTI, 102 SNDRV_PCM_CLASS_MODEM, 103 SNDRV_PCM_CLASS_DIGITIZER, 104 105 SNDRV_PCM_CLASS_LAST = SNDRV_PCM_CLASS_DIGITIZER, 106}; 107enum { 108 SNDRV_PCM_SUBCLASS_GENERIC_MIX = 0, 109 SNDRV_PCM_SUBCLASS_MULTI_MIX, 110 111 SNDRV_PCM_SUBCLASS_LAST = SNDRV_PCM_SUBCLASS_MULTI_MIX, 112}; 113enum { 114 SNDRV_PCM_STREAM_PLAYBACK = 0, 115 SNDRV_PCM_STREAM_CAPTURE, 116 SNDRV_PCM_STREAM_LAST = SNDRV_PCM_STREAM_CAPTURE, 117}; 118typedef int __bitwise snd_pcm_access_t; 119#define SNDRV_PCM_ACCESS_MMAP_INTERLEAVED ((__force snd_pcm_access_t) 0) 120#define SNDRV_PCM_ACCESS_MMAP_NONINTERLEAVED ((__force snd_pcm_access_t) 1) 121#define SNDRV_PCM_ACCESS_MMAP_COMPLEX ((__force snd_pcm_access_t) 2) 122#define SNDRV_PCM_ACCESS_RW_INTERLEAVED ((__force snd_pcm_access_t) 3) 123#define SNDRV_PCM_ACCESS_RW_NONINTERLEAVED ((__force snd_pcm_access_t) 4) 124#define SNDRV_PCM_ACCESS_LAST SNDRV_PCM_ACCESS_RW_NONINTERLEAVED 125typedef int __bitwise snd_pcm_format_t; 126#define SNDRV_PCM_FORMAT_S8 ((__force snd_pcm_format_t) 0) 127#define SNDRV_PCM_FORMAT_U8 ((__force snd_pcm_format_t) 1) 128#define SNDRV_PCM_FORMAT_S16_LE ((__force snd_pcm_format_t) 2) 129#define SNDRV_PCM_FORMAT_S16_BE ((__force snd_pcm_format_t) 3) 130#define SNDRV_PCM_FORMAT_U16_LE ((__force snd_pcm_format_t) 4) 131#define SNDRV_PCM_FORMAT_U16_BE ((__force snd_pcm_format_t) 5) 132#define SNDRV_PCM_FORMAT_S24_LE ((__force snd_pcm_format_t) 6) 133#define SNDRV_PCM_FORMAT_S24_BE ((__force snd_pcm_format_t) 7) 134#define SNDRV_PCM_FORMAT_U24_LE ((__force snd_pcm_format_t) 8) 135#define SNDRV_PCM_FORMAT_U24_BE ((__force snd_pcm_format_t) 9) 136#define SNDRV_PCM_FORMAT_S32_LE ((__force snd_pcm_format_t) 10) 137#define SNDRV_PCM_FORMAT_S32_BE ((__force snd_pcm_format_t) 11) 138#define SNDRV_PCM_FORMAT_U32_LE ((__force snd_pcm_format_t) 12) 139#define SNDRV_PCM_FORMAT_U32_BE ((__force snd_pcm_format_t) 13) 140#define SNDRV_PCM_FORMAT_FLOAT_LE ((__force snd_pcm_format_t) 14) 141#define SNDRV_PCM_FORMAT_FLOAT_BE ((__force snd_pcm_format_t) 15) 142#define SNDRV_PCM_FORMAT_FLOAT64_LE ((__force snd_pcm_format_t) 16) 143#define SNDRV_PCM_FORMAT_FLOAT64_BE ((__force snd_pcm_format_t) 17) 144#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE ((__force snd_pcm_format_t) 18) 145#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE ((__force snd_pcm_format_t) 19) 146#define SNDRV_PCM_FORMAT_MU_LAW ((__force snd_pcm_format_t) 20) 147#define SNDRV_PCM_FORMAT_A_LAW ((__force snd_pcm_format_t) 21) 148#define SNDRV_PCM_FORMAT_IMA_ADPCM ((__force snd_pcm_format_t) 22) 149#define SNDRV_PCM_FORMAT_MPEG ((__force snd_pcm_format_t) 23) 150#define SNDRV_PCM_FORMAT_GSM ((__force snd_pcm_format_t) 24) 151#define SNDRV_PCM_FORMAT_S20_LE ((__force snd_pcm_format_t) 25) 152#define SNDRV_PCM_FORMAT_S20_BE ((__force snd_pcm_format_t) 26) 153#define SNDRV_PCM_FORMAT_U20_LE ((__force snd_pcm_format_t) 27) 154#define SNDRV_PCM_FORMAT_U20_BE ((__force snd_pcm_format_t) 28) 155#define SNDRV_PCM_FORMAT_SPECIAL ((__force snd_pcm_format_t) 31) 156#define SNDRV_PCM_FORMAT_S24_3LE ((__force snd_pcm_format_t) 32) 157#define SNDRV_PCM_FORMAT_S24_3BE ((__force snd_pcm_format_t) 33) 158#define SNDRV_PCM_FORMAT_U24_3LE ((__force snd_pcm_format_t) 34) 159#define SNDRV_PCM_FORMAT_U24_3BE ((__force snd_pcm_format_t) 35) 160#define SNDRV_PCM_FORMAT_S20_3LE ((__force snd_pcm_format_t) 36) 161#define SNDRV_PCM_FORMAT_S20_3BE ((__force snd_pcm_format_t) 37) 162#define SNDRV_PCM_FORMAT_U20_3LE ((__force snd_pcm_format_t) 38) 163#define SNDRV_PCM_FORMAT_U20_3BE ((__force snd_pcm_format_t) 39) 164#define SNDRV_PCM_FORMAT_S18_3LE ((__force snd_pcm_format_t) 40) 165#define SNDRV_PCM_FORMAT_S18_3BE ((__force snd_pcm_format_t) 41) 166#define SNDRV_PCM_FORMAT_U18_3LE ((__force snd_pcm_format_t) 42) 167#define SNDRV_PCM_FORMAT_U18_3BE ((__force snd_pcm_format_t) 43) 168#define SNDRV_PCM_FORMAT_G723_24 ((__force snd_pcm_format_t) 44) 169#define SNDRV_PCM_FORMAT_G723_24_1B ((__force snd_pcm_format_t) 45) 170#define SNDRV_PCM_FORMAT_G723_40 ((__force snd_pcm_format_t) 46) 171#define SNDRV_PCM_FORMAT_G723_40_1B ((__force snd_pcm_format_t) 47) 172#define SNDRV_PCM_FORMAT_DSD_U8 ((__force snd_pcm_format_t) 48) 173#define SNDRV_PCM_FORMAT_DSD_U16_LE ((__force snd_pcm_format_t) 49) 174#define SNDRV_PCM_FORMAT_DSD_U32_LE ((__force snd_pcm_format_t) 50) 175#define SNDRV_PCM_FORMAT_DSD_U16_BE ((__force snd_pcm_format_t) 51) 176#define SNDRV_PCM_FORMAT_DSD_U32_BE ((__force snd_pcm_format_t) 52) 177#define SNDRV_PCM_FORMAT_LAST SNDRV_PCM_FORMAT_DSD_U32_BE 178#define SNDRV_PCM_FORMAT_FIRST SNDRV_PCM_FORMAT_S8 179#ifdef SNDRV_LITTLE_ENDIAN 180#define SNDRV_PCM_FORMAT_S16 SNDRV_PCM_FORMAT_S16_LE 181#define SNDRV_PCM_FORMAT_U16 SNDRV_PCM_FORMAT_U16_LE 182#define SNDRV_PCM_FORMAT_S24 SNDRV_PCM_FORMAT_S24_LE 183#define SNDRV_PCM_FORMAT_U24 SNDRV_PCM_FORMAT_U24_LE 184#define SNDRV_PCM_FORMAT_S32 SNDRV_PCM_FORMAT_S32_LE 185#define SNDRV_PCM_FORMAT_U32 SNDRV_PCM_FORMAT_U32_LE 186#define SNDRV_PCM_FORMAT_FLOAT SNDRV_PCM_FORMAT_FLOAT_LE 187#define SNDRV_PCM_FORMAT_FLOAT64 SNDRV_PCM_FORMAT_FLOAT64_LE 188#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE 189#define SNDRV_PCM_FORMAT_S20 SNDRV_PCM_FORMAT_S20_LE 190#define SNDRV_PCM_FORMAT_U20 SNDRV_PCM_FORMAT_U20_LE 191#endif 192#ifdef SNDRV_BIG_ENDIAN 193#define SNDRV_PCM_FORMAT_S16 SNDRV_PCM_FORMAT_S16_BE 194#define SNDRV_PCM_FORMAT_U16 SNDRV_PCM_FORMAT_U16_BE 195#define SNDRV_PCM_FORMAT_S24 SNDRV_PCM_FORMAT_S24_BE 196#define SNDRV_PCM_FORMAT_U24 SNDRV_PCM_FORMAT_U24_BE 197#define SNDRV_PCM_FORMAT_S32 SNDRV_PCM_FORMAT_S32_BE 198#define SNDRV_PCM_FORMAT_U32 SNDRV_PCM_FORMAT_U32_BE 199#define SNDRV_PCM_FORMAT_FLOAT SNDRV_PCM_FORMAT_FLOAT_BE 200#define SNDRV_PCM_FORMAT_FLOAT64 SNDRV_PCM_FORMAT_FLOAT64_BE 201#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE 202#define SNDRV_PCM_FORMAT_S20 SNDRV_PCM_FORMAT_S20_BE 203#define SNDRV_PCM_FORMAT_U20 SNDRV_PCM_FORMAT_U20_BE 204#endif 205typedef int __bitwise snd_pcm_subformat_t; 206#define SNDRV_PCM_SUBFORMAT_STD ((__force snd_pcm_subformat_t) 0) 207#define SNDRV_PCM_SUBFORMAT_LAST SNDRV_PCM_SUBFORMAT_STD 208#define SNDRV_PCM_INFO_MMAP 0x00000001 209#define SNDRV_PCM_INFO_MMAP_VALID 0x00000002 210#define SNDRV_PCM_INFO_DOUBLE 0x00000004 211#define SNDRV_PCM_INFO_BATCH 0x00000010 212#define SNDRV_PCM_INFO_SYNC_APPLPTR 0x00000020 213#define SNDRV_PCM_INFO_INTERLEAVED 0x00000100 214#define SNDRV_PCM_INFO_NONINTERLEAVED 0x00000200 215#define SNDRV_PCM_INFO_COMPLEX 0x00000400 216#define SNDRV_PCM_INFO_BLOCK_TRANSFER 0x00010000 217#define SNDRV_PCM_INFO_OVERRANGE 0x00020000 218#define SNDRV_PCM_INFO_RESUME 0x00040000 219#define SNDRV_PCM_INFO_PAUSE 0x00080000 220#define SNDRV_PCM_INFO_HALF_DUPLEX 0x00100000 221#define SNDRV_PCM_INFO_JOINT_DUPLEX 0x00200000 222#define SNDRV_PCM_INFO_SYNC_START 0x00400000 223#define SNDRV_PCM_INFO_NO_PERIOD_WAKEUP 0x00800000 224#define SNDRV_PCM_INFO_HAS_WALL_CLOCK 0x01000000 225#define SNDRV_PCM_INFO_HAS_LINK_ATIME 0x01000000 226#define SNDRV_PCM_INFO_HAS_LINK_ABSOLUTE_ATIME 0x02000000 227#define SNDRV_PCM_INFO_HAS_LINK_ESTIMATED_ATIME 0x04000000 228#define SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME 0x08000000 229#define SNDRV_PCM_INFO_DRAIN_TRIGGER 0x40000000 230#define SNDRV_PCM_INFO_FIFO_IN_FRAMES 0x80000000 231typedef int __bitwise snd_pcm_state_t; 232#define SNDRV_PCM_STATE_OPEN ((__force snd_pcm_state_t) 0) 233#define SNDRV_PCM_STATE_SETUP ((__force snd_pcm_state_t) 1) 234#define SNDRV_PCM_STATE_PREPARED ((__force snd_pcm_state_t) 2) 235#define SNDRV_PCM_STATE_RUNNING ((__force snd_pcm_state_t) 3) 236#define SNDRV_PCM_STATE_XRUN ((__force snd_pcm_state_t) 4) 237#define SNDRV_PCM_STATE_DRAINING ((__force snd_pcm_state_t) 5) 238#define SNDRV_PCM_STATE_PAUSED ((__force snd_pcm_state_t) 6) 239#define SNDRV_PCM_STATE_SUSPENDED ((__force snd_pcm_state_t) 7) 240#define SNDRV_PCM_STATE_DISCONNECTED ((__force snd_pcm_state_t) 8) 241#define SNDRV_PCM_STATE_LAST SNDRV_PCM_STATE_DISCONNECTED 242enum { 243 SNDRV_PCM_MMAP_OFFSET_DATA = 0x00000000, 244 SNDRV_PCM_MMAP_OFFSET_STATUS = 0x80000000, 245 SNDRV_PCM_MMAP_OFFSET_CONTROL = 0x81000000, 246}; 247union snd_pcm_sync_id { 248 unsigned char id[16]; 249 unsigned short id16[8]; 250 unsigned int id32[4]; 251}; 252struct snd_pcm_info { 253 unsigned int device; 254 unsigned int subdevice; 255 int stream; 256 int card; 257 unsigned char id[64]; 258 unsigned char name[80]; 259 unsigned char subname[32]; 260 int dev_class; 261 int dev_subclass; 262 unsigned int subdevices_count; 263 unsigned int subdevices_avail; 264 union snd_pcm_sync_id sync; 265 unsigned char reserved[64]; 266}; 267typedef int snd_pcm_hw_param_t; 268#define SNDRV_PCM_HW_PARAM_ACCESS 0 269#define SNDRV_PCM_HW_PARAM_FORMAT 1 270#define SNDRV_PCM_HW_PARAM_SUBFORMAT 2 271#define SNDRV_PCM_HW_PARAM_FIRST_MASK SNDRV_PCM_HW_PARAM_ACCESS 272#define SNDRV_PCM_HW_PARAM_LAST_MASK SNDRV_PCM_HW_PARAM_SUBFORMAT 273#define SNDRV_PCM_HW_PARAM_SAMPLE_BITS 8 274#define SNDRV_PCM_HW_PARAM_FRAME_BITS 9 275#define SNDRV_PCM_HW_PARAM_CHANNELS 10 276#define SNDRV_PCM_HW_PARAM_RATE 11 277#define SNDRV_PCM_HW_PARAM_PERIOD_TIME 12 278#define SNDRV_PCM_HW_PARAM_PERIOD_SIZE 13 279#define SNDRV_PCM_HW_PARAM_PERIOD_BYTES 14 280#define SNDRV_PCM_HW_PARAM_PERIODS 15 281#define SNDRV_PCM_HW_PARAM_BUFFER_TIME 16 282#define SNDRV_PCM_HW_PARAM_BUFFER_SIZE 17 283#define SNDRV_PCM_HW_PARAM_BUFFER_BYTES 18 284#define SNDRV_PCM_HW_PARAM_TICK_TIME 19 285#define SNDRV_PCM_HW_PARAM_FIRST_INTERVAL SNDRV_PCM_HW_PARAM_SAMPLE_BITS 286#define SNDRV_PCM_HW_PARAM_LAST_INTERVAL SNDRV_PCM_HW_PARAM_TICK_TIME 287#define SNDRV_PCM_HW_PARAMS_NORESAMPLE (1<<0) 288#define SNDRV_PCM_HW_PARAMS_EXPORT_BUFFER (1<<1) 289#define SNDRV_PCM_HW_PARAMS_NO_PERIOD_WAKEUP (1<<2) 290struct snd_interval { 291 unsigned int min, max; 292 unsigned int openmin:1, 293 openmax:1, 294 integer:1, 295 empty:1; 296}; 297#define SNDRV_MASK_MAX 256 298struct snd_mask { 299 __u32 bits[(SNDRV_MASK_MAX+31)/32]; 300}; 301struct snd_pcm_hw_params { 302 unsigned int flags; 303 struct snd_mask masks[SNDRV_PCM_HW_PARAM_LAST_MASK - 304 SNDRV_PCM_HW_PARAM_FIRST_MASK + 1]; 305 struct snd_mask mres[5]; 306 struct snd_interval intervals[SNDRV_PCM_HW_PARAM_LAST_INTERVAL - 307 SNDRV_PCM_HW_PARAM_FIRST_INTERVAL + 1]; 308 struct snd_interval ires[9]; 309 unsigned int rmask; 310 unsigned int cmask; 311 unsigned int info; 312 unsigned int msbits; 313 unsigned int rate_num; 314 unsigned int rate_den; 315 snd_pcm_uframes_t fifo_size; 316 unsigned char reserved[64]; 317}; 318enum { 319 SNDRV_PCM_TSTAMP_NONE = 0, 320 SNDRV_PCM_TSTAMP_ENABLE, 321 SNDRV_PCM_TSTAMP_LAST = SNDRV_PCM_TSTAMP_ENABLE, 322}; 323struct snd_pcm_sw_params { 324 int tstamp_mode; 325 unsigned int period_step; 326 unsigned int sleep_min; 327 snd_pcm_uframes_t avail_min; 328 snd_pcm_uframes_t xfer_align; 329 snd_pcm_uframes_t start_threshold; 330 snd_pcm_uframes_t stop_threshold; 331 snd_pcm_uframes_t silence_threshold; 332 snd_pcm_uframes_t silence_size; 333 snd_pcm_uframes_t boundary; 334 unsigned int proto; 335 unsigned int tstamp_type; 336 unsigned char reserved[56]; 337}; 338struct snd_pcm_channel_info { 339 unsigned int channel; 340 __kernel_off_t offset; 341 unsigned int first; 342 unsigned int step; 343}; 344enum { 345 346 SNDRV_PCM_AUDIO_TSTAMP_TYPE_COMPAT = 0, 347 348 SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT = 1, 349 SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK = 2, 350 SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_ABSOLUTE = 3, 351 SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_ESTIMATED = 4, 352 SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED = 5, 353 SNDRV_PCM_AUDIO_TSTAMP_TYPE_LAST = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED 354}; 355struct snd_pcm_status { 356 snd_pcm_state_t state; 357 struct timespec trigger_tstamp; 358 struct timespec tstamp; 359 snd_pcm_uframes_t appl_ptr; 360 snd_pcm_uframes_t hw_ptr; 361 snd_pcm_sframes_t delay; 362 snd_pcm_uframes_t avail; 363 snd_pcm_uframes_t avail_max; 364 snd_pcm_uframes_t overrange; 365 snd_pcm_state_t suspended_state; 366 __u32 audio_tstamp_data; 367 struct timespec audio_tstamp; 368 struct timespec driver_tstamp; 369 __u32 audio_tstamp_accuracy; 370 unsigned char reserved[52-2*sizeof(struct timespec)]; 371}; 372struct snd_pcm_mmap_status { 373 snd_pcm_state_t state; 374 int pad1; 375 snd_pcm_uframes_t hw_ptr; 376 struct timespec tstamp; 377 snd_pcm_state_t suspended_state; 378 struct timespec audio_tstamp; 379}; 380struct snd_pcm_mmap_control { 381 snd_pcm_uframes_t appl_ptr; 382 snd_pcm_uframes_t avail_min; 383}; 384#define SNDRV_PCM_SYNC_PTR_HWSYNC (1<<0) 385#define SNDRV_PCM_SYNC_PTR_APPL (1<<1) 386#define SNDRV_PCM_SYNC_PTR_AVAIL_MIN (1<<2) 387struct snd_pcm_sync_ptr { 388 unsigned int flags; 389 union { 390 struct snd_pcm_mmap_status status; 391 unsigned char reserved[64]; 392 } s; 393 union { 394 struct snd_pcm_mmap_control control; 395 unsigned char reserved[64]; 396 } c; 397}; 398struct snd_xferi { 399 snd_pcm_sframes_t result; 400 void __user *buf; 401 snd_pcm_uframes_t frames; 402}; 403struct snd_xfern { 404 snd_pcm_sframes_t result; 405 void __user * __user *bufs; 406 snd_pcm_uframes_t frames; 407}; 408enum { 409 SNDRV_PCM_TSTAMP_TYPE_GETTIMEOFDAY = 0, 410 SNDRV_PCM_TSTAMP_TYPE_MONOTONIC, 411 SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW, 412 SNDRV_PCM_TSTAMP_TYPE_LAST = SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW, 413}; 414enum { 415 SNDRV_CHMAP_UNKNOWN = 0, 416 SNDRV_CHMAP_NA, 417 SNDRV_CHMAP_MONO, 418 419 SNDRV_CHMAP_FL, 420 SNDRV_CHMAP_FR, 421 SNDRV_CHMAP_RL, 422 SNDRV_CHMAP_RR, 423 SNDRV_CHMAP_FC, 424 SNDRV_CHMAP_LFE, 425 SNDRV_CHMAP_SL, 426 SNDRV_CHMAP_SR, 427 SNDRV_CHMAP_RC, 428 429 SNDRV_CHMAP_FLC, 430 SNDRV_CHMAP_FRC, 431 SNDRV_CHMAP_RLC, 432 SNDRV_CHMAP_RRC, 433 SNDRV_CHMAP_FLW, 434 SNDRV_CHMAP_FRW, 435 SNDRV_CHMAP_FLH, 436 SNDRV_CHMAP_FCH, 437 SNDRV_CHMAP_FRH, 438 SNDRV_CHMAP_TC, 439 SNDRV_CHMAP_TFL, 440 SNDRV_CHMAP_TFR, 441 SNDRV_CHMAP_TFC, 442 SNDRV_CHMAP_TRL, 443 SNDRV_CHMAP_TRR, 444 SNDRV_CHMAP_TRC, 445 446 SNDRV_CHMAP_TFLC, 447 SNDRV_CHMAP_TFRC, 448 SNDRV_CHMAP_TSL, 449 SNDRV_CHMAP_TSR, 450 SNDRV_CHMAP_LLFE, 451 SNDRV_CHMAP_RLFE, 452 SNDRV_CHMAP_BC, 453 SNDRV_CHMAP_BLC, 454 SNDRV_CHMAP_BRC, 455 SNDRV_CHMAP_LAST = SNDRV_CHMAP_BRC, 456}; 457#define SNDRV_CHMAP_POSITION_MASK 0xffff 458#define SNDRV_CHMAP_PHASE_INVERSE (0x01 << 16) 459#define SNDRV_CHMAP_DRIVER_SPEC (0x02 << 16) 460#define SNDRV_PCM_IOCTL_PVERSION _IOR('A', 0x00, int) 461#define SNDRV_PCM_IOCTL_INFO _IOR('A', 0x01, struct snd_pcm_info) 462#define SNDRV_PCM_IOCTL_TSTAMP _IOW('A', 0x02, int) 463#define SNDRV_PCM_IOCTL_TTSTAMP _IOW('A', 0x03, int) 464#define SNDRV_PCM_IOCTL_USER_PVERSION _IOW('A', 0x04, int) 465#define SNDRV_PCM_IOCTL_HW_REFINE _IOWR('A', 0x10, struct snd_pcm_hw_params) 466#define SNDRV_PCM_IOCTL_HW_PARAMS _IOWR('A', 0x11, struct snd_pcm_hw_params) 467#define SNDRV_PCM_IOCTL_HW_FREE _IO('A', 0x12) 468#define SNDRV_PCM_IOCTL_SW_PARAMS _IOWR('A', 0x13, struct snd_pcm_sw_params) 469#define SNDRV_PCM_IOCTL_STATUS _IOR('A', 0x20, struct snd_pcm_status) 470#define SNDRV_PCM_IOCTL_DELAY _IOR('A', 0x21, snd_pcm_sframes_t) 471#define SNDRV_PCM_IOCTL_HWSYNC _IO('A', 0x22) 472#define SNDRV_PCM_IOCTL_SYNC_PTR _IOWR('A', 0x23, struct snd_pcm_sync_ptr) 473#define SNDRV_PCM_IOCTL_STATUS_EXT _IOWR('A', 0x24, struct snd_pcm_status) 474#define SNDRV_PCM_IOCTL_CHANNEL_INFO _IOR('A', 0x32, struct snd_pcm_channel_info) 475#define SNDRV_PCM_IOCTL_PREPARE _IO('A', 0x40) 476#define SNDRV_PCM_IOCTL_RESET _IO('A', 0x41) 477#define SNDRV_PCM_IOCTL_START _IO('A', 0x42) 478#define SNDRV_PCM_IOCTL_DROP _IO('A', 0x43) 479#define SNDRV_PCM_IOCTL_DRAIN _IO('A', 0x44) 480#define SNDRV_PCM_IOCTL_PAUSE _IOW('A', 0x45, int) 481#define SNDRV_PCM_IOCTL_REWIND _IOW('A', 0x46, snd_pcm_uframes_t) 482#define SNDRV_PCM_IOCTL_RESUME _IO('A', 0x47) 483#define SNDRV_PCM_IOCTL_XRUN _IO('A', 0x48) 484#define SNDRV_PCM_IOCTL_FORWARD _IOW('A', 0x49, snd_pcm_uframes_t) 485#define SNDRV_PCM_IOCTL_WRITEI_FRAMES _IOW('A', 0x50, struct snd_xferi) 486#define SNDRV_PCM_IOCTL_READI_FRAMES _IOR('A', 0x51, struct snd_xferi) 487#define SNDRV_PCM_IOCTL_WRITEN_FRAMES _IOW('A', 0x52, struct snd_xfern) 488#define SNDRV_PCM_IOCTL_READN_FRAMES _IOR('A', 0x53, struct snd_xfern) 489#define SNDRV_PCM_IOCTL_LINK _IOW('A', 0x60, int) 490#define SNDRV_PCM_IOCTL_UNLINK _IO('A', 0x61) 491#define SNDRV_RAWMIDI_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 0) 492enum { 493 SNDRV_RAWMIDI_STREAM_OUTPUT = 0, 494 SNDRV_RAWMIDI_STREAM_INPUT, 495 SNDRV_RAWMIDI_STREAM_LAST = SNDRV_RAWMIDI_STREAM_INPUT, 496}; 497#define SNDRV_RAWMIDI_INFO_OUTPUT 0x00000001 498#define SNDRV_RAWMIDI_INFO_INPUT 0x00000002 499#define SNDRV_RAWMIDI_INFO_DUPLEX 0x00000004 500struct snd_rawmidi_info { 501 unsigned int device; 502 unsigned int subdevice; 503 int stream; 504 int card; 505 unsigned int flags; 506 unsigned char id[64]; 507 unsigned char name[80]; 508 unsigned char subname[32]; 509 unsigned int subdevices_count; 510 unsigned int subdevices_avail; 511 unsigned char reserved[64]; 512}; 513struct snd_rawmidi_params { 514 int stream; 515 size_t buffer_size; 516 size_t avail_min; 517 unsigned int no_active_sensing: 1; 518 unsigned char reserved[16]; 519}; 520struct snd_rawmidi_status { 521 int stream; 522 struct timespec tstamp; 523 size_t avail; 524 size_t xruns; 525 unsigned char reserved[16]; 526}; 527#define SNDRV_RAWMIDI_IOCTL_PVERSION _IOR('W', 0x00, int) 528#define SNDRV_RAWMIDI_IOCTL_INFO _IOR('W', 0x01, struct snd_rawmidi_info) 529#define SNDRV_RAWMIDI_IOCTL_PARAMS _IOWR('W', 0x10, struct snd_rawmidi_params) 530#define SNDRV_RAWMIDI_IOCTL_STATUS _IOWR('W', 0x20, struct snd_rawmidi_status) 531#define SNDRV_RAWMIDI_IOCTL_DROP _IOW('W', 0x30, int) 532#define SNDRV_RAWMIDI_IOCTL_DRAIN _IOW('W', 0x31, int) 533#define SNDRV_TIMER_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 6) 534enum { 535 SNDRV_TIMER_CLASS_NONE = -1, 536 SNDRV_TIMER_CLASS_SLAVE = 0, 537 SNDRV_TIMER_CLASS_GLOBAL, 538 SNDRV_TIMER_CLASS_CARD, 539 SNDRV_TIMER_CLASS_PCM, 540 SNDRV_TIMER_CLASS_LAST = SNDRV_TIMER_CLASS_PCM, 541}; 542enum { 543 SNDRV_TIMER_SCLASS_NONE = 0, 544 SNDRV_TIMER_SCLASS_APPLICATION, 545 SNDRV_TIMER_SCLASS_SEQUENCER, 546 SNDRV_TIMER_SCLASS_OSS_SEQUENCER, 547 SNDRV_TIMER_SCLASS_LAST = SNDRV_TIMER_SCLASS_OSS_SEQUENCER, 548}; 549#define SNDRV_TIMER_GLOBAL_SYSTEM 0 550#define SNDRV_TIMER_GLOBAL_RTC 1 551#define SNDRV_TIMER_GLOBAL_HPET 2 552#define SNDRV_TIMER_GLOBAL_HRTIMER 3 553#define SNDRV_TIMER_FLG_SLAVE (1<<0) 554struct snd_timer_id { 555 int dev_class; 556 int dev_sclass; 557 int card; 558 int device; 559 int subdevice; 560}; 561struct snd_timer_ginfo { 562 struct snd_timer_id tid; 563 unsigned int flags; 564 int card; 565 unsigned char id[64]; 566 unsigned char name[80]; 567 unsigned long reserved0; 568 unsigned long resolution; 569 unsigned long resolution_min; 570 unsigned long resolution_max; 571 unsigned int clients; 572 unsigned char reserved[32]; 573}; 574struct snd_timer_gparams { 575 struct snd_timer_id tid; 576 unsigned long period_num; 577 unsigned long period_den; 578 unsigned char reserved[32]; 579}; 580struct snd_timer_gstatus { 581 struct snd_timer_id tid; 582 unsigned long resolution; 583 unsigned long resolution_num; 584 unsigned long resolution_den; 585 unsigned char reserved[32]; 586}; 587struct snd_timer_select { 588 struct snd_timer_id id; 589 unsigned char reserved[32]; 590}; 591struct snd_timer_info { 592 unsigned int flags; 593 int card; 594 unsigned char id[64]; 595 unsigned char name[80]; 596 unsigned long reserved0; 597 unsigned long resolution; 598 unsigned char reserved[64]; 599}; 600#define SNDRV_TIMER_PSFLG_AUTO (1<<0) 601#define SNDRV_TIMER_PSFLG_EXCLUSIVE (1<<1) 602#define SNDRV_TIMER_PSFLG_EARLY_EVENT (1<<2) 603struct snd_timer_params { 604 unsigned int flags; 605 unsigned int ticks; 606 unsigned int queue_size; 607 unsigned int reserved0; 608 unsigned int filter; 609 unsigned char reserved[60]; 610}; 611struct snd_timer_status { 612 struct timespec tstamp; 613 unsigned int resolution; 614 unsigned int lost; 615 unsigned int overrun; 616 unsigned int queue; 617 unsigned char reserved[64]; 618}; 619#define SNDRV_TIMER_IOCTL_PVERSION _IOR('T', 0x00, int) 620#define SNDRV_TIMER_IOCTL_NEXT_DEVICE _IOWR('T', 0x01, struct snd_timer_id) 621#define SNDRV_TIMER_IOCTL_TREAD _IOW('T', 0x02, int) 622#define SNDRV_TIMER_IOCTL_GINFO _IOWR('T', 0x03, struct snd_timer_ginfo) 623#define SNDRV_TIMER_IOCTL_GPARAMS _IOW('T', 0x04, struct snd_timer_gparams) 624#define SNDRV_TIMER_IOCTL_GSTATUS _IOWR('T', 0x05, struct snd_timer_gstatus) 625#define SNDRV_TIMER_IOCTL_SELECT _IOW('T', 0x10, struct snd_timer_select) 626#define SNDRV_TIMER_IOCTL_INFO _IOR('T', 0x11, struct snd_timer_info) 627#define SNDRV_TIMER_IOCTL_PARAMS _IOW('T', 0x12, struct snd_timer_params) 628#define SNDRV_TIMER_IOCTL_STATUS _IOR('T', 0x14, struct snd_timer_status) 629#define SNDRV_TIMER_IOCTL_START _IO('T', 0xa0) 630#define SNDRV_TIMER_IOCTL_STOP _IO('T', 0xa1) 631#define SNDRV_TIMER_IOCTL_CONTINUE _IO('T', 0xa2) 632#define SNDRV_TIMER_IOCTL_PAUSE _IO('T', 0xa3) 633struct snd_timer_read { 634 unsigned int resolution; 635 unsigned int ticks; 636}; 637enum { 638 SNDRV_TIMER_EVENT_RESOLUTION = 0, 639 SNDRV_TIMER_EVENT_TICK, 640 SNDRV_TIMER_EVENT_START, 641 SNDRV_TIMER_EVENT_STOP, 642 SNDRV_TIMER_EVENT_CONTINUE, 643 SNDRV_TIMER_EVENT_PAUSE, 644 SNDRV_TIMER_EVENT_EARLY, 645 SNDRV_TIMER_EVENT_SUSPEND, 646 SNDRV_TIMER_EVENT_RESUME, 647 648 SNDRV_TIMER_EVENT_MSTART = SNDRV_TIMER_EVENT_START + 10, 649 SNDRV_TIMER_EVENT_MSTOP = SNDRV_TIMER_EVENT_STOP + 10, 650 SNDRV_TIMER_EVENT_MCONTINUE = SNDRV_TIMER_EVENT_CONTINUE + 10, 651 SNDRV_TIMER_EVENT_MPAUSE = SNDRV_TIMER_EVENT_PAUSE + 10, 652 SNDRV_TIMER_EVENT_MSUSPEND = SNDRV_TIMER_EVENT_SUSPEND + 10, 653 SNDRV_TIMER_EVENT_MRESUME = SNDRV_TIMER_EVENT_RESUME + 10, 654}; 655struct snd_timer_tread { 656 int event; 657 struct timespec tstamp; 658 unsigned int val; 659}; 660#define SNDRV_CTL_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 7) 661struct snd_ctl_card_info { 662 int card; 663 int pad; 664 unsigned char id[16]; 665 unsigned char driver[16]; 666 unsigned char name[32]; 667 unsigned char longname[80]; 668 unsigned char reserved_[16]; 669 unsigned char mixername[80]; 670 unsigned char components[128]; 671}; 672typedef int __bitwise snd_ctl_elem_type_t; 673#define SNDRV_CTL_ELEM_TYPE_NONE ((__force snd_ctl_elem_type_t) 0) 674#define SNDRV_CTL_ELEM_TYPE_BOOLEAN ((__force snd_ctl_elem_type_t) 1) 675#define SNDRV_CTL_ELEM_TYPE_INTEGER ((__force snd_ctl_elem_type_t) 2) 676#define SNDRV_CTL_ELEM_TYPE_ENUMERATED ((__force snd_ctl_elem_type_t) 3) 677#define SNDRV_CTL_ELEM_TYPE_BYTES ((__force snd_ctl_elem_type_t) 4) 678#define SNDRV_CTL_ELEM_TYPE_IEC958 ((__force snd_ctl_elem_type_t) 5) 679#define SNDRV_CTL_ELEM_TYPE_INTEGER64 ((__force snd_ctl_elem_type_t) 6) 680#define SNDRV_CTL_ELEM_TYPE_LAST SNDRV_CTL_ELEM_TYPE_INTEGER64 681typedef int __bitwise snd_ctl_elem_iface_t; 682#define SNDRV_CTL_ELEM_IFACE_CARD ((__force snd_ctl_elem_iface_t) 0) 683#define SNDRV_CTL_ELEM_IFACE_HWDEP ((__force snd_ctl_elem_iface_t) 1) 684#define SNDRV_CTL_ELEM_IFACE_MIXER ((__force snd_ctl_elem_iface_t) 2) 685#define SNDRV_CTL_ELEM_IFACE_PCM ((__force snd_ctl_elem_iface_t) 3) 686#define SNDRV_CTL_ELEM_IFACE_RAWMIDI ((__force snd_ctl_elem_iface_t) 4) 687#define SNDRV_CTL_ELEM_IFACE_TIMER ((__force snd_ctl_elem_iface_t) 5) 688#define SNDRV_CTL_ELEM_IFACE_SEQUENCER ((__force snd_ctl_elem_iface_t) 6) 689#define SNDRV_CTL_ELEM_IFACE_LAST SNDRV_CTL_ELEM_IFACE_SEQUENCER 690#define SNDRV_CTL_ELEM_ACCESS_READ (1<<0) 691#define SNDRV_CTL_ELEM_ACCESS_WRITE (1<<1) 692#define SNDRV_CTL_ELEM_ACCESS_READWRITE (SNDRV_CTL_ELEM_ACCESS_READ|SNDRV_CTL_ELEM_ACCESS_WRITE) 693#define SNDRV_CTL_ELEM_ACCESS_VOLATILE (1<<2) 694#define SNDRV_CTL_ELEM_ACCESS_TIMESTAMP (1<<3) 695#define SNDRV_CTL_ELEM_ACCESS_TLV_READ (1<<4) 696#define SNDRV_CTL_ELEM_ACCESS_TLV_WRITE (1<<5) 697#define SNDRV_CTL_ELEM_ACCESS_TLV_READWRITE (SNDRV_CTL_ELEM_ACCESS_TLV_READ|SNDRV_CTL_ELEM_ACCESS_TLV_WRITE) 698#define SNDRV_CTL_ELEM_ACCESS_TLV_COMMAND (1<<6) 699#define SNDRV_CTL_ELEM_ACCESS_INACTIVE (1<<8) 700#define SNDRV_CTL_ELEM_ACCESS_LOCK (1<<9) 701#define SNDRV_CTL_ELEM_ACCESS_OWNER (1<<10) 702#define SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK (1<<28) 703#define SNDRV_CTL_ELEM_ACCESS_USER (1<<29) 704#define SNDRV_CTL_POWER_D0 0x0000 705#define SNDRV_CTL_POWER_D1 0x0100 706#define SNDRV_CTL_POWER_D2 0x0200 707#define SNDRV_CTL_POWER_D3 0x0300 708#define SNDRV_CTL_POWER_D3hot (SNDRV_CTL_POWER_D3|0x0000) 709#define SNDRV_CTL_POWER_D3cold (SNDRV_CTL_POWER_D3|0x0001) 710#define SNDRV_CTL_ELEM_ID_NAME_MAXLEN 44 711struct snd_ctl_elem_id { 712 unsigned int numid; 713 snd_ctl_elem_iface_t iface; 714 unsigned int device; 715 unsigned int subdevice; 716 unsigned char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 717 unsigned int index; 718}; 719struct snd_ctl_elem_list { 720 unsigned int offset; 721 unsigned int space; 722 unsigned int used; 723 unsigned int count; 724 struct snd_ctl_elem_id __user *pids; 725 unsigned char reserved[50]; 726}; 727struct snd_ctl_elem_info { 728 struct snd_ctl_elem_id id; 729 snd_ctl_elem_type_t type; 730 unsigned int access; 731 unsigned int count; 732 __kernel_pid_t owner; 733 union { 734 struct { 735 long min; 736 long max; 737 long step; 738 } integer; 739 struct { 740 long long min; 741 long long max; 742 long long step; 743 } integer64; 744 struct { 745 unsigned int items; 746 unsigned int item; 747 char name[64]; 748 __u64 names_ptr; 749 unsigned int names_length; 750 } enumerated; 751 unsigned char reserved[128]; 752 } value; 753 union { 754 unsigned short d[4]; 755 unsigned short *d_ptr; 756 } dimen; 757 unsigned char reserved[64-4*sizeof(unsigned short)]; 758}; 759struct snd_ctl_elem_value { 760 struct snd_ctl_elem_id id; 761 unsigned int indirect: 1; 762 union { 763 union { 764 long value[128]; 765 long *value_ptr; 766 } integer; 767 union { 768 long long value[64]; 769 long long *value_ptr; 770 } integer64; 771 union { 772 unsigned int item[128]; 773 unsigned int *item_ptr; 774 } enumerated; 775 union { 776 unsigned char data[512]; 777 unsigned char *data_ptr; 778 } bytes; 779 struct snd_aes_iec958 iec958; 780 } value; 781 struct timespec tstamp; 782 unsigned char reserved[128-sizeof(struct timespec)]; 783}; 784struct snd_ctl_tlv { 785 unsigned int numid; 786 unsigned int length; 787 unsigned int tlv[0]; 788}; 789#define SNDRV_CTL_IOCTL_PVERSION _IOR('U', 0x00, int) 790#define SNDRV_CTL_IOCTL_CARD_INFO _IOR('U', 0x01, struct snd_ctl_card_info) 791#define SNDRV_CTL_IOCTL_ELEM_LIST _IOWR('U', 0x10, struct snd_ctl_elem_list) 792#define SNDRV_CTL_IOCTL_ELEM_INFO _IOWR('U', 0x11, struct snd_ctl_elem_info) 793#define SNDRV_CTL_IOCTL_ELEM_READ _IOWR('U', 0x12, struct snd_ctl_elem_value) 794#define SNDRV_CTL_IOCTL_ELEM_WRITE _IOWR('U', 0x13, struct snd_ctl_elem_value) 795#define SNDRV_CTL_IOCTL_ELEM_LOCK _IOW('U', 0x14, struct snd_ctl_elem_id) 796#define SNDRV_CTL_IOCTL_ELEM_UNLOCK _IOW('U', 0x15, struct snd_ctl_elem_id) 797#define SNDRV_CTL_IOCTL_SUBSCRIBE_EVENTS _IOWR('U', 0x16, int) 798#define SNDRV_CTL_IOCTL_ELEM_ADD _IOWR('U', 0x17, struct snd_ctl_elem_info) 799#define SNDRV_CTL_IOCTL_ELEM_REPLACE _IOWR('U', 0x18, struct snd_ctl_elem_info) 800#define SNDRV_CTL_IOCTL_ELEM_REMOVE _IOWR('U', 0x19, struct snd_ctl_elem_id) 801#define SNDRV_CTL_IOCTL_TLV_READ _IOWR('U', 0x1a, struct snd_ctl_tlv) 802#define SNDRV_CTL_IOCTL_TLV_WRITE _IOWR('U', 0x1b, struct snd_ctl_tlv) 803#define SNDRV_CTL_IOCTL_TLV_COMMAND _IOWR('U', 0x1c, struct snd_ctl_tlv) 804#define SNDRV_CTL_IOCTL_HWDEP_NEXT_DEVICE _IOWR('U', 0x20, int) 805#define SNDRV_CTL_IOCTL_HWDEP_INFO _IOR('U', 0x21, struct snd_hwdep_info) 806#define SNDRV_CTL_IOCTL_PCM_NEXT_DEVICE _IOR('U', 0x30, int) 807#define SNDRV_CTL_IOCTL_PCM_INFO _IOWR('U', 0x31, struct snd_pcm_info) 808#define SNDRV_CTL_IOCTL_PCM_PREFER_SUBDEVICE _IOW('U', 0x32, int) 809#define SNDRV_CTL_IOCTL_RAWMIDI_NEXT_DEVICE _IOWR('U', 0x40, int) 810#define SNDRV_CTL_IOCTL_RAWMIDI_INFO _IOWR('U', 0x41, struct snd_rawmidi_info) 811#define SNDRV_CTL_IOCTL_RAWMIDI_PREFER_SUBDEVICE _IOW('U', 0x42, int) 812#define SNDRV_CTL_IOCTL_POWER _IOWR('U', 0xd0, int) 813#define SNDRV_CTL_IOCTL_POWER_STATE _IOR('U', 0xd1, int) 814enum sndrv_ctl_event_type { 815 SNDRV_CTL_EVENT_ELEM = 0, 816 SNDRV_CTL_EVENT_LAST = SNDRV_CTL_EVENT_ELEM, 817}; 818#define SNDRV_CTL_EVENT_MASK_VALUE (1<<0) 819#define SNDRV_CTL_EVENT_MASK_INFO (1<<1) 820#define SNDRV_CTL_EVENT_MASK_ADD (1<<2) 821#define SNDRV_CTL_EVENT_MASK_TLV (1<<3) 822#define SNDRV_CTL_EVENT_MASK_REMOVE (~0U) 823struct snd_ctl_event { 824 int type; 825 union { 826 struct { 827 unsigned int mask; 828 struct snd_ctl_elem_id id; 829 } elem; 830 unsigned char data8[60]; 831 } data; 832}; 833#define SNDRV_CTL_NAME_NONE "" 834#define SNDRV_CTL_NAME_PLAYBACK "Playback " 835#define SNDRV_CTL_NAME_CAPTURE "Capture " 836#define SNDRV_CTL_NAME_IEC958_NONE "" 837#define SNDRV_CTL_NAME_IEC958_SWITCH "Switch" 838#define SNDRV_CTL_NAME_IEC958_VOLUME "Volume" 839#define SNDRV_CTL_NAME_IEC958_DEFAULT "Default" 840#define SNDRV_CTL_NAME_IEC958_MASK "Mask" 841#define SNDRV_CTL_NAME_IEC958_CON_MASK "Con Mask" 842#define SNDRV_CTL_NAME_IEC958_PRO_MASK "Pro Mask" 843#define SNDRV_CTL_NAME_IEC958_PCM_STREAM "PCM Stream" 844#define SNDRV_CTL_NAME_IEC958(expl,direction,what) "IEC958 " expl SNDRV_CTL_NAME_##direction SNDRV_CTL_NAME_IEC958_##what 845#endif 846