1/*
2 * This header was generated from the Linux kernel headers by update_headers.py,
3 * to provide necessary information from kernel to userspace, such as constants,
4 * structures, and macros, and thus, contains no copyrightable information.
5 */
6#ifndef VIRTIO_GPU_HW_H
7#define VIRTIO_GPU_HW_H
8#include <linux/types.h>
9#define VIRTIO_GPU_F_VIRGL 0
10enum virtio_gpu_ctrl_type {
11	VIRTIO_GPU_UNDEFINED = 0,
12
13	VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100,
14	VIRTIO_GPU_CMD_RESOURCE_CREATE_2D,
15	VIRTIO_GPU_CMD_RESOURCE_UNREF,
16	VIRTIO_GPU_CMD_SET_SCANOUT,
17	VIRTIO_GPU_CMD_RESOURCE_FLUSH,
18	VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D,
19	VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING,
20	VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING,
21	VIRTIO_GPU_CMD_GET_CAPSET_INFO,
22	VIRTIO_GPU_CMD_GET_CAPSET,
23
24	VIRTIO_GPU_CMD_CTX_CREATE = 0x0200,
25	VIRTIO_GPU_CMD_CTX_DESTROY,
26	VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE,
27	VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE,
28	VIRTIO_GPU_CMD_RESOURCE_CREATE_3D,
29	VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D,
30	VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D,
31	VIRTIO_GPU_CMD_SUBMIT_3D,
32
33	VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300,
34	VIRTIO_GPU_CMD_MOVE_CURSOR,
35
36	VIRTIO_GPU_RESP_OK_NODATA = 0x1100,
37	VIRTIO_GPU_RESP_OK_DISPLAY_INFO,
38	VIRTIO_GPU_RESP_OK_CAPSET_INFO,
39	VIRTIO_GPU_RESP_OK_CAPSET,
40
41	VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200,
42	VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY,
43	VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID,
44	VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID,
45	VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID,
46	VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER,
47};
48#define VIRTIO_GPU_FLAG_FENCE (1 << 0)
49struct virtio_gpu_ctrl_hdr {
50	__le32 type;
51	__le32 flags;
52	__le64 fence_id;
53	__le32 ctx_id;
54	__le32 padding;
55};
56struct virtio_gpu_cursor_pos {
57	__le32 scanout_id;
58	__le32 x;
59	__le32 y;
60	__le32 padding;
61};
62struct virtio_gpu_update_cursor {
63	struct virtio_gpu_ctrl_hdr hdr;
64	struct virtio_gpu_cursor_pos pos;
65	__le32 resource_id;
66	__le32 hot_x;
67	__le32 hot_y;
68	__le32 padding;
69};
70struct virtio_gpu_rect {
71	__le32 x;
72	__le32 y;
73	__le32 width;
74	__le32 height;
75};
76struct virtio_gpu_resource_unref {
77	struct virtio_gpu_ctrl_hdr hdr;
78	__le32 resource_id;
79	__le32 padding;
80};
81struct virtio_gpu_resource_create_2d {
82	struct virtio_gpu_ctrl_hdr hdr;
83	__le32 resource_id;
84	__le32 format;
85	__le32 width;
86	__le32 height;
87};
88struct virtio_gpu_set_scanout {
89	struct virtio_gpu_ctrl_hdr hdr;
90	struct virtio_gpu_rect r;
91	__le32 scanout_id;
92	__le32 resource_id;
93};
94struct virtio_gpu_resource_flush {
95	struct virtio_gpu_ctrl_hdr hdr;
96	struct virtio_gpu_rect r;
97	__le32 resource_id;
98	__le32 padding;
99};
100struct virtio_gpu_transfer_to_host_2d {
101	struct virtio_gpu_ctrl_hdr hdr;
102	struct virtio_gpu_rect r;
103	__le64 offset;
104	__le32 resource_id;
105	__le32 padding;
106};
107struct virtio_gpu_mem_entry {
108	__le64 addr;
109	__le32 length;
110	__le32 padding;
111};
112struct virtio_gpu_resource_attach_backing {
113	struct virtio_gpu_ctrl_hdr hdr;
114	__le32 resource_id;
115	__le32 nr_entries;
116};
117struct virtio_gpu_resource_detach_backing {
118	struct virtio_gpu_ctrl_hdr hdr;
119	__le32 resource_id;
120	__le32 padding;
121};
122#define VIRTIO_GPU_MAX_SCANOUTS 16
123struct virtio_gpu_resp_display_info {
124	struct virtio_gpu_ctrl_hdr hdr;
125	struct virtio_gpu_display_one {
126		struct virtio_gpu_rect r;
127		__le32 enabled;
128		__le32 flags;
129	} pmodes[VIRTIO_GPU_MAX_SCANOUTS];
130};
131struct virtio_gpu_box {
132	__le32 x, y, z;
133	__le32 w, h, d;
134};
135struct virtio_gpu_transfer_host_3d {
136	struct virtio_gpu_ctrl_hdr hdr;
137	struct virtio_gpu_box box;
138	__le64 offset;
139	__le32 resource_id;
140	__le32 level;
141	__le32 stride;
142	__le32 layer_stride;
143};
144#define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0)
145struct virtio_gpu_resource_create_3d {
146	struct virtio_gpu_ctrl_hdr hdr;
147	__le32 resource_id;
148	__le32 target;
149	__le32 format;
150	__le32 bind;
151	__le32 width;
152	__le32 height;
153	__le32 depth;
154	__le32 array_size;
155	__le32 last_level;
156	__le32 nr_samples;
157	__le32 flags;
158	__le32 padding;
159};
160struct virtio_gpu_ctx_create {
161	struct virtio_gpu_ctrl_hdr hdr;
162	__le32 nlen;
163	__le32 padding;
164	char debug_name[64];
165};
166struct virtio_gpu_ctx_destroy {
167	struct virtio_gpu_ctrl_hdr hdr;
168};
169struct virtio_gpu_ctx_resource {
170	struct virtio_gpu_ctrl_hdr hdr;
171	__le32 resource_id;
172	__le32 padding;
173};
174struct virtio_gpu_cmd_submit {
175	struct virtio_gpu_ctrl_hdr hdr;
176	__le32 size;
177	__le32 padding;
178};
179#define VIRTIO_GPU_CAPSET_VIRGL 1
180#define VIRTIO_GPU_CAPSET_VIRGL2 2
181struct virtio_gpu_get_capset_info {
182	struct virtio_gpu_ctrl_hdr hdr;
183	__le32 capset_index;
184	__le32 padding;
185};
186struct virtio_gpu_resp_capset_info {
187	struct virtio_gpu_ctrl_hdr hdr;
188	__le32 capset_id;
189	__le32 capset_max_version;
190	__le32 capset_max_size;
191	__le32 padding;
192};
193struct virtio_gpu_get_capset {
194	struct virtio_gpu_ctrl_hdr hdr;
195	__le32 capset_id;
196	__le32 capset_version;
197};
198struct virtio_gpu_resp_capset {
199	struct virtio_gpu_ctrl_hdr hdr;
200	__u8 capset_data[];
201};
202#define VIRTIO_GPU_EVENT_DISPLAY (1 << 0)
203struct virtio_gpu_config {
204	__u32 events_read;
205	__u32 events_clear;
206	__u32 num_scanouts;
207	__u32 num_capsets;
208};
209enum virtio_gpu_formats {
210	VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM  = 1,
211	VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM  = 2,
212	VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM  = 3,
213	VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM  = 4,
214	VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM  = 67,
215	VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM  = 68,
216	VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM  = 121,
217	VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM  = 134,
218};
219#endif
220