1/* 2 * This header was generated from the Linux kernel headers by update_headers.py, 3 * to provide necessary information from kernel to userspace, such as constants, 4 * structures, and macros, and thus, contains no copyrightable information. 5 */ 6#ifndef _UAPI_VC4_DRM_H_ 7#define _UAPI_VC4_DRM_H_ 8#include "drm.h" 9#if defined(__cplusplus) 10extern "C" { 11#endif 12#define DRM_VC4_SUBMIT_CL 0x00 13#define DRM_VC4_WAIT_SEQNO 0x01 14#define DRM_VC4_WAIT_BO 0x02 15#define DRM_VC4_CREATE_BO 0x03 16#define DRM_VC4_MMAP_BO 0x04 17#define DRM_VC4_CREATE_SHADER_BO 0x05 18#define DRM_VC4_GET_HANG_STATE 0x06 19#define DRM_VC4_GET_PARAM 0x07 20#define DRM_VC4_SET_TILING 0x08 21#define DRM_VC4_GET_TILING 0x09 22#define DRM_VC4_LABEL_BO 0x0a 23#define DRM_VC4_GEM_MADVISE 0x0b 24#define DRM_VC4_PERFMON_CREATE 0x0c 25#define DRM_VC4_PERFMON_DESTROY 0x0d 26#define DRM_VC4_PERFMON_GET_VALUES 0x0e 27#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl) 28#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno) 29#define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo) 30#define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo) 31#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo) 32#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo) 33#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state) 34#define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param) 35#define DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling) 36#define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling) 37#define DRM_IOCTL_VC4_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_LABEL_BO, struct drm_vc4_label_bo) 38#define DRM_IOCTL_VC4_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GEM_MADVISE, struct drm_vc4_gem_madvise) 39#define DRM_IOCTL_VC4_PERFMON_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_CREATE, struct drm_vc4_perfmon_create) 40#define DRM_IOCTL_VC4_PERFMON_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_DESTROY, struct drm_vc4_perfmon_destroy) 41#define DRM_IOCTL_VC4_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_GET_VALUES, struct drm_vc4_perfmon_get_values) 42struct drm_vc4_submit_rcl_surface { 43 __u32 hindex; 44 __u32 offset; 45 46 __u16 bits; 47#define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0) 48 __u16 flags; 49}; 50struct drm_vc4_submit_cl { 51 52 __u64 bin_cl; 53 54 __u64 shader_rec; 55 56 __u64 uniforms; 57 __u64 bo_handles; 58 59 __u32 bin_cl_size; 60 61 __u32 shader_rec_size; 62 63 __u32 shader_rec_count; 64 65 __u32 uniforms_size; 66 67 __u32 bo_handle_count; 68 69 __u16 width; 70 __u16 height; 71 __u8 min_x_tile; 72 __u8 min_y_tile; 73 __u8 max_x_tile; 74 __u8 max_y_tile; 75 struct drm_vc4_submit_rcl_surface color_read; 76 struct drm_vc4_submit_rcl_surface color_write; 77 struct drm_vc4_submit_rcl_surface zs_read; 78 struct drm_vc4_submit_rcl_surface zs_write; 79 struct drm_vc4_submit_rcl_surface msaa_color_write; 80 struct drm_vc4_submit_rcl_surface msaa_zs_write; 81 __u32 clear_color[2]; 82 __u32 clear_z; 83 __u8 clear_s; 84 __u32 pad:24; 85#define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0) 86#define VC4_SUBMIT_CL_FIXED_RCL_ORDER (1 << 1) 87#define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X (1 << 2) 88#define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y (1 << 3) 89 __u32 flags; 90 91 __u64 seqno; 92 93 __u32 perfmonid; 94 95 __u32 in_sync; 96 97 __u32 out_sync; 98 __u32 pad2; 99}; 100struct drm_vc4_wait_seqno { 101 __u64 seqno; 102 __u64 timeout_ns; 103}; 104struct drm_vc4_wait_bo { 105 __u32 handle; 106 __u32 pad; 107 __u64 timeout_ns; 108}; 109struct drm_vc4_create_bo { 110 __u32 size; 111 __u32 flags; 112 113 __u32 handle; 114 __u32 pad; 115}; 116struct drm_vc4_mmap_bo { 117 118 __u32 handle; 119 __u32 flags; 120 121 __u64 offset; 122}; 123struct drm_vc4_create_shader_bo { 124 125 __u32 size; 126 127 __u32 flags; 128 129 __u64 data; 130 131 __u32 handle; 132 133 __u32 pad; 134}; 135struct drm_vc4_get_hang_state_bo { 136 __u32 handle; 137 __u32 paddr; 138 __u32 size; 139 __u32 pad; 140}; 141struct drm_vc4_get_hang_state { 142 143 __u64 bo; 144 145 __u32 bo_count; 146 __u32 start_bin, start_render; 147 __u32 ct0ca, ct0ea; 148 __u32 ct1ca, ct1ea; 149 __u32 ct0cs, ct1cs; 150 __u32 ct0ra0, ct1ra0; 151 __u32 bpca, bpcs; 152 __u32 bpoa, bpos; 153 __u32 vpmbase; 154 __u32 dbge; 155 __u32 fdbgo; 156 __u32 fdbgb; 157 __u32 fdbgr; 158 __u32 fdbgs; 159 __u32 errstat; 160 161 __u32 pad[16]; 162}; 163#define DRM_VC4_PARAM_V3D_IDENT0 0 164#define DRM_VC4_PARAM_V3D_IDENT1 1 165#define DRM_VC4_PARAM_V3D_IDENT2 2 166#define DRM_VC4_PARAM_SUPPORTS_BRANCHES 3 167#define DRM_VC4_PARAM_SUPPORTS_ETC1 4 168#define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5 169#define DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER 6 170#define DRM_VC4_PARAM_SUPPORTS_MADVISE 7 171#define DRM_VC4_PARAM_SUPPORTS_PERFMON 8 172struct drm_vc4_get_param { 173 __u32 param; 174 __u32 pad; 175 __u64 value; 176}; 177struct drm_vc4_get_tiling { 178 __u32 handle; 179 __u32 flags; 180 __u64 modifier; 181}; 182struct drm_vc4_set_tiling { 183 __u32 handle; 184 __u32 flags; 185 __u64 modifier; 186}; 187struct drm_vc4_label_bo { 188 __u32 handle; 189 __u32 len; 190 __u64 name; 191}; 192#define VC4_MADV_WILLNEED 0 193#define VC4_MADV_DONTNEED 1 194#define __VC4_MADV_PURGED 2 195#define __VC4_MADV_NOTSUPP 3 196struct drm_vc4_gem_madvise { 197 __u32 handle; 198 __u32 madv; 199 __u32 retained; 200 __u32 pad; 201}; 202enum { 203 VC4_PERFCNT_FEP_VALID_PRIMS_NO_RENDER, 204 VC4_PERFCNT_FEP_VALID_PRIMS_RENDER, 205 VC4_PERFCNT_FEP_CLIPPED_QUADS, 206 VC4_PERFCNT_FEP_VALID_QUADS, 207 VC4_PERFCNT_TLB_QUADS_NOT_PASSING_STENCIL, 208 VC4_PERFCNT_TLB_QUADS_NOT_PASSING_Z_AND_STENCIL, 209 VC4_PERFCNT_TLB_QUADS_PASSING_Z_AND_STENCIL, 210 VC4_PERFCNT_TLB_QUADS_ZERO_COVERAGE, 211 VC4_PERFCNT_TLB_QUADS_NON_ZERO_COVERAGE, 212 VC4_PERFCNT_TLB_QUADS_WRITTEN_TO_COLOR_BUF, 213 VC4_PERFCNT_PLB_PRIMS_OUTSIDE_VIEWPORT, 214 VC4_PERFCNT_PLB_PRIMS_NEED_CLIPPING, 215 VC4_PERFCNT_PSE_PRIMS_REVERSED, 216 VC4_PERFCNT_QPU_TOTAL_IDLE_CYCLES, 217 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_VERTEX_COORD_SHADING, 218 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_FRAGMENT_SHADING, 219 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_EXEC_VALID_INST, 220 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_TMUS, 221 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_SCOREBOARD, 222 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_VARYINGS, 223 VC4_PERFCNT_QPU_TOTAL_INST_CACHE_HIT, 224 VC4_PERFCNT_QPU_TOTAL_INST_CACHE_MISS, 225 VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_HIT, 226 VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_MISS, 227 VC4_PERFCNT_TMU_TOTAL_TEXT_QUADS_PROCESSED, 228 VC4_PERFCNT_TMU_TOTAL_TEXT_CACHE_MISS, 229 VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VDW_STALLED, 230 VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VCD_STALLED, 231 VC4_PERFCNT_L2C_TOTAL_L2_CACHE_HIT, 232 VC4_PERFCNT_L2C_TOTAL_L2_CACHE_MISS, 233 VC4_PERFCNT_NUM_EVENTS, 234}; 235#define DRM_VC4_MAX_PERF_COUNTERS 16 236struct drm_vc4_perfmon_create { 237 __u32 id; 238 __u32 ncounters; 239 __u8 events[DRM_VC4_MAX_PERF_COUNTERS]; 240}; 241struct drm_vc4_perfmon_destroy { 242 __u32 id; 243}; 244struct drm_vc4_perfmon_get_values { 245 __u32 id; 246 __u64 values_ptr; 247}; 248#if defined(__cplusplus) 249} 250#endif 251#endif 252