1/* 2 * This header was generated from the Linux kernel headers by update_headers.py, 3 * to provide necessary information from kernel to userspace, such as constants, 4 * structures, and macros, and thus, contains no copyrightable information. 5 */ 6#ifndef _UAPI_I915_DRM_H_ 7#define _UAPI_I915_DRM_H_ 8#include "drm.h" 9#if defined(__cplusplus) 10extern "C" { 11#endif 12#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" 13#define I915_ERROR_UEVENT "ERROR" 14#define I915_RESET_UEVENT "RESET" 15enum i915_mocs_table_index { 16 17 I915_MOCS_UNCACHED, 18 19 I915_MOCS_PTE, 20 21 I915_MOCS_CACHED, 22}; 23enum drm_i915_gem_engine_class { 24 I915_ENGINE_CLASS_RENDER = 0, 25 I915_ENGINE_CLASS_COPY = 1, 26 I915_ENGINE_CLASS_VIDEO = 2, 27 I915_ENGINE_CLASS_VIDEO_ENHANCE = 3, 28 I915_ENGINE_CLASS_INVALID = -1 29}; 30enum drm_i915_pmu_engine_sample { 31 I915_SAMPLE_BUSY = 0, 32 I915_SAMPLE_WAIT = 1, 33 I915_SAMPLE_SEMA = 2 34}; 35#define I915_PMU_SAMPLE_BITS (4) 36#define I915_PMU_SAMPLE_MASK (0xf) 37#define I915_PMU_SAMPLE_INSTANCE_BITS (8) 38#define I915_PMU_CLASS_SHIFT \ 39 (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS) 40#define __I915_PMU_ENGINE(class, instance, sample) \ 41 ((class) << I915_PMU_CLASS_SHIFT | \ 42 (instance) << I915_PMU_SAMPLE_BITS | \ 43 (sample)) 44#define I915_PMU_ENGINE_BUSY(class, instance) \ 45 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY) 46#define I915_PMU_ENGINE_WAIT(class, instance) \ 47 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT) 48#define I915_PMU_ENGINE_SEMA(class, instance) \ 49 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA) 50#define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) 51#define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0) 52#define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1) 53#define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2) 54#define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3) 55#define I915_PMU_LAST I915_PMU_RC6_RESIDENCY 56#define I915_NR_TEX_REGIONS 255 57#define I915_LOG_MIN_TEX_REGION_SIZE 14 58typedef struct _drm_i915_init { 59 enum { 60 I915_INIT_DMA = 0x01, 61 I915_CLEANUP_DMA = 0x02, 62 I915_RESUME_DMA = 0x03 63 } func; 64 unsigned int mmio_offset; 65 int sarea_priv_offset; 66 unsigned int ring_start; 67 unsigned int ring_end; 68 unsigned int ring_size; 69 unsigned int front_offset; 70 unsigned int back_offset; 71 unsigned int depth_offset; 72 unsigned int w; 73 unsigned int h; 74 unsigned int pitch; 75 unsigned int pitch_bits; 76 unsigned int back_pitch; 77 unsigned int depth_pitch; 78 unsigned int cpp; 79 unsigned int chipset; 80} drm_i915_init_t; 81typedef struct _drm_i915_sarea { 82 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 83 int last_upload; 84 int last_enqueue; 85 int last_dispatch; 86 int ctxOwner; 87 int texAge; 88 int pf_enabled; 89 int pf_active; 90 int pf_current_page; 91 int perf_boxes; 92 int width, height; 93 drm_handle_t front_handle; 94 int front_offset; 95 int front_size; 96 drm_handle_t back_handle; 97 int back_offset; 98 int back_size; 99 drm_handle_t depth_handle; 100 int depth_offset; 101 int depth_size; 102 drm_handle_t tex_handle; 103 int tex_offset; 104 int tex_size; 105 int log_tex_granularity; 106 int pitch; 107 int rotation; 108 int rotated_offset; 109 int rotated_size; 110 int rotated_pitch; 111 int virtualX, virtualY; 112 unsigned int front_tiled; 113 unsigned int back_tiled; 114 unsigned int depth_tiled; 115 unsigned int rotated_tiled; 116 unsigned int rotated2_tiled; 117 int pipeA_x; 118 int pipeA_y; 119 int pipeA_w; 120 int pipeA_h; 121 int pipeB_x; 122 int pipeB_y; 123 int pipeB_w; 124 int pipeB_h; 125 126 drm_handle_t unused_handle; 127 __u32 unused1, unused2, unused3; 128 129 __u32 front_bo_handle; 130 __u32 back_bo_handle; 131 __u32 unused_bo_handle; 132 __u32 depth_bo_handle; 133} drm_i915_sarea_t; 134#define planeA_x pipeA_x 135#define planeA_y pipeA_y 136#define planeA_w pipeA_w 137#define planeA_h pipeA_h 138#define planeB_x pipeB_x 139#define planeB_y pipeB_y 140#define planeB_w pipeB_w 141#define planeB_h pipeB_h 142#define I915_BOX_RING_EMPTY 0x1 143#define I915_BOX_FLIP 0x2 144#define I915_BOX_WAIT 0x4 145#define I915_BOX_TEXTURE_LOAD 0x8 146#define I915_BOX_LOST_CONTEXT 0x10 147#define DRM_I915_INIT 0x00 148#define DRM_I915_FLUSH 0x01 149#define DRM_I915_FLIP 0x02 150#define DRM_I915_BATCHBUFFER 0x03 151#define DRM_I915_IRQ_EMIT 0x04 152#define DRM_I915_IRQ_WAIT 0x05 153#define DRM_I915_GETPARAM 0x06 154#define DRM_I915_SETPARAM 0x07 155#define DRM_I915_ALLOC 0x08 156#define DRM_I915_FREE 0x09 157#define DRM_I915_INIT_HEAP 0x0a 158#define DRM_I915_CMDBUFFER 0x0b 159#define DRM_I915_DESTROY_HEAP 0x0c 160#define DRM_I915_SET_VBLANK_PIPE 0x0d 161#define DRM_I915_GET_VBLANK_PIPE 0x0e 162#define DRM_I915_VBLANK_SWAP 0x0f 163#define DRM_I915_HWS_ADDR 0x11 164#define DRM_I915_GEM_INIT 0x13 165#define DRM_I915_GEM_EXECBUFFER 0x14 166#define DRM_I915_GEM_PIN 0x15 167#define DRM_I915_GEM_UNPIN 0x16 168#define DRM_I915_GEM_BUSY 0x17 169#define DRM_I915_GEM_THROTTLE 0x18 170#define DRM_I915_GEM_ENTERVT 0x19 171#define DRM_I915_GEM_LEAVEVT 0x1a 172#define DRM_I915_GEM_CREATE 0x1b 173#define DRM_I915_GEM_PREAD 0x1c 174#define DRM_I915_GEM_PWRITE 0x1d 175#define DRM_I915_GEM_MMAP 0x1e 176#define DRM_I915_GEM_SET_DOMAIN 0x1f 177#define DRM_I915_GEM_SW_FINISH 0x20 178#define DRM_I915_GEM_SET_TILING 0x21 179#define DRM_I915_GEM_GET_TILING 0x22 180#define DRM_I915_GEM_GET_APERTURE 0x23 181#define DRM_I915_GEM_MMAP_GTT 0x24 182#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 183#define DRM_I915_GEM_MADVISE 0x26 184#define DRM_I915_OVERLAY_PUT_IMAGE 0x27 185#define DRM_I915_OVERLAY_ATTRS 0x28 186#define DRM_I915_GEM_EXECBUFFER2 0x29 187#define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2 188#define DRM_I915_GET_SPRITE_COLORKEY 0x2a 189#define DRM_I915_SET_SPRITE_COLORKEY 0x2b 190#define DRM_I915_GEM_WAIT 0x2c 191#define DRM_I915_GEM_CONTEXT_CREATE 0x2d 192#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 193#define DRM_I915_GEM_SET_CACHING 0x2f 194#define DRM_I915_GEM_GET_CACHING 0x30 195#define DRM_I915_REG_READ 0x31 196#define DRM_I915_GET_RESET_STATS 0x32 197#define DRM_I915_GEM_USERPTR 0x33 198#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 199#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 200#define DRM_I915_PERF_OPEN 0x36 201#define DRM_I915_PERF_ADD_CONFIG 0x37 202#define DRM_I915_PERF_REMOVE_CONFIG 0x38 203#define DRM_I915_QUERY 0x39 204#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 205#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 206#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 207#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 208#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 209#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 210#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 211#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 212#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 213#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 214#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 215#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 216#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 217#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 218#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 219#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 220#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 221#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 222#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 223#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 224#define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2) 225#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 226#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 227#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 228#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 229#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 230#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 231#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 232#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 233#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 234#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 235#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 236#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 237#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 238#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 239#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 240#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 241#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 242#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 243#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 244#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 245#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 246#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 247#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 248#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 249#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 250#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 251#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 252#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 253#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) 254#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) 255#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) 256#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) 257#define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param) 258#define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config) 259#define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64) 260#define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query) 261typedef struct drm_i915_batchbuffer { 262 int start; 263 int used; 264 int DR1; 265 int DR4; 266 int num_cliprects; 267 struct drm_clip_rect __user *cliprects; 268} drm_i915_batchbuffer_t; 269typedef struct _drm_i915_cmdbuffer { 270 char __user *buf; 271 int sz; 272 int DR1; 273 int DR4; 274 int num_cliprects; 275 struct drm_clip_rect __user *cliprects; 276} drm_i915_cmdbuffer_t; 277typedef struct drm_i915_irq_emit { 278 int __user *irq_seq; 279} drm_i915_irq_emit_t; 280typedef struct drm_i915_irq_wait { 281 int irq_seq; 282} drm_i915_irq_wait_t; 283#define I915_PARAM_IRQ_ACTIVE 1 284#define I915_PARAM_ALLOW_BATCHBUFFER 2 285#define I915_PARAM_LAST_DISPATCH 3 286#define I915_PARAM_CHIPSET_ID 4 287#define I915_PARAM_HAS_GEM 5 288#define I915_PARAM_NUM_FENCES_AVAIL 6 289#define I915_PARAM_HAS_OVERLAY 7 290#define I915_PARAM_HAS_PAGEFLIPPING 8 291#define I915_PARAM_HAS_EXECBUF2 9 292#define I915_PARAM_HAS_BSD 10 293#define I915_PARAM_HAS_BLT 11 294#define I915_PARAM_HAS_RELAXED_FENCING 12 295#define I915_PARAM_HAS_COHERENT_RINGS 13 296#define I915_PARAM_HAS_EXEC_CONSTANTS 14 297#define I915_PARAM_HAS_RELAXED_DELTA 15 298#define I915_PARAM_HAS_GEN7_SOL_RESET 16 299#define I915_PARAM_HAS_LLC 17 300#define I915_PARAM_HAS_ALIASING_PPGTT 18 301#define I915_PARAM_HAS_WAIT_TIMEOUT 19 302#define I915_PARAM_HAS_SEMAPHORES 20 303#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 304#define I915_PARAM_HAS_VEBOX 22 305#define I915_PARAM_HAS_SECURE_BATCHES 23 306#define I915_PARAM_HAS_PINNED_BATCHES 24 307#define I915_PARAM_HAS_EXEC_NO_RELOC 25 308#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 309#define I915_PARAM_HAS_WT 27 310#define I915_PARAM_CMD_PARSER_VERSION 28 311#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 312#define I915_PARAM_MMAP_VERSION 30 313#define I915_PARAM_HAS_BSD2 31 314#define I915_PARAM_REVISION 32 315#define I915_PARAM_SUBSLICE_TOTAL 33 316#define I915_PARAM_EU_TOTAL 34 317#define I915_PARAM_HAS_GPU_RESET 35 318#define I915_PARAM_HAS_RESOURCE_STREAMER 36 319#define I915_PARAM_HAS_EXEC_SOFTPIN 37 320#define I915_PARAM_HAS_POOLED_EU 38 321#define I915_PARAM_MIN_EU_IN_POOL 39 322#define I915_PARAM_MMAP_GTT_VERSION 40 323#define I915_PARAM_HAS_SCHEDULER 41 324#define I915_SCHEDULER_CAP_ENABLED (1ul << 0) 325#define I915_SCHEDULER_CAP_PRIORITY (1ul << 1) 326#define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) 327#define I915_PARAM_HUC_STATUS 42 328#define I915_PARAM_HAS_EXEC_ASYNC 43 329#define I915_PARAM_HAS_EXEC_FENCE 44 330#define I915_PARAM_HAS_EXEC_CAPTURE 45 331#define I915_PARAM_SLICE_MASK 46 332#define I915_PARAM_SUBSLICE_MASK 47 333#define I915_PARAM_HAS_EXEC_BATCH_FIRST 48 334#define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49 335#define I915_PARAM_HAS_CONTEXT_ISOLATION 50 336#define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51 337typedef struct drm_i915_getparam { 338 __s32 param; 339 340 int __user *value; 341} drm_i915_getparam_t; 342#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 343#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 344#define I915_SETPARAM_ALLOW_BATCHBUFFER 3 345#define I915_SETPARAM_NUM_USED_FENCES 4 346typedef struct drm_i915_setparam { 347 int param; 348 int value; 349} drm_i915_setparam_t; 350#define I915_MEM_REGION_AGP 1 351typedef struct drm_i915_mem_alloc { 352 int region; 353 int alignment; 354 int size; 355 int __user *region_offset; 356} drm_i915_mem_alloc_t; 357typedef struct drm_i915_mem_free { 358 int region; 359 int region_offset; 360} drm_i915_mem_free_t; 361typedef struct drm_i915_mem_init_heap { 362 int region; 363 int size; 364 int start; 365} drm_i915_mem_init_heap_t; 366typedef struct drm_i915_mem_destroy_heap { 367 int region; 368} drm_i915_mem_destroy_heap_t; 369#define DRM_I915_VBLANK_PIPE_A 1 370#define DRM_I915_VBLANK_PIPE_B 2 371typedef struct drm_i915_vblank_pipe { 372 int pipe; 373} drm_i915_vblank_pipe_t; 374typedef struct drm_i915_vblank_swap { 375 drm_drawable_t drawable; 376 enum drm_vblank_seq_type seqtype; 377 unsigned int sequence; 378} drm_i915_vblank_swap_t; 379typedef struct drm_i915_hws_addr { 380 __u64 addr; 381} drm_i915_hws_addr_t; 382struct drm_i915_gem_init { 383 384 __u64 gtt_start; 385 386 __u64 gtt_end; 387}; 388struct drm_i915_gem_create { 389 390 __u64 size; 391 392 __u32 handle; 393 __u32 pad; 394}; 395struct drm_i915_gem_pread { 396 397 __u32 handle; 398 __u32 pad; 399 400 __u64 offset; 401 402 __u64 size; 403 404 __u64 data_ptr; 405}; 406struct drm_i915_gem_pwrite { 407 408 __u32 handle; 409 __u32 pad; 410 411 __u64 offset; 412 413 __u64 size; 414 415 __u64 data_ptr; 416}; 417struct drm_i915_gem_mmap { 418 419 __u32 handle; 420 __u32 pad; 421 422 __u64 offset; 423 424 __u64 size; 425 426 __u64 addr_ptr; 427 428 __u64 flags; 429#define I915_MMAP_WC 0x1 430}; 431struct drm_i915_gem_mmap_gtt { 432 433 __u32 handle; 434 __u32 pad; 435 436 __u64 offset; 437}; 438struct drm_i915_gem_set_domain { 439 440 __u32 handle; 441 442 __u32 read_domains; 443 444 __u32 write_domain; 445}; 446struct drm_i915_gem_sw_finish { 447 448 __u32 handle; 449}; 450struct drm_i915_gem_relocation_entry { 451 452 __u32 target_handle; 453 454 __u32 delta; 455 456 __u64 offset; 457 458 __u64 presumed_offset; 459 460 __u32 read_domains; 461 462 __u32 write_domain; 463}; 464#define I915_GEM_DOMAIN_CPU 0x00000001 465#define I915_GEM_DOMAIN_RENDER 0x00000002 466#define I915_GEM_DOMAIN_SAMPLER 0x00000004 467#define I915_GEM_DOMAIN_COMMAND 0x00000008 468#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 469#define I915_GEM_DOMAIN_VERTEX 0x00000020 470#define I915_GEM_DOMAIN_GTT 0x00000040 471#define I915_GEM_DOMAIN_WC 0x00000080 472struct drm_i915_gem_exec_object { 473 474 __u32 handle; 475 476 __u32 relocation_count; 477 478 __u64 relocs_ptr; 479 480 __u64 alignment; 481 482 __u64 offset; 483}; 484struct drm_i915_gem_execbuffer { 485 486 __u64 buffers_ptr; 487 __u32 buffer_count; 488 489 __u32 batch_start_offset; 490 491 __u32 batch_len; 492 __u32 DR1; 493 __u32 DR4; 494 __u32 num_cliprects; 495 496 __u64 cliprects_ptr; 497}; 498struct drm_i915_gem_exec_object2 { 499 500 __u32 handle; 501 502 __u32 relocation_count; 503 504 __u64 relocs_ptr; 505 506 __u64 alignment; 507 508 __u64 offset; 509#define EXEC_OBJECT_NEEDS_FENCE (1<<0) 510#define EXEC_OBJECT_NEEDS_GTT (1<<1) 511#define EXEC_OBJECT_WRITE (1<<2) 512#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3) 513#define EXEC_OBJECT_PINNED (1<<4) 514#define EXEC_OBJECT_PAD_TO_SIZE (1<<5) 515#define EXEC_OBJECT_ASYNC (1<<6) 516#define EXEC_OBJECT_CAPTURE (1<<7) 517#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1) 518 __u64 flags; 519 union { 520 __u64 rsvd1; 521 __u64 pad_to_size; 522 }; 523 __u64 rsvd2; 524}; 525struct drm_i915_gem_exec_fence { 526 527 __u32 handle; 528#define I915_EXEC_FENCE_WAIT (1<<0) 529#define I915_EXEC_FENCE_SIGNAL (1<<1) 530#define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1)) 531 __u32 flags; 532}; 533struct drm_i915_gem_execbuffer2 { 534 535 __u64 buffers_ptr; 536 __u32 buffer_count; 537 538 __u32 batch_start_offset; 539 540 __u32 batch_len; 541 __u32 DR1; 542 __u32 DR4; 543 __u32 num_cliprects; 544 545 __u64 cliprects_ptr; 546#define I915_EXEC_RING_MASK (0x3f) 547#define I915_EXEC_DEFAULT (0<<0) 548#define I915_EXEC_RENDER (1<<0) 549#define I915_EXEC_BSD (2<<0) 550#define I915_EXEC_BLT (3<<0) 551#define I915_EXEC_VEBOX (4<<0) 552#define I915_EXEC_CONSTANTS_MASK (3<<6) 553#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) 554#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 555#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) 556 __u64 flags; 557 __u64 rsvd1; 558 __u64 rsvd2; 559}; 560#define I915_EXEC_GEN7_SOL_RESET (1<<8) 561#define I915_EXEC_SECURE (1<<9) 562#define I915_EXEC_IS_PINNED (1<<10) 563#define I915_EXEC_NO_RELOC (1<<11) 564#define I915_EXEC_HANDLE_LUT (1<<12) 565#define I915_EXEC_BSD_SHIFT (13) 566#define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT) 567#define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT) 568#define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT) 569#define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT) 570#define I915_EXEC_RESOURCE_STREAMER (1<<15) 571#define I915_EXEC_FENCE_IN (1<<16) 572#define I915_EXEC_FENCE_OUT (1<<17) 573#define I915_EXEC_BATCH_FIRST (1<<18) 574#define I915_EXEC_FENCE_ARRAY (1<<19) 575#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_ARRAY<<1)) 576#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 577#define i915_execbuffer2_set_context_id(eb2, context) \ 578 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 579#define i915_execbuffer2_get_context_id(eb2) \ 580 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 581struct drm_i915_gem_pin { 582 583 __u32 handle; 584 __u32 pad; 585 586 __u64 alignment; 587 588 __u64 offset; 589}; 590struct drm_i915_gem_unpin { 591 592 __u32 handle; 593 __u32 pad; 594}; 595struct drm_i915_gem_busy { 596 597 __u32 handle; 598 599 __u32 busy; 600}; 601#define I915_CACHING_NONE 0 602#define I915_CACHING_CACHED 1 603#define I915_CACHING_DISPLAY 2 604struct drm_i915_gem_caching { 605 606 __u32 handle; 607 608 __u32 caching; 609}; 610#define I915_TILING_NONE 0 611#define I915_TILING_X 1 612#define I915_TILING_Y 2 613#define I915_TILING_LAST I915_TILING_Y 614#define I915_BIT_6_SWIZZLE_NONE 0 615#define I915_BIT_6_SWIZZLE_9 1 616#define I915_BIT_6_SWIZZLE_9_10 2 617#define I915_BIT_6_SWIZZLE_9_11 3 618#define I915_BIT_6_SWIZZLE_9_10_11 4 619#define I915_BIT_6_SWIZZLE_UNKNOWN 5 620#define I915_BIT_6_SWIZZLE_9_17 6 621#define I915_BIT_6_SWIZZLE_9_10_17 7 622struct drm_i915_gem_set_tiling { 623 624 __u32 handle; 625 626 __u32 tiling_mode; 627 628 __u32 stride; 629 630 __u32 swizzle_mode; 631}; 632struct drm_i915_gem_get_tiling { 633 634 __u32 handle; 635 636 __u32 tiling_mode; 637 638 __u32 swizzle_mode; 639 640 __u32 phys_swizzle_mode; 641}; 642struct drm_i915_gem_get_aperture { 643 644 __u64 aper_size; 645 646 __u64 aper_available_size; 647}; 648struct drm_i915_get_pipe_from_crtc_id { 649 650 __u32 crtc_id; 651 652 __u32 pipe; 653}; 654#define I915_MADV_WILLNEED 0 655#define I915_MADV_DONTNEED 1 656#define __I915_MADV_PURGED 2 657struct drm_i915_gem_madvise { 658 659 __u32 handle; 660 661 __u32 madv; 662 663 __u32 retained; 664}; 665#define I915_OVERLAY_TYPE_MASK 0xff 666#define I915_OVERLAY_YUV_PLANAR 0x01 667#define I915_OVERLAY_YUV_PACKED 0x02 668#define I915_OVERLAY_RGB 0x03 669#define I915_OVERLAY_DEPTH_MASK 0xff00 670#define I915_OVERLAY_RGB24 0x1000 671#define I915_OVERLAY_RGB16 0x2000 672#define I915_OVERLAY_RGB15 0x3000 673#define I915_OVERLAY_YUV422 0x0100 674#define I915_OVERLAY_YUV411 0x0200 675#define I915_OVERLAY_YUV420 0x0300 676#define I915_OVERLAY_YUV410 0x0400 677#define I915_OVERLAY_SWAP_MASK 0xff0000 678#define I915_OVERLAY_NO_SWAP 0x000000 679#define I915_OVERLAY_UV_SWAP 0x010000 680#define I915_OVERLAY_Y_SWAP 0x020000 681#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 682#define I915_OVERLAY_FLAGS_MASK 0xff000000 683#define I915_OVERLAY_ENABLE 0x01000000 684struct drm_intel_overlay_put_image { 685 686 __u32 flags; 687 688 __u32 bo_handle; 689 690 __u16 stride_Y; 691 __u16 stride_UV; 692 __u32 offset_Y; 693 __u32 offset_U; 694 __u32 offset_V; 695 696 __u16 src_width; 697 __u16 src_height; 698 699 __u16 src_scan_width; 700 __u16 src_scan_height; 701 702 __u32 crtc_id; 703 __u16 dst_x; 704 __u16 dst_y; 705 __u16 dst_width; 706 __u16 dst_height; 707}; 708#define I915_OVERLAY_UPDATE_ATTRS (1<<0) 709#define I915_OVERLAY_UPDATE_GAMMA (1<<1) 710#define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2) 711struct drm_intel_overlay_attrs { 712 __u32 flags; 713 __u32 color_key; 714 __s32 brightness; 715 __u32 contrast; 716 __u32 saturation; 717 __u32 gamma0; 718 __u32 gamma1; 719 __u32 gamma2; 720 __u32 gamma3; 721 __u32 gamma4; 722 __u32 gamma5; 723}; 724#define I915_SET_COLORKEY_NONE (1<<0) 725#define I915_SET_COLORKEY_DESTINATION (1<<1) 726#define I915_SET_COLORKEY_SOURCE (1<<2) 727struct drm_intel_sprite_colorkey { 728 __u32 plane_id; 729 __u32 min_value; 730 __u32 channel_mask; 731 __u32 max_value; 732 __u32 flags; 733}; 734struct drm_i915_gem_wait { 735 736 __u32 bo_handle; 737 __u32 flags; 738 739 __s64 timeout_ns; 740}; 741struct drm_i915_gem_context_create { 742 743 __u32 ctx_id; 744 __u32 pad; 745}; 746struct drm_i915_gem_context_destroy { 747 __u32 ctx_id; 748 __u32 pad; 749}; 750struct drm_i915_reg_read { 751 752 __u64 offset; 753#define I915_REG_READ_8B_WA (1ul << 0) 754 __u64 val; 755}; 756struct drm_i915_reset_stats { 757 __u32 ctx_id; 758 __u32 flags; 759 760 __u32 reset_count; 761 762 __u32 batch_active; 763 764 __u32 batch_pending; 765 __u32 pad; 766}; 767struct drm_i915_gem_userptr { 768 __u64 user_ptr; 769 __u64 user_size; 770 __u32 flags; 771#define I915_USERPTR_READ_ONLY 0x1 772#define I915_USERPTR_UNSYNCHRONIZED 0x80000000 773 774 __u32 handle; 775}; 776struct drm_i915_gem_context_param { 777 __u32 ctx_id; 778 __u32 size; 779 __u64 param; 780#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 781#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 782#define I915_CONTEXT_PARAM_GTT_SIZE 0x3 783#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4 784#define I915_CONTEXT_PARAM_BANNABLE 0x5 785#define I915_CONTEXT_PARAM_PRIORITY 0x6 786#define I915_CONTEXT_MAX_USER_PRIORITY 1023 787#define I915_CONTEXT_DEFAULT_PRIORITY 0 788#define I915_CONTEXT_MIN_USER_PRIORITY -1023 789 __u64 value; 790}; 791enum drm_i915_oa_format { 792 I915_OA_FORMAT_A13 = 1, 793 I915_OA_FORMAT_A29, 794 I915_OA_FORMAT_A13_B8_C8, 795 I915_OA_FORMAT_B4_C8, 796 I915_OA_FORMAT_A45_B8_C8, 797 I915_OA_FORMAT_B4_C8_A16, 798 I915_OA_FORMAT_C4_B8, 799 800 I915_OA_FORMAT_A12, 801 I915_OA_FORMAT_A12_B8_C8, 802 I915_OA_FORMAT_A32u40_A4u32_B8_C8, 803 I915_OA_FORMAT_MAX 804}; 805enum drm_i915_perf_property_id { 806 807 DRM_I915_PERF_PROP_CTX_HANDLE = 1, 808 809 DRM_I915_PERF_PROP_SAMPLE_OA, 810 811 DRM_I915_PERF_PROP_OA_METRICS_SET, 812 813 DRM_I915_PERF_PROP_OA_FORMAT, 814 815 DRM_I915_PERF_PROP_OA_EXPONENT, 816 DRM_I915_PERF_PROP_MAX 817}; 818struct drm_i915_perf_open_param { 819 __u32 flags; 820#define I915_PERF_FLAG_FD_CLOEXEC (1<<0) 821#define I915_PERF_FLAG_FD_NONBLOCK (1<<1) 822#define I915_PERF_FLAG_DISABLED (1<<2) 823 824 __u32 num_properties; 825 826 __u64 properties_ptr; 827}; 828#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0) 829#define I915_PERF_IOCTL_DISABLE _IO('i', 0x1) 830struct drm_i915_perf_record_header { 831 __u32 type; 832 __u16 pad; 833 __u16 size; 834}; 835enum drm_i915_perf_record_type { 836 837 DRM_I915_PERF_RECORD_SAMPLE = 1, 838 839 DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2, 840 841 DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3, 842 DRM_I915_PERF_RECORD_MAX 843}; 844struct drm_i915_perf_oa_config { 845 846 char uuid[36]; 847 __u32 n_mux_regs; 848 __u32 n_boolean_regs; 849 __u32 n_flex_regs; 850 851 __u64 mux_regs_ptr; 852 __u64 boolean_regs_ptr; 853 __u64 flex_regs_ptr; 854}; 855struct drm_i915_query_item { 856 __u64 query_id; 857#define DRM_I915_QUERY_TOPOLOGY_INFO 1 858 859 __s32 length; 860 861 __u32 flags; 862 863 __u64 data_ptr; 864}; 865struct drm_i915_query { 866 __u32 num_items; 867 868 __u32 flags; 869 870 __u64 items_ptr; 871}; 872struct drm_i915_query_topology_info { 873 874 __u16 flags; 875 __u16 max_slices; 876 __u16 max_subslices; 877 __u16 max_eus_per_subslice; 878 879 __u16 subslice_offset; 880 881 __u16 subslice_stride; 882 883 __u16 eu_offset; 884 885 __u16 eu_stride; 886 __u8 data[]; 887}; 888#if defined(__cplusplus) 889} 890#endif 891#endif 892