1/* 2 * This header was generated from the Linux kernel headers by update_headers.py, 3 * to provide necessary information from kernel to userspace, such as constants, 4 * structures, and macros, and thus, contains no copyrightable information. 5 */ 6#ifndef __ETNAVIV_DRM_H__ 7#define __ETNAVIV_DRM_H__ 8#include "drm.h" 9#if defined(__cplusplus) 10extern "C" { 11#endif 12struct drm_etnaviv_timespec { 13 __s64 tv_sec; 14 __s64 tv_nsec; 15}; 16#define ETNAVIV_PARAM_GPU_MODEL 0x01 17#define ETNAVIV_PARAM_GPU_REVISION 0x02 18#define ETNAVIV_PARAM_GPU_FEATURES_0 0x03 19#define ETNAVIV_PARAM_GPU_FEATURES_1 0x04 20#define ETNAVIV_PARAM_GPU_FEATURES_2 0x05 21#define ETNAVIV_PARAM_GPU_FEATURES_3 0x06 22#define ETNAVIV_PARAM_GPU_FEATURES_4 0x07 23#define ETNAVIV_PARAM_GPU_FEATURES_5 0x08 24#define ETNAVIV_PARAM_GPU_FEATURES_6 0x09 25#define ETNAVIV_PARAM_GPU_FEATURES_7 0x0a 26#define ETNAVIV_PARAM_GPU_FEATURES_8 0x0b 27#define ETNAVIV_PARAM_GPU_FEATURES_9 0x0c 28#define ETNAVIV_PARAM_GPU_FEATURES_10 0x0d 29#define ETNAVIV_PARAM_GPU_FEATURES_11 0x0e 30#define ETNAVIV_PARAM_GPU_FEATURES_12 0x0f 31#define ETNAVIV_PARAM_GPU_STREAM_COUNT 0x10 32#define ETNAVIV_PARAM_GPU_REGISTER_MAX 0x11 33#define ETNAVIV_PARAM_GPU_THREAD_COUNT 0x12 34#define ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE 0x13 35#define ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT 0x14 36#define ETNAVIV_PARAM_GPU_PIXEL_PIPES 0x15 37#define ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE 0x16 38#define ETNAVIV_PARAM_GPU_BUFFER_SIZE 0x17 39#define ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT 0x18 40#define ETNAVIV_PARAM_GPU_NUM_CONSTANTS 0x19 41#define ETNAVIV_PARAM_GPU_NUM_VARYINGS 0x1a 42#define ETNA_MAX_PIPES 4 43struct drm_etnaviv_param { 44 __u32 pipe; 45 __u32 param; 46 __u64 value; 47}; 48#define ETNA_BO_CACHE_MASK 0x000f0000 49#define ETNA_BO_CACHED 0x00010000 50#define ETNA_BO_WC 0x00020000 51#define ETNA_BO_UNCACHED 0x00040000 52#define ETNA_BO_FORCE_MMU 0x00100000 53struct drm_etnaviv_gem_new { 54 __u64 size; 55 __u32 flags; 56 __u32 handle; 57}; 58struct drm_etnaviv_gem_info { 59 __u32 handle; 60 __u32 pad; 61 __u64 offset; 62}; 63#define ETNA_PREP_READ 0x01 64#define ETNA_PREP_WRITE 0x02 65#define ETNA_PREP_NOSYNC 0x04 66struct drm_etnaviv_gem_cpu_prep { 67 __u32 handle; 68 __u32 op; 69 struct drm_etnaviv_timespec timeout; 70}; 71struct drm_etnaviv_gem_cpu_fini { 72 __u32 handle; 73 __u32 flags; 74}; 75struct drm_etnaviv_gem_submit_reloc { 76 __u32 submit_offset; 77 __u32 reloc_idx; 78 __u64 reloc_offset; 79 __u32 flags; 80}; 81#define ETNA_SUBMIT_BO_READ 0x0001 82#define ETNA_SUBMIT_BO_WRITE 0x0002 83struct drm_etnaviv_gem_submit_bo { 84 __u32 flags; 85 __u32 handle; 86 __u64 presumed; 87}; 88#define ETNA_PM_PROCESS_PRE 0x0001 89#define ETNA_PM_PROCESS_POST 0x0002 90struct drm_etnaviv_gem_submit_pmr { 91 __u32 flags; 92 __u8 domain; 93 __u8 pad; 94 __u16 signal; 95 __u32 sequence; 96 __u32 read_offset; 97 __u32 read_idx; 98}; 99#define ETNA_SUBMIT_NO_IMPLICIT 0x0001 100#define ETNA_SUBMIT_FENCE_FD_IN 0x0002 101#define ETNA_SUBMIT_FENCE_FD_OUT 0x0004 102#define ETNA_SUBMIT_FLAGS (ETNA_SUBMIT_NO_IMPLICIT | \ 103 ETNA_SUBMIT_FENCE_FD_IN | \ 104 ETNA_SUBMIT_FENCE_FD_OUT) 105#define ETNA_PIPE_3D 0x00 106#define ETNA_PIPE_2D 0x01 107#define ETNA_PIPE_VG 0x02 108struct drm_etnaviv_gem_submit { 109 __u32 fence; 110 __u32 pipe; 111 __u32 exec_state; 112 __u32 nr_bos; 113 __u32 nr_relocs; 114 __u32 stream_size; 115 __u64 bos; 116 __u64 relocs; 117 __u64 stream; 118 __u32 flags; 119 __s32 fence_fd; 120 __u64 pmrs; 121 __u32 nr_pmrs; 122 __u32 pad; 123}; 124#define ETNA_WAIT_NONBLOCK 0x01 125struct drm_etnaviv_wait_fence { 126 __u32 pipe; 127 __u32 fence; 128 __u32 flags; 129 __u32 pad; 130 struct drm_etnaviv_timespec timeout; 131}; 132#define ETNA_USERPTR_READ 0x01 133#define ETNA_USERPTR_WRITE 0x02 134struct drm_etnaviv_gem_userptr { 135 __u64 user_ptr; 136 __u64 user_size; 137 __u32 flags; 138 __u32 handle; 139}; 140struct drm_etnaviv_gem_wait { 141 __u32 pipe; 142 __u32 handle; 143 __u32 flags; 144 __u32 pad; 145 struct drm_etnaviv_timespec timeout; 146}; 147struct drm_etnaviv_pm_domain { 148 __u32 pipe; 149 __u8 iter; 150 __u8 id; 151 __u16 nr_signals; 152 char name[64]; 153}; 154struct drm_etnaviv_pm_signal { 155 __u32 pipe; 156 __u8 domain; 157 __u8 pad; 158 __u16 iter; 159 __u16 id; 160 char name[64]; 161}; 162#define DRM_ETNAVIV_GET_PARAM 0x00 163#define DRM_ETNAVIV_GEM_NEW 0x02 164#define DRM_ETNAVIV_GEM_INFO 0x03 165#define DRM_ETNAVIV_GEM_CPU_PREP 0x04 166#define DRM_ETNAVIV_GEM_CPU_FINI 0x05 167#define DRM_ETNAVIV_GEM_SUBMIT 0x06 168#define DRM_ETNAVIV_WAIT_FENCE 0x07 169#define DRM_ETNAVIV_GEM_USERPTR 0x08 170#define DRM_ETNAVIV_GEM_WAIT 0x09 171#define DRM_ETNAVIV_PM_QUERY_DOM 0x0a 172#define DRM_ETNAVIV_PM_QUERY_SIG 0x0b 173#define DRM_ETNAVIV_NUM_IOCTLS 0x0c 174#define DRM_IOCTL_ETNAVIV_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param) 175#define DRM_IOCTL_ETNAVIV_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new) 176#define DRM_IOCTL_ETNAVIV_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_INFO, struct drm_etnaviv_gem_info) 177#define DRM_IOCTL_ETNAVIV_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_PREP, struct drm_etnaviv_gem_cpu_prep) 178#define DRM_IOCTL_ETNAVIV_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_FINI, struct drm_etnaviv_gem_cpu_fini) 179#define DRM_IOCTL_ETNAVIV_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_SUBMIT, struct drm_etnaviv_gem_submit) 180#define DRM_IOCTL_ETNAVIV_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence) 181#define DRM_IOCTL_ETNAVIV_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr) 182#define DRM_IOCTL_ETNAVIV_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait) 183#define DRM_IOCTL_ETNAVIV_PM_QUERY_DOM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_DOM, struct drm_etnaviv_pm_domain) 184#define DRM_IOCTL_ETNAVIV_PM_QUERY_SIG DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_SIG, struct drm_etnaviv_pm_signal) 185#if defined(__cplusplus) 186} 187#endif 188#endif 189