1/* 2 * This header was generated from the Linux kernel headers by update_headers.py, 3 * to provide necessary information from kernel to userspace, such as constants, 4 * structures, and macros, and thus, contains no copyrightable information. 5 */ 6#ifndef __ARM_KVM_H__ 7#define __ARM_KVM_H__ 8#define KVM_SPSR_EL1 0 9#define KVM_SPSR_SVC KVM_SPSR_EL1 10#define KVM_SPSR_ABT 1 11#define KVM_SPSR_UND 2 12#define KVM_SPSR_IRQ 3 13#define KVM_SPSR_FIQ 4 14#define KVM_NR_SPSR 5 15#ifndef __ASSEMBLY__ 16#include <linux/psci.h> 17#include <linux/types.h> 18#include <asm/ptrace.h> 19#define __KVM_HAVE_GUEST_DEBUG 20#define __KVM_HAVE_IRQ_LINE 21#define __KVM_HAVE_READONLY_MEM 22#define __KVM_HAVE_VCPU_EVENTS 23#define KVM_COALESCED_MMIO_PAGE_OFFSET 1 24#define KVM_REG_SIZE(id) \ 25 (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT)) 26struct kvm_regs { 27 struct user_pt_regs regs; 28 __u64 sp_el1; 29 __u64 elr_el1; 30 __u64 spsr[KVM_NR_SPSR]; 31 struct user_fpsimd_state fp_regs; 32}; 33#define KVM_ARM_TARGET_AEM_V8 0 34#define KVM_ARM_TARGET_FOUNDATION_V8 1 35#define KVM_ARM_TARGET_CORTEX_A57 2 36#define KVM_ARM_TARGET_XGENE_POTENZA 3 37#define KVM_ARM_TARGET_CORTEX_A53 4 38#define KVM_ARM_TARGET_GENERIC_V8 5 39#define KVM_ARM_NUM_TARGETS 6 40#define KVM_ARM_DEVICE_TYPE_SHIFT 0 41#define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT) 42#define KVM_ARM_DEVICE_ID_SHIFT 16 43#define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT) 44#define KVM_ARM_DEVICE_VGIC_V2 0 45#define KVM_VGIC_V2_ADDR_TYPE_DIST 0 46#define KVM_VGIC_V2_ADDR_TYPE_CPU 1 47#define KVM_VGIC_V2_DIST_SIZE 0x1000 48#define KVM_VGIC_V2_CPU_SIZE 0x2000 49#define KVM_VGIC_V3_ADDR_TYPE_DIST 2 50#define KVM_VGIC_V3_ADDR_TYPE_REDIST 3 51#define KVM_VGIC_ITS_ADDR_TYPE 4 52#define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION 5 53#define KVM_VGIC_V3_DIST_SIZE SZ_64K 54#define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K) 55#define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K) 56#define KVM_ARM_VCPU_POWER_OFF 0 57#define KVM_ARM_VCPU_EL1_32BIT 1 58#define KVM_ARM_VCPU_PSCI_0_2 2 59#define KVM_ARM_VCPU_PMU_V3 3 60struct kvm_vcpu_init { 61 __u32 target; 62 __u32 features[7]; 63}; 64struct kvm_sregs { 65}; 66struct kvm_fpu { 67}; 68#define KVM_ARM_MAX_DBG_REGS 16 69struct kvm_guest_debug_arch { 70 __u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS]; 71 __u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS]; 72 __u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS]; 73 __u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS]; 74}; 75struct kvm_debug_exit_arch { 76 __u32 hsr; 77 __u64 far; 78}; 79#define KVM_GUESTDBG_USE_SW_BP (1 << 16) 80#define KVM_GUESTDBG_USE_HW (1 << 17) 81struct kvm_sync_regs { 82 83 __u64 device_irq_level; 84}; 85struct kvm_arch_memory_slot { 86}; 87struct kvm_vcpu_events { 88 struct { 89 __u8 serror_pending; 90 __u8 serror_has_esr; 91 92 __u8 pad[6]; 93 __u64 serror_esr; 94 } exception; 95 __u32 reserved[12]; 96}; 97#define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000 98#define KVM_REG_ARM_COPROC_SHIFT 16 99#define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT) 100#define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32)) 101#define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT) 102#define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00 103#define KVM_REG_ARM_DEMUX_ID_SHIFT 8 104#define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT) 105#define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF 106#define KVM_REG_ARM_DEMUX_VAL_SHIFT 0 107#define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT) 108#define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000 109#define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14 110#define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800 111#define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11 112#define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780 113#define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7 114#define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078 115#define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3 116#define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007 117#define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0 118#define ARM64_SYS_REG_SHIFT_MASK(x,n) \ 119 (((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \ 120 KVM_REG_ARM64_SYSREG_ ## n ## _MASK) 121#define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \ 122 (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \ 123 ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \ 124 ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \ 125 ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \ 126 ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \ 127 ARM64_SYS_REG_SHIFT_MASK(op2, OP2)) 128#define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64) 129#define KVM_REG_ARM_PTIMER_CTL ARM64_SYS_REG(3, 3, 14, 2, 1) 130#define KVM_REG_ARM_PTIMER_CVAL ARM64_SYS_REG(3, 3, 14, 2, 2) 131#define KVM_REG_ARM_PTIMER_CNT ARM64_SYS_REG(3, 3, 14, 0, 1) 132#define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1) 133#define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2) 134#define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2) 135#define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT) 136#define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ 137 KVM_REG_ARM_FW | ((r) & 0xffff)) 138#define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0) 139#define KVM_DEV_ARM_VGIC_GRP_ADDR 0 140#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1 141#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2 142#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32 143#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT) 144#define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32 145#define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \ 146 (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT) 147#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0 148#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) 149#define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff) 150#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3 151#define KVM_DEV_ARM_VGIC_GRP_CTRL 4 152#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5 153#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6 154#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7 155#define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8 156#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10 157#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \ 158 (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) 159#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff 160#define VGIC_LEVEL_INFO_LINE_LEVEL 0 161#define KVM_DEV_ARM_VGIC_CTRL_INIT 0 162#define KVM_DEV_ARM_ITS_SAVE_TABLES 1 163#define KVM_DEV_ARM_ITS_RESTORE_TABLES 2 164#define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3 165#define KVM_DEV_ARM_ITS_CTRL_RESET 4 166#define KVM_ARM_VCPU_PMU_V3_CTRL 0 167#define KVM_ARM_VCPU_PMU_V3_IRQ 0 168#define KVM_ARM_VCPU_PMU_V3_INIT 1 169#define KVM_ARM_VCPU_TIMER_CTRL 1 170#define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0 171#define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 172#define KVM_ARM_IRQ_TYPE_SHIFT 24 173#define KVM_ARM_IRQ_TYPE_MASK 0xff 174#define KVM_ARM_IRQ_VCPU_SHIFT 16 175#define KVM_ARM_IRQ_VCPU_MASK 0xff 176#define KVM_ARM_IRQ_NUM_SHIFT 0 177#define KVM_ARM_IRQ_NUM_MASK 0xffff 178#define KVM_ARM_IRQ_TYPE_CPU 0 179#define KVM_ARM_IRQ_TYPE_SPI 1 180#define KVM_ARM_IRQ_TYPE_PPI 2 181#define KVM_ARM_IRQ_CPU_IRQ 0 182#define KVM_ARM_IRQ_CPU_FIQ 1 183#define KVM_ARM_IRQ_GIC_MAX 127 184#define KVM_NR_IRQCHIPS 1 185#define KVM_PSCI_FN_BASE 0x95c1ba5e 186#define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n)) 187#define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0) 188#define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1) 189#define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2) 190#define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3) 191#define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS 192#define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED 193#define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS 194#define KVM_PSCI_RET_DENIED PSCI_RET_DENIED 195#endif 196#endif 197