1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * turbostat -- show CPU frequency and C-state residency 4 * on modern Intel and AMD processors. 5 * 6 * Copyright (c) 2023 Intel Corporation. 7 * Len Brown <len.brown@intel.com> 8 */ 9 10#define _GNU_SOURCE 11#include MSRHEADER 12#include INTEL_FAMILY_HEADER 13#include <stdarg.h> 14#include <stdio.h> 15#include <err.h> 16#include <unistd.h> 17#include <sys/types.h> 18#include <sys/wait.h> 19#include <sys/stat.h> 20#include <sys/select.h> 21#include <sys/resource.h> 22#include <fcntl.h> 23#include <signal.h> 24#include <sys/time.h> 25#include <stdlib.h> 26#include <getopt.h> 27#include <dirent.h> 28#include <string.h> 29#include <ctype.h> 30#include <sched.h> 31#include <time.h> 32#include <cpuid.h> 33#include <sys/capability.h> 34#include <errno.h> 35#include <math.h> 36#include <linux/perf_event.h> 37#include <asm/unistd.h> 38#include <stdbool.h> 39 40#define UNUSED(x) (void)(x) 41 42/* 43 * This list matches the column headers, except 44 * 1. built-in only, the sysfs counters are not here -- we learn of those at run-time 45 * 2. Core and CPU are moved to the end, we can't have strings that contain them 46 * matching on them for --show and --hide. 47 */ 48 49/* 50 * buffer size used by sscanf() for added column names 51 * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters 52 */ 53#define NAME_BYTES 20 54#define PATH_BYTES 128 55 56enum counter_scope { SCOPE_CPU, SCOPE_CORE, SCOPE_PACKAGE }; 57enum counter_type { COUNTER_ITEMS, COUNTER_CYCLES, COUNTER_SECONDS, COUNTER_USEC }; 58enum counter_format { FORMAT_RAW, FORMAT_DELTA, FORMAT_PERCENT }; 59 60struct msr_counter { 61 unsigned int msr_num; 62 char name[NAME_BYTES]; 63 char path[PATH_BYTES]; 64 unsigned int width; 65 enum counter_type type; 66 enum counter_format format; 67 struct msr_counter *next; 68 unsigned int flags; 69#define FLAGS_HIDE (1 << 0) 70#define FLAGS_SHOW (1 << 1) 71#define SYSFS_PERCPU (1 << 1) 72}; 73 74struct msr_counter bic[] = { 75 { 0x0, "usec", "", 0, 0, 0, NULL, 0 }, 76 { 0x0, "Time_Of_Day_Seconds", "", 0, 0, 0, NULL, 0 }, 77 { 0x0, "Package", "", 0, 0, 0, NULL, 0 }, 78 { 0x0, "Node", "", 0, 0, 0, NULL, 0 }, 79 { 0x0, "Avg_MHz", "", 0, 0, 0, NULL, 0 }, 80 { 0x0, "Busy%", "", 0, 0, 0, NULL, 0 }, 81 { 0x0, "Bzy_MHz", "", 0, 0, 0, NULL, 0 }, 82 { 0x0, "TSC_MHz", "", 0, 0, 0, NULL, 0 }, 83 { 0x0, "IRQ", "", 0, 0, 0, NULL, 0 }, 84 { 0x0, "SMI", "", 32, 0, FORMAT_DELTA, NULL, 0 }, 85 { 0x0, "sysfs", "", 0, 0, 0, NULL, 0 }, 86 { 0x0, "CPU%c1", "", 0, 0, 0, NULL, 0 }, 87 { 0x0, "CPU%c3", "", 0, 0, 0, NULL, 0 }, 88 { 0x0, "CPU%c6", "", 0, 0, 0, NULL, 0 }, 89 { 0x0, "CPU%c7", "", 0, 0, 0, NULL, 0 }, 90 { 0x0, "ThreadC", "", 0, 0, 0, NULL, 0 }, 91 { 0x0, "CoreTmp", "", 0, 0, 0, NULL, 0 }, 92 { 0x0, "CoreCnt", "", 0, 0, 0, NULL, 0 }, 93 { 0x0, "PkgTmp", "", 0, 0, 0, NULL, 0 }, 94 { 0x0, "GFX%rc6", "", 0, 0, 0, NULL, 0 }, 95 { 0x0, "GFXMHz", "", 0, 0, 0, NULL, 0 }, 96 { 0x0, "Pkg%pc2", "", 0, 0, 0, NULL, 0 }, 97 { 0x0, "Pkg%pc3", "", 0, 0, 0, NULL, 0 }, 98 { 0x0, "Pkg%pc6", "", 0, 0, 0, NULL, 0 }, 99 { 0x0, "Pkg%pc7", "", 0, 0, 0, NULL, 0 }, 100 { 0x0, "Pkg%pc8", "", 0, 0, 0, NULL, 0 }, 101 { 0x0, "Pkg%pc9", "", 0, 0, 0, NULL, 0 }, 102 { 0x0, "Pk%pc10", "", 0, 0, 0, NULL, 0 }, 103 { 0x0, "CPU%LPI", "", 0, 0, 0, NULL, 0 }, 104 { 0x0, "SYS%LPI", "", 0, 0, 0, NULL, 0 }, 105 { 0x0, "PkgWatt", "", 0, 0, 0, NULL, 0 }, 106 { 0x0, "CorWatt", "", 0, 0, 0, NULL, 0 }, 107 { 0x0, "GFXWatt", "", 0, 0, 0, NULL, 0 }, 108 { 0x0, "PkgCnt", "", 0, 0, 0, NULL, 0 }, 109 { 0x0, "RAMWatt", "", 0, 0, 0, NULL, 0 }, 110 { 0x0, "PKG_%", "", 0, 0, 0, NULL, 0 }, 111 { 0x0, "RAM_%", "", 0, 0, 0, NULL, 0 }, 112 { 0x0, "Pkg_J", "", 0, 0, 0, NULL, 0 }, 113 { 0x0, "Cor_J", "", 0, 0, 0, NULL, 0 }, 114 { 0x0, "GFX_J", "", 0, 0, 0, NULL, 0 }, 115 { 0x0, "RAM_J", "", 0, 0, 0, NULL, 0 }, 116 { 0x0, "Mod%c6", "", 0, 0, 0, NULL, 0 }, 117 { 0x0, "Totl%C0", "", 0, 0, 0, NULL, 0 }, 118 { 0x0, "Any%C0", "", 0, 0, 0, NULL, 0 }, 119 { 0x0, "GFX%C0", "", 0, 0, 0, NULL, 0 }, 120 { 0x0, "CPUGFX%", "", 0, 0, 0, NULL, 0 }, 121 { 0x0, "Core", "", 0, 0, 0, NULL, 0 }, 122 { 0x0, "CPU", "", 0, 0, 0, NULL, 0 }, 123 { 0x0, "APIC", "", 0, 0, 0, NULL, 0 }, 124 { 0x0, "X2APIC", "", 0, 0, 0, NULL, 0 }, 125 { 0x0, "Die", "", 0, 0, 0, NULL, 0 }, 126 { 0x0, "GFXAMHz", "", 0, 0, 0, NULL, 0 }, 127 { 0x0, "IPC", "", 0, 0, 0, NULL, 0 }, 128 { 0x0, "CoreThr", "", 0, 0, 0, NULL, 0 }, 129 { 0x0, "UncMHz", "", 0, 0, 0, NULL, 0 }, 130}; 131 132#define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter)) 133#define BIC_USEC (1ULL << 0) 134#define BIC_TOD (1ULL << 1) 135#define BIC_Package (1ULL << 2) 136#define BIC_Node (1ULL << 3) 137#define BIC_Avg_MHz (1ULL << 4) 138#define BIC_Busy (1ULL << 5) 139#define BIC_Bzy_MHz (1ULL << 6) 140#define BIC_TSC_MHz (1ULL << 7) 141#define BIC_IRQ (1ULL << 8) 142#define BIC_SMI (1ULL << 9) 143#define BIC_sysfs (1ULL << 10) 144#define BIC_CPU_c1 (1ULL << 11) 145#define BIC_CPU_c3 (1ULL << 12) 146#define BIC_CPU_c6 (1ULL << 13) 147#define BIC_CPU_c7 (1ULL << 14) 148#define BIC_ThreadC (1ULL << 15) 149#define BIC_CoreTmp (1ULL << 16) 150#define BIC_CoreCnt (1ULL << 17) 151#define BIC_PkgTmp (1ULL << 18) 152#define BIC_GFX_rc6 (1ULL << 19) 153#define BIC_GFXMHz (1ULL << 20) 154#define BIC_Pkgpc2 (1ULL << 21) 155#define BIC_Pkgpc3 (1ULL << 22) 156#define BIC_Pkgpc6 (1ULL << 23) 157#define BIC_Pkgpc7 (1ULL << 24) 158#define BIC_Pkgpc8 (1ULL << 25) 159#define BIC_Pkgpc9 (1ULL << 26) 160#define BIC_Pkgpc10 (1ULL << 27) 161#define BIC_CPU_LPI (1ULL << 28) 162#define BIC_SYS_LPI (1ULL << 29) 163#define BIC_PkgWatt (1ULL << 30) 164#define BIC_CorWatt (1ULL << 31) 165#define BIC_GFXWatt (1ULL << 32) 166#define BIC_PkgCnt (1ULL << 33) 167#define BIC_RAMWatt (1ULL << 34) 168#define BIC_PKG__ (1ULL << 35) 169#define BIC_RAM__ (1ULL << 36) 170#define BIC_Pkg_J (1ULL << 37) 171#define BIC_Cor_J (1ULL << 38) 172#define BIC_GFX_J (1ULL << 39) 173#define BIC_RAM_J (1ULL << 40) 174#define BIC_Mod_c6 (1ULL << 41) 175#define BIC_Totl_c0 (1ULL << 42) 176#define BIC_Any_c0 (1ULL << 43) 177#define BIC_GFX_c0 (1ULL << 44) 178#define BIC_CPUGFX (1ULL << 45) 179#define BIC_Core (1ULL << 46) 180#define BIC_CPU (1ULL << 47) 181#define BIC_APIC (1ULL << 48) 182#define BIC_X2APIC (1ULL << 49) 183#define BIC_Die (1ULL << 50) 184#define BIC_GFXACTMHz (1ULL << 51) 185#define BIC_IPC (1ULL << 52) 186#define BIC_CORE_THROT_CNT (1ULL << 53) 187#define BIC_UNCORE_MHZ (1ULL << 54) 188 189#define BIC_TOPOLOGY (BIC_Package | BIC_Node | BIC_CoreCnt | BIC_PkgCnt | BIC_Core | BIC_CPU | BIC_Die ) 190#define BIC_THERMAL_PWR ( BIC_CoreTmp | BIC_PkgTmp | BIC_PkgWatt | BIC_CorWatt | BIC_GFXWatt | BIC_RAMWatt | BIC_PKG__ | BIC_RAM__) 191#define BIC_FREQUENCY ( BIC_Avg_MHz | BIC_Busy | BIC_Bzy_MHz | BIC_TSC_MHz | BIC_GFXMHz | BIC_GFXACTMHz | BIC_UNCORE_MHZ) 192#define BIC_IDLE ( BIC_sysfs | BIC_CPU_c1 | BIC_CPU_c3 | BIC_CPU_c6 | BIC_CPU_c7 | BIC_GFX_rc6 | BIC_Pkgpc2 | BIC_Pkgpc3 | BIC_Pkgpc6 | BIC_Pkgpc7 | BIC_Pkgpc8 | BIC_Pkgpc9 | BIC_Pkgpc10 | BIC_CPU_LPI | BIC_SYS_LPI | BIC_Mod_c6 | BIC_Totl_c0 | BIC_Any_c0 | BIC_GFX_c0 | BIC_CPUGFX) 193#define BIC_OTHER ( BIC_IRQ | BIC_SMI | BIC_ThreadC | BIC_CoreTmp | BIC_IPC) 194 195#define BIC_DISABLED_BY_DEFAULT (BIC_USEC | BIC_TOD | BIC_APIC | BIC_X2APIC) 196 197unsigned long long bic_enabled = (0xFFFFFFFFFFFFFFFFULL & ~BIC_DISABLED_BY_DEFAULT); 198unsigned long long bic_present = BIC_USEC | BIC_TOD | BIC_sysfs | BIC_APIC | BIC_X2APIC; 199 200#define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME) 201#define DO_BIC_READ(COUNTER_NAME) (bic_present & COUNTER_NAME) 202#define ENABLE_BIC(COUNTER_NAME) (bic_enabled |= COUNTER_NAME) 203#define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT) 204#define BIC_NOT_PRESENT(COUNTER_BIT) (bic_present &= ~COUNTER_BIT) 205#define BIC_IS_ENABLED(COUNTER_BIT) (bic_enabled & COUNTER_BIT) 206 207char *proc_stat = "/proc/stat"; 208FILE *outf; 209int *fd_percpu; 210int *fd_instr_count_percpu; 211struct timeval interval_tv = { 5, 0 }; 212struct timespec interval_ts = { 5, 0 }; 213 214/* Save original CPU model */ 215unsigned int model_orig; 216 217unsigned int num_iterations; 218unsigned int header_iterations; 219unsigned int debug; 220unsigned int quiet; 221unsigned int shown; 222unsigned int sums_need_wide_columns; 223unsigned int rapl_joules; 224unsigned int summary_only; 225unsigned int list_header_only; 226unsigned int dump_only; 227unsigned int do_snb_cstates; 228unsigned int do_knl_cstates; 229unsigned int do_slm_cstates; 230unsigned int use_c1_residency_msr; 231unsigned int has_aperf; 232unsigned int has_epb; 233unsigned int has_turbo; 234unsigned int is_hybrid; 235unsigned int do_irtl_snb; 236unsigned int do_irtl_hsw; 237unsigned int units = 1000000; /* MHz etc */ 238unsigned int genuine_intel; 239unsigned int authentic_amd; 240unsigned int hygon_genuine; 241unsigned int max_level, max_extended_level; 242unsigned int has_invariant_tsc; 243unsigned int do_nhm_platform_info; 244unsigned int no_MSR_MISC_PWR_MGMT; 245unsigned int aperf_mperf_multiplier = 1; 246double bclk; 247double base_hz; 248unsigned int has_base_hz; 249double tsc_tweak = 1.0; 250unsigned int show_pkg_only; 251unsigned int show_core_only; 252char *output_buffer, *outp; 253unsigned int do_rapl; 254unsigned int do_dts; 255unsigned int do_ptm; 256unsigned int do_ipc; 257unsigned long long gfx_cur_rc6_ms; 258unsigned long long cpuidle_cur_cpu_lpi_us; 259unsigned long long cpuidle_cur_sys_lpi_us; 260unsigned int gfx_cur_mhz; 261unsigned int gfx_act_mhz; 262unsigned int tj_max; 263unsigned int tj_max_override; 264int tcc_offset_bits; 265double rapl_power_units, rapl_time_units; 266double rapl_dram_energy_units, rapl_energy_units; 267double rapl_joule_counter_range; 268unsigned int do_core_perf_limit_reasons; 269unsigned int has_automatic_cstate_conversion; 270unsigned int dis_cstate_prewake; 271unsigned int do_gfx_perf_limit_reasons; 272unsigned int do_ring_perf_limit_reasons; 273unsigned int crystal_hz; 274unsigned long long tsc_hz; 275int base_cpu; 276double discover_bclk(unsigned int family, unsigned int model); 277unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */ 278 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */ 279unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */ 280unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */ 281unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */ 282unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */ 283unsigned int has_misc_feature_control; 284unsigned int first_counter_read = 1; 285int ignore_stdin; 286 287#define RAPL_PKG (1 << 0) 288 /* 0x610 MSR_PKG_POWER_LIMIT */ 289 /* 0x611 MSR_PKG_ENERGY_STATUS */ 290#define RAPL_PKG_PERF_STATUS (1 << 1) 291 /* 0x613 MSR_PKG_PERF_STATUS */ 292#define RAPL_PKG_POWER_INFO (1 << 2) 293 /* 0x614 MSR_PKG_POWER_INFO */ 294 295#define RAPL_DRAM (1 << 3) 296 /* 0x618 MSR_DRAM_POWER_LIMIT */ 297 /* 0x619 MSR_DRAM_ENERGY_STATUS */ 298#define RAPL_DRAM_PERF_STATUS (1 << 4) 299 /* 0x61b MSR_DRAM_PERF_STATUS */ 300#define RAPL_DRAM_POWER_INFO (1 << 5) 301 /* 0x61c MSR_DRAM_POWER_INFO */ 302 303#define RAPL_CORES_POWER_LIMIT (1 << 6) 304 /* 0x638 MSR_PP0_POWER_LIMIT */ 305#define RAPL_CORE_POLICY (1 << 7) 306 /* 0x63a MSR_PP0_POLICY */ 307 308#define RAPL_GFX (1 << 8) 309 /* 0x640 MSR_PP1_POWER_LIMIT */ 310 /* 0x641 MSR_PP1_ENERGY_STATUS */ 311 /* 0x642 MSR_PP1_POLICY */ 312 313#define RAPL_CORES_ENERGY_STATUS (1 << 9) 314 /* 0x639 MSR_PP0_ENERGY_STATUS */ 315#define RAPL_PER_CORE_ENERGY (1 << 10) 316 /* Indicates cores energy collection is per-core, 317 * not per-package. */ 318#define RAPL_AMD_F17H (1 << 11) 319 /* 0xc0010299 MSR_RAPL_PWR_UNIT */ 320 /* 0xc001029a MSR_CORE_ENERGY_STAT */ 321 /* 0xc001029b MSR_PKG_ENERGY_STAT */ 322#define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT) 323#define TJMAX_DEFAULT 100 324 325/* MSRs that are not yet in the kernel-provided header. */ 326#define MSR_RAPL_PWR_UNIT 0xc0010299 327#define MSR_CORE_ENERGY_STAT 0xc001029a 328#define MSR_PKG_ENERGY_STAT 0xc001029b 329 330#define MAX(a, b) ((a) > (b) ? (a) : (b)) 331 332int backwards_count; 333char *progname; 334 335#define CPU_SUBSET_MAXCPUS 1024 /* need to use before probe... */ 336cpu_set_t *cpu_present_set, *cpu_affinity_set, *cpu_subset; 337size_t cpu_present_setsize, cpu_affinity_setsize, cpu_subset_size; 338#define MAX_ADDED_COUNTERS 8 339#define MAX_ADDED_THREAD_COUNTERS 24 340#define BITMASK_SIZE 32 341 342struct thread_data { 343 struct timeval tv_begin; 344 struct timeval tv_end; 345 struct timeval tv_delta; 346 unsigned long long tsc; 347 unsigned long long aperf; 348 unsigned long long mperf; 349 unsigned long long c1; 350 unsigned long long instr_count; 351 unsigned long long irq_count; 352 unsigned int smi_count; 353 unsigned int cpu_id; 354 unsigned int apic_id; 355 unsigned int x2apic_id; 356 unsigned int flags; 357 bool is_atom; 358#define CPU_IS_FIRST_THREAD_IN_CORE 0x2 359#define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4 360 unsigned long long counter[MAX_ADDED_THREAD_COUNTERS]; 361} *thread_even, *thread_odd; 362 363struct core_data { 364 unsigned long long c3; 365 unsigned long long c6; 366 unsigned long long c7; 367 unsigned long long mc6_us; /* duplicate as per-core for now, even though per module */ 368 unsigned int core_temp_c; 369 unsigned int core_energy; /* MSR_CORE_ENERGY_STAT */ 370 unsigned int core_id; 371 unsigned long long core_throt_cnt; 372 unsigned long long counter[MAX_ADDED_COUNTERS]; 373} *core_even, *core_odd; 374 375struct pkg_data { 376 unsigned long long pc2; 377 unsigned long long pc3; 378 unsigned long long pc6; 379 unsigned long long pc7; 380 unsigned long long pc8; 381 unsigned long long pc9; 382 unsigned long long pc10; 383 unsigned long long cpu_lpi; 384 unsigned long long sys_lpi; 385 unsigned long long pkg_wtd_core_c0; 386 unsigned long long pkg_any_core_c0; 387 unsigned long long pkg_any_gfxe_c0; 388 unsigned long long pkg_both_core_gfxe_c0; 389 long long gfx_rc6_ms; 390 unsigned int gfx_mhz; 391 unsigned int gfx_act_mhz; 392 unsigned int package_id; 393 unsigned long long energy_pkg; /* MSR_PKG_ENERGY_STATUS */ 394 unsigned long long energy_dram; /* MSR_DRAM_ENERGY_STATUS */ 395 unsigned long long energy_cores; /* MSR_PP0_ENERGY_STATUS */ 396 unsigned long long energy_gfx; /* MSR_PP1_ENERGY_STATUS */ 397 unsigned long long rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */ 398 unsigned long long rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */ 399 unsigned int pkg_temp_c; 400 unsigned int uncore_mhz; 401 unsigned long long counter[MAX_ADDED_COUNTERS]; 402} *package_even, *package_odd; 403 404#define ODD_COUNTERS thread_odd, core_odd, package_odd 405#define EVEN_COUNTERS thread_even, core_even, package_even 406 407#define GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no) \ 408 ((thread_base) + \ 409 ((pkg_no) * \ 410 topo.nodes_per_pkg * topo.cores_per_node * topo.threads_per_core) + \ 411 ((node_no) * topo.cores_per_node * topo.threads_per_core) + \ 412 ((core_no) * topo.threads_per_core) + \ 413 (thread_no)) 414 415#define GET_CORE(core_base, core_no, node_no, pkg_no) \ 416 ((core_base) + \ 417 ((pkg_no) * topo.nodes_per_pkg * topo.cores_per_node) + \ 418 ((node_no) * topo.cores_per_node) + \ 419 (core_no)) 420 421#define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no) 422 423/* 424 * The accumulated sum of MSR is defined as a monotonic 425 * increasing MSR, it will be accumulated periodically, 426 * despite its register's bit width. 427 */ 428enum { 429 IDX_PKG_ENERGY, 430 IDX_DRAM_ENERGY, 431 IDX_PP0_ENERGY, 432 IDX_PP1_ENERGY, 433 IDX_PKG_PERF, 434 IDX_DRAM_PERF, 435 IDX_COUNT, 436}; 437 438int get_msr_sum(int cpu, off_t offset, unsigned long long *msr); 439 440struct msr_sum_array { 441 /* get_msr_sum() = sum + (get_msr() - last) */ 442 struct { 443 /*The accumulated MSR value is updated by the timer */ 444 unsigned long long sum; 445 /*The MSR footprint recorded in last timer */ 446 unsigned long long last; 447 } entries[IDX_COUNT]; 448}; 449 450/* The percpu MSR sum array.*/ 451struct msr_sum_array *per_cpu_msr_sum; 452 453off_t idx_to_offset(int idx) 454{ 455 off_t offset; 456 457 switch (idx) { 458 case IDX_PKG_ENERGY: 459 if (do_rapl & RAPL_AMD_F17H) 460 offset = MSR_PKG_ENERGY_STAT; 461 else 462 offset = MSR_PKG_ENERGY_STATUS; 463 break; 464 case IDX_DRAM_ENERGY: 465 offset = MSR_DRAM_ENERGY_STATUS; 466 break; 467 case IDX_PP0_ENERGY: 468 offset = MSR_PP0_ENERGY_STATUS; 469 break; 470 case IDX_PP1_ENERGY: 471 offset = MSR_PP1_ENERGY_STATUS; 472 break; 473 case IDX_PKG_PERF: 474 offset = MSR_PKG_PERF_STATUS; 475 break; 476 case IDX_DRAM_PERF: 477 offset = MSR_DRAM_PERF_STATUS; 478 break; 479 default: 480 offset = -1; 481 } 482 return offset; 483} 484 485int offset_to_idx(off_t offset) 486{ 487 int idx; 488 489 switch (offset) { 490 case MSR_PKG_ENERGY_STATUS: 491 case MSR_PKG_ENERGY_STAT: 492 idx = IDX_PKG_ENERGY; 493 break; 494 case MSR_DRAM_ENERGY_STATUS: 495 idx = IDX_DRAM_ENERGY; 496 break; 497 case MSR_PP0_ENERGY_STATUS: 498 idx = IDX_PP0_ENERGY; 499 break; 500 case MSR_PP1_ENERGY_STATUS: 501 idx = IDX_PP1_ENERGY; 502 break; 503 case MSR_PKG_PERF_STATUS: 504 idx = IDX_PKG_PERF; 505 break; 506 case MSR_DRAM_PERF_STATUS: 507 idx = IDX_DRAM_PERF; 508 break; 509 default: 510 idx = -1; 511 } 512 return idx; 513} 514 515int idx_valid(int idx) 516{ 517 switch (idx) { 518 case IDX_PKG_ENERGY: 519 return do_rapl & (RAPL_PKG | RAPL_AMD_F17H); 520 case IDX_DRAM_ENERGY: 521 return do_rapl & RAPL_DRAM; 522 case IDX_PP0_ENERGY: 523 return do_rapl & RAPL_CORES_ENERGY_STATUS; 524 case IDX_PP1_ENERGY: 525 return do_rapl & RAPL_GFX; 526 case IDX_PKG_PERF: 527 return do_rapl & RAPL_PKG_PERF_STATUS; 528 case IDX_DRAM_PERF: 529 return do_rapl & RAPL_DRAM_PERF_STATUS; 530 default: 531 return 0; 532 } 533} 534 535struct sys_counters { 536 unsigned int added_thread_counters; 537 unsigned int added_core_counters; 538 unsigned int added_package_counters; 539 struct msr_counter *tp; 540 struct msr_counter *cp; 541 struct msr_counter *pp; 542} sys; 543 544struct system_summary { 545 struct thread_data threads; 546 struct core_data cores; 547 struct pkg_data packages; 548} average; 549 550struct cpu_topology { 551 int physical_package_id; 552 int die_id; 553 int logical_cpu_id; 554 int physical_node_id; 555 int logical_node_id; /* 0-based count within the package */ 556 int physical_core_id; 557 int thread_id; 558 cpu_set_t *put_ids; /* Processing Unit/Thread IDs */ 559} *cpus; 560 561struct topo_params { 562 int num_packages; 563 int num_die; 564 int num_cpus; 565 int num_cores; 566 int max_cpu_num; 567 int max_node_num; 568 int nodes_per_pkg; 569 int cores_per_node; 570 int threads_per_core; 571} topo; 572 573struct timeval tv_even, tv_odd, tv_delta; 574 575int *irq_column_2_cpu; /* /proc/interrupts column numbers */ 576int *irqs_per_cpu; /* indexed by cpu_num */ 577 578void setup_all_buffers(void); 579 580char *sys_lpi_file; 581char *sys_lpi_file_sysfs = "/sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us"; 582char *sys_lpi_file_debugfs = "/sys/kernel/debug/pmc_core/slp_s0_residency_usec"; 583 584int cpu_is_not_present(int cpu) 585{ 586 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set); 587} 588 589/* 590 * run func(thread, core, package) in topology order 591 * skip non-present cpus 592 */ 593 594int for_all_cpus(int (func) (struct thread_data *, struct core_data *, struct pkg_data *), 595 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base) 596{ 597 int retval, pkg_no, core_no, thread_no, node_no; 598 599 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 600 for (node_no = 0; node_no < topo.nodes_per_pkg; node_no++) { 601 for (core_no = 0; core_no < topo.cores_per_node; ++core_no) { 602 for (thread_no = 0; thread_no < topo.threads_per_core; ++thread_no) { 603 struct thread_data *t; 604 struct core_data *c; 605 struct pkg_data *p; 606 607 t = GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no); 608 609 if (cpu_is_not_present(t->cpu_id)) 610 continue; 611 612 c = GET_CORE(core_base, core_no, node_no, pkg_no); 613 p = GET_PKG(pkg_base, pkg_no); 614 615 retval = func(t, c, p); 616 if (retval) 617 return retval; 618 } 619 } 620 } 621 } 622 return 0; 623} 624 625int cpu_migrate(int cpu) 626{ 627 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 628 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set); 629 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1) 630 return -1; 631 else 632 return 0; 633} 634 635int get_msr_fd(int cpu) 636{ 637 char pathname[32]; 638 int fd; 639 640 fd = fd_percpu[cpu]; 641 642 if (fd) 643 return fd; 644 645 sprintf(pathname, "/dev/cpu/%d/msr", cpu); 646 fd = open(pathname, O_RDONLY); 647 if (fd < 0) 648 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname); 649 650 fd_percpu[cpu] = fd; 651 652 return fd; 653} 654 655static long perf_event_open(struct perf_event_attr *hw_event, pid_t pid, int cpu, int group_fd, unsigned long flags) 656{ 657 return syscall(__NR_perf_event_open, hw_event, pid, cpu, group_fd, flags); 658} 659 660static int perf_instr_count_open(int cpu_num) 661{ 662 struct perf_event_attr pea; 663 int fd; 664 665 memset(&pea, 0, sizeof(struct perf_event_attr)); 666 pea.type = PERF_TYPE_HARDWARE; 667 pea.size = sizeof(struct perf_event_attr); 668 pea.config = PERF_COUNT_HW_INSTRUCTIONS; 669 670 /* counter for cpu_num, including user + kernel and all processes */ 671 fd = perf_event_open(&pea, -1, cpu_num, -1, 0); 672 if (fd == -1) { 673 warnx("capget(CAP_PERFMON) failed, try \"# setcap cap_sys_admin=ep %s\"", progname); 674 BIC_NOT_PRESENT(BIC_IPC); 675 } 676 677 return fd; 678} 679 680int get_instr_count_fd(int cpu) 681{ 682 if (fd_instr_count_percpu[cpu]) 683 return fd_instr_count_percpu[cpu]; 684 685 fd_instr_count_percpu[cpu] = perf_instr_count_open(cpu); 686 687 return fd_instr_count_percpu[cpu]; 688} 689 690int get_msr(int cpu, off_t offset, unsigned long long *msr) 691{ 692 ssize_t retval; 693 694 retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset); 695 696 if (retval != sizeof *msr) 697 err(-1, "cpu%d: msr offset 0x%llx read failed", cpu, (unsigned long long)offset); 698 699 return 0; 700} 701 702#define MAX_DEFERRED 16 703char *deferred_add_names[MAX_DEFERRED]; 704char *deferred_skip_names[MAX_DEFERRED]; 705int deferred_add_index; 706int deferred_skip_index; 707 708/* 709 * HIDE_LIST - hide this list of counters, show the rest [default] 710 * SHOW_LIST - show this list of counters, hide the rest 711 */ 712enum show_hide_mode { SHOW_LIST, HIDE_LIST } global_show_hide_mode = HIDE_LIST; 713 714void help(void) 715{ 716 fprintf(outf, 717 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n" 718 "\n" 719 "Turbostat forks the specified COMMAND and prints statistics\n" 720 "when COMMAND completes.\n" 721 "If no COMMAND is specified, turbostat wakes every 5-seconds\n" 722 "to print statistics, until interrupted.\n" 723 " -a, --add add a counter\n" 724 " eg. --add msr0x10,u64,cpu,delta,MY_TSC\n" 725 " -c, --cpu cpu-set limit output to summary plus cpu-set:\n" 726 " {core | package | j,k,l..m,n-p }\n" 727 " -d, --debug displays usec, Time_Of_Day_Seconds and more debugging\n" 728 " -D, --Dump displays the raw counter values\n" 729 " -e, --enable [all | column]\n" 730 " shows all or the specified disabled column\n" 731 " -H, --hide [column|column,column,...]\n" 732 " hide the specified column(s)\n" 733 " -i, --interval sec.subsec\n" 734 " Override default 5-second measurement interval\n" 735 " -J, --Joules displays energy in Joules instead of Watts\n" 736 " -l, --list list column headers only\n" 737 " -n, --num_iterations num\n" 738 " number of the measurement iterations\n" 739 " -N, --header_iterations num\n" 740 " print header every num iterations\n" 741 " -o, --out file\n" 742 " create or truncate \"file\" for all output\n" 743 " -q, --quiet skip decoding system configuration header\n" 744 " -s, --show [column|column,column,...]\n" 745 " show only the specified column(s)\n" 746 " -S, --Summary\n" 747 " limits output to 1-line system summary per interval\n" 748 " -T, --TCC temperature\n" 749 " sets the Thermal Control Circuit temperature in\n" 750 " degrees Celsius\n" 751 " -h, --help print this help message\n" 752 " -v, --version print version information\n" "\n" "For more help, run \"man turbostat\"\n"); 753} 754 755/* 756 * bic_lookup 757 * for all the strings in comma separate name_list, 758 * set the approprate bit in return value. 759 */ 760unsigned long long bic_lookup(char *name_list, enum show_hide_mode mode) 761{ 762 unsigned int i; 763 unsigned long long retval = 0; 764 765 while (name_list) { 766 char *comma; 767 768 comma = strchr(name_list, ','); 769 770 if (comma) 771 *comma = '\0'; 772 773 for (i = 0; i < MAX_BIC; ++i) { 774 if (!strcmp(name_list, bic[i].name)) { 775 retval |= (1ULL << i); 776 break; 777 } 778 if (!strcmp(name_list, "all")) { 779 retval |= ~0; 780 break; 781 } else if (!strcmp(name_list, "topology")) { 782 retval |= BIC_TOPOLOGY; 783 break; 784 } else if (!strcmp(name_list, "power")) { 785 retval |= BIC_THERMAL_PWR; 786 break; 787 } else if (!strcmp(name_list, "idle")) { 788 retval |= BIC_IDLE; 789 break; 790 } else if (!strcmp(name_list, "frequency")) { 791 retval |= BIC_FREQUENCY; 792 break; 793 } else if (!strcmp(name_list, "other")) { 794 retval |= BIC_OTHER; 795 break; 796 } 797 798 } 799 if (i == MAX_BIC) { 800 if (mode == SHOW_LIST) { 801 deferred_add_names[deferred_add_index++] = name_list; 802 if (deferred_add_index >= MAX_DEFERRED) { 803 fprintf(stderr, "More than max %d un-recognized --add options '%s'\n", 804 MAX_DEFERRED, name_list); 805 help(); 806 exit(1); 807 } 808 } else { 809 deferred_skip_names[deferred_skip_index++] = name_list; 810 if (debug) 811 fprintf(stderr, "deferred \"%s\"\n", name_list); 812 if (deferred_skip_index >= MAX_DEFERRED) { 813 fprintf(stderr, "More than max %d un-recognized --skip options '%s'\n", 814 MAX_DEFERRED, name_list); 815 help(); 816 exit(1); 817 } 818 } 819 } 820 821 name_list = comma; 822 if (name_list) 823 name_list++; 824 825 } 826 return retval; 827} 828 829void print_header(char *delim) 830{ 831 struct msr_counter *mp; 832 int printed = 0; 833 834 if (DO_BIC(BIC_USEC)) 835 outp += sprintf(outp, "%susec", (printed++ ? delim : "")); 836 if (DO_BIC(BIC_TOD)) 837 outp += sprintf(outp, "%sTime_Of_Day_Seconds", (printed++ ? delim : "")); 838 if (DO_BIC(BIC_Package)) 839 outp += sprintf(outp, "%sPackage", (printed++ ? delim : "")); 840 if (DO_BIC(BIC_Die)) 841 outp += sprintf(outp, "%sDie", (printed++ ? delim : "")); 842 if (DO_BIC(BIC_Node)) 843 outp += sprintf(outp, "%sNode", (printed++ ? delim : "")); 844 if (DO_BIC(BIC_Core)) 845 outp += sprintf(outp, "%sCore", (printed++ ? delim : "")); 846 if (DO_BIC(BIC_CPU)) 847 outp += sprintf(outp, "%sCPU", (printed++ ? delim : "")); 848 if (DO_BIC(BIC_APIC)) 849 outp += sprintf(outp, "%sAPIC", (printed++ ? delim : "")); 850 if (DO_BIC(BIC_X2APIC)) 851 outp += sprintf(outp, "%sX2APIC", (printed++ ? delim : "")); 852 if (DO_BIC(BIC_Avg_MHz)) 853 outp += sprintf(outp, "%sAvg_MHz", (printed++ ? delim : "")); 854 if (DO_BIC(BIC_Busy)) 855 outp += sprintf(outp, "%sBusy%%", (printed++ ? delim : "")); 856 if (DO_BIC(BIC_Bzy_MHz)) 857 outp += sprintf(outp, "%sBzy_MHz", (printed++ ? delim : "")); 858 if (DO_BIC(BIC_TSC_MHz)) 859 outp += sprintf(outp, "%sTSC_MHz", (printed++ ? delim : "")); 860 861 if (DO_BIC(BIC_IPC)) 862 outp += sprintf(outp, "%sIPC", (printed++ ? delim : "")); 863 864 if (DO_BIC(BIC_IRQ)) { 865 if (sums_need_wide_columns) 866 outp += sprintf(outp, "%s IRQ", (printed++ ? delim : "")); 867 else 868 outp += sprintf(outp, "%sIRQ", (printed++ ? delim : "")); 869 } 870 871 if (DO_BIC(BIC_SMI)) 872 outp += sprintf(outp, "%sSMI", (printed++ ? delim : "")); 873 874 for (mp = sys.tp; mp; mp = mp->next) { 875 876 if (mp->format == FORMAT_RAW) { 877 if (mp->width == 64) 878 outp += sprintf(outp, "%s%18.18s", (printed++ ? delim : ""), mp->name); 879 else 880 outp += sprintf(outp, "%s%10.10s", (printed++ ? delim : ""), mp->name); 881 } else { 882 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 883 outp += sprintf(outp, "%s%8s", (printed++ ? delim : ""), mp->name); 884 else 885 outp += sprintf(outp, "%s%s", (printed++ ? delim : ""), mp->name); 886 } 887 } 888 889 if (DO_BIC(BIC_CPU_c1)) 890 outp += sprintf(outp, "%sCPU%%c1", (printed++ ? delim : "")); 891 if (DO_BIC(BIC_CPU_c3)) 892 outp += sprintf(outp, "%sCPU%%c3", (printed++ ? delim : "")); 893 if (DO_BIC(BIC_CPU_c6)) 894 outp += sprintf(outp, "%sCPU%%c6", (printed++ ? delim : "")); 895 if (DO_BIC(BIC_CPU_c7)) 896 outp += sprintf(outp, "%sCPU%%c7", (printed++ ? delim : "")); 897 898 if (DO_BIC(BIC_Mod_c6)) 899 outp += sprintf(outp, "%sMod%%c6", (printed++ ? delim : "")); 900 901 if (DO_BIC(BIC_CoreTmp)) 902 outp += sprintf(outp, "%sCoreTmp", (printed++ ? delim : "")); 903 904 if (DO_BIC(BIC_CORE_THROT_CNT)) 905 outp += sprintf(outp, "%sCoreThr", (printed++ ? delim : "")); 906 907 if (do_rapl && !rapl_joules) { 908 if (DO_BIC(BIC_CorWatt) && (do_rapl & RAPL_PER_CORE_ENERGY)) 909 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : "")); 910 } else if (do_rapl && rapl_joules) { 911 if (DO_BIC(BIC_Cor_J) && (do_rapl & RAPL_PER_CORE_ENERGY)) 912 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : "")); 913 } 914 915 for (mp = sys.cp; mp; mp = mp->next) { 916 if (mp->format == FORMAT_RAW) { 917 if (mp->width == 64) 918 outp += sprintf(outp, "%s%18.18s", delim, mp->name); 919 else 920 outp += sprintf(outp, "%s%10.10s", delim, mp->name); 921 } else { 922 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 923 outp += sprintf(outp, "%s%8s", delim, mp->name); 924 else 925 outp += sprintf(outp, "%s%s", delim, mp->name); 926 } 927 } 928 929 if (DO_BIC(BIC_PkgTmp)) 930 outp += sprintf(outp, "%sPkgTmp", (printed++ ? delim : "")); 931 932 if (DO_BIC(BIC_GFX_rc6)) 933 outp += sprintf(outp, "%sGFX%%rc6", (printed++ ? delim : "")); 934 935 if (DO_BIC(BIC_GFXMHz)) 936 outp += sprintf(outp, "%sGFXMHz", (printed++ ? delim : "")); 937 938 if (DO_BIC(BIC_GFXACTMHz)) 939 outp += sprintf(outp, "%sGFXAMHz", (printed++ ? delim : "")); 940 941 if (DO_BIC(BIC_Totl_c0)) 942 outp += sprintf(outp, "%sTotl%%C0", (printed++ ? delim : "")); 943 if (DO_BIC(BIC_Any_c0)) 944 outp += sprintf(outp, "%sAny%%C0", (printed++ ? delim : "")); 945 if (DO_BIC(BIC_GFX_c0)) 946 outp += sprintf(outp, "%sGFX%%C0", (printed++ ? delim : "")); 947 if (DO_BIC(BIC_CPUGFX)) 948 outp += sprintf(outp, "%sCPUGFX%%", (printed++ ? delim : "")); 949 950 if (DO_BIC(BIC_Pkgpc2)) 951 outp += sprintf(outp, "%sPkg%%pc2", (printed++ ? delim : "")); 952 if (DO_BIC(BIC_Pkgpc3)) 953 outp += sprintf(outp, "%sPkg%%pc3", (printed++ ? delim : "")); 954 if (DO_BIC(BIC_Pkgpc6)) 955 outp += sprintf(outp, "%sPkg%%pc6", (printed++ ? delim : "")); 956 if (DO_BIC(BIC_Pkgpc7)) 957 outp += sprintf(outp, "%sPkg%%pc7", (printed++ ? delim : "")); 958 if (DO_BIC(BIC_Pkgpc8)) 959 outp += sprintf(outp, "%sPkg%%pc8", (printed++ ? delim : "")); 960 if (DO_BIC(BIC_Pkgpc9)) 961 outp += sprintf(outp, "%sPkg%%pc9", (printed++ ? delim : "")); 962 if (DO_BIC(BIC_Pkgpc10)) 963 outp += sprintf(outp, "%sPk%%pc10", (printed++ ? delim : "")); 964 if (DO_BIC(BIC_CPU_LPI)) 965 outp += sprintf(outp, "%sCPU%%LPI", (printed++ ? delim : "")); 966 if (DO_BIC(BIC_SYS_LPI)) 967 outp += sprintf(outp, "%sSYS%%LPI", (printed++ ? delim : "")); 968 969 if (do_rapl && !rapl_joules) { 970 if (DO_BIC(BIC_PkgWatt)) 971 outp += sprintf(outp, "%sPkgWatt", (printed++ ? delim : "")); 972 if (DO_BIC(BIC_CorWatt) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 973 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : "")); 974 if (DO_BIC(BIC_GFXWatt)) 975 outp += sprintf(outp, "%sGFXWatt", (printed++ ? delim : "")); 976 if (DO_BIC(BIC_RAMWatt)) 977 outp += sprintf(outp, "%sRAMWatt", (printed++ ? delim : "")); 978 if (DO_BIC(BIC_PKG__)) 979 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : "")); 980 if (DO_BIC(BIC_RAM__)) 981 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : "")); 982 } else if (do_rapl && rapl_joules) { 983 if (DO_BIC(BIC_Pkg_J)) 984 outp += sprintf(outp, "%sPkg_J", (printed++ ? delim : "")); 985 if (DO_BIC(BIC_Cor_J) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 986 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : "")); 987 if (DO_BIC(BIC_GFX_J)) 988 outp += sprintf(outp, "%sGFX_J", (printed++ ? delim : "")); 989 if (DO_BIC(BIC_RAM_J)) 990 outp += sprintf(outp, "%sRAM_J", (printed++ ? delim : "")); 991 if (DO_BIC(BIC_PKG__)) 992 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : "")); 993 if (DO_BIC(BIC_RAM__)) 994 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : "")); 995 } 996 if (DO_BIC(BIC_UNCORE_MHZ)) 997 outp += sprintf(outp, "%sUncMHz", (printed++ ? delim : "")); 998 999 for (mp = sys.pp; mp; mp = mp->next) { 1000 if (mp->format == FORMAT_RAW) { 1001 if (mp->width == 64) 1002 outp += sprintf(outp, "%s%18.18s", delim, mp->name); 1003 else 1004 outp += sprintf(outp, "%s%10.10s", delim, mp->name); 1005 } else { 1006 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1007 outp += sprintf(outp, "%s%8s", delim, mp->name); 1008 else 1009 outp += sprintf(outp, "%s%s", delim, mp->name); 1010 } 1011 } 1012 1013 outp += sprintf(outp, "\n"); 1014} 1015 1016int dump_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1017{ 1018 int i; 1019 struct msr_counter *mp; 1020 1021 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p); 1022 1023 if (t) { 1024 outp += sprintf(outp, "CPU: %d flags 0x%x\n", t->cpu_id, t->flags); 1025 outp += sprintf(outp, "TSC: %016llX\n", t->tsc); 1026 outp += sprintf(outp, "aperf: %016llX\n", t->aperf); 1027 outp += sprintf(outp, "mperf: %016llX\n", t->mperf); 1028 outp += sprintf(outp, "c1: %016llX\n", t->c1); 1029 1030 if (DO_BIC(BIC_IPC)) 1031 outp += sprintf(outp, "IPC: %lld\n", t->instr_count); 1032 1033 if (DO_BIC(BIC_IRQ)) 1034 outp += sprintf(outp, "IRQ: %lld\n", t->irq_count); 1035 if (DO_BIC(BIC_SMI)) 1036 outp += sprintf(outp, "SMI: %d\n", t->smi_count); 1037 1038 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1039 outp += sprintf(outp, "tADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, t->counter[i]); 1040 } 1041 } 1042 1043 if (c) { 1044 outp += sprintf(outp, "core: %d\n", c->core_id); 1045 outp += sprintf(outp, "c3: %016llX\n", c->c3); 1046 outp += sprintf(outp, "c6: %016llX\n", c->c6); 1047 outp += sprintf(outp, "c7: %016llX\n", c->c7); 1048 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c); 1049 outp += sprintf(outp, "cpu_throt_count: %016llX\n", c->core_throt_cnt); 1050 outp += sprintf(outp, "Joules: %0X\n", c->core_energy); 1051 1052 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1053 outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, c->counter[i]); 1054 } 1055 outp += sprintf(outp, "mc6_us: %016llX\n", c->mc6_us); 1056 } 1057 1058 if (p) { 1059 outp += sprintf(outp, "package: %d\n", p->package_id); 1060 1061 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0); 1062 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0); 1063 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0); 1064 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0); 1065 1066 outp += sprintf(outp, "pc2: %016llX\n", p->pc2); 1067 if (DO_BIC(BIC_Pkgpc3)) 1068 outp += sprintf(outp, "pc3: %016llX\n", p->pc3); 1069 if (DO_BIC(BIC_Pkgpc6)) 1070 outp += sprintf(outp, "pc6: %016llX\n", p->pc6); 1071 if (DO_BIC(BIC_Pkgpc7)) 1072 outp += sprintf(outp, "pc7: %016llX\n", p->pc7); 1073 outp += sprintf(outp, "pc8: %016llX\n", p->pc8); 1074 outp += sprintf(outp, "pc9: %016llX\n", p->pc9); 1075 outp += sprintf(outp, "pc10: %016llX\n", p->pc10); 1076 outp += sprintf(outp, "cpu_lpi: %016llX\n", p->cpu_lpi); 1077 outp += sprintf(outp, "sys_lpi: %016llX\n", p->sys_lpi); 1078 outp += sprintf(outp, "Joules PKG: %0llX\n", p->energy_pkg); 1079 outp += sprintf(outp, "Joules COR: %0llX\n", p->energy_cores); 1080 outp += sprintf(outp, "Joules GFX: %0llX\n", p->energy_gfx); 1081 outp += sprintf(outp, "Joules RAM: %0llX\n", p->energy_dram); 1082 outp += sprintf(outp, "Throttle PKG: %0llX\n", p->rapl_pkg_perf_status); 1083 outp += sprintf(outp, "Throttle RAM: %0llX\n", p->rapl_dram_perf_status); 1084 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c); 1085 1086 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1087 outp += sprintf(outp, "pADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, p->counter[i]); 1088 } 1089 } 1090 1091 outp += sprintf(outp, "\n"); 1092 1093 return 0; 1094} 1095 1096/* 1097 * column formatting convention & formats 1098 */ 1099int format_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1100{ 1101 double interval_float, tsc; 1102 char *fmt8; 1103 int i; 1104 struct msr_counter *mp; 1105 char *delim = "\t"; 1106 int printed = 0; 1107 1108 /* if showing only 1st thread in core and this isn't one, bail out */ 1109 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1110 return 0; 1111 1112 /* if showing only 1st thread in pkg and this isn't one, bail out */ 1113 if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1114 return 0; 1115 1116 /*if not summary line and --cpu is used */ 1117 if ((t != &average.threads) && (cpu_subset && !CPU_ISSET_S(t->cpu_id, cpu_subset_size, cpu_subset))) 1118 return 0; 1119 1120 if (DO_BIC(BIC_USEC)) { 1121 /* on each row, print how many usec each timestamp took to gather */ 1122 struct timeval tv; 1123 1124 timersub(&t->tv_end, &t->tv_begin, &tv); 1125 outp += sprintf(outp, "%5ld\t", tv.tv_sec * 1000000 + tv.tv_usec); 1126 } 1127 1128 /* Time_Of_Day_Seconds: on each row, print sec.usec last timestamp taken */ 1129 if (DO_BIC(BIC_TOD)) 1130 outp += sprintf(outp, "%10ld.%06ld\t", t->tv_end.tv_sec, t->tv_end.tv_usec); 1131 1132 interval_float = t->tv_delta.tv_sec + t->tv_delta.tv_usec / 1000000.0; 1133 1134 tsc = t->tsc * tsc_tweak; 1135 1136 /* topo columns, print blanks on 1st (average) line */ 1137 if (t == &average.threads) { 1138 if (DO_BIC(BIC_Package)) 1139 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1140 if (DO_BIC(BIC_Die)) 1141 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1142 if (DO_BIC(BIC_Node)) 1143 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1144 if (DO_BIC(BIC_Core)) 1145 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1146 if (DO_BIC(BIC_CPU)) 1147 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1148 if (DO_BIC(BIC_APIC)) 1149 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1150 if (DO_BIC(BIC_X2APIC)) 1151 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1152 } else { 1153 if (DO_BIC(BIC_Package)) { 1154 if (p) 1155 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->package_id); 1156 else 1157 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1158 } 1159 if (DO_BIC(BIC_Die)) { 1160 if (c) 1161 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), cpus[t->cpu_id].die_id); 1162 else 1163 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1164 } 1165 if (DO_BIC(BIC_Node)) { 1166 if (t) 1167 outp += sprintf(outp, "%s%d", 1168 (printed++ ? delim : ""), cpus[t->cpu_id].physical_node_id); 1169 else 1170 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1171 } 1172 if (DO_BIC(BIC_Core)) { 1173 if (c) 1174 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_id); 1175 else 1176 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1177 } 1178 if (DO_BIC(BIC_CPU)) 1179 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->cpu_id); 1180 if (DO_BIC(BIC_APIC)) 1181 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->apic_id); 1182 if (DO_BIC(BIC_X2APIC)) 1183 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->x2apic_id); 1184 } 1185 1186 if (DO_BIC(BIC_Avg_MHz)) 1187 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 / units * t->aperf / interval_float); 1188 1189 if (DO_BIC(BIC_Busy)) 1190 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->mperf / tsc); 1191 1192 if (DO_BIC(BIC_Bzy_MHz)) { 1193 if (has_base_hz) 1194 outp += 1195 sprintf(outp, "%s%.0f", (printed++ ? delim : ""), base_hz / units * t->aperf / t->mperf); 1196 else 1197 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1198 tsc / units * t->aperf / t->mperf / interval_float); 1199 } 1200 1201 if (DO_BIC(BIC_TSC_MHz)) 1202 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 * t->tsc / units / interval_float); 1203 1204 if (DO_BIC(BIC_IPC)) 1205 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 1.0 * t->instr_count / t->aperf); 1206 1207 /* IRQ */ 1208 if (DO_BIC(BIC_IRQ)) { 1209 if (sums_need_wide_columns) 1210 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->irq_count); 1211 else 1212 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->irq_count); 1213 } 1214 1215 /* SMI */ 1216 if (DO_BIC(BIC_SMI)) 1217 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->smi_count); 1218 1219 /* Added counters */ 1220 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1221 if (mp->format == FORMAT_RAW) { 1222 if (mp->width == 32) 1223 outp += 1224 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)t->counter[i]); 1225 else 1226 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), t->counter[i]); 1227 } else if (mp->format == FORMAT_DELTA) { 1228 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1229 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->counter[i]); 1230 else 1231 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->counter[i]); 1232 } else if (mp->format == FORMAT_PERCENT) { 1233 if (mp->type == COUNTER_USEC) 1234 outp += 1235 sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 1236 t->counter[i] / interval_float / 10000); 1237 else 1238 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->counter[i] / tsc); 1239 } 1240 } 1241 1242 /* C1 */ 1243 if (DO_BIC(BIC_CPU_c1)) 1244 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->c1 / tsc); 1245 1246 /* print per-core data only for 1st thread in core */ 1247 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1248 goto done; 1249 1250 if (DO_BIC(BIC_CPU_c3)) 1251 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c3 / tsc); 1252 if (DO_BIC(BIC_CPU_c6)) 1253 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c6 / tsc); 1254 if (DO_BIC(BIC_CPU_c7)) 1255 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c7 / tsc); 1256 1257 /* Mod%c6 */ 1258 if (DO_BIC(BIC_Mod_c6)) 1259 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->mc6_us / tsc); 1260 1261 if (DO_BIC(BIC_CoreTmp)) 1262 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_temp_c); 1263 1264 /* Core throttle count */ 1265 if (DO_BIC(BIC_CORE_THROT_CNT)) 1266 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), c->core_throt_cnt); 1267 1268 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1269 if (mp->format == FORMAT_RAW) { 1270 if (mp->width == 32) 1271 outp += 1272 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)c->counter[i]); 1273 else 1274 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), c->counter[i]); 1275 } else if (mp->format == FORMAT_DELTA) { 1276 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1277 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), c->counter[i]); 1278 else 1279 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), c->counter[i]); 1280 } else if (mp->format == FORMAT_PERCENT) { 1281 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->counter[i] / tsc); 1282 } 1283 } 1284 1285 fmt8 = "%s%.2f"; 1286 1287 if (DO_BIC(BIC_CorWatt) && (do_rapl & RAPL_PER_CORE_ENERGY)) 1288 outp += 1289 sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units / interval_float); 1290 if (DO_BIC(BIC_Cor_J) && (do_rapl & RAPL_PER_CORE_ENERGY)) 1291 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units); 1292 1293 /* print per-package data only for 1st core in package */ 1294 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1295 goto done; 1296 1297 /* PkgTmp */ 1298 if (DO_BIC(BIC_PkgTmp)) 1299 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->pkg_temp_c); 1300 1301 /* GFXrc6 */ 1302 if (DO_BIC(BIC_GFX_rc6)) { 1303 if (p->gfx_rc6_ms == -1) { /* detect GFX counter reset */ 1304 outp += sprintf(outp, "%s**.**", (printed++ ? delim : "")); 1305 } else { 1306 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 1307 p->gfx_rc6_ms / 10.0 / interval_float); 1308 } 1309 } 1310 1311 /* GFXMHz */ 1312 if (DO_BIC(BIC_GFXMHz)) 1313 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_mhz); 1314 1315 /* GFXACTMHz */ 1316 if (DO_BIC(BIC_GFXACTMHz)) 1317 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_act_mhz); 1318 1319 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */ 1320 if (DO_BIC(BIC_Totl_c0)) 1321 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_wtd_core_c0 / tsc); 1322 if (DO_BIC(BIC_Any_c0)) 1323 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_core_c0 / tsc); 1324 if (DO_BIC(BIC_GFX_c0)) 1325 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_gfxe_c0 / tsc); 1326 if (DO_BIC(BIC_CPUGFX)) 1327 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_both_core_gfxe_c0 / tsc); 1328 1329 if (DO_BIC(BIC_Pkgpc2)) 1330 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc2 / tsc); 1331 if (DO_BIC(BIC_Pkgpc3)) 1332 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc3 / tsc); 1333 if (DO_BIC(BIC_Pkgpc6)) 1334 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc6 / tsc); 1335 if (DO_BIC(BIC_Pkgpc7)) 1336 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc7 / tsc); 1337 if (DO_BIC(BIC_Pkgpc8)) 1338 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc8 / tsc); 1339 if (DO_BIC(BIC_Pkgpc9)) 1340 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc9 / tsc); 1341 if (DO_BIC(BIC_Pkgpc10)) 1342 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc10 / tsc); 1343 1344 if (DO_BIC(BIC_CPU_LPI)) 1345 outp += 1346 sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->cpu_lpi / 1000000.0 / interval_float); 1347 if (DO_BIC(BIC_SYS_LPI)) 1348 outp += 1349 sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->sys_lpi / 1000000.0 / interval_float); 1350 1351 if (DO_BIC(BIC_PkgWatt)) 1352 outp += 1353 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units / interval_float); 1354 1355 if (DO_BIC(BIC_CorWatt) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 1356 outp += 1357 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units / interval_float); 1358 if (DO_BIC(BIC_GFXWatt)) 1359 outp += 1360 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units / interval_float); 1361 if (DO_BIC(BIC_RAMWatt)) 1362 outp += 1363 sprintf(outp, fmt8, (printed++ ? delim : ""), 1364 p->energy_dram * rapl_dram_energy_units / interval_float); 1365 if (DO_BIC(BIC_Pkg_J)) 1366 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units); 1367 if (DO_BIC(BIC_Cor_J) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 1368 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units); 1369 if (DO_BIC(BIC_GFX_J)) 1370 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units); 1371 if (DO_BIC(BIC_RAM_J)) 1372 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_dram * rapl_dram_energy_units); 1373 if (DO_BIC(BIC_PKG__)) 1374 outp += 1375 sprintf(outp, fmt8, (printed++ ? delim : ""), 1376 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float); 1377 if (DO_BIC(BIC_RAM__)) 1378 outp += 1379 sprintf(outp, fmt8, (printed++ ? delim : ""), 1380 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float); 1381 /* UncMHz */ 1382 if (DO_BIC(BIC_UNCORE_MHZ)) 1383 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->uncore_mhz); 1384 1385 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1386 if (mp->format == FORMAT_RAW) { 1387 if (mp->width == 32) 1388 outp += 1389 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)p->counter[i]); 1390 else 1391 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), p->counter[i]); 1392 } else if (mp->format == FORMAT_DELTA) { 1393 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1394 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), p->counter[i]); 1395 else 1396 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), p->counter[i]); 1397 } else if (mp->format == FORMAT_PERCENT) { 1398 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->counter[i] / tsc); 1399 } 1400 } 1401 1402done: 1403 if (*(outp - 1) != '\n') 1404 outp += sprintf(outp, "\n"); 1405 1406 return 0; 1407} 1408 1409void flush_output_stdout(void) 1410{ 1411 FILE *filep; 1412 1413 if (outf == stderr) 1414 filep = stdout; 1415 else 1416 filep = outf; 1417 1418 fputs(output_buffer, filep); 1419 fflush(filep); 1420 1421 outp = output_buffer; 1422} 1423 1424void flush_output_stderr(void) 1425{ 1426 fputs(output_buffer, outf); 1427 fflush(outf); 1428 outp = output_buffer; 1429} 1430 1431void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1432{ 1433 static int count; 1434 1435 if ((!count || (header_iterations && !(count % header_iterations))) || !summary_only) 1436 print_header("\t"); 1437 1438 format_counters(&average.threads, &average.cores, &average.packages); 1439 1440 count++; 1441 1442 if (summary_only) 1443 return; 1444 1445 for_all_cpus(format_counters, t, c, p); 1446} 1447 1448#define DELTA_WRAP32(new, old) \ 1449 old = ((((unsigned long long)new << 32) - ((unsigned long long)old << 32)) >> 32); 1450 1451int delta_package(struct pkg_data *new, struct pkg_data *old) 1452{ 1453 int i; 1454 struct msr_counter *mp; 1455 1456 if (DO_BIC(BIC_Totl_c0)) 1457 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0; 1458 if (DO_BIC(BIC_Any_c0)) 1459 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0; 1460 if (DO_BIC(BIC_GFX_c0)) 1461 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0; 1462 if (DO_BIC(BIC_CPUGFX)) 1463 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0; 1464 1465 old->pc2 = new->pc2 - old->pc2; 1466 if (DO_BIC(BIC_Pkgpc3)) 1467 old->pc3 = new->pc3 - old->pc3; 1468 if (DO_BIC(BIC_Pkgpc6)) 1469 old->pc6 = new->pc6 - old->pc6; 1470 if (DO_BIC(BIC_Pkgpc7)) 1471 old->pc7 = new->pc7 - old->pc7; 1472 old->pc8 = new->pc8 - old->pc8; 1473 old->pc9 = new->pc9 - old->pc9; 1474 old->pc10 = new->pc10 - old->pc10; 1475 old->cpu_lpi = new->cpu_lpi - old->cpu_lpi; 1476 old->sys_lpi = new->sys_lpi - old->sys_lpi; 1477 old->pkg_temp_c = new->pkg_temp_c; 1478 1479 /* flag an error when rc6 counter resets/wraps */ 1480 if (old->gfx_rc6_ms > new->gfx_rc6_ms) 1481 old->gfx_rc6_ms = -1; 1482 else 1483 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms; 1484 1485 old->uncore_mhz = new->uncore_mhz; 1486 old->gfx_mhz = new->gfx_mhz; 1487 old->gfx_act_mhz = new->gfx_act_mhz; 1488 1489 old->energy_pkg = new->energy_pkg - old->energy_pkg; 1490 old->energy_cores = new->energy_cores - old->energy_cores; 1491 old->energy_gfx = new->energy_gfx - old->energy_gfx; 1492 old->energy_dram = new->energy_dram - old->energy_dram; 1493 old->rapl_pkg_perf_status = new->rapl_pkg_perf_status - old->rapl_pkg_perf_status; 1494 old->rapl_dram_perf_status = new->rapl_dram_perf_status - old->rapl_dram_perf_status; 1495 1496 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1497 if (mp->format == FORMAT_RAW) 1498 old->counter[i] = new->counter[i]; 1499 else 1500 old->counter[i] = new->counter[i] - old->counter[i]; 1501 } 1502 1503 return 0; 1504} 1505 1506void delta_core(struct core_data *new, struct core_data *old) 1507{ 1508 int i; 1509 struct msr_counter *mp; 1510 1511 old->c3 = new->c3 - old->c3; 1512 old->c6 = new->c6 - old->c6; 1513 old->c7 = new->c7 - old->c7; 1514 old->core_temp_c = new->core_temp_c; 1515 old->core_throt_cnt = new->core_throt_cnt; 1516 old->mc6_us = new->mc6_us - old->mc6_us; 1517 1518 DELTA_WRAP32(new->core_energy, old->core_energy); 1519 1520 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1521 if (mp->format == FORMAT_RAW) 1522 old->counter[i] = new->counter[i]; 1523 else 1524 old->counter[i] = new->counter[i] - old->counter[i]; 1525 } 1526} 1527 1528int soft_c1_residency_display(int bic) 1529{ 1530 if (!DO_BIC(BIC_CPU_c1) || use_c1_residency_msr) 1531 return 0; 1532 1533 return DO_BIC_READ(bic); 1534} 1535 1536/* 1537 * old = new - old 1538 */ 1539int delta_thread(struct thread_data *new, struct thread_data *old, struct core_data *core_delta) 1540{ 1541 int i; 1542 struct msr_counter *mp; 1543 1544 /* we run cpuid just the 1st time, copy the results */ 1545 if (DO_BIC(BIC_APIC)) 1546 new->apic_id = old->apic_id; 1547 if (DO_BIC(BIC_X2APIC)) 1548 new->x2apic_id = old->x2apic_id; 1549 1550 /* 1551 * the timestamps from start of measurement interval are in "old" 1552 * the timestamp from end of measurement interval are in "new" 1553 * over-write old w/ new so we can print end of interval values 1554 */ 1555 1556 timersub(&new->tv_begin, &old->tv_begin, &old->tv_delta); 1557 old->tv_begin = new->tv_begin; 1558 old->tv_end = new->tv_end; 1559 1560 old->tsc = new->tsc - old->tsc; 1561 1562 /* check for TSC < 1 Mcycles over interval */ 1563 if (old->tsc < (1000 * 1000)) 1564 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n" 1565 "You can disable all c-states by booting with \"idle=poll\"\n" 1566 "or just the deep ones with \"processor.max_cstate=1\""); 1567 1568 old->c1 = new->c1 - old->c1; 1569 1570 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || soft_c1_residency_display(BIC_Avg_MHz)) { 1571 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) { 1572 old->aperf = new->aperf - old->aperf; 1573 old->mperf = new->mperf - old->mperf; 1574 } else { 1575 return -1; 1576 } 1577 } 1578 1579 if (use_c1_residency_msr) { 1580 /* 1581 * Some models have a dedicated C1 residency MSR, 1582 * which should be more accurate than the derivation below. 1583 */ 1584 } else { 1585 /* 1586 * As counter collection is not atomic, 1587 * it is possible for mperf's non-halted cycles + idle states 1588 * to exceed TSC's all cycles: show c1 = 0% in that case. 1589 */ 1590 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > (old->tsc * tsc_tweak)) 1591 old->c1 = 0; 1592 else { 1593 /* normal case, derive c1 */ 1594 old->c1 = (old->tsc * tsc_tweak) - old->mperf - core_delta->c3 1595 - core_delta->c6 - core_delta->c7; 1596 } 1597 } 1598 1599 if (old->mperf == 0) { 1600 if (debug > 1) 1601 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id); 1602 old->mperf = 1; /* divide by 0 protection */ 1603 } 1604 1605 if (DO_BIC(BIC_IPC)) 1606 old->instr_count = new->instr_count - old->instr_count; 1607 1608 if (DO_BIC(BIC_IRQ)) 1609 old->irq_count = new->irq_count - old->irq_count; 1610 1611 if (DO_BIC(BIC_SMI)) 1612 old->smi_count = new->smi_count - old->smi_count; 1613 1614 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1615 if (mp->format == FORMAT_RAW) 1616 old->counter[i] = new->counter[i]; 1617 else 1618 old->counter[i] = new->counter[i] - old->counter[i]; 1619 } 1620 return 0; 1621} 1622 1623int delta_cpu(struct thread_data *t, struct core_data *c, 1624 struct pkg_data *p, struct thread_data *t2, struct core_data *c2, struct pkg_data *p2) 1625{ 1626 int retval = 0; 1627 1628 /* calculate core delta only for 1st thread in core */ 1629 if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE) 1630 delta_core(c, c2); 1631 1632 /* always calculate thread delta */ 1633 retval = delta_thread(t, t2, c2); /* c2 is core delta */ 1634 if (retval) 1635 return retval; 1636 1637 /* calculate package delta only for 1st core in package */ 1638 if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE) 1639 retval = delta_package(p, p2); 1640 1641 return retval; 1642} 1643 1644void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1645{ 1646 int i; 1647 struct msr_counter *mp; 1648 1649 t->tv_begin.tv_sec = 0; 1650 t->tv_begin.tv_usec = 0; 1651 t->tv_end.tv_sec = 0; 1652 t->tv_end.tv_usec = 0; 1653 t->tv_delta.tv_sec = 0; 1654 t->tv_delta.tv_usec = 0; 1655 1656 t->tsc = 0; 1657 t->aperf = 0; 1658 t->mperf = 0; 1659 t->c1 = 0; 1660 1661 t->instr_count = 0; 1662 1663 t->irq_count = 0; 1664 t->smi_count = 0; 1665 1666 /* tells format_counters to dump all fields from this set */ 1667 t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE; 1668 1669 c->c3 = 0; 1670 c->c6 = 0; 1671 c->c7 = 0; 1672 c->mc6_us = 0; 1673 c->core_temp_c = 0; 1674 c->core_energy = 0; 1675 c->core_throt_cnt = 0; 1676 1677 p->pkg_wtd_core_c0 = 0; 1678 p->pkg_any_core_c0 = 0; 1679 p->pkg_any_gfxe_c0 = 0; 1680 p->pkg_both_core_gfxe_c0 = 0; 1681 1682 p->pc2 = 0; 1683 if (DO_BIC(BIC_Pkgpc3)) 1684 p->pc3 = 0; 1685 if (DO_BIC(BIC_Pkgpc6)) 1686 p->pc6 = 0; 1687 if (DO_BIC(BIC_Pkgpc7)) 1688 p->pc7 = 0; 1689 p->pc8 = 0; 1690 p->pc9 = 0; 1691 p->pc10 = 0; 1692 p->cpu_lpi = 0; 1693 p->sys_lpi = 0; 1694 1695 p->energy_pkg = 0; 1696 p->energy_dram = 0; 1697 p->energy_cores = 0; 1698 p->energy_gfx = 0; 1699 p->rapl_pkg_perf_status = 0; 1700 p->rapl_dram_perf_status = 0; 1701 p->pkg_temp_c = 0; 1702 1703 p->gfx_rc6_ms = 0; 1704 p->uncore_mhz = 0; 1705 p->gfx_mhz = 0; 1706 p->gfx_act_mhz = 0; 1707 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) 1708 t->counter[i] = 0; 1709 1710 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) 1711 c->counter[i] = 0; 1712 1713 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) 1714 p->counter[i] = 0; 1715} 1716 1717int sum_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1718{ 1719 int i; 1720 struct msr_counter *mp; 1721 1722 /* copy un-changing apic_id's */ 1723 if (DO_BIC(BIC_APIC)) 1724 average.threads.apic_id = t->apic_id; 1725 if (DO_BIC(BIC_X2APIC)) 1726 average.threads.x2apic_id = t->x2apic_id; 1727 1728 /* remember first tv_begin */ 1729 if (average.threads.tv_begin.tv_sec == 0) 1730 average.threads.tv_begin = t->tv_begin; 1731 1732 /* remember last tv_end */ 1733 average.threads.tv_end = t->tv_end; 1734 1735 average.threads.tsc += t->tsc; 1736 average.threads.aperf += t->aperf; 1737 average.threads.mperf += t->mperf; 1738 average.threads.c1 += t->c1; 1739 1740 average.threads.instr_count += t->instr_count; 1741 1742 average.threads.irq_count += t->irq_count; 1743 average.threads.smi_count += t->smi_count; 1744 1745 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1746 if (mp->format == FORMAT_RAW) 1747 continue; 1748 average.threads.counter[i] += t->counter[i]; 1749 } 1750 1751 /* sum per-core values only for 1st thread in core */ 1752 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1753 return 0; 1754 1755 average.cores.c3 += c->c3; 1756 average.cores.c6 += c->c6; 1757 average.cores.c7 += c->c7; 1758 average.cores.mc6_us += c->mc6_us; 1759 1760 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c); 1761 average.cores.core_throt_cnt = MAX(average.cores.core_throt_cnt, c->core_throt_cnt); 1762 1763 average.cores.core_energy += c->core_energy; 1764 1765 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1766 if (mp->format == FORMAT_RAW) 1767 continue; 1768 average.cores.counter[i] += c->counter[i]; 1769 } 1770 1771 /* sum per-pkg values only for 1st core in pkg */ 1772 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1773 return 0; 1774 1775 if (DO_BIC(BIC_Totl_c0)) 1776 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0; 1777 if (DO_BIC(BIC_Any_c0)) 1778 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0; 1779 if (DO_BIC(BIC_GFX_c0)) 1780 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0; 1781 if (DO_BIC(BIC_CPUGFX)) 1782 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0; 1783 1784 average.packages.pc2 += p->pc2; 1785 if (DO_BIC(BIC_Pkgpc3)) 1786 average.packages.pc3 += p->pc3; 1787 if (DO_BIC(BIC_Pkgpc6)) 1788 average.packages.pc6 += p->pc6; 1789 if (DO_BIC(BIC_Pkgpc7)) 1790 average.packages.pc7 += p->pc7; 1791 average.packages.pc8 += p->pc8; 1792 average.packages.pc9 += p->pc9; 1793 average.packages.pc10 += p->pc10; 1794 1795 average.packages.cpu_lpi = p->cpu_lpi; 1796 average.packages.sys_lpi = p->sys_lpi; 1797 1798 average.packages.energy_pkg += p->energy_pkg; 1799 average.packages.energy_dram += p->energy_dram; 1800 average.packages.energy_cores += p->energy_cores; 1801 average.packages.energy_gfx += p->energy_gfx; 1802 1803 average.packages.gfx_rc6_ms = p->gfx_rc6_ms; 1804 average.packages.uncore_mhz = p->uncore_mhz; 1805 average.packages.gfx_mhz = p->gfx_mhz; 1806 average.packages.gfx_act_mhz = p->gfx_act_mhz; 1807 1808 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c); 1809 1810 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status; 1811 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status; 1812 1813 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1814 if (mp->format == FORMAT_RAW) 1815 continue; 1816 average.packages.counter[i] += p->counter[i]; 1817 } 1818 return 0; 1819} 1820 1821/* 1822 * sum the counters for all cpus in the system 1823 * compute the weighted average 1824 */ 1825void compute_average(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1826{ 1827 int i; 1828 struct msr_counter *mp; 1829 1830 clear_counters(&average.threads, &average.cores, &average.packages); 1831 1832 for_all_cpus(sum_counters, t, c, p); 1833 1834 /* Use the global time delta for the average. */ 1835 average.threads.tv_delta = tv_delta; 1836 1837 average.threads.tsc /= topo.num_cpus; 1838 average.threads.aperf /= topo.num_cpus; 1839 average.threads.mperf /= topo.num_cpus; 1840 average.threads.instr_count /= topo.num_cpus; 1841 average.threads.c1 /= topo.num_cpus; 1842 1843 if (average.threads.irq_count > 9999999) 1844 sums_need_wide_columns = 1; 1845 1846 average.cores.c3 /= topo.num_cores; 1847 average.cores.c6 /= topo.num_cores; 1848 average.cores.c7 /= topo.num_cores; 1849 average.cores.mc6_us /= topo.num_cores; 1850 1851 if (DO_BIC(BIC_Totl_c0)) 1852 average.packages.pkg_wtd_core_c0 /= topo.num_packages; 1853 if (DO_BIC(BIC_Any_c0)) 1854 average.packages.pkg_any_core_c0 /= topo.num_packages; 1855 if (DO_BIC(BIC_GFX_c0)) 1856 average.packages.pkg_any_gfxe_c0 /= topo.num_packages; 1857 if (DO_BIC(BIC_CPUGFX)) 1858 average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages; 1859 1860 average.packages.pc2 /= topo.num_packages; 1861 if (DO_BIC(BIC_Pkgpc3)) 1862 average.packages.pc3 /= topo.num_packages; 1863 if (DO_BIC(BIC_Pkgpc6)) 1864 average.packages.pc6 /= topo.num_packages; 1865 if (DO_BIC(BIC_Pkgpc7)) 1866 average.packages.pc7 /= topo.num_packages; 1867 1868 average.packages.pc8 /= topo.num_packages; 1869 average.packages.pc9 /= topo.num_packages; 1870 average.packages.pc10 /= topo.num_packages; 1871 1872 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1873 if (mp->format == FORMAT_RAW) 1874 continue; 1875 if (mp->type == COUNTER_ITEMS) { 1876 if (average.threads.counter[i] > 9999999) 1877 sums_need_wide_columns = 1; 1878 continue; 1879 } 1880 average.threads.counter[i] /= topo.num_cpus; 1881 } 1882 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1883 if (mp->format == FORMAT_RAW) 1884 continue; 1885 if (mp->type == COUNTER_ITEMS) { 1886 if (average.cores.counter[i] > 9999999) 1887 sums_need_wide_columns = 1; 1888 } 1889 average.cores.counter[i] /= topo.num_cores; 1890 } 1891 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1892 if (mp->format == FORMAT_RAW) 1893 continue; 1894 if (mp->type == COUNTER_ITEMS) { 1895 if (average.packages.counter[i] > 9999999) 1896 sums_need_wide_columns = 1; 1897 } 1898 average.packages.counter[i] /= topo.num_packages; 1899 } 1900} 1901 1902static unsigned long long rdtsc(void) 1903{ 1904 unsigned int low, high; 1905 1906 asm volatile ("rdtsc":"=a" (low), "=d"(high)); 1907 1908 return low | ((unsigned long long)high) << 32; 1909} 1910 1911/* 1912 * Open a file, and exit on failure 1913 */ 1914FILE *fopen_or_die(const char *path, const char *mode) 1915{ 1916 FILE *filep = fopen(path, mode); 1917 1918 if (!filep) 1919 err(1, "%s: open failed", path); 1920 return filep; 1921} 1922 1923/* 1924 * snapshot_sysfs_counter() 1925 * 1926 * return snapshot of given counter 1927 */ 1928unsigned long long snapshot_sysfs_counter(char *path) 1929{ 1930 FILE *fp; 1931 int retval; 1932 unsigned long long counter; 1933 1934 fp = fopen_or_die(path, "r"); 1935 1936 retval = fscanf(fp, "%lld", &counter); 1937 if (retval != 1) 1938 err(1, "snapshot_sysfs_counter(%s)", path); 1939 1940 fclose(fp); 1941 1942 return counter; 1943} 1944 1945int get_mp(int cpu, struct msr_counter *mp, unsigned long long *counterp) 1946{ 1947 if (mp->msr_num != 0) { 1948 if (get_msr(cpu, mp->msr_num, counterp)) 1949 return -1; 1950 } else { 1951 char path[128 + PATH_BYTES]; 1952 1953 if (mp->flags & SYSFS_PERCPU) { 1954 sprintf(path, "/sys/devices/system/cpu/cpu%d/%s", cpu, mp->path); 1955 1956 *counterp = snapshot_sysfs_counter(path); 1957 } else { 1958 *counterp = snapshot_sysfs_counter(mp->path); 1959 } 1960 } 1961 1962 return 0; 1963} 1964 1965unsigned long long get_uncore_mhz(int package, int die) 1966{ 1967 char path[128]; 1968 1969 sprintf(path, "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/current_freq_khz", package, 1970 die); 1971 1972 return (snapshot_sysfs_counter(path) / 1000); 1973} 1974 1975int get_epb(int cpu) 1976{ 1977 char path[128 + PATH_BYTES]; 1978 unsigned long long msr; 1979 int ret, epb = -1; 1980 FILE *fp; 1981 1982 sprintf(path, "/sys/devices/system/cpu/cpu%d/power/energy_perf_bias", cpu); 1983 1984 fp = fopen(path, "r"); 1985 if (!fp) 1986 goto msr_fallback; 1987 1988 ret = fscanf(fp, "%d", &epb); 1989 if (ret != 1) 1990 err(1, "%s(%s)", __func__, path); 1991 1992 fclose(fp); 1993 1994 return epb; 1995 1996msr_fallback: 1997 get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr); 1998 1999 return msr & 0xf; 2000} 2001 2002void get_apic_id(struct thread_data *t) 2003{ 2004 unsigned int eax, ebx, ecx, edx; 2005 2006 if (DO_BIC(BIC_APIC)) { 2007 eax = ebx = ecx = edx = 0; 2008 __cpuid(1, eax, ebx, ecx, edx); 2009 2010 t->apic_id = (ebx >> 24) & 0xff; 2011 } 2012 2013 if (!DO_BIC(BIC_X2APIC)) 2014 return; 2015 2016 if (authentic_amd || hygon_genuine) { 2017 unsigned int topology_extensions; 2018 2019 if (max_extended_level < 0x8000001e) 2020 return; 2021 2022 eax = ebx = ecx = edx = 0; 2023 __cpuid(0x80000001, eax, ebx, ecx, edx); 2024 topology_extensions = ecx & (1 << 22); 2025 2026 if (topology_extensions == 0) 2027 return; 2028 2029 eax = ebx = ecx = edx = 0; 2030 __cpuid(0x8000001e, eax, ebx, ecx, edx); 2031 2032 t->x2apic_id = eax; 2033 return; 2034 } 2035 2036 if (!genuine_intel) 2037 return; 2038 2039 if (max_level < 0xb) 2040 return; 2041 2042 ecx = 0; 2043 __cpuid(0xb, eax, ebx, ecx, edx); 2044 t->x2apic_id = edx; 2045 2046 if (debug && (t->apic_id != (t->x2apic_id & 0xff))) 2047 fprintf(outf, "cpu%d: BIOS BUG: apic 0x%x x2apic 0x%x\n", t->cpu_id, t->apic_id, t->x2apic_id); 2048} 2049 2050int get_core_throt_cnt(int cpu, unsigned long long *cnt) 2051{ 2052 char path[128 + PATH_BYTES]; 2053 unsigned long long tmp; 2054 FILE *fp; 2055 int ret; 2056 2057 sprintf(path, "/sys/devices/system/cpu/cpu%d/thermal_throttle/core_throttle_count", cpu); 2058 fp = fopen(path, "r"); 2059 if (!fp) 2060 return -1; 2061 ret = fscanf(fp, "%lld", &tmp); 2062 fclose(fp); 2063 if (ret != 1) 2064 return -1; 2065 *cnt = tmp; 2066 2067 return 0; 2068} 2069 2070/* 2071 * get_counters(...) 2072 * migrate to cpu 2073 * acquire and record local counters for that cpu 2074 */ 2075int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2076{ 2077 int cpu = t->cpu_id; 2078 unsigned long long msr; 2079 int aperf_mperf_retry_count = 0; 2080 struct msr_counter *mp; 2081 int i; 2082 2083 if (cpu_migrate(cpu)) { 2084 fprintf(outf, "get_counters: Could not migrate to CPU %d\n", cpu); 2085 return -1; 2086 } 2087 2088 gettimeofday(&t->tv_begin, (struct timezone *)NULL); 2089 2090 if (first_counter_read) 2091 get_apic_id(t); 2092retry: 2093 t->tsc = rdtsc(); /* we are running on local CPU of interest */ 2094 2095 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || soft_c1_residency_display(BIC_Avg_MHz)) { 2096 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time; 2097 2098 /* 2099 * The TSC, APERF and MPERF must be read together for 2100 * APERF/MPERF and MPERF/TSC to give accurate results. 2101 * 2102 * Unfortunately, APERF and MPERF are read by 2103 * individual system call, so delays may occur 2104 * between them. If the time to read them 2105 * varies by a large amount, we re-read them. 2106 */ 2107 2108 /* 2109 * This initial dummy APERF read has been seen to 2110 * reduce jitter in the subsequent reads. 2111 */ 2112 2113 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 2114 return -3; 2115 2116 t->tsc = rdtsc(); /* re-read close to APERF */ 2117 2118 tsc_before = t->tsc; 2119 2120 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 2121 return -3; 2122 2123 tsc_between = rdtsc(); 2124 2125 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf)) 2126 return -4; 2127 2128 tsc_after = rdtsc(); 2129 2130 aperf_time = tsc_between - tsc_before; 2131 mperf_time = tsc_after - tsc_between; 2132 2133 /* 2134 * If the system call latency to read APERF and MPERF 2135 * differ by more than 2x, then try again. 2136 */ 2137 if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) { 2138 aperf_mperf_retry_count++; 2139 if (aperf_mperf_retry_count < 5) 2140 goto retry; 2141 else 2142 warnx("cpu%d jitter %lld %lld", cpu, aperf_time, mperf_time); 2143 } 2144 aperf_mperf_retry_count = 0; 2145 2146 t->aperf = t->aperf * aperf_mperf_multiplier; 2147 t->mperf = t->mperf * aperf_mperf_multiplier; 2148 } 2149 2150 if (DO_BIC(BIC_IPC)) 2151 if (read(get_instr_count_fd(cpu), &t->instr_count, sizeof(long long)) != sizeof(long long)) 2152 return -4; 2153 2154 if (DO_BIC(BIC_IRQ)) 2155 t->irq_count = irqs_per_cpu[cpu]; 2156 if (DO_BIC(BIC_SMI)) { 2157 if (get_msr(cpu, MSR_SMI_COUNT, &msr)) 2158 return -5; 2159 t->smi_count = msr & 0xFFFFFFFF; 2160 } 2161 if (DO_BIC(BIC_CPU_c1) && use_c1_residency_msr) { 2162 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1)) 2163 return -6; 2164 } 2165 2166 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 2167 if (get_mp(cpu, mp, &t->counter[i])) 2168 return -10; 2169 } 2170 2171 /* collect core counters only for 1st thread in core */ 2172 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 2173 goto done; 2174 2175 if (DO_BIC(BIC_CPU_c3) || soft_c1_residency_display(BIC_CPU_c3)) { 2176 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3)) 2177 return -6; 2178 } 2179 2180 if ((DO_BIC(BIC_CPU_c6) || soft_c1_residency_display(BIC_CPU_c6)) && !do_knl_cstates) { 2181 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6)) 2182 return -7; 2183 } else if (do_knl_cstates && soft_c1_residency_display(BIC_CPU_c6)) { 2184 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6)) 2185 return -7; 2186 } 2187 2188 if (DO_BIC(BIC_CPU_c7) || soft_c1_residency_display(BIC_CPU_c7)) { 2189 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7)) 2190 return -8; 2191 else if (t->is_atom) { 2192 /* 2193 * For Atom CPUs that has core cstate deeper than c6, 2194 * MSR_CORE_C6_RESIDENCY returns residency of cc6 and deeper. 2195 * Minus CC7 (and deeper cstates) residency to get 2196 * accturate cc6 residency. 2197 */ 2198 c->c6 -= c->c7; 2199 } 2200 } 2201 2202 if (DO_BIC(BIC_Mod_c6)) 2203 if (get_msr(cpu, MSR_MODULE_C6_RES_MS, &c->mc6_us)) 2204 return -8; 2205 2206 if (DO_BIC(BIC_CoreTmp)) { 2207 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 2208 return -9; 2209 c->core_temp_c = tj_max - ((msr >> 16) & 0x7F); 2210 } 2211 2212 if (DO_BIC(BIC_CORE_THROT_CNT)) 2213 get_core_throt_cnt(cpu, &c->core_throt_cnt); 2214 2215 if (do_rapl & RAPL_AMD_F17H) { 2216 if (get_msr(cpu, MSR_CORE_ENERGY_STAT, &msr)) 2217 return -14; 2218 c->core_energy = msr & 0xFFFFFFFF; 2219 } 2220 2221 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 2222 if (get_mp(cpu, mp, &c->counter[i])) 2223 return -10; 2224 } 2225 2226 /* collect package counters only for 1st core in package */ 2227 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 2228 goto done; 2229 2230 if (DO_BIC(BIC_Totl_c0)) { 2231 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0)) 2232 return -10; 2233 } 2234 if (DO_BIC(BIC_Any_c0)) { 2235 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0)) 2236 return -11; 2237 } 2238 if (DO_BIC(BIC_GFX_c0)) { 2239 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0)) 2240 return -12; 2241 } 2242 if (DO_BIC(BIC_CPUGFX)) { 2243 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0)) 2244 return -13; 2245 } 2246 if (DO_BIC(BIC_Pkgpc3)) 2247 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3)) 2248 return -9; 2249 if (DO_BIC(BIC_Pkgpc6)) { 2250 if (do_slm_cstates) { 2251 if (get_msr(cpu, MSR_ATOM_PKG_C6_RESIDENCY, &p->pc6)) 2252 return -10; 2253 } else { 2254 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6)) 2255 return -10; 2256 } 2257 } 2258 2259 if (DO_BIC(BIC_Pkgpc2)) 2260 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2)) 2261 return -11; 2262 if (DO_BIC(BIC_Pkgpc7)) 2263 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7)) 2264 return -12; 2265 if (DO_BIC(BIC_Pkgpc8)) 2266 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8)) 2267 return -13; 2268 if (DO_BIC(BIC_Pkgpc9)) 2269 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9)) 2270 return -13; 2271 if (DO_BIC(BIC_Pkgpc10)) 2272 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10)) 2273 return -13; 2274 2275 if (DO_BIC(BIC_CPU_LPI)) 2276 p->cpu_lpi = cpuidle_cur_cpu_lpi_us; 2277 if (DO_BIC(BIC_SYS_LPI)) 2278 p->sys_lpi = cpuidle_cur_sys_lpi_us; 2279 2280 if (do_rapl & RAPL_PKG) { 2281 if (get_msr_sum(cpu, MSR_PKG_ENERGY_STATUS, &msr)) 2282 return -13; 2283 p->energy_pkg = msr; 2284 } 2285 if (do_rapl & RAPL_CORES_ENERGY_STATUS) { 2286 if (get_msr_sum(cpu, MSR_PP0_ENERGY_STATUS, &msr)) 2287 return -14; 2288 p->energy_cores = msr; 2289 } 2290 if (do_rapl & RAPL_DRAM) { 2291 if (get_msr_sum(cpu, MSR_DRAM_ENERGY_STATUS, &msr)) 2292 return -15; 2293 p->energy_dram = msr; 2294 } 2295 if (do_rapl & RAPL_GFX) { 2296 if (get_msr_sum(cpu, MSR_PP1_ENERGY_STATUS, &msr)) 2297 return -16; 2298 p->energy_gfx = msr; 2299 } 2300 if (do_rapl & RAPL_PKG_PERF_STATUS) { 2301 if (get_msr_sum(cpu, MSR_PKG_PERF_STATUS, &msr)) 2302 return -16; 2303 p->rapl_pkg_perf_status = msr; 2304 } 2305 if (do_rapl & RAPL_DRAM_PERF_STATUS) { 2306 if (get_msr_sum(cpu, MSR_DRAM_PERF_STATUS, &msr)) 2307 return -16; 2308 p->rapl_dram_perf_status = msr; 2309 } 2310 if (do_rapl & RAPL_AMD_F17H) { 2311 if (get_msr_sum(cpu, MSR_PKG_ENERGY_STAT, &msr)) 2312 return -13; 2313 p->energy_pkg = msr; 2314 } 2315 if (DO_BIC(BIC_PkgTmp)) { 2316 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 2317 return -17; 2318 p->pkg_temp_c = tj_max - ((msr >> 16) & 0x7F); 2319 } 2320 2321 if (DO_BIC(BIC_GFX_rc6)) 2322 p->gfx_rc6_ms = gfx_cur_rc6_ms; 2323 2324 /* n.b. assume die0 uncore frequency applies to whole package */ 2325 if (DO_BIC(BIC_UNCORE_MHZ)) 2326 p->uncore_mhz = get_uncore_mhz(p->package_id, 0); 2327 2328 if (DO_BIC(BIC_GFXMHz)) 2329 p->gfx_mhz = gfx_cur_mhz; 2330 2331 if (DO_BIC(BIC_GFXACTMHz)) 2332 p->gfx_act_mhz = gfx_act_mhz; 2333 2334 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 2335 if (get_mp(cpu, mp, &p->counter[i])) 2336 return -10; 2337 } 2338done: 2339 gettimeofday(&t->tv_end, (struct timezone *)NULL); 2340 2341 return 0; 2342} 2343 2344/* 2345 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit: 2346 * If you change the values, note they are used both in comparisons 2347 * (>= PCL__7) and to index pkg_cstate_limit_strings[]. 2348 */ 2349 2350#define PCLUKN 0 /* Unknown */ 2351#define PCLRSV 1 /* Reserved */ 2352#define PCL__0 2 /* PC0 */ 2353#define PCL__1 3 /* PC1 */ 2354#define PCL__2 4 /* PC2 */ 2355#define PCL__3 5 /* PC3 */ 2356#define PCL__4 6 /* PC4 */ 2357#define PCL__6 7 /* PC6 */ 2358#define PCL_6N 8 /* PC6 No Retention */ 2359#define PCL_6R 9 /* PC6 Retention */ 2360#define PCL__7 10 /* PC7 */ 2361#define PCL_7S 11 /* PC7 Shrink */ 2362#define PCL__8 12 /* PC8 */ 2363#define PCL__9 13 /* PC9 */ 2364#define PCL_10 14 /* PC10 */ 2365#define PCLUNL 15 /* Unlimited */ 2366 2367int pkg_cstate_limit = PCLUKN; 2368char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2", 2369 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "pc10", "unlimited" 2370}; 2371 2372int nhm_pkg_cstate_limits[16] = 2373 { PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2374 PCLRSV, PCLRSV 2375}; 2376 2377int snb_pkg_cstate_limits[16] = 2378 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2379 PCLRSV, PCLRSV 2380}; 2381 2382int hsw_pkg_cstate_limits[16] = 2383 { PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2384 PCLRSV, PCLRSV 2385}; 2386 2387int slv_pkg_cstate_limits[16] = 2388 { PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2389 PCL__6, PCL__7 2390}; 2391 2392int amt_pkg_cstate_limits[16] = 2393 { PCLUNL, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2394 PCLRSV, PCLRSV 2395}; 2396 2397int phi_pkg_cstate_limits[16] = 2398 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2399 PCLRSV, PCLRSV 2400}; 2401 2402int glm_pkg_cstate_limits[16] = 2403 { PCLUNL, PCL__1, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCL_10, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2404 PCLRSV, PCLRSV 2405}; 2406 2407int skx_pkg_cstate_limits[16] = 2408 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2409 PCLRSV, PCLRSV 2410}; 2411 2412int icx_pkg_cstate_limits[16] = 2413 { PCL__0, PCL__2, PCL__6, PCL__6, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2414 PCLRSV, PCLRSV 2415}; 2416 2417static void calculate_tsc_tweak() 2418{ 2419 tsc_tweak = base_hz / tsc_hz; 2420} 2421 2422void prewake_cstate_probe(unsigned int family, unsigned int model); 2423 2424static void dump_nhm_platform_info(void) 2425{ 2426 unsigned long long msr; 2427 unsigned int ratio; 2428 2429 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 2430 2431 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr); 2432 2433 ratio = (msr >> 40) & 0xFF; 2434 fprintf(outf, "%d * %.1f = %.1f MHz max efficiency frequency\n", ratio, bclk, ratio * bclk); 2435 2436 ratio = (msr >> 8) & 0xFF; 2437 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", ratio, bclk, ratio * bclk); 2438 2439 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr); 2440 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n", 2441 base_cpu, msr, msr & 0x2 ? "EN" : "DIS"); 2442 2443 /* C-state Pre-wake Disable (CSTATE_PREWAKE_DISABLE) */ 2444 if (dis_cstate_prewake) 2445 fprintf(outf, "C-state Pre-wake: %sabled\n", msr & 0x40000000 ? "DIS" : "EN"); 2446 2447 return; 2448} 2449 2450static void dump_hsw_turbo_ratio_limits(void) 2451{ 2452 unsigned long long msr; 2453 unsigned int ratio; 2454 2455 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr); 2456 2457 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr); 2458 2459 ratio = (msr >> 8) & 0xFF; 2460 if (ratio) 2461 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 18 active cores\n", ratio, bclk, ratio * bclk); 2462 2463 ratio = (msr >> 0) & 0xFF; 2464 if (ratio) 2465 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 17 active cores\n", ratio, bclk, ratio * bclk); 2466 return; 2467} 2468 2469static void dump_ivt_turbo_ratio_limits(void) 2470{ 2471 unsigned long long msr; 2472 unsigned int ratio; 2473 2474 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr); 2475 2476 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr); 2477 2478 ratio = (msr >> 56) & 0xFF; 2479 if (ratio) 2480 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 16 active cores\n", ratio, bclk, ratio * bclk); 2481 2482 ratio = (msr >> 48) & 0xFF; 2483 if (ratio) 2484 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 15 active cores\n", ratio, bclk, ratio * bclk); 2485 2486 ratio = (msr >> 40) & 0xFF; 2487 if (ratio) 2488 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 14 active cores\n", ratio, bclk, ratio * bclk); 2489 2490 ratio = (msr >> 32) & 0xFF; 2491 if (ratio) 2492 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 13 active cores\n", ratio, bclk, ratio * bclk); 2493 2494 ratio = (msr >> 24) & 0xFF; 2495 if (ratio) 2496 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 12 active cores\n", ratio, bclk, ratio * bclk); 2497 2498 ratio = (msr >> 16) & 0xFF; 2499 if (ratio) 2500 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 11 active cores\n", ratio, bclk, ratio * bclk); 2501 2502 ratio = (msr >> 8) & 0xFF; 2503 if (ratio) 2504 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 10 active cores\n", ratio, bclk, ratio * bclk); 2505 2506 ratio = (msr >> 0) & 0xFF; 2507 if (ratio) 2508 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 9 active cores\n", ratio, bclk, ratio * bclk); 2509 return; 2510} 2511 2512int has_turbo_ratio_group_limits(int family, int model) 2513{ 2514 2515 if (!genuine_intel) 2516 return 0; 2517 2518 if (family != 6) 2519 return 0; 2520 2521 switch (model) { 2522 case INTEL_FAM6_ATOM_GOLDMONT: 2523 case INTEL_FAM6_SKYLAKE_X: 2524 case INTEL_FAM6_ICELAKE_X: 2525 case INTEL_FAM6_SAPPHIRERAPIDS_X: 2526 case INTEL_FAM6_ATOM_GOLDMONT_D: 2527 case INTEL_FAM6_ATOM_TREMONT_D: 2528 return 1; 2529 default: 2530 return 0; 2531 } 2532} 2533 2534static void dump_turbo_ratio_limits(int trl_msr_offset, int family, int model) 2535{ 2536 unsigned long long msr, core_counts; 2537 int shift; 2538 2539 get_msr(base_cpu, trl_msr_offset, &msr); 2540 fprintf(outf, "cpu%d: MSR_%sTURBO_RATIO_LIMIT: 0x%08llx\n", 2541 base_cpu, trl_msr_offset == MSR_SECONDARY_TURBO_RATIO_LIMIT ? "SECONDARY_" : "", msr); 2542 2543 if (has_turbo_ratio_group_limits(family, model)) { 2544 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &core_counts); 2545 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, core_counts); 2546 } else { 2547 core_counts = 0x0807060504030201; 2548 } 2549 2550 for (shift = 56; shift >= 0; shift -= 8) { 2551 unsigned int ratio, group_size; 2552 2553 ratio = (msr >> shift) & 0xFF; 2554 group_size = (core_counts >> shift) & 0xFF; 2555 if (ratio) 2556 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2557 ratio, bclk, ratio * bclk, group_size); 2558 } 2559 2560 return; 2561} 2562 2563static void dump_atom_turbo_ratio_limits(void) 2564{ 2565 unsigned long long msr; 2566 unsigned int ratio; 2567 2568 get_msr(base_cpu, MSR_ATOM_CORE_RATIOS, &msr); 2569 fprintf(outf, "cpu%d: MSR_ATOM_CORE_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF); 2570 2571 ratio = (msr >> 0) & 0x3F; 2572 if (ratio) 2573 fprintf(outf, "%d * %.1f = %.1f MHz minimum operating frequency\n", ratio, bclk, ratio * bclk); 2574 2575 ratio = (msr >> 8) & 0x3F; 2576 if (ratio) 2577 fprintf(outf, "%d * %.1f = %.1f MHz low frequency mode (LFM)\n", ratio, bclk, ratio * bclk); 2578 2579 ratio = (msr >> 16) & 0x3F; 2580 if (ratio) 2581 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", ratio, bclk, ratio * bclk); 2582 2583 get_msr(base_cpu, MSR_ATOM_CORE_TURBO_RATIOS, &msr); 2584 fprintf(outf, "cpu%d: MSR_ATOM_CORE_TURBO_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF); 2585 2586 ratio = (msr >> 24) & 0x3F; 2587 if (ratio) 2588 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n", ratio, bclk, ratio * bclk); 2589 2590 ratio = (msr >> 16) & 0x3F; 2591 if (ratio) 2592 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n", ratio, bclk, ratio * bclk); 2593 2594 ratio = (msr >> 8) & 0x3F; 2595 if (ratio) 2596 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n", ratio, bclk, ratio * bclk); 2597 2598 ratio = (msr >> 0) & 0x3F; 2599 if (ratio) 2600 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active core\n", ratio, bclk, ratio * bclk); 2601} 2602 2603static void dump_knl_turbo_ratio_limits(void) 2604{ 2605 const unsigned int buckets_no = 7; 2606 2607 unsigned long long msr; 2608 int delta_cores, delta_ratio; 2609 int i, b_nr; 2610 unsigned int cores[buckets_no]; 2611 unsigned int ratio[buckets_no]; 2612 2613 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 2614 2615 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr); 2616 2617 /* 2618 * Turbo encoding in KNL is as follows: 2619 * [0] -- Reserved 2620 * [7:1] -- Base value of number of active cores of bucket 1. 2621 * [15:8] -- Base value of freq ratio of bucket 1. 2622 * [20:16] -- +ve delta of number of active cores of bucket 2. 2623 * i.e. active cores of bucket 2 = 2624 * active cores of bucket 1 + delta 2625 * [23:21] -- Negative delta of freq ratio of bucket 2. 2626 * i.e. freq ratio of bucket 2 = 2627 * freq ratio of bucket 1 - delta 2628 * [28:24]-- +ve delta of number of active cores of bucket 3. 2629 * [31:29]-- -ve delta of freq ratio of bucket 3. 2630 * [36:32]-- +ve delta of number of active cores of bucket 4. 2631 * [39:37]-- -ve delta of freq ratio of bucket 4. 2632 * [44:40]-- +ve delta of number of active cores of bucket 5. 2633 * [47:45]-- -ve delta of freq ratio of bucket 5. 2634 * [52:48]-- +ve delta of number of active cores of bucket 6. 2635 * [55:53]-- -ve delta of freq ratio of bucket 6. 2636 * [60:56]-- +ve delta of number of active cores of bucket 7. 2637 * [63:61]-- -ve delta of freq ratio of bucket 7. 2638 */ 2639 2640 b_nr = 0; 2641 cores[b_nr] = (msr & 0xFF) >> 1; 2642 ratio[b_nr] = (msr >> 8) & 0xFF; 2643 2644 for (i = 16; i < 64; i += 8) { 2645 delta_cores = (msr >> i) & 0x1F; 2646 delta_ratio = (msr >> (i + 5)) & 0x7; 2647 2648 cores[b_nr + 1] = cores[b_nr] + delta_cores; 2649 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio; 2650 b_nr++; 2651 } 2652 2653 for (i = buckets_no - 1; i >= 0; i--) 2654 if (i > 0 ? ratio[i] != ratio[i - 1] : 1) 2655 fprintf(outf, 2656 "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2657 ratio[i], bclk, ratio[i] * bclk, cores[i]); 2658} 2659 2660static void dump_nhm_cst_cfg(void) 2661{ 2662 unsigned long long msr; 2663 2664 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr); 2665 2666 fprintf(outf, "cpu%d: MSR_PKG_CST_CONFIG_CONTROL: 0x%08llx", base_cpu, msr); 2667 2668 fprintf(outf, " (%s%s%s%s%slocked, pkg-cstate-limit=%d (%s)", 2669 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "", 2670 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "", 2671 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "", 2672 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "", 2673 (msr & (1 << 15)) ? "" : "UN", (unsigned int)msr & 0xF, pkg_cstate_limit_strings[pkg_cstate_limit]); 2674 2675#define AUTOMATIC_CSTATE_CONVERSION (1UL << 16) 2676 if (has_automatic_cstate_conversion) { 2677 fprintf(outf, ", automatic c-state conversion=%s", (msr & AUTOMATIC_CSTATE_CONVERSION) ? "on" : "off"); 2678 } 2679 2680 fprintf(outf, ")\n"); 2681 2682 return; 2683} 2684 2685static void dump_config_tdp(void) 2686{ 2687 unsigned long long msr; 2688 2689 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr); 2690 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr); 2691 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF); 2692 2693 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr); 2694 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr); 2695 if (msr) { 2696 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 2697 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 2698 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 2699 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF); 2700 } 2701 fprintf(outf, ")\n"); 2702 2703 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr); 2704 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr); 2705 if (msr) { 2706 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 2707 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 2708 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 2709 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF); 2710 } 2711 fprintf(outf, ")\n"); 2712 2713 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr); 2714 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr); 2715 if ((msr) & 0x3) 2716 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3); 2717 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 2718 fprintf(outf, ")\n"); 2719 2720 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr); 2721 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr); 2722 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF); 2723 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 2724 fprintf(outf, ")\n"); 2725} 2726 2727unsigned int irtl_time_units[] = { 1, 32, 1024, 32768, 1048576, 33554432, 0, 0 }; 2728 2729void print_irtl(void) 2730{ 2731 unsigned long long msr; 2732 2733 get_msr(base_cpu, MSR_PKGC3_IRTL, &msr); 2734 fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr); 2735 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2736 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2737 2738 get_msr(base_cpu, MSR_PKGC6_IRTL, &msr); 2739 fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr); 2740 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2741 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2742 2743 get_msr(base_cpu, MSR_PKGC7_IRTL, &msr); 2744 fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr); 2745 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2746 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2747 2748 if (!do_irtl_hsw) 2749 return; 2750 2751 get_msr(base_cpu, MSR_PKGC8_IRTL, &msr); 2752 fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr); 2753 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2754 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2755 2756 get_msr(base_cpu, MSR_PKGC9_IRTL, &msr); 2757 fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr); 2758 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2759 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2760 2761 get_msr(base_cpu, MSR_PKGC10_IRTL, &msr); 2762 fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr); 2763 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2764 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2765 2766} 2767 2768void free_fd_percpu(void) 2769{ 2770 int i; 2771 2772 for (i = 0; i < topo.max_cpu_num + 1; ++i) { 2773 if (fd_percpu[i] != 0) 2774 close(fd_percpu[i]); 2775 } 2776 2777 free(fd_percpu); 2778} 2779 2780void free_all_buffers(void) 2781{ 2782 int i; 2783 2784 CPU_FREE(cpu_present_set); 2785 cpu_present_set = NULL; 2786 cpu_present_setsize = 0; 2787 2788 CPU_FREE(cpu_affinity_set); 2789 cpu_affinity_set = NULL; 2790 cpu_affinity_setsize = 0; 2791 2792 free(thread_even); 2793 free(core_even); 2794 free(package_even); 2795 2796 thread_even = NULL; 2797 core_even = NULL; 2798 package_even = NULL; 2799 2800 free(thread_odd); 2801 free(core_odd); 2802 free(package_odd); 2803 2804 thread_odd = NULL; 2805 core_odd = NULL; 2806 package_odd = NULL; 2807 2808 free(output_buffer); 2809 output_buffer = NULL; 2810 outp = NULL; 2811 2812 free_fd_percpu(); 2813 2814 free(irq_column_2_cpu); 2815 free(irqs_per_cpu); 2816 2817 for (i = 0; i <= topo.max_cpu_num; ++i) { 2818 if (cpus[i].put_ids) 2819 CPU_FREE(cpus[i].put_ids); 2820 } 2821 free(cpus); 2822} 2823 2824/* 2825 * Parse a file containing a single int. 2826 * Return 0 if file can not be opened 2827 * Exit if file can be opened, but can not be parsed 2828 */ 2829int parse_int_file(const char *fmt, ...) 2830{ 2831 va_list args; 2832 char path[PATH_MAX]; 2833 FILE *filep; 2834 int value; 2835 2836 va_start(args, fmt); 2837 vsnprintf(path, sizeof(path), fmt, args); 2838 va_end(args); 2839 filep = fopen(path, "r"); 2840 if (!filep) 2841 return 0; 2842 if (fscanf(filep, "%d", &value) != 1) 2843 err(1, "%s: failed to parse number from file", path); 2844 fclose(filep); 2845 return value; 2846} 2847 2848/* 2849 * cpu_is_first_core_in_package(cpu) 2850 * return 1 if given CPU is 1st core in package 2851 */ 2852int cpu_is_first_core_in_package(int cpu) 2853{ 2854 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu); 2855} 2856 2857int get_physical_package_id(int cpu) 2858{ 2859 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu); 2860} 2861 2862int get_die_id(int cpu) 2863{ 2864 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/die_id", cpu); 2865} 2866 2867int get_core_id(int cpu) 2868{ 2869 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu); 2870} 2871 2872void set_node_data(void) 2873{ 2874 int pkg, node, lnode, cpu, cpux; 2875 int cpu_count; 2876 2877 /* initialize logical_node_id */ 2878 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu) 2879 cpus[cpu].logical_node_id = -1; 2880 2881 cpu_count = 0; 2882 for (pkg = 0; pkg < topo.num_packages; pkg++) { 2883 lnode = 0; 2884 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu) { 2885 if (cpus[cpu].physical_package_id != pkg) 2886 continue; 2887 /* find a cpu with an unset logical_node_id */ 2888 if (cpus[cpu].logical_node_id != -1) 2889 continue; 2890 cpus[cpu].logical_node_id = lnode; 2891 node = cpus[cpu].physical_node_id; 2892 cpu_count++; 2893 /* 2894 * find all matching cpus on this pkg and set 2895 * the logical_node_id 2896 */ 2897 for (cpux = cpu; cpux <= topo.max_cpu_num; cpux++) { 2898 if ((cpus[cpux].physical_package_id == pkg) && (cpus[cpux].physical_node_id == node)) { 2899 cpus[cpux].logical_node_id = lnode; 2900 cpu_count++; 2901 } 2902 } 2903 lnode++; 2904 if (lnode > topo.nodes_per_pkg) 2905 topo.nodes_per_pkg = lnode; 2906 } 2907 if (cpu_count >= topo.max_cpu_num) 2908 break; 2909 } 2910} 2911 2912int get_physical_node_id(struct cpu_topology *thiscpu) 2913{ 2914 char path[80]; 2915 FILE *filep; 2916 int i; 2917 int cpu = thiscpu->logical_cpu_id; 2918 2919 for (i = 0; i <= topo.max_cpu_num; i++) { 2920 sprintf(path, "/sys/devices/system/cpu/cpu%d/node%i/cpulist", cpu, i); 2921 filep = fopen(path, "r"); 2922 if (!filep) 2923 continue; 2924 fclose(filep); 2925 return i; 2926 } 2927 return -1; 2928} 2929 2930int get_thread_siblings(struct cpu_topology *thiscpu) 2931{ 2932 char path[80], character; 2933 FILE *filep; 2934 unsigned long map; 2935 int so, shift, sib_core; 2936 int cpu = thiscpu->logical_cpu_id; 2937 int offset = topo.max_cpu_num + 1; 2938 size_t size; 2939 int thread_id = 0; 2940 2941 thiscpu->put_ids = CPU_ALLOC((topo.max_cpu_num + 1)); 2942 if (thiscpu->thread_id < 0) 2943 thiscpu->thread_id = thread_id++; 2944 if (!thiscpu->put_ids) 2945 return -1; 2946 2947 size = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 2948 CPU_ZERO_S(size, thiscpu->put_ids); 2949 2950 sprintf(path, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", cpu); 2951 filep = fopen(path, "r"); 2952 2953 if (!filep) { 2954 warnx("%s: open failed", path); 2955 return -1; 2956 } 2957 do { 2958 offset -= BITMASK_SIZE; 2959 if (fscanf(filep, "%lx%c", &map, &character) != 2) 2960 err(1, "%s: failed to parse file", path); 2961 for (shift = 0; shift < BITMASK_SIZE; shift++) { 2962 if ((map >> shift) & 0x1) { 2963 so = shift + offset; 2964 sib_core = get_core_id(so); 2965 if (sib_core == thiscpu->physical_core_id) { 2966 CPU_SET_S(so, size, thiscpu->put_ids); 2967 if ((so != cpu) && (cpus[so].thread_id < 0)) 2968 cpus[so].thread_id = thread_id++; 2969 } 2970 } 2971 } 2972 } while (character == ','); 2973 fclose(filep); 2974 2975 return CPU_COUNT_S(size, thiscpu->put_ids); 2976} 2977 2978/* 2979 * run func(thread, core, package) in topology order 2980 * skip non-present cpus 2981 */ 2982 2983int for_all_cpus_2(int (func) (struct thread_data *, struct core_data *, 2984 struct pkg_data *, struct thread_data *, struct core_data *, 2985 struct pkg_data *), struct thread_data *thread_base, 2986 struct core_data *core_base, struct pkg_data *pkg_base, 2987 struct thread_data *thread_base2, struct core_data *core_base2, struct pkg_data *pkg_base2) 2988{ 2989 int retval, pkg_no, node_no, core_no, thread_no; 2990 2991 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 2992 for (node_no = 0; node_no < topo.nodes_per_pkg; ++node_no) { 2993 for (core_no = 0; core_no < topo.cores_per_node; ++core_no) { 2994 for (thread_no = 0; thread_no < topo.threads_per_core; ++thread_no) { 2995 struct thread_data *t, *t2; 2996 struct core_data *c, *c2; 2997 struct pkg_data *p, *p2; 2998 2999 t = GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no); 3000 3001 if (cpu_is_not_present(t->cpu_id)) 3002 continue; 3003 3004 t2 = GET_THREAD(thread_base2, thread_no, core_no, node_no, pkg_no); 3005 3006 c = GET_CORE(core_base, core_no, node_no, pkg_no); 3007 c2 = GET_CORE(core_base2, core_no, node_no, pkg_no); 3008 3009 p = GET_PKG(pkg_base, pkg_no); 3010 p2 = GET_PKG(pkg_base2, pkg_no); 3011 3012 retval = func(t, c, p, t2, c2, p2); 3013 if (retval) 3014 return retval; 3015 } 3016 } 3017 } 3018 } 3019 return 0; 3020} 3021 3022/* 3023 * run func(cpu) on every cpu in /proc/stat 3024 * return max_cpu number 3025 */ 3026int for_all_proc_cpus(int (func) (int)) 3027{ 3028 FILE *fp; 3029 int cpu_num; 3030 int retval; 3031 3032 fp = fopen_or_die(proc_stat, "r"); 3033 3034 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n"); 3035 if (retval != 0) 3036 err(1, "%s: failed to parse format", proc_stat); 3037 3038 while (1) { 3039 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num); 3040 if (retval != 1) 3041 break; 3042 3043 retval = func(cpu_num); 3044 if (retval) { 3045 fclose(fp); 3046 return (retval); 3047 } 3048 } 3049 fclose(fp); 3050 return 0; 3051} 3052 3053void re_initialize(void) 3054{ 3055 free_all_buffers(); 3056 setup_all_buffers(); 3057 fprintf(outf, "turbostat: re-initialized with num_cpus %d\n", topo.num_cpus); 3058} 3059 3060void set_max_cpu_num(void) 3061{ 3062 FILE *filep; 3063 int base_cpu; 3064 unsigned long dummy; 3065 char pathname[64]; 3066 3067 base_cpu = sched_getcpu(); 3068 if (base_cpu < 0) 3069 err(1, "cannot find calling cpu ID"); 3070 sprintf(pathname, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", base_cpu); 3071 3072 filep = fopen_or_die(pathname, "r"); 3073 topo.max_cpu_num = 0; 3074 while (fscanf(filep, "%lx,", &dummy) == 1) 3075 topo.max_cpu_num += BITMASK_SIZE; 3076 fclose(filep); 3077 topo.max_cpu_num--; /* 0 based */ 3078} 3079 3080/* 3081 * count_cpus() 3082 * remember the last one seen, it will be the max 3083 */ 3084int count_cpus(int cpu) 3085{ 3086 UNUSED(cpu); 3087 3088 topo.num_cpus++; 3089 return 0; 3090} 3091 3092int mark_cpu_present(int cpu) 3093{ 3094 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set); 3095 return 0; 3096} 3097 3098int init_thread_id(int cpu) 3099{ 3100 cpus[cpu].thread_id = -1; 3101 return 0; 3102} 3103 3104/* 3105 * snapshot_proc_interrupts() 3106 * 3107 * read and record summary of /proc/interrupts 3108 * 3109 * return 1 if config change requires a restart, else return 0 3110 */ 3111int snapshot_proc_interrupts(void) 3112{ 3113 static FILE *fp; 3114 int column, retval; 3115 3116 if (fp == NULL) 3117 fp = fopen_or_die("/proc/interrupts", "r"); 3118 else 3119 rewind(fp); 3120 3121 /* read 1st line of /proc/interrupts to get cpu* name for each column */ 3122 for (column = 0; column < topo.num_cpus; ++column) { 3123 int cpu_number; 3124 3125 retval = fscanf(fp, " CPU%d", &cpu_number); 3126 if (retval != 1) 3127 break; 3128 3129 if (cpu_number > topo.max_cpu_num) { 3130 warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num); 3131 return 1; 3132 } 3133 3134 irq_column_2_cpu[column] = cpu_number; 3135 irqs_per_cpu[cpu_number] = 0; 3136 } 3137 3138 /* read /proc/interrupt count lines and sum up irqs per cpu */ 3139 while (1) { 3140 int column; 3141 char buf[64]; 3142 3143 retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */ 3144 if (retval != 1) 3145 break; 3146 3147 /* read the count per cpu */ 3148 for (column = 0; column < topo.num_cpus; ++column) { 3149 3150 int cpu_number, irq_count; 3151 3152 retval = fscanf(fp, " %d", &irq_count); 3153 if (retval != 1) 3154 break; 3155 3156 cpu_number = irq_column_2_cpu[column]; 3157 irqs_per_cpu[cpu_number] += irq_count; 3158 3159 } 3160 3161 while (getc(fp) != '\n') ; /* flush interrupt description */ 3162 3163 } 3164 return 0; 3165} 3166 3167/* 3168 * snapshot_gfx_rc6_ms() 3169 * 3170 * record snapshot of 3171 * /sys/class/drm/card0/power/rc6_residency_ms 3172 * 3173 * return 1 if config change requires a restart, else return 0 3174 */ 3175int snapshot_gfx_rc6_ms(void) 3176{ 3177 FILE *fp; 3178 int retval; 3179 3180 fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r"); 3181 3182 retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms); 3183 if (retval != 1) 3184 err(1, "GFX rc6"); 3185 3186 fclose(fp); 3187 3188 return 0; 3189} 3190 3191/* 3192 * snapshot_gfx_mhz() 3193 * 3194 * record snapshot of 3195 * /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz 3196 * 3197 * return 1 if config change requires a restart, else return 0 3198 */ 3199int snapshot_gfx_mhz(void) 3200{ 3201 static FILE *fp; 3202 int retval; 3203 3204 if (fp == NULL) 3205 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r"); 3206 else { 3207 rewind(fp); 3208 fflush(fp); 3209 } 3210 3211 retval = fscanf(fp, "%d", &gfx_cur_mhz); 3212 if (retval != 1) 3213 err(1, "GFX MHz"); 3214 3215 return 0; 3216} 3217 3218/* 3219 * snapshot_gfx_cur_mhz() 3220 * 3221 * record snapshot of 3222 * /sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz 3223 * 3224 * return 1 if config change requires a restart, else return 0 3225 */ 3226int snapshot_gfx_act_mhz(void) 3227{ 3228 static FILE *fp; 3229 int retval; 3230 3231 if (fp == NULL) 3232 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz", "r"); 3233 else { 3234 rewind(fp); 3235 fflush(fp); 3236 } 3237 3238 retval = fscanf(fp, "%d", &gfx_act_mhz); 3239 if (retval != 1) 3240 err(1, "GFX ACT MHz"); 3241 3242 return 0; 3243} 3244 3245/* 3246 * snapshot_cpu_lpi() 3247 * 3248 * record snapshot of 3249 * /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us 3250 */ 3251int snapshot_cpu_lpi_us(void) 3252{ 3253 FILE *fp; 3254 int retval; 3255 3256 fp = fopen_or_die("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", "r"); 3257 3258 retval = fscanf(fp, "%lld", &cpuidle_cur_cpu_lpi_us); 3259 if (retval != 1) { 3260 fprintf(stderr, "Disabling Low Power Idle CPU output\n"); 3261 BIC_NOT_PRESENT(BIC_CPU_LPI); 3262 fclose(fp); 3263 return -1; 3264 } 3265 3266 fclose(fp); 3267 3268 return 0; 3269} 3270 3271/* 3272 * snapshot_sys_lpi() 3273 * 3274 * record snapshot of sys_lpi_file 3275 */ 3276int snapshot_sys_lpi_us(void) 3277{ 3278 FILE *fp; 3279 int retval; 3280 3281 fp = fopen_or_die(sys_lpi_file, "r"); 3282 3283 retval = fscanf(fp, "%lld", &cpuidle_cur_sys_lpi_us); 3284 if (retval != 1) { 3285 fprintf(stderr, "Disabling Low Power Idle System output\n"); 3286 BIC_NOT_PRESENT(BIC_SYS_LPI); 3287 fclose(fp); 3288 return -1; 3289 } 3290 fclose(fp); 3291 3292 return 0; 3293} 3294 3295/* 3296 * snapshot /proc and /sys files 3297 * 3298 * return 1 if configuration restart needed, else return 0 3299 */ 3300int snapshot_proc_sysfs_files(void) 3301{ 3302 if (DO_BIC(BIC_IRQ)) 3303 if (snapshot_proc_interrupts()) 3304 return 1; 3305 3306 if (DO_BIC(BIC_GFX_rc6)) 3307 snapshot_gfx_rc6_ms(); 3308 3309 if (DO_BIC(BIC_GFXMHz)) 3310 snapshot_gfx_mhz(); 3311 3312 if (DO_BIC(BIC_GFXACTMHz)) 3313 snapshot_gfx_act_mhz(); 3314 3315 if (DO_BIC(BIC_CPU_LPI)) 3316 snapshot_cpu_lpi_us(); 3317 3318 if (DO_BIC(BIC_SYS_LPI)) 3319 snapshot_sys_lpi_us(); 3320 3321 return 0; 3322} 3323 3324int exit_requested; 3325 3326static void signal_handler(int signal) 3327{ 3328 switch (signal) { 3329 case SIGINT: 3330 exit_requested = 1; 3331 if (debug) 3332 fprintf(stderr, " SIGINT\n"); 3333 break; 3334 case SIGUSR1: 3335 if (debug > 1) 3336 fprintf(stderr, "SIGUSR1\n"); 3337 break; 3338 } 3339} 3340 3341void setup_signal_handler(void) 3342{ 3343 struct sigaction sa; 3344 3345 memset(&sa, 0, sizeof(sa)); 3346 3347 sa.sa_handler = &signal_handler; 3348 3349 if (sigaction(SIGINT, &sa, NULL) < 0) 3350 err(1, "sigaction SIGINT"); 3351 if (sigaction(SIGUSR1, &sa, NULL) < 0) 3352 err(1, "sigaction SIGUSR1"); 3353} 3354 3355void do_sleep(void) 3356{ 3357 struct timeval tout; 3358 struct timespec rest; 3359 fd_set readfds; 3360 int retval; 3361 3362 FD_ZERO(&readfds); 3363 FD_SET(0, &readfds); 3364 3365 if (ignore_stdin) { 3366 nanosleep(&interval_ts, NULL); 3367 return; 3368 } 3369 3370 tout = interval_tv; 3371 retval = select(1, &readfds, NULL, NULL, &tout); 3372 3373 if (retval == 1) { 3374 switch (getc(stdin)) { 3375 case 'q': 3376 exit_requested = 1; 3377 break; 3378 case EOF: 3379 /* 3380 * 'stdin' is a pipe closed on the other end. There 3381 * won't be any further input. 3382 */ 3383 ignore_stdin = 1; 3384 /* Sleep the rest of the time */ 3385 rest.tv_sec = (tout.tv_sec + tout.tv_usec / 1000000); 3386 rest.tv_nsec = (tout.tv_usec % 1000000) * 1000; 3387 nanosleep(&rest, NULL); 3388 } 3389 } 3390} 3391 3392int get_msr_sum(int cpu, off_t offset, unsigned long long *msr) 3393{ 3394 int ret, idx; 3395 unsigned long long msr_cur, msr_last; 3396 3397 if (!per_cpu_msr_sum) 3398 return 1; 3399 3400 idx = offset_to_idx(offset); 3401 if (idx < 0) 3402 return idx; 3403 /* get_msr_sum() = sum + (get_msr() - last) */ 3404 ret = get_msr(cpu, offset, &msr_cur); 3405 if (ret) 3406 return ret; 3407 msr_last = per_cpu_msr_sum[cpu].entries[idx].last; 3408 DELTA_WRAP32(msr_cur, msr_last); 3409 *msr = msr_last + per_cpu_msr_sum[cpu].entries[idx].sum; 3410 3411 return 0; 3412} 3413 3414timer_t timerid; 3415 3416/* Timer callback, update the sum of MSRs periodically. */ 3417static int update_msr_sum(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3418{ 3419 int i, ret; 3420 int cpu = t->cpu_id; 3421 3422 UNUSED(c); 3423 UNUSED(p); 3424 3425 for (i = IDX_PKG_ENERGY; i < IDX_COUNT; i++) { 3426 unsigned long long msr_cur, msr_last; 3427 off_t offset; 3428 3429 if (!idx_valid(i)) 3430 continue; 3431 offset = idx_to_offset(i); 3432 if (offset < 0) 3433 continue; 3434 ret = get_msr(cpu, offset, &msr_cur); 3435 if (ret) { 3436 fprintf(outf, "Can not update msr(0x%llx)\n", (unsigned long long)offset); 3437 continue; 3438 } 3439 3440 msr_last = per_cpu_msr_sum[cpu].entries[i].last; 3441 per_cpu_msr_sum[cpu].entries[i].last = msr_cur & 0xffffffff; 3442 3443 DELTA_WRAP32(msr_cur, msr_last); 3444 per_cpu_msr_sum[cpu].entries[i].sum += msr_last; 3445 } 3446 return 0; 3447} 3448 3449static void msr_record_handler(union sigval v) 3450{ 3451 UNUSED(v); 3452 3453 for_all_cpus(update_msr_sum, EVEN_COUNTERS); 3454} 3455 3456void msr_sum_record(void) 3457{ 3458 struct itimerspec its; 3459 struct sigevent sev; 3460 3461 per_cpu_msr_sum = calloc(topo.max_cpu_num + 1, sizeof(struct msr_sum_array)); 3462 if (!per_cpu_msr_sum) { 3463 fprintf(outf, "Can not allocate memory for long time MSR.\n"); 3464 return; 3465 } 3466 /* 3467 * Signal handler might be restricted, so use thread notifier instead. 3468 */ 3469 memset(&sev, 0, sizeof(struct sigevent)); 3470 sev.sigev_notify = SIGEV_THREAD; 3471 sev.sigev_notify_function = msr_record_handler; 3472 3473 sev.sigev_value.sival_ptr = &timerid; 3474 if (timer_create(CLOCK_REALTIME, &sev, &timerid) == -1) { 3475 fprintf(outf, "Can not create timer.\n"); 3476 goto release_msr; 3477 } 3478 3479 its.it_value.tv_sec = 0; 3480 its.it_value.tv_nsec = 1; 3481 /* 3482 * A wraparound time has been calculated early. 3483 * Some sources state that the peak power for a 3484 * microprocessor is usually 1.5 times the TDP rating, 3485 * use 2 * TDP for safety. 3486 */ 3487 its.it_interval.tv_sec = rapl_joule_counter_range / 2; 3488 its.it_interval.tv_nsec = 0; 3489 3490 if (timer_settime(timerid, 0, &its, NULL) == -1) { 3491 fprintf(outf, "Can not set timer.\n"); 3492 goto release_timer; 3493 } 3494 return; 3495 3496release_timer: 3497 timer_delete(timerid); 3498release_msr: 3499 free(per_cpu_msr_sum); 3500} 3501 3502/* 3503 * set_my_sched_priority(pri) 3504 * return previous 3505 */ 3506int set_my_sched_priority(int priority) 3507{ 3508 int retval; 3509 int original_priority; 3510 3511 errno = 0; 3512 original_priority = getpriority(PRIO_PROCESS, 0); 3513 if (errno && (original_priority == -1)) 3514 err(errno, "getpriority"); 3515 3516 retval = setpriority(PRIO_PROCESS, 0, priority); 3517 if (retval) 3518 errx(retval, "capget(CAP_SYS_NICE) failed,try \"# setcap cap_sys_nice=ep %s\"", progname); 3519 3520 errno = 0; 3521 retval = getpriority(PRIO_PROCESS, 0); 3522 if (retval != priority) 3523 err(retval, "getpriority(%d) != setpriority(%d)", retval, priority); 3524 3525 return original_priority; 3526} 3527 3528void turbostat_loop() 3529{ 3530 int retval; 3531 int restarted = 0; 3532 unsigned int done_iters = 0; 3533 3534 setup_signal_handler(); 3535 3536 /* 3537 * elevate own priority for interval mode 3538 */ 3539 set_my_sched_priority(-20); 3540 3541restart: 3542 restarted++; 3543 3544 snapshot_proc_sysfs_files(); 3545 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 3546 first_counter_read = 0; 3547 if (retval < -1) { 3548 exit(retval); 3549 } else if (retval == -1) { 3550 if (restarted > 10) { 3551 exit(retval); 3552 } 3553 re_initialize(); 3554 goto restart; 3555 } 3556 restarted = 0; 3557 done_iters = 0; 3558 gettimeofday(&tv_even, (struct timezone *)NULL); 3559 3560 while (1) { 3561 if (for_all_proc_cpus(cpu_is_not_present)) { 3562 re_initialize(); 3563 goto restart; 3564 } 3565 do_sleep(); 3566 if (snapshot_proc_sysfs_files()) 3567 goto restart; 3568 retval = for_all_cpus(get_counters, ODD_COUNTERS); 3569 if (retval < -1) { 3570 exit(retval); 3571 } else if (retval == -1) { 3572 re_initialize(); 3573 goto restart; 3574 } 3575 gettimeofday(&tv_odd, (struct timezone *)NULL); 3576 timersub(&tv_odd, &tv_even, &tv_delta); 3577 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) { 3578 re_initialize(); 3579 goto restart; 3580 } 3581 compute_average(EVEN_COUNTERS); 3582 format_all_counters(EVEN_COUNTERS); 3583 flush_output_stdout(); 3584 if (exit_requested) 3585 break; 3586 if (num_iterations && ++done_iters >= num_iterations) 3587 break; 3588 do_sleep(); 3589 if (snapshot_proc_sysfs_files()) 3590 goto restart; 3591 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 3592 if (retval < -1) { 3593 exit(retval); 3594 } else if (retval == -1) { 3595 re_initialize(); 3596 goto restart; 3597 } 3598 gettimeofday(&tv_even, (struct timezone *)NULL); 3599 timersub(&tv_even, &tv_odd, &tv_delta); 3600 if (for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS)) { 3601 re_initialize(); 3602 goto restart; 3603 } 3604 compute_average(ODD_COUNTERS); 3605 format_all_counters(ODD_COUNTERS); 3606 flush_output_stdout(); 3607 if (exit_requested) 3608 break; 3609 if (num_iterations && ++done_iters >= num_iterations) 3610 break; 3611 } 3612} 3613 3614void check_dev_msr() 3615{ 3616 struct stat sb; 3617 char pathname[32]; 3618 3619 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 3620 if (stat(pathname, &sb)) 3621 if (system("/sbin/modprobe msr > /dev/null 2>&1")) 3622 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" "); 3623} 3624 3625/* 3626 * check for CAP_SYS_RAWIO 3627 * return 0 on success 3628 * return 1 on fail 3629 */ 3630int check_for_cap_sys_rawio(void) 3631{ 3632 cap_t caps; 3633 cap_flag_value_t cap_flag_value; 3634 3635 caps = cap_get_proc(); 3636 if (caps == NULL) 3637 err(-6, "cap_get_proc\n"); 3638 3639 if (cap_get_flag(caps, CAP_SYS_RAWIO, CAP_EFFECTIVE, &cap_flag_value)) 3640 err(-6, "cap_get\n"); 3641 3642 if (cap_flag_value != CAP_SET) { 3643 warnx("capget(CAP_SYS_RAWIO) failed," " try \"# setcap cap_sys_rawio=ep %s\"", progname); 3644 return 1; 3645 } 3646 3647 if (cap_free(caps) == -1) 3648 err(-6, "cap_free\n"); 3649 3650 return 0; 3651} 3652 3653void check_permissions(void) 3654{ 3655 int do_exit = 0; 3656 char pathname[32]; 3657 3658 /* check for CAP_SYS_RAWIO */ 3659 do_exit += check_for_cap_sys_rawio(); 3660 3661 /* test file permissions */ 3662 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 3663 if (euidaccess(pathname, R_OK)) { 3664 do_exit++; 3665 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr"); 3666 } 3667 3668 /* if all else fails, thell them to be root */ 3669 if (do_exit) 3670 if (getuid() != 0) 3671 warnx("... or simply run as root"); 3672 3673 if (do_exit) 3674 exit(-6); 3675} 3676 3677/* 3678 * NHM adds support for additional MSRs: 3679 * 3680 * MSR_SMI_COUNT 0x00000034 3681 * 3682 * MSR_PLATFORM_INFO 0x000000ce 3683 * MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 3684 * 3685 * MSR_MISC_PWR_MGMT 0x000001aa 3686 * 3687 * MSR_PKG_C3_RESIDENCY 0x000003f8 3688 * MSR_PKG_C6_RESIDENCY 0x000003f9 3689 * MSR_CORE_C3_RESIDENCY 0x000003fc 3690 * MSR_CORE_C6_RESIDENCY 0x000003fd 3691 * 3692 * Side effect: 3693 * sets global pkg_cstate_limit to decode MSR_PKG_CST_CONFIG_CONTROL 3694 * sets has_misc_feature_control 3695 */ 3696int probe_nhm_msrs(unsigned int family, unsigned int model) 3697{ 3698 unsigned long long msr; 3699 unsigned int base_ratio; 3700 int *pkg_cstate_limits; 3701 3702 if (!genuine_intel) 3703 return 0; 3704 3705 if (family != 6) 3706 return 0; 3707 3708 bclk = discover_bclk(family, model); 3709 3710 switch (model) { 3711 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ 3712 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 3713 pkg_cstate_limits = nhm_pkg_cstate_limits; 3714 break; 3715 case INTEL_FAM6_SANDYBRIDGE: /* SNB */ 3716 case INTEL_FAM6_SANDYBRIDGE_X: /* SNB Xeon */ 3717 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 3718 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 3719 pkg_cstate_limits = snb_pkg_cstate_limits; 3720 has_misc_feature_control = 1; 3721 break; 3722 case INTEL_FAM6_HASWELL: /* HSW */ 3723 case INTEL_FAM6_HASWELL_G: /* HSW */ 3724 case INTEL_FAM6_HASWELL_X: /* HSX */ 3725 case INTEL_FAM6_HASWELL_L: /* HSW */ 3726 case INTEL_FAM6_BROADWELL: /* BDW */ 3727 case INTEL_FAM6_BROADWELL_G: /* BDW */ 3728 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3729 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 3730 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 3731 pkg_cstate_limits = hsw_pkg_cstate_limits; 3732 has_misc_feature_control = 1; 3733 break; 3734 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3735 case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */ 3736 pkg_cstate_limits = skx_pkg_cstate_limits; 3737 has_misc_feature_control = 1; 3738 break; 3739 case INTEL_FAM6_ICELAKE_X: /* ICX */ 3740 pkg_cstate_limits = icx_pkg_cstate_limits; 3741 has_misc_feature_control = 1; 3742 break; 3743 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */ 3744 no_MSR_MISC_PWR_MGMT = 1; 3745 /* FALLTHRU */ 3746 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */ 3747 pkg_cstate_limits = slv_pkg_cstate_limits; 3748 break; 3749 case INTEL_FAM6_ATOM_AIRMONT: /* AMT */ 3750 pkg_cstate_limits = amt_pkg_cstate_limits; 3751 no_MSR_MISC_PWR_MGMT = 1; 3752 break; 3753 case INTEL_FAM6_XEON_PHI_KNL: /* PHI */ 3754 pkg_cstate_limits = phi_pkg_cstate_limits; 3755 break; 3756 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 3757 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 3758 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */ 3759 case INTEL_FAM6_ATOM_TREMONT: /* EHL */ 3760 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */ 3761 pkg_cstate_limits = glm_pkg_cstate_limits; 3762 break; 3763 default: 3764 return 0; 3765 } 3766 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr); 3767 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF]; 3768 3769 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 3770 base_ratio = (msr >> 8) & 0xFF; 3771 3772 base_hz = base_ratio * bclk * 1000000; 3773 has_base_hz = 1; 3774 return 1; 3775} 3776 3777/* 3778 * SLV client has support for unique MSRs: 3779 * 3780 * MSR_CC6_DEMOTION_POLICY_CONFIG 3781 * MSR_MC6_DEMOTION_POLICY_CONFIG 3782 */ 3783 3784int has_slv_msrs(unsigned int family, unsigned int model) 3785{ 3786 if (!genuine_intel) 3787 return 0; 3788 3789 if (family != 6) 3790 return 0; 3791 3792 switch (model) { 3793 case INTEL_FAM6_ATOM_SILVERMONT: 3794 case INTEL_FAM6_ATOM_SILVERMONT_MID: 3795 case INTEL_FAM6_ATOM_AIRMONT_MID: 3796 return 1; 3797 } 3798 return 0; 3799} 3800 3801int is_dnv(unsigned int family, unsigned int model) 3802{ 3803 3804 if (!genuine_intel) 3805 return 0; 3806 3807 if (family != 6) 3808 return 0; 3809 3810 switch (model) { 3811 case INTEL_FAM6_ATOM_GOLDMONT_D: 3812 return 1; 3813 } 3814 return 0; 3815} 3816 3817int is_bdx(unsigned int family, unsigned int model) 3818{ 3819 3820 if (!genuine_intel) 3821 return 0; 3822 3823 if (family != 6) 3824 return 0; 3825 3826 switch (model) { 3827 case INTEL_FAM6_BROADWELL_X: 3828 return 1; 3829 } 3830 return 0; 3831} 3832 3833int is_skx(unsigned int family, unsigned int model) 3834{ 3835 3836 if (!genuine_intel) 3837 return 0; 3838 3839 if (family != 6) 3840 return 0; 3841 3842 switch (model) { 3843 case INTEL_FAM6_SKYLAKE_X: 3844 return 1; 3845 } 3846 return 0; 3847} 3848 3849int is_icx(unsigned int family, unsigned int model) 3850{ 3851 3852 if (!genuine_intel) 3853 return 0; 3854 3855 if (family != 6) 3856 return 0; 3857 3858 switch (model) { 3859 case INTEL_FAM6_ICELAKE_X: 3860 return 1; 3861 } 3862 return 0; 3863} 3864 3865int is_spr(unsigned int family, unsigned int model) 3866{ 3867 3868 if (!genuine_intel) 3869 return 0; 3870 3871 if (family != 6) 3872 return 0; 3873 3874 switch (model) { 3875 case INTEL_FAM6_SAPPHIRERAPIDS_X: 3876 return 1; 3877 } 3878 return 0; 3879} 3880 3881int is_ehl(unsigned int family, unsigned int model) 3882{ 3883 if (!genuine_intel) 3884 return 0; 3885 3886 if (family != 6) 3887 return 0; 3888 3889 switch (model) { 3890 case INTEL_FAM6_ATOM_TREMONT: 3891 return 1; 3892 } 3893 return 0; 3894} 3895 3896int is_jvl(unsigned int family, unsigned int model) 3897{ 3898 if (!genuine_intel) 3899 return 0; 3900 3901 if (family != 6) 3902 return 0; 3903 3904 switch (model) { 3905 case INTEL_FAM6_ATOM_TREMONT_D: 3906 return 1; 3907 } 3908 return 0; 3909} 3910 3911int has_turbo_ratio_limit(unsigned int family, unsigned int model) 3912{ 3913 if (has_slv_msrs(family, model)) 3914 return 0; 3915 3916 if (family != 6) 3917 return 0; 3918 3919 switch (model) { 3920 /* Nehalem compatible, but do not include turbo-ratio limit support */ 3921 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 3922 case INTEL_FAM6_XEON_PHI_KNL: /* PHI - Knights Landing (different MSR definition) */ 3923 return 0; 3924 default: 3925 return 1; 3926 } 3927} 3928 3929int has_atom_turbo_ratio_limit(unsigned int family, unsigned int model) 3930{ 3931 if (has_slv_msrs(family, model)) 3932 return 1; 3933 3934 return 0; 3935} 3936 3937int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model) 3938{ 3939 if (!genuine_intel) 3940 return 0; 3941 3942 if (family != 6) 3943 return 0; 3944 3945 switch (model) { 3946 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 3947 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ 3948 return 1; 3949 default: 3950 return 0; 3951 } 3952} 3953 3954int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model) 3955{ 3956 if (!genuine_intel) 3957 return 0; 3958 3959 if (family != 6) 3960 return 0; 3961 3962 switch (model) { 3963 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ 3964 return 1; 3965 default: 3966 return 0; 3967 } 3968} 3969 3970int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model) 3971{ 3972 if (!genuine_intel) 3973 return 0; 3974 3975 if (family != 6) 3976 return 0; 3977 3978 switch (model) { 3979 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ 3980 return 1; 3981 default: 3982 return 0; 3983 } 3984} 3985 3986int has_glm_turbo_ratio_limit(unsigned int family, unsigned int model) 3987{ 3988 if (!genuine_intel) 3989 return 0; 3990 3991 if (family != 6) 3992 return 0; 3993 3994 switch (model) { 3995 case INTEL_FAM6_ATOM_GOLDMONT: 3996 case INTEL_FAM6_SKYLAKE_X: 3997 case INTEL_FAM6_ICELAKE_X: 3998 case INTEL_FAM6_SAPPHIRERAPIDS_X: 3999 return 1; 4000 default: 4001 return 0; 4002 } 4003} 4004 4005int has_config_tdp(unsigned int family, unsigned int model) 4006{ 4007 if (!genuine_intel) 4008 return 0; 4009 4010 if (family != 6) 4011 return 0; 4012 4013 switch (model) { 4014 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 4015 case INTEL_FAM6_HASWELL: /* HSW */ 4016 case INTEL_FAM6_HASWELL_X: /* HSX */ 4017 case INTEL_FAM6_HASWELL_L: /* HSW */ 4018 case INTEL_FAM6_HASWELL_G: /* HSW */ 4019 case INTEL_FAM6_BROADWELL: /* BDW */ 4020 case INTEL_FAM6_BROADWELL_G: /* BDW */ 4021 case INTEL_FAM6_BROADWELL_X: /* BDX */ 4022 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 4023 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 4024 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 4025 case INTEL_FAM6_ICELAKE_X: /* ICX */ 4026 case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */ 4027 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ 4028 return 1; 4029 default: 4030 return 0; 4031 } 4032} 4033 4034/* 4035 * tcc_offset_bits: 4036 * 0: Tcc Offset not supported (Default) 4037 * 6: Bit 29:24 of MSR_PLATFORM_INFO 4038 * 4: Bit 27:24 of MSR_PLATFORM_INFO 4039 */ 4040void check_tcc_offset(int model) 4041{ 4042 unsigned long long msr; 4043 4044 if (!genuine_intel) 4045 return; 4046 4047 switch (model) { 4048 case INTEL_FAM6_SKYLAKE_L: 4049 case INTEL_FAM6_SKYLAKE: 4050 case INTEL_FAM6_KABYLAKE_L: 4051 case INTEL_FAM6_KABYLAKE: 4052 case INTEL_FAM6_ICELAKE_L: 4053 case INTEL_FAM6_ICELAKE: 4054 case INTEL_FAM6_TIGERLAKE_L: 4055 case INTEL_FAM6_TIGERLAKE: 4056 case INTEL_FAM6_COMETLAKE: 4057 if (!get_msr(base_cpu, MSR_PLATFORM_INFO, &msr)) { 4058 msr = (msr >> 30) & 1; 4059 if (msr) 4060 tcc_offset_bits = 6; 4061 } 4062 return; 4063 default: 4064 return; 4065 } 4066} 4067 4068static void remove_underbar(char *s) 4069{ 4070 char *to = s; 4071 4072 while (*s) { 4073 if (*s != '_') 4074 *to++ = *s; 4075 s++; 4076 } 4077 4078 *to = 0; 4079} 4080 4081static void dump_turbo_ratio_info(unsigned int family, unsigned int model) 4082{ 4083 if (!has_turbo) 4084 return; 4085 4086 if (has_hsw_turbo_ratio_limit(family, model)) 4087 dump_hsw_turbo_ratio_limits(); 4088 4089 if (has_ivt_turbo_ratio_limit(family, model)) 4090 dump_ivt_turbo_ratio_limits(); 4091 4092 if (has_turbo_ratio_limit(family, model)) { 4093 dump_turbo_ratio_limits(MSR_TURBO_RATIO_LIMIT, family, model); 4094 4095 if (is_hybrid) 4096 dump_turbo_ratio_limits(MSR_SECONDARY_TURBO_RATIO_LIMIT, family, model); 4097 } 4098 4099 if (has_atom_turbo_ratio_limit(family, model)) 4100 dump_atom_turbo_ratio_limits(); 4101 4102 if (has_knl_turbo_ratio_limit(family, model)) 4103 dump_knl_turbo_ratio_limits(); 4104 4105 if (has_config_tdp(family, model)) 4106 dump_config_tdp(); 4107} 4108 4109static void dump_cstate_pstate_config_info(unsigned int family, unsigned int model) 4110{ 4111 if (!do_nhm_platform_info) 4112 return; 4113 4114 dump_nhm_platform_info(); 4115 dump_turbo_ratio_info(family, model); 4116 dump_nhm_cst_cfg(); 4117} 4118 4119static int read_sysfs_int(char *path) 4120{ 4121 FILE *input; 4122 int retval = -1; 4123 4124 input = fopen(path, "r"); 4125 if (input == NULL) { 4126 if (debug) 4127 fprintf(outf, "NSFOD %s\n", path); 4128 return (-1); 4129 } 4130 if (fscanf(input, "%d", &retval) != 1) 4131 err(1, "%s: failed to read int from file", path); 4132 fclose(input); 4133 4134 return (retval); 4135} 4136 4137static void dump_sysfs_file(char *path) 4138{ 4139 FILE *input; 4140 char cpuidle_buf[64]; 4141 4142 input = fopen(path, "r"); 4143 if (input == NULL) { 4144 if (debug) 4145 fprintf(outf, "NSFOD %s\n", path); 4146 return; 4147 } 4148 if (!fgets(cpuidle_buf, sizeof(cpuidle_buf), input)) 4149 err(1, "%s: failed to read file", path); 4150 fclose(input); 4151 4152 fprintf(outf, "%s: %s", strrchr(path, '/') + 1, cpuidle_buf); 4153} 4154 4155static void intel_uncore_frequency_probe(void) 4156{ 4157 int i, j; 4158 char path[128]; 4159 4160 if (!genuine_intel) 4161 return; 4162 4163 if (access("/sys/devices/system/cpu/intel_uncore_frequency/package_00_die_00", R_OK)) 4164 return; 4165 4166 if (!access("/sys/devices/system/cpu/intel_uncore_frequency/package_00_die_00/current_freq_khz", R_OK)) 4167 BIC_PRESENT(BIC_UNCORE_MHZ); 4168 4169 if (quiet) 4170 return; 4171 4172 for (i = 0; i < topo.num_packages; ++i) { 4173 for (j = 0; j < topo.num_die; ++j) { 4174 int k, l; 4175 4176 sprintf(path, "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/min_freq_khz", 4177 i, j); 4178 k = read_sysfs_int(path); 4179 sprintf(path, "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/max_freq_khz", 4180 i, j); 4181 l = read_sysfs_int(path); 4182 fprintf(outf, "Uncore Frequency pkg%d die%d: %d - %d MHz ", i, j, k / 1000, l / 1000); 4183 4184 sprintf(path, 4185 "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/initial_min_freq_khz", 4186 i, j); 4187 k = read_sysfs_int(path); 4188 sprintf(path, 4189 "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/initial_max_freq_khz", 4190 i, j); 4191 l = read_sysfs_int(path); 4192 fprintf(outf, "(%d - %d MHz)\n", k / 1000, l / 1000); 4193 } 4194 } 4195} 4196 4197static void dump_sysfs_cstate_config(void) 4198{ 4199 char path[64]; 4200 char name_buf[16]; 4201 char desc[64]; 4202 FILE *input; 4203 int state; 4204 char *sp; 4205 4206 if (access("/sys/devices/system/cpu/cpuidle", R_OK)) { 4207 fprintf(outf, "cpuidle not loaded\n"); 4208 return; 4209 } 4210 4211 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_driver"); 4212 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_governor"); 4213 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_governor_ro"); 4214 4215 for (state = 0; state < 10; ++state) { 4216 4217 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state); 4218 input = fopen(path, "r"); 4219 if (input == NULL) 4220 continue; 4221 if (!fgets(name_buf, sizeof(name_buf), input)) 4222 err(1, "%s: failed to read file", path); 4223 4224 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 4225 sp = strchr(name_buf, '-'); 4226 if (!sp) 4227 sp = strchrnul(name_buf, '\n'); 4228 *sp = '\0'; 4229 fclose(input); 4230 4231 remove_underbar(name_buf); 4232 4233 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/desc", base_cpu, state); 4234 input = fopen(path, "r"); 4235 if (input == NULL) 4236 continue; 4237 if (!fgets(desc, sizeof(desc), input)) 4238 err(1, "%s: failed to read file", path); 4239 4240 fprintf(outf, "cpu%d: %s: %s", base_cpu, name_buf, desc); 4241 fclose(input); 4242 } 4243} 4244 4245static void dump_sysfs_pstate_config(void) 4246{ 4247 char path[64]; 4248 char driver_buf[64]; 4249 char governor_buf[64]; 4250 FILE *input; 4251 int turbo; 4252 4253 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_driver", base_cpu); 4254 input = fopen(path, "r"); 4255 if (input == NULL) { 4256 fprintf(outf, "NSFOD %s\n", path); 4257 return; 4258 } 4259 if (!fgets(driver_buf, sizeof(driver_buf), input)) 4260 err(1, "%s: failed to read file", path); 4261 fclose(input); 4262 4263 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_governor", base_cpu); 4264 input = fopen(path, "r"); 4265 if (input == NULL) { 4266 fprintf(outf, "NSFOD %s\n", path); 4267 return; 4268 } 4269 if (!fgets(governor_buf, sizeof(governor_buf), input)) 4270 err(1, "%s: failed to read file", path); 4271 fclose(input); 4272 4273 fprintf(outf, "cpu%d: cpufreq driver: %s", base_cpu, driver_buf); 4274 fprintf(outf, "cpu%d: cpufreq governor: %s", base_cpu, governor_buf); 4275 4276 sprintf(path, "/sys/devices/system/cpu/cpufreq/boost"); 4277 input = fopen(path, "r"); 4278 if (input != NULL) { 4279 if (fscanf(input, "%d", &turbo) != 1) 4280 err(1, "%s: failed to parse number from file", path); 4281 fprintf(outf, "cpufreq boost: %d\n", turbo); 4282 fclose(input); 4283 } 4284 4285 sprintf(path, "/sys/devices/system/cpu/intel_pstate/no_turbo"); 4286 input = fopen(path, "r"); 4287 if (input != NULL) { 4288 if (fscanf(input, "%d", &turbo) != 1) 4289 err(1, "%s: failed to parse number from file", path); 4290 fprintf(outf, "cpufreq intel_pstate no_turbo: %d\n", turbo); 4291 fclose(input); 4292 } 4293} 4294 4295/* 4296 * print_epb() 4297 * Decode the ENERGY_PERF_BIAS MSR 4298 */ 4299int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4300{ 4301 char *epb_string; 4302 int cpu, epb; 4303 4304 UNUSED(c); 4305 UNUSED(p); 4306 4307 if (!has_epb) 4308 return 0; 4309 4310 cpu = t->cpu_id; 4311 4312 /* EPB is per-package */ 4313 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4314 return 0; 4315 4316 if (cpu_migrate(cpu)) { 4317 fprintf(outf, "print_epb: Could not migrate to CPU %d\n", cpu); 4318 return -1; 4319 } 4320 4321 epb = get_epb(cpu); 4322 if (epb < 0) 4323 return 0; 4324 4325 switch (epb) { 4326 case ENERGY_PERF_BIAS_PERFORMANCE: 4327 epb_string = "performance"; 4328 break; 4329 case ENERGY_PERF_BIAS_NORMAL: 4330 epb_string = "balanced"; 4331 break; 4332 case ENERGY_PERF_BIAS_POWERSAVE: 4333 epb_string = "powersave"; 4334 break; 4335 default: 4336 epb_string = "custom"; 4337 break; 4338 } 4339 fprintf(outf, "cpu%d: EPB: %d (%s)\n", cpu, epb, epb_string); 4340 4341 return 0; 4342} 4343 4344/* 4345 * print_hwp() 4346 * Decode the MSR_HWP_CAPABILITIES 4347 */ 4348int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4349{ 4350 unsigned long long msr; 4351 int cpu; 4352 4353 UNUSED(c); 4354 UNUSED(p); 4355 4356 if (!has_hwp) 4357 return 0; 4358 4359 cpu = t->cpu_id; 4360 4361 /* MSR_HWP_CAPABILITIES is per-package */ 4362 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4363 return 0; 4364 4365 if (cpu_migrate(cpu)) { 4366 fprintf(outf, "print_hwp: Could not migrate to CPU %d\n", cpu); 4367 return -1; 4368 } 4369 4370 if (get_msr(cpu, MSR_PM_ENABLE, &msr)) 4371 return 0; 4372 4373 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n", cpu, msr, (msr & (1 << 0)) ? "" : "No-"); 4374 4375 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */ 4376 if ((msr & (1 << 0)) == 0) 4377 return 0; 4378 4379 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr)) 4380 return 0; 4381 4382 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx " 4383 "(high %d guar %d eff %d low %d)\n", 4384 cpu, msr, 4385 (unsigned int)HWP_HIGHEST_PERF(msr), 4386 (unsigned int)HWP_GUARANTEED_PERF(msr), 4387 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr), (unsigned int)HWP_LOWEST_PERF(msr)); 4388 4389 if (get_msr(cpu, MSR_HWP_REQUEST, &msr)) 4390 return 0; 4391 4392 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx " 4393 "(min %d max %d des %d epp 0x%x window 0x%x pkg 0x%x)\n", 4394 cpu, msr, 4395 (unsigned int)(((msr) >> 0) & 0xff), 4396 (unsigned int)(((msr) >> 8) & 0xff), 4397 (unsigned int)(((msr) >> 16) & 0xff), 4398 (unsigned int)(((msr) >> 24) & 0xff), 4399 (unsigned int)(((msr) >> 32) & 0xff3), (unsigned int)(((msr) >> 42) & 0x1)); 4400 4401 if (has_hwp_pkg) { 4402 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr)) 4403 return 0; 4404 4405 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx " 4406 "(min %d max %d des %d epp 0x%x window 0x%x)\n", 4407 cpu, msr, 4408 (unsigned int)(((msr) >> 0) & 0xff), 4409 (unsigned int)(((msr) >> 8) & 0xff), 4410 (unsigned int)(((msr) >> 16) & 0xff), 4411 (unsigned int)(((msr) >> 24) & 0xff), (unsigned int)(((msr) >> 32) & 0xff3)); 4412 } 4413 if (has_hwp_notify) { 4414 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr)) 4415 return 0; 4416 4417 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx " 4418 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n", 4419 cpu, msr, ((msr) & 0x1) ? "EN" : "Dis", ((msr) & 0x2) ? "EN" : "Dis"); 4420 } 4421 if (get_msr(cpu, MSR_HWP_STATUS, &msr)) 4422 return 0; 4423 4424 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx " 4425 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n", 4426 cpu, msr, ((msr) & 0x1) ? "" : "No-", ((msr) & 0x4) ? "" : "No-"); 4427 4428 return 0; 4429} 4430 4431/* 4432 * print_perf_limit() 4433 */ 4434int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4435{ 4436 unsigned long long msr; 4437 int cpu; 4438 4439 UNUSED(c); 4440 UNUSED(p); 4441 4442 cpu = t->cpu_id; 4443 4444 /* per-package */ 4445 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4446 return 0; 4447 4448 if (cpu_migrate(cpu)) { 4449 fprintf(outf, "print_perf_limit: Could not migrate to CPU %d\n", cpu); 4450 return -1; 4451 } 4452 4453 if (do_core_perf_limit_reasons) { 4454 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr); 4455 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 4456 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)", 4457 (msr & 1 << 15) ? "bit15, " : "", 4458 (msr & 1 << 14) ? "bit14, " : "", 4459 (msr & 1 << 13) ? "Transitions, " : "", 4460 (msr & 1 << 12) ? "MultiCoreTurbo, " : "", 4461 (msr & 1 << 11) ? "PkgPwrL2, " : "", 4462 (msr & 1 << 10) ? "PkgPwrL1, " : "", 4463 (msr & 1 << 9) ? "CorePwr, " : "", 4464 (msr & 1 << 8) ? "Amps, " : "", 4465 (msr & 1 << 6) ? "VR-Therm, " : "", 4466 (msr & 1 << 5) ? "Auto-HWP, " : "", 4467 (msr & 1 << 4) ? "Graphics, " : "", 4468 (msr & 1 << 2) ? "bit2, " : "", 4469 (msr & 1 << 1) ? "ThermStatus, " : "", (msr & 1 << 0) ? "PROCHOT, " : ""); 4470 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n", 4471 (msr & 1 << 31) ? "bit31, " : "", 4472 (msr & 1 << 30) ? "bit30, " : "", 4473 (msr & 1 << 29) ? "Transitions, " : "", 4474 (msr & 1 << 28) ? "MultiCoreTurbo, " : "", 4475 (msr & 1 << 27) ? "PkgPwrL2, " : "", 4476 (msr & 1 << 26) ? "PkgPwrL1, " : "", 4477 (msr & 1 << 25) ? "CorePwr, " : "", 4478 (msr & 1 << 24) ? "Amps, " : "", 4479 (msr & 1 << 22) ? "VR-Therm, " : "", 4480 (msr & 1 << 21) ? "Auto-HWP, " : "", 4481 (msr & 1 << 20) ? "Graphics, " : "", 4482 (msr & 1 << 18) ? "bit18, " : "", 4483 (msr & 1 << 17) ? "ThermStatus, " : "", (msr & 1 << 16) ? "PROCHOT, " : ""); 4484 4485 } 4486 if (do_gfx_perf_limit_reasons) { 4487 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr); 4488 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 4489 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)", 4490 (msr & 1 << 0) ? "PROCHOT, " : "", 4491 (msr & 1 << 1) ? "ThermStatus, " : "", 4492 (msr & 1 << 4) ? "Graphics, " : "", 4493 (msr & 1 << 6) ? "VR-Therm, " : "", 4494 (msr & 1 << 8) ? "Amps, " : "", 4495 (msr & 1 << 9) ? "GFXPwr, " : "", 4496 (msr & 1 << 10) ? "PkgPwrL1, " : "", (msr & 1 << 11) ? "PkgPwrL2, " : ""); 4497 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n", 4498 (msr & 1 << 16) ? "PROCHOT, " : "", 4499 (msr & 1 << 17) ? "ThermStatus, " : "", 4500 (msr & 1 << 20) ? "Graphics, " : "", 4501 (msr & 1 << 22) ? "VR-Therm, " : "", 4502 (msr & 1 << 24) ? "Amps, " : "", 4503 (msr & 1 << 25) ? "GFXPwr, " : "", 4504 (msr & 1 << 26) ? "PkgPwrL1, " : "", (msr & 1 << 27) ? "PkgPwrL2, " : ""); 4505 } 4506 if (do_ring_perf_limit_reasons) { 4507 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr); 4508 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 4509 fprintf(outf, " (Active: %s%s%s%s%s%s)", 4510 (msr & 1 << 0) ? "PROCHOT, " : "", 4511 (msr & 1 << 1) ? "ThermStatus, " : "", 4512 (msr & 1 << 6) ? "VR-Therm, " : "", 4513 (msr & 1 << 8) ? "Amps, " : "", 4514 (msr & 1 << 10) ? "PkgPwrL1, " : "", (msr & 1 << 11) ? "PkgPwrL2, " : ""); 4515 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n", 4516 (msr & 1 << 16) ? "PROCHOT, " : "", 4517 (msr & 1 << 17) ? "ThermStatus, " : "", 4518 (msr & 1 << 22) ? "VR-Therm, " : "", 4519 (msr & 1 << 24) ? "Amps, " : "", 4520 (msr & 1 << 26) ? "PkgPwrL1, " : "", (msr & 1 << 27) ? "PkgPwrL2, " : ""); 4521 } 4522 return 0; 4523} 4524 4525#define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */ 4526#define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */ 4527 4528double get_tdp_intel(unsigned int model) 4529{ 4530 unsigned long long msr; 4531 4532 if (do_rapl & RAPL_PKG_POWER_INFO) 4533 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr)) 4534 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units; 4535 4536 switch (model) { 4537 case INTEL_FAM6_ATOM_SILVERMONT: 4538 case INTEL_FAM6_ATOM_SILVERMONT_D: 4539 return 30.0; 4540 default: 4541 return 135.0; 4542 } 4543} 4544 4545double get_tdp_amd(unsigned int family) 4546{ 4547 UNUSED(family); 4548 4549 /* This is the max stock TDP of HEDT/Server Fam17h+ chips */ 4550 return 280.0; 4551} 4552 4553/* 4554 * rapl_dram_energy_units_probe() 4555 * Energy units are either hard-coded, or come from RAPL Energy Unit MSR. 4556 */ 4557static double rapl_dram_energy_units_probe(int model, double rapl_energy_units) 4558{ 4559 /* only called for genuine_intel, family 6 */ 4560 4561 switch (model) { 4562 case INTEL_FAM6_HASWELL_X: /* HSX */ 4563 case INTEL_FAM6_BROADWELL_X: /* BDX */ 4564 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 4565 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 4566 case INTEL_FAM6_ICELAKE_X: /* ICX */ 4567 return (rapl_dram_energy_units = 15.3 / 1000000); 4568 default: 4569 return (rapl_energy_units); 4570 } 4571} 4572 4573void rapl_probe_intel(unsigned int family, unsigned int model) 4574{ 4575 unsigned long long msr; 4576 unsigned int time_unit; 4577 double tdp; 4578 4579 if (family != 6) 4580 return; 4581 4582 switch (model) { 4583 case INTEL_FAM6_SANDYBRIDGE: 4584 case INTEL_FAM6_IVYBRIDGE: 4585 case INTEL_FAM6_HASWELL: /* HSW */ 4586 case INTEL_FAM6_HASWELL_L: /* HSW */ 4587 case INTEL_FAM6_HASWELL_G: /* HSW */ 4588 case INTEL_FAM6_BROADWELL: /* BDW */ 4589 case INTEL_FAM6_BROADWELL_G: /* BDW */ 4590 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO; 4591 if (rapl_joules) { 4592 BIC_PRESENT(BIC_Pkg_J); 4593 BIC_PRESENT(BIC_Cor_J); 4594 BIC_PRESENT(BIC_GFX_J); 4595 } else { 4596 BIC_PRESENT(BIC_PkgWatt); 4597 BIC_PRESENT(BIC_CorWatt); 4598 BIC_PRESENT(BIC_GFXWatt); 4599 } 4600 break; 4601 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 4602 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 4603 do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO; 4604 if (rapl_joules) 4605 BIC_PRESENT(BIC_Pkg_J); 4606 else 4607 BIC_PRESENT(BIC_PkgWatt); 4608 break; 4609 case INTEL_FAM6_ATOM_TREMONT: /* EHL */ 4610 do_rapl = 4611 RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS 4612 | RAPL_GFX | RAPL_PKG_POWER_INFO; 4613 if (rapl_joules) { 4614 BIC_PRESENT(BIC_Pkg_J); 4615 BIC_PRESENT(BIC_Cor_J); 4616 BIC_PRESENT(BIC_RAM_J); 4617 BIC_PRESENT(BIC_GFX_J); 4618 } else { 4619 BIC_PRESENT(BIC_PkgWatt); 4620 BIC_PRESENT(BIC_CorWatt); 4621 BIC_PRESENT(BIC_RAMWatt); 4622 BIC_PRESENT(BIC_GFXWatt); 4623 } 4624 break; 4625 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */ 4626 do_rapl = RAPL_PKG | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; 4627 BIC_PRESENT(BIC_PKG__); 4628 if (rapl_joules) 4629 BIC_PRESENT(BIC_Pkg_J); 4630 else 4631 BIC_PRESENT(BIC_PkgWatt); 4632 break; 4633 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 4634 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 4635 do_rapl = 4636 RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS 4637 | RAPL_GFX | RAPL_PKG_POWER_INFO; 4638 BIC_PRESENT(BIC_PKG__); 4639 BIC_PRESENT(BIC_RAM__); 4640 if (rapl_joules) { 4641 BIC_PRESENT(BIC_Pkg_J); 4642 BIC_PRESENT(BIC_Cor_J); 4643 BIC_PRESENT(BIC_RAM_J); 4644 BIC_PRESENT(BIC_GFX_J); 4645 } else { 4646 BIC_PRESENT(BIC_PkgWatt); 4647 BIC_PRESENT(BIC_CorWatt); 4648 BIC_PRESENT(BIC_RAMWatt); 4649 BIC_PRESENT(BIC_GFXWatt); 4650 } 4651 break; 4652 case INTEL_FAM6_HASWELL_X: /* HSX */ 4653 case INTEL_FAM6_BROADWELL_X: /* BDX */ 4654 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 4655 case INTEL_FAM6_ICELAKE_X: /* ICX */ 4656 case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */ 4657 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 4658 do_rapl = 4659 RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | 4660 RAPL_PKG_POWER_INFO; 4661 BIC_PRESENT(BIC_PKG__); 4662 BIC_PRESENT(BIC_RAM__); 4663 if (rapl_joules) { 4664 BIC_PRESENT(BIC_Pkg_J); 4665 BIC_PRESENT(BIC_RAM_J); 4666 } else { 4667 BIC_PRESENT(BIC_PkgWatt); 4668 BIC_PRESENT(BIC_RAMWatt); 4669 } 4670 break; 4671 case INTEL_FAM6_SANDYBRIDGE_X: 4672 case INTEL_FAM6_IVYBRIDGE_X: 4673 do_rapl = 4674 RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | 4675 RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO; 4676 BIC_PRESENT(BIC_PKG__); 4677 BIC_PRESENT(BIC_RAM__); 4678 if (rapl_joules) { 4679 BIC_PRESENT(BIC_Pkg_J); 4680 BIC_PRESENT(BIC_Cor_J); 4681 BIC_PRESENT(BIC_RAM_J); 4682 } else { 4683 BIC_PRESENT(BIC_PkgWatt); 4684 BIC_PRESENT(BIC_CorWatt); 4685 BIC_PRESENT(BIC_RAMWatt); 4686 } 4687 break; 4688 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */ 4689 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */ 4690 do_rapl = RAPL_PKG | RAPL_CORES; 4691 if (rapl_joules) { 4692 BIC_PRESENT(BIC_Pkg_J); 4693 BIC_PRESENT(BIC_Cor_J); 4694 } else { 4695 BIC_PRESENT(BIC_PkgWatt); 4696 BIC_PRESENT(BIC_CorWatt); 4697 } 4698 break; 4699 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */ 4700 do_rapl = 4701 RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | 4702 RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS; 4703 BIC_PRESENT(BIC_PKG__); 4704 BIC_PRESENT(BIC_RAM__); 4705 if (rapl_joules) { 4706 BIC_PRESENT(BIC_Pkg_J); 4707 BIC_PRESENT(BIC_Cor_J); 4708 BIC_PRESENT(BIC_RAM_J); 4709 } else { 4710 BIC_PRESENT(BIC_PkgWatt); 4711 BIC_PRESENT(BIC_CorWatt); 4712 BIC_PRESENT(BIC_RAMWatt); 4713 } 4714 break; 4715 default: 4716 return; 4717 } 4718 4719 /* units on package 0, verify later other packages match */ 4720 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr)) 4721 return; 4722 4723 rapl_power_units = 1.0 / (1 << (msr & 0xF)); 4724 if (model == INTEL_FAM6_ATOM_SILVERMONT) 4725 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000; 4726 else 4727 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F)); 4728 4729 rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units); 4730 4731 time_unit = msr >> 16 & 0xF; 4732 if (time_unit == 0) 4733 time_unit = 0xA; 4734 4735 rapl_time_units = 1.0 / (1 << (time_unit)); 4736 4737 tdp = get_tdp_intel(model); 4738 4739 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; 4740 if (!quiet) 4741 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp); 4742} 4743 4744void rapl_probe_amd(unsigned int family, unsigned int model) 4745{ 4746 unsigned long long msr; 4747 unsigned int eax, ebx, ecx, edx; 4748 unsigned int has_rapl = 0; 4749 double tdp; 4750 4751 UNUSED(model); 4752 4753 if (max_extended_level >= 0x80000007) { 4754 __cpuid(0x80000007, eax, ebx, ecx, edx); 4755 /* RAPL (Fam 17h+) */ 4756 has_rapl = edx & (1 << 14); 4757 } 4758 4759 if (!has_rapl || family < 0x17) 4760 return; 4761 4762 do_rapl = RAPL_AMD_F17H | RAPL_PER_CORE_ENERGY; 4763 if (rapl_joules) { 4764 BIC_PRESENT(BIC_Pkg_J); 4765 BIC_PRESENT(BIC_Cor_J); 4766 } else { 4767 BIC_PRESENT(BIC_PkgWatt); 4768 BIC_PRESENT(BIC_CorWatt); 4769 } 4770 4771 if (get_msr(base_cpu, MSR_RAPL_PWR_UNIT, &msr)) 4772 return; 4773 4774 rapl_time_units = ldexp(1.0, -(msr >> 16 & 0xf)); 4775 rapl_energy_units = ldexp(1.0, -(msr >> 8 & 0x1f)); 4776 rapl_power_units = ldexp(1.0, -(msr & 0xf)); 4777 4778 tdp = get_tdp_amd(family); 4779 4780 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; 4781 if (!quiet) 4782 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp); 4783} 4784 4785/* 4786 * rapl_probe() 4787 * 4788 * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units 4789 */ 4790void rapl_probe(unsigned int family, unsigned int model) 4791{ 4792 if (genuine_intel) 4793 rapl_probe_intel(family, model); 4794 if (authentic_amd || hygon_genuine) 4795 rapl_probe_amd(family, model); 4796} 4797 4798void perf_limit_reasons_probe(unsigned int family, unsigned int model) 4799{ 4800 if (!genuine_intel) 4801 return; 4802 4803 if (family != 6) 4804 return; 4805 4806 switch (model) { 4807 case INTEL_FAM6_HASWELL: /* HSW */ 4808 case INTEL_FAM6_HASWELL_L: /* HSW */ 4809 case INTEL_FAM6_HASWELL_G: /* HSW */ 4810 do_gfx_perf_limit_reasons = 1; 4811 /* FALLTHRU */ 4812 case INTEL_FAM6_HASWELL_X: /* HSX */ 4813 do_core_perf_limit_reasons = 1; 4814 do_ring_perf_limit_reasons = 1; 4815 default: 4816 return; 4817 } 4818} 4819 4820void automatic_cstate_conversion_probe(unsigned int family, unsigned int model) 4821{ 4822 if (family != 6) 4823 return; 4824 4825 switch (model) { 4826 case INTEL_FAM6_BROADWELL_X: 4827 case INTEL_FAM6_SKYLAKE_X: 4828 has_automatic_cstate_conversion = 1; 4829 } 4830} 4831 4832void prewake_cstate_probe(unsigned int family, unsigned int model) 4833{ 4834 if (is_icx(family, model) || is_spr(family, model)) 4835 dis_cstate_prewake = 1; 4836} 4837 4838int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4839{ 4840 unsigned long long msr; 4841 unsigned int dts, dts2; 4842 int cpu; 4843 4844 UNUSED(c); 4845 UNUSED(p); 4846 4847 if (!(do_dts || do_ptm)) 4848 return 0; 4849 4850 cpu = t->cpu_id; 4851 4852 /* DTS is per-core, no need to print for each thread */ 4853 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 4854 return 0; 4855 4856 if (cpu_migrate(cpu)) { 4857 fprintf(outf, "print_thermal: Could not migrate to CPU %d\n", cpu); 4858 return -1; 4859 } 4860 4861 if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) { 4862 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 4863 return 0; 4864 4865 dts = (msr >> 16) & 0x7F; 4866 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n", cpu, msr, tj_max - dts); 4867 4868 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr)) 4869 return 0; 4870 4871 dts = (msr >> 16) & 0x7F; 4872 dts2 = (msr >> 8) & 0x7F; 4873 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 4874 cpu, msr, tj_max - dts, tj_max - dts2); 4875 } 4876 4877 if (do_dts && debug) { 4878 unsigned int resolution; 4879 4880 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 4881 return 0; 4882 4883 dts = (msr >> 16) & 0x7F; 4884 resolution = (msr >> 27) & 0xF; 4885 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n", 4886 cpu, msr, tj_max - dts, resolution); 4887 4888 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr)) 4889 return 0; 4890 4891 dts = (msr >> 16) & 0x7F; 4892 dts2 = (msr >> 8) & 0x7F; 4893 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 4894 cpu, msr, tj_max - dts, tj_max - dts2); 4895 } 4896 4897 return 0; 4898} 4899 4900void print_power_limit_msr(int cpu, unsigned long long msr, char *label) 4901{ 4902 fprintf(outf, "cpu%d: %s: %sabled (%0.3f Watts, %f sec, clamp %sabled)\n", 4903 cpu, label, 4904 ((msr >> 15) & 1) ? "EN" : "DIS", 4905 ((msr >> 0) & 0x7FFF) * rapl_power_units, 4906 (1.0 + (((msr >> 22) & 0x3) / 4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units, 4907 (((msr >> 16) & 1) ? "EN" : "DIS")); 4908 4909 return; 4910} 4911 4912int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4913{ 4914 unsigned long long msr; 4915 const char *msr_name; 4916 int cpu; 4917 4918 UNUSED(c); 4919 UNUSED(p); 4920 4921 if (!do_rapl) 4922 return 0; 4923 4924 /* RAPL counters are per package, so print only for 1st thread/package */ 4925 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4926 return 0; 4927 4928 cpu = t->cpu_id; 4929 if (cpu_migrate(cpu)) { 4930 fprintf(outf, "print_rapl: Could not migrate to CPU %d\n", cpu); 4931 return -1; 4932 } 4933 4934 if (do_rapl & RAPL_AMD_F17H) { 4935 msr_name = "MSR_RAPL_PWR_UNIT"; 4936 if (get_msr(cpu, MSR_RAPL_PWR_UNIT, &msr)) 4937 return -1; 4938 } else { 4939 msr_name = "MSR_RAPL_POWER_UNIT"; 4940 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr)) 4941 return -1; 4942 } 4943 4944 fprintf(outf, "cpu%d: %s: 0x%08llx (%f Watts, %f Joules, %f sec.)\n", cpu, msr_name, msr, 4945 rapl_power_units, rapl_energy_units, rapl_time_units); 4946 4947 if (do_rapl & RAPL_PKG_POWER_INFO) { 4948 4949 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr)) 4950 return -5; 4951 4952 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 4953 cpu, msr, 4954 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4955 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4956 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4957 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 4958 4959 } 4960 if (do_rapl & RAPL_PKG) { 4961 4962 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr)) 4963 return -9; 4964 4965 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n", 4966 cpu, msr, (msr >> 63) & 1 ? "" : "UN"); 4967 4968 print_power_limit_msr(cpu, msr, "PKG Limit #1"); 4969 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%0.3f Watts, %f* sec, clamp %sabled)\n", 4970 cpu, 4971 ((msr >> 47) & 1) ? "EN" : "DIS", 4972 ((msr >> 32) & 0x7FFF) * rapl_power_units, 4973 (1.0 + (((msr >> 54) & 0x3) / 4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units, 4974 ((msr >> 48) & 1) ? "EN" : "DIS"); 4975 4976 if (get_msr(cpu, MSR_VR_CURRENT_CONFIG, &msr)) 4977 return -9; 4978 4979 fprintf(outf, "cpu%d: MSR_VR_CURRENT_CONFIG: 0x%08llx\n", cpu, msr); 4980 fprintf(outf, "cpu%d: PKG Limit #4: %f Watts (%slocked)\n", 4981 cpu, ((msr >> 0) & 0x1FFF) * rapl_power_units, (msr >> 31) & 1 ? "" : "UN"); 4982 } 4983 4984 if (do_rapl & RAPL_DRAM_POWER_INFO) { 4985 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr)) 4986 return -6; 4987 4988 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 4989 cpu, msr, 4990 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4991 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4992 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4993 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 4994 } 4995 if (do_rapl & RAPL_DRAM) { 4996 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr)) 4997 return -9; 4998 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n", 4999 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 5000 5001 print_power_limit_msr(cpu, msr, "DRAM Limit"); 5002 } 5003 if (do_rapl & RAPL_CORE_POLICY) { 5004 if (get_msr(cpu, MSR_PP0_POLICY, &msr)) 5005 return -7; 5006 5007 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF); 5008 } 5009 if (do_rapl & RAPL_CORES_POWER_LIMIT) { 5010 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr)) 5011 return -9; 5012 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n", 5013 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 5014 print_power_limit_msr(cpu, msr, "Cores Limit"); 5015 } 5016 if (do_rapl & RAPL_GFX) { 5017 if (get_msr(cpu, MSR_PP1_POLICY, &msr)) 5018 return -8; 5019 5020 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF); 5021 5022 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr)) 5023 return -9; 5024 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n", 5025 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 5026 print_power_limit_msr(cpu, msr, "GFX Limit"); 5027 } 5028 return 0; 5029} 5030 5031/* 5032 * SNB adds support for additional MSRs: 5033 * 5034 * MSR_PKG_C7_RESIDENCY 0x000003fa 5035 * MSR_CORE_C7_RESIDENCY 0x000003fe 5036 * MSR_PKG_C2_RESIDENCY 0x0000060d 5037 */ 5038 5039int has_snb_msrs(unsigned int family, unsigned int model) 5040{ 5041 if (!genuine_intel) 5042 return 0; 5043 5044 if (family != 6) 5045 return 0; 5046 5047 switch (model) { 5048 case INTEL_FAM6_SANDYBRIDGE: 5049 case INTEL_FAM6_SANDYBRIDGE_X: 5050 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 5051 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 5052 case INTEL_FAM6_HASWELL: /* HSW */ 5053 case INTEL_FAM6_HASWELL_X: /* HSW */ 5054 case INTEL_FAM6_HASWELL_L: /* HSW */ 5055 case INTEL_FAM6_HASWELL_G: /* HSW */ 5056 case INTEL_FAM6_BROADWELL: /* BDW */ 5057 case INTEL_FAM6_BROADWELL_G: /* BDW */ 5058 case INTEL_FAM6_BROADWELL_X: /* BDX */ 5059 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 5060 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 5061 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 5062 case INTEL_FAM6_ICELAKE_X: /* ICX */ 5063 case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */ 5064 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 5065 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 5066 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */ 5067 case INTEL_FAM6_ATOM_TREMONT: /* EHL */ 5068 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */ 5069 return 1; 5070 } 5071 return 0; 5072} 5073 5074/* 5075 * HSW ULT added support for C8/C9/C10 MSRs: 5076 * 5077 * MSR_PKG_C8_RESIDENCY 0x00000630 5078 * MSR_PKG_C9_RESIDENCY 0x00000631 5079 * MSR_PKG_C10_RESIDENCY 0x00000632 5080 * 5081 * MSR_PKGC8_IRTL 0x00000633 5082 * MSR_PKGC9_IRTL 0x00000634 5083 * MSR_PKGC10_IRTL 0x00000635 5084 * 5085 */ 5086int has_c8910_msrs(unsigned int family, unsigned int model) 5087{ 5088 if (!genuine_intel) 5089 return 0; 5090 5091 if (family != 6) 5092 return 0; 5093 5094 switch (model) { 5095 case INTEL_FAM6_HASWELL_L: /* HSW */ 5096 case INTEL_FAM6_BROADWELL: /* BDW */ 5097 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 5098 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 5099 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 5100 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 5101 case INTEL_FAM6_ATOM_TREMONT: /* EHL */ 5102 return 1; 5103 } 5104 return 0; 5105} 5106 5107/* 5108 * SKL adds support for additional MSRS: 5109 * 5110 * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 5111 * MSR_PKG_ANY_CORE_C0_RES 0x00000659 5112 * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 5113 * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 5114 */ 5115int has_skl_msrs(unsigned int family, unsigned int model) 5116{ 5117 if (!genuine_intel) 5118 return 0; 5119 5120 if (family != 6) 5121 return 0; 5122 5123 switch (model) { 5124 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 5125 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 5126 return 1; 5127 } 5128 return 0; 5129} 5130 5131int is_slm(unsigned int family, unsigned int model) 5132{ 5133 if (!genuine_intel) 5134 return 0; 5135 5136 if (family != 6) 5137 return 0; 5138 5139 switch (model) { 5140 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */ 5141 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */ 5142 return 1; 5143 } 5144 return 0; 5145} 5146 5147int is_knl(unsigned int family, unsigned int model) 5148{ 5149 if (!genuine_intel) 5150 return 0; 5151 5152 if (family != 6) 5153 return 0; 5154 5155 switch (model) { 5156 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 5157 return 1; 5158 } 5159 return 0; 5160} 5161 5162int is_cnl(unsigned int family, unsigned int model) 5163{ 5164 if (!genuine_intel) 5165 return 0; 5166 5167 if (family != 6) 5168 return 0; 5169 5170 switch (model) { 5171 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 5172 return 1; 5173 } 5174 5175 return 0; 5176} 5177 5178unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model) 5179{ 5180 if (is_knl(family, model)) 5181 return 1024; 5182 return 1; 5183} 5184 5185#define SLM_BCLK_FREQS 5 5186double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0 }; 5187 5188double slm_bclk(void) 5189{ 5190 unsigned long long msr = 3; 5191 unsigned int i; 5192 double freq; 5193 5194 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr)) 5195 fprintf(outf, "SLM BCLK: unknown\n"); 5196 5197 i = msr & 0xf; 5198 if (i >= SLM_BCLK_FREQS) { 5199 fprintf(outf, "SLM BCLK[%d] invalid\n", i); 5200 i = 3; 5201 } 5202 freq = slm_freq_table[i]; 5203 5204 if (!quiet) 5205 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq); 5206 5207 return freq; 5208} 5209 5210double discover_bclk(unsigned int family, unsigned int model) 5211{ 5212 if (has_snb_msrs(family, model) || is_knl(family, model)) 5213 return 100.00; 5214 else if (is_slm(family, model)) 5215 return slm_bclk(); 5216 else 5217 return 133.33; 5218} 5219 5220int get_cpu_type(struct thread_data *t, struct core_data *c, struct pkg_data *p) 5221{ 5222 unsigned int eax, ebx, ecx, edx; 5223 5224 UNUSED(c); 5225 UNUSED(p); 5226 5227 if (!genuine_intel) 5228 return 0; 5229 5230 if (cpu_migrate(t->cpu_id)) { 5231 fprintf(outf, "Could not migrate to CPU %d\n", t->cpu_id); 5232 return -1; 5233 } 5234 5235 if (max_level < 0x1a) 5236 return 0; 5237 5238 __cpuid(0x1a, eax, ebx, ecx, edx); 5239 eax = (eax >> 24) & 0xFF; 5240 if (eax == 0x20) 5241 t->is_atom = true; 5242 return 0; 5243} 5244 5245/* 5246 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where 5247 * the Thermal Control Circuit (TCC) activates. 5248 * This is usually equal to tjMax. 5249 * 5250 * Older processors do not have this MSR, so there we guess, 5251 * but also allow cmdline over-ride with -T. 5252 * 5253 * Several MSR temperature values are in units of degrees-C 5254 * below this value, including the Digital Thermal Sensor (DTS), 5255 * Package Thermal Management Sensor (PTM), and thermal event thresholds. 5256 */ 5257int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p) 5258{ 5259 unsigned long long msr; 5260 unsigned int tcc_default, tcc_offset; 5261 int cpu; 5262 5263 UNUSED(c); 5264 UNUSED(p); 5265 5266 /* tj_max is used only for dts or ptm */ 5267 if (!(do_dts || do_ptm)) 5268 return 0; 5269 5270 /* this is a per-package concept */ 5271 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 5272 return 0; 5273 5274 cpu = t->cpu_id; 5275 if (cpu_migrate(cpu)) { 5276 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 5277 return -1; 5278 } 5279 5280 if (tj_max_override != 0) { 5281 tj_max = tj_max_override; 5282 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n", cpu, tj_max); 5283 return 0; 5284 } 5285 5286 /* Temperature Target MSR is Nehalem and newer only */ 5287 if (!do_nhm_platform_info) 5288 goto guess; 5289 5290 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr)) 5291 goto guess; 5292 5293 tcc_default = (msr >> 16) & 0xFF; 5294 5295 if (!quiet) { 5296 switch (tcc_offset_bits) { 5297 case 4: 5298 tcc_offset = (msr >> 24) & 0xF; 5299 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C) (%d default - %d offset)\n", 5300 cpu, msr, tcc_default - tcc_offset, tcc_default, tcc_offset); 5301 break; 5302 case 6: 5303 tcc_offset = (msr >> 24) & 0x3F; 5304 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C) (%d default - %d offset)\n", 5305 cpu, msr, tcc_default - tcc_offset, tcc_default, tcc_offset); 5306 break; 5307 default: 5308 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n", cpu, msr, tcc_default); 5309 break; 5310 } 5311 } 5312 5313 if (!tcc_default) 5314 goto guess; 5315 5316 tj_max = tcc_default; 5317 5318 return 0; 5319 5320guess: 5321 tj_max = TJMAX_DEFAULT; 5322 fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n", cpu, tj_max); 5323 5324 return 0; 5325} 5326 5327void decode_feature_control_msr(void) 5328{ 5329 unsigned long long msr; 5330 5331 if (!get_msr(base_cpu, MSR_IA32_FEAT_CTL, &msr)) 5332 fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n", 5333 base_cpu, msr, msr & FEAT_CTL_LOCKED ? "" : "UN-", msr & (1 << 18) ? "SGX" : ""); 5334} 5335 5336void decode_misc_enable_msr(void) 5337{ 5338 unsigned long long msr; 5339 5340 if (!genuine_intel) 5341 return; 5342 5343 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr)) 5344 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n", 5345 base_cpu, msr, 5346 msr & MSR_IA32_MISC_ENABLE_TM1 ? "" : "No-", 5347 msr & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP ? "" : "No-", 5348 msr & MSR_IA32_MISC_ENABLE_MWAIT ? "" : "No-", 5349 msr & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE ? "No-" : "", 5350 msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ? "No-" : ""); 5351} 5352 5353void decode_misc_feature_control(void) 5354{ 5355 unsigned long long msr; 5356 5357 if (!has_misc_feature_control) 5358 return; 5359 5360 if (!get_msr(base_cpu, MSR_MISC_FEATURE_CONTROL, &msr)) 5361 fprintf(outf, 5362 "cpu%d: MSR_MISC_FEATURE_CONTROL: 0x%08llx (%sL2-Prefetch %sL2-Prefetch-pair %sL1-Prefetch %sL1-IP-Prefetch)\n", 5363 base_cpu, msr, msr & (0 << 0) ? "No-" : "", msr & (1 << 0) ? "No-" : "", 5364 msr & (2 << 0) ? "No-" : "", msr & (3 << 0) ? "No-" : ""); 5365} 5366 5367/* 5368 * Decode MSR_MISC_PWR_MGMT 5369 * 5370 * Decode the bits according to the Nehalem documentation 5371 * bit[0] seems to continue to have same meaning going forward 5372 * bit[1] less so... 5373 */ 5374void decode_misc_pwr_mgmt_msr(void) 5375{ 5376 unsigned long long msr; 5377 5378 if (!do_nhm_platform_info) 5379 return; 5380 5381 if (no_MSR_MISC_PWR_MGMT) 5382 return; 5383 5384 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr)) 5385 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n", 5386 base_cpu, msr, 5387 msr & (1 << 0) ? "DIS" : "EN", msr & (1 << 1) ? "EN" : "DIS", msr & (1 << 8) ? "EN" : "DIS"); 5388} 5389 5390/* 5391 * Decode MSR_CC6_DEMOTION_POLICY_CONFIG, MSR_MC6_DEMOTION_POLICY_CONFIG 5392 * 5393 * This MSRs are present on Silvermont processors, 5394 * Intel Atom processor E3000 series (Baytrail), and friends. 5395 */ 5396void decode_c6_demotion_policy_msr(void) 5397{ 5398 unsigned long long msr; 5399 5400 if (!get_msr(base_cpu, MSR_CC6_DEMOTION_POLICY_CONFIG, &msr)) 5401 fprintf(outf, "cpu%d: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-CC6-Demotion)\n", 5402 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS"); 5403 5404 if (!get_msr(base_cpu, MSR_MC6_DEMOTION_POLICY_CONFIG, &msr)) 5405 fprintf(outf, "cpu%d: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-MC6-Demotion)\n", 5406 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS"); 5407} 5408 5409/* 5410 * When models are the same, for the purpose of turbostat, reuse 5411 */ 5412unsigned int intel_model_duplicates(unsigned int model) 5413{ 5414 5415 switch (model) { 5416 case INTEL_FAM6_NEHALEM_EP: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */ 5417 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ 5418 case 0x1F: /* Core i7 and i5 Processor - Nehalem */ 5419 case INTEL_FAM6_WESTMERE: /* Westmere Client - Clarkdale, Arrandale */ 5420 case INTEL_FAM6_WESTMERE_EP: /* Westmere EP - Gulftown */ 5421 return INTEL_FAM6_NEHALEM; 5422 5423 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 5424 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */ 5425 return INTEL_FAM6_NEHALEM_EX; 5426 5427 case INTEL_FAM6_XEON_PHI_KNM: 5428 return INTEL_FAM6_XEON_PHI_KNL; 5429 5430 case INTEL_FAM6_BROADWELL_X: 5431 case INTEL_FAM6_BROADWELL_D: /* BDX-DE */ 5432 return INTEL_FAM6_BROADWELL_X; 5433 5434 case INTEL_FAM6_SKYLAKE_L: 5435 case INTEL_FAM6_SKYLAKE: 5436 case INTEL_FAM6_KABYLAKE_L: 5437 case INTEL_FAM6_KABYLAKE: 5438 case INTEL_FAM6_COMETLAKE_L: 5439 case INTEL_FAM6_COMETLAKE: 5440 return INTEL_FAM6_SKYLAKE_L; 5441 5442 case INTEL_FAM6_ICELAKE_L: 5443 case INTEL_FAM6_ICELAKE_NNPI: 5444 case INTEL_FAM6_TIGERLAKE_L: 5445 case INTEL_FAM6_TIGERLAKE: 5446 case INTEL_FAM6_ROCKETLAKE: 5447 case INTEL_FAM6_LAKEFIELD: 5448 case INTEL_FAM6_ALDERLAKE: 5449 case INTEL_FAM6_ALDERLAKE_L: 5450 case INTEL_FAM6_ATOM_GRACEMONT: 5451 case INTEL_FAM6_RAPTORLAKE: 5452 case INTEL_FAM6_RAPTORLAKE_P: 5453 case INTEL_FAM6_RAPTORLAKE_S: 5454 case INTEL_FAM6_METEORLAKE: 5455 case INTEL_FAM6_METEORLAKE_L: 5456 return INTEL_FAM6_CANNONLAKE_L; 5457 5458 case INTEL_FAM6_ATOM_TREMONT_L: 5459 return INTEL_FAM6_ATOM_TREMONT; 5460 5461 case INTEL_FAM6_ICELAKE_D: 5462 return INTEL_FAM6_ICELAKE_X; 5463 5464 case INTEL_FAM6_EMERALDRAPIDS_X: 5465 return INTEL_FAM6_SAPPHIRERAPIDS_X; 5466 } 5467 return model; 5468} 5469 5470void print_dev_latency(void) 5471{ 5472 char *path = "/dev/cpu_dma_latency"; 5473 int fd; 5474 int value; 5475 int retval; 5476 5477 fd = open(path, O_RDONLY); 5478 if (fd < 0) { 5479 warnx("capget(CAP_SYS_ADMIN) failed, try \"# setcap cap_sys_admin=ep %s\"", progname); 5480 return; 5481 } 5482 5483 retval = read(fd, (void *)&value, sizeof(int)); 5484 if (retval != sizeof(int)) { 5485 warn("read failed %s", path); 5486 close(fd); 5487 return; 5488 } 5489 fprintf(outf, "/dev/cpu_dma_latency: %d usec (%s)\n", value, value == 2000000000 ? "default" : "constrained"); 5490 5491 close(fd); 5492} 5493 5494/* 5495 * Linux-perf manages the HW instructions-retired counter 5496 * by enabling when requested, and hiding rollover 5497 */ 5498void linux_perf_init(void) 5499{ 5500 if (!BIC_IS_ENABLED(BIC_IPC)) 5501 return; 5502 5503 if (access("/proc/sys/kernel/perf_event_paranoid", F_OK)) 5504 return; 5505 5506 fd_instr_count_percpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 5507 if (fd_instr_count_percpu == NULL) 5508 err(-1, "calloc fd_instr_count_percpu"); 5509 5510 BIC_PRESENT(BIC_IPC); 5511} 5512 5513void process_cpuid() 5514{ 5515 unsigned int eax, ebx, ecx, edx; 5516 unsigned int fms, family, model, stepping, ecx_flags, edx_flags; 5517 unsigned long long ucode_patch = 0; 5518 5519 eax = ebx = ecx = edx = 0; 5520 5521 __cpuid(0, max_level, ebx, ecx, edx); 5522 5523 if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69) 5524 genuine_intel = 1; 5525 else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65) 5526 authentic_amd = 1; 5527 else if (ebx == 0x6f677948 && ecx == 0x656e6975 && edx == 0x6e65476e) 5528 hygon_genuine = 1; 5529 5530 if (!quiet) 5531 fprintf(outf, "CPUID(0): %.4s%.4s%.4s 0x%x CPUID levels\n", 5532 (char *)&ebx, (char *)&edx, (char *)&ecx, max_level); 5533 5534 __cpuid(1, fms, ebx, ecx, edx); 5535 family = (fms >> 8) & 0xf; 5536 model = (fms >> 4) & 0xf; 5537 stepping = fms & 0xf; 5538 if (family == 0xf) 5539 family += (fms >> 20) & 0xff; 5540 if (family >= 6) 5541 model += ((fms >> 16) & 0xf) << 4; 5542 ecx_flags = ecx; 5543 edx_flags = edx; 5544 5545 if (get_msr(sched_getcpu(), MSR_IA32_UCODE_REV, &ucode_patch)) 5546 warnx("get_msr(UCODE)"); 5547 5548 /* 5549 * check max extended function levels of CPUID. 5550 * This is needed to check for invariant TSC. 5551 * This check is valid for both Intel and AMD. 5552 */ 5553 ebx = ecx = edx = 0; 5554 __cpuid(0x80000000, max_extended_level, ebx, ecx, edx); 5555 5556 if (!quiet) { 5557 fprintf(outf, "CPUID(1): family:model:stepping 0x%x:%x:%x (%d:%d:%d) microcode 0x%x\n", 5558 family, model, stepping, family, model, stepping, 5559 (unsigned int)((ucode_patch >> 32) & 0xFFFFFFFF)); 5560 fprintf(outf, "CPUID(0x80000000): max_extended_levels: 0x%x\n", max_extended_level); 5561 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s %s\n", 5562 ecx_flags & (1 << 0) ? "SSE3" : "-", 5563 ecx_flags & (1 << 3) ? "MONITOR" : "-", 5564 ecx_flags & (1 << 6) ? "SMX" : "-", 5565 ecx_flags & (1 << 7) ? "EIST" : "-", 5566 ecx_flags & (1 << 8) ? "TM2" : "-", 5567 edx_flags & (1 << 4) ? "TSC" : "-", 5568 edx_flags & (1 << 5) ? "MSR" : "-", 5569 edx_flags & (1 << 22) ? "ACPI-TM" : "-", 5570 edx_flags & (1 << 28) ? "HT" : "-", edx_flags & (1 << 29) ? "TM" : "-"); 5571 } 5572 if (genuine_intel) { 5573 model_orig = model; 5574 model = intel_model_duplicates(model); 5575 } 5576 5577 if (!(edx_flags & (1 << 5))) 5578 errx(1, "CPUID: no MSR"); 5579 5580 if (max_extended_level >= 0x80000007) { 5581 5582 /* 5583 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8 5584 * this check is valid for both Intel and AMD 5585 */ 5586 __cpuid(0x80000007, eax, ebx, ecx, edx); 5587 has_invariant_tsc = edx & (1 << 8); 5588 } 5589 5590 /* 5591 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0 5592 * this check is valid for both Intel and AMD 5593 */ 5594 5595 __cpuid(0x6, eax, ebx, ecx, edx); 5596 has_aperf = ecx & (1 << 0); 5597 if (has_aperf) { 5598 BIC_PRESENT(BIC_Avg_MHz); 5599 BIC_PRESENT(BIC_Busy); 5600 BIC_PRESENT(BIC_Bzy_MHz); 5601 } 5602 do_dts = eax & (1 << 0); 5603 if (do_dts) 5604 BIC_PRESENT(BIC_CoreTmp); 5605 has_turbo = eax & (1 << 1); 5606 do_ptm = eax & (1 << 6); 5607 if (do_ptm) 5608 BIC_PRESENT(BIC_PkgTmp); 5609 has_hwp = eax & (1 << 7); 5610 has_hwp_notify = eax & (1 << 8); 5611 has_hwp_activity_window = eax & (1 << 9); 5612 has_hwp_epp = eax & (1 << 10); 5613 has_hwp_pkg = eax & (1 << 11); 5614 has_epb = ecx & (1 << 3); 5615 5616 if (!quiet) 5617 fprintf(outf, "CPUID(6): %sAPERF, %sTURBO, %sDTS, %sPTM, %sHWP, " 5618 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n", 5619 has_aperf ? "" : "No-", 5620 has_turbo ? "" : "No-", 5621 do_dts ? "" : "No-", 5622 do_ptm ? "" : "No-", 5623 has_hwp ? "" : "No-", 5624 has_hwp_notify ? "" : "No-", 5625 has_hwp_activity_window ? "" : "No-", 5626 has_hwp_epp ? "" : "No-", has_hwp_pkg ? "" : "No-", has_epb ? "" : "No-"); 5627 5628 if (!quiet) 5629 decode_misc_enable_msr(); 5630 5631 if (max_level >= 0x7 && !quiet) { 5632 int has_sgx; 5633 5634 ecx = 0; 5635 5636 __cpuid_count(0x7, 0, eax, ebx, ecx, edx); 5637 5638 has_sgx = ebx & (1 << 2); 5639 5640 is_hybrid = edx & (1 << 15); 5641 5642 fprintf(outf, "CPUID(7): %sSGX %sHybrid\n", has_sgx ? "" : "No-", is_hybrid ? "" : "No-"); 5643 5644 if (has_sgx) 5645 decode_feature_control_msr(); 5646 } 5647 5648 if (max_level >= 0x15) { 5649 unsigned int eax_crystal; 5650 unsigned int ebx_tsc; 5651 5652 /* 5653 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz 5654 */ 5655 eax_crystal = ebx_tsc = crystal_hz = edx = 0; 5656 __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx); 5657 5658 if (ebx_tsc != 0) { 5659 5660 if (!quiet && (ebx != 0)) 5661 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n", 5662 eax_crystal, ebx_tsc, crystal_hz); 5663 5664 if (crystal_hz == 0) 5665 switch (model) { 5666 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 5667 crystal_hz = 24000000; /* 24.0 MHz */ 5668 break; 5669 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */ 5670 crystal_hz = 25000000; /* 25.0 MHz */ 5671 break; 5672 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 5673 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 5674 crystal_hz = 19200000; /* 19.2 MHz */ 5675 break; 5676 default: 5677 crystal_hz = 0; 5678 } 5679 5680 if (crystal_hz) { 5681 tsc_hz = (unsigned long long)crystal_hz *ebx_tsc / eax_crystal; 5682 if (!quiet) 5683 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n", 5684 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal); 5685 } 5686 } 5687 } 5688 if (max_level >= 0x16) { 5689 unsigned int base_mhz, max_mhz, bus_mhz, edx; 5690 5691 /* 5692 * CPUID 16H Base MHz, Max MHz, Bus MHz 5693 */ 5694 base_mhz = max_mhz = bus_mhz = edx = 0; 5695 5696 __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx); 5697 if (!quiet) 5698 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n", 5699 base_mhz, max_mhz, bus_mhz); 5700 } 5701 5702 if (has_aperf) 5703 aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model); 5704 5705 BIC_PRESENT(BIC_IRQ); 5706 BIC_PRESENT(BIC_TSC_MHz); 5707 5708 if (probe_nhm_msrs(family, model)) { 5709 do_nhm_platform_info = 1; 5710 BIC_PRESENT(BIC_CPU_c1); 5711 BIC_PRESENT(BIC_CPU_c3); 5712 BIC_PRESENT(BIC_CPU_c6); 5713 BIC_PRESENT(BIC_SMI); 5714 } 5715 do_snb_cstates = has_snb_msrs(family, model); 5716 5717 if (do_snb_cstates) 5718 BIC_PRESENT(BIC_CPU_c7); 5719 5720 do_irtl_snb = has_snb_msrs(family, model); 5721 if (do_snb_cstates && (pkg_cstate_limit >= PCL__2)) 5722 BIC_PRESENT(BIC_Pkgpc2); 5723 if (pkg_cstate_limit >= PCL__3) 5724 BIC_PRESENT(BIC_Pkgpc3); 5725 if (pkg_cstate_limit >= PCL__6) 5726 BIC_PRESENT(BIC_Pkgpc6); 5727 if (do_snb_cstates && (pkg_cstate_limit >= PCL__7)) 5728 BIC_PRESENT(BIC_Pkgpc7); 5729 if (has_slv_msrs(family, model)) { 5730 BIC_NOT_PRESENT(BIC_Pkgpc2); 5731 BIC_NOT_PRESENT(BIC_Pkgpc3); 5732 BIC_PRESENT(BIC_Pkgpc6); 5733 BIC_NOT_PRESENT(BIC_Pkgpc7); 5734 BIC_PRESENT(BIC_Mod_c6); 5735 use_c1_residency_msr = 1; 5736 } 5737 if (is_jvl(family, model)) { 5738 BIC_NOT_PRESENT(BIC_CPU_c3); 5739 BIC_NOT_PRESENT(BIC_CPU_c7); 5740 BIC_NOT_PRESENT(BIC_Pkgpc2); 5741 BIC_NOT_PRESENT(BIC_Pkgpc3); 5742 BIC_NOT_PRESENT(BIC_Pkgpc6); 5743 BIC_NOT_PRESENT(BIC_Pkgpc7); 5744 } 5745 if (is_dnv(family, model)) { 5746 BIC_PRESENT(BIC_CPU_c1); 5747 BIC_NOT_PRESENT(BIC_CPU_c3); 5748 BIC_NOT_PRESENT(BIC_Pkgpc3); 5749 BIC_NOT_PRESENT(BIC_CPU_c7); 5750 BIC_NOT_PRESENT(BIC_Pkgpc7); 5751 use_c1_residency_msr = 1; 5752 } 5753 if (is_skx(family, model) || is_icx(family, model) || is_spr(family, model)) { 5754 BIC_NOT_PRESENT(BIC_CPU_c3); 5755 BIC_NOT_PRESENT(BIC_Pkgpc3); 5756 BIC_NOT_PRESENT(BIC_CPU_c7); 5757 BIC_NOT_PRESENT(BIC_Pkgpc7); 5758 } 5759 if (is_bdx(family, model)) { 5760 BIC_NOT_PRESENT(BIC_CPU_c7); 5761 BIC_NOT_PRESENT(BIC_Pkgpc7); 5762 } 5763 if (has_c8910_msrs(family, model)) { 5764 if (pkg_cstate_limit >= PCL__8) 5765 BIC_PRESENT(BIC_Pkgpc8); 5766 if (pkg_cstate_limit >= PCL__9) 5767 BIC_PRESENT(BIC_Pkgpc9); 5768 if (pkg_cstate_limit >= PCL_10) 5769 BIC_PRESENT(BIC_Pkgpc10); 5770 } 5771 do_irtl_hsw = has_c8910_msrs(family, model); 5772 if (has_skl_msrs(family, model)) { 5773 BIC_PRESENT(BIC_Totl_c0); 5774 BIC_PRESENT(BIC_Any_c0); 5775 BIC_PRESENT(BIC_GFX_c0); 5776 BIC_PRESENT(BIC_CPUGFX); 5777 } 5778 do_slm_cstates = is_slm(family, model); 5779 do_knl_cstates = is_knl(family, model); 5780 5781 if (do_slm_cstates || do_knl_cstates || is_cnl(family, model) || is_ehl(family, model)) 5782 BIC_NOT_PRESENT(BIC_CPU_c3); 5783 5784 if (!quiet) 5785 decode_misc_pwr_mgmt_msr(); 5786 5787 if (!quiet && has_slv_msrs(family, model)) 5788 decode_c6_demotion_policy_msr(); 5789 5790 rapl_probe(family, model); 5791 perf_limit_reasons_probe(family, model); 5792 automatic_cstate_conversion_probe(family, model); 5793 prewake_cstate_probe(family, model); 5794 5795 check_tcc_offset(model_orig); 5796 5797 if (!quiet) 5798 dump_cstate_pstate_config_info(family, model); 5799 intel_uncore_frequency_probe(); 5800 5801 if (!quiet) 5802 print_dev_latency(); 5803 if (!quiet) 5804 dump_sysfs_cstate_config(); 5805 if (!quiet) 5806 dump_sysfs_pstate_config(); 5807 5808 if (has_skl_msrs(family, model) || is_ehl(family, model)) 5809 calculate_tsc_tweak(); 5810 5811 if (!access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK)) 5812 BIC_PRESENT(BIC_GFX_rc6); 5813 5814 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK)) 5815 BIC_PRESENT(BIC_GFXMHz); 5816 5817 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz", R_OK)) 5818 BIC_PRESENT(BIC_GFXACTMHz); 5819 5820 if (!access("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", R_OK)) 5821 BIC_PRESENT(BIC_CPU_LPI); 5822 else 5823 BIC_NOT_PRESENT(BIC_CPU_LPI); 5824 5825 if (!access("/sys/devices/system/cpu/cpu0/thermal_throttle/core_throttle_count", R_OK)) 5826 BIC_PRESENT(BIC_CORE_THROT_CNT); 5827 else 5828 BIC_NOT_PRESENT(BIC_CORE_THROT_CNT); 5829 5830 if (!access(sys_lpi_file_sysfs, R_OK)) { 5831 sys_lpi_file = sys_lpi_file_sysfs; 5832 BIC_PRESENT(BIC_SYS_LPI); 5833 } else if (!access(sys_lpi_file_debugfs, R_OK)) { 5834 sys_lpi_file = sys_lpi_file_debugfs; 5835 BIC_PRESENT(BIC_SYS_LPI); 5836 } else { 5837 sys_lpi_file_sysfs = NULL; 5838 BIC_NOT_PRESENT(BIC_SYS_LPI); 5839 } 5840 5841 if (!quiet) 5842 decode_misc_feature_control(); 5843 5844 return; 5845} 5846 5847/* 5848 * in /dev/cpu/ return success for names that are numbers 5849 * ie. filter out ".", "..", "microcode". 5850 */ 5851int dir_filter(const struct dirent *dirp) 5852{ 5853 if (isdigit(dirp->d_name[0])) 5854 return 1; 5855 else 5856 return 0; 5857} 5858 5859void topology_probe() 5860{ 5861 int i; 5862 int max_core_id = 0; 5863 int max_package_id = 0; 5864 int max_die_id = 0; 5865 int max_siblings = 0; 5866 5867 /* Initialize num_cpus, max_cpu_num */ 5868 set_max_cpu_num(); 5869 topo.num_cpus = 0; 5870 for_all_proc_cpus(count_cpus); 5871 if (!summary_only && topo.num_cpus > 1) 5872 BIC_PRESENT(BIC_CPU); 5873 5874 if (debug > 1) 5875 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num); 5876 5877 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology)); 5878 if (cpus == NULL) 5879 err(1, "calloc cpus"); 5880 5881 /* 5882 * Allocate and initialize cpu_present_set 5883 */ 5884 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1)); 5885 if (cpu_present_set == NULL) 5886 err(3, "CPU_ALLOC"); 5887 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 5888 CPU_ZERO_S(cpu_present_setsize, cpu_present_set); 5889 for_all_proc_cpus(mark_cpu_present); 5890 5891 /* 5892 * Validate that all cpus in cpu_subset are also in cpu_present_set 5893 */ 5894 for (i = 0; i < CPU_SUBSET_MAXCPUS; ++i) { 5895 if (CPU_ISSET_S(i, cpu_subset_size, cpu_subset)) 5896 if (!CPU_ISSET_S(i, cpu_present_setsize, cpu_present_set)) 5897 err(1, "cpu%d not present", i); 5898 } 5899 5900 /* 5901 * Allocate and initialize cpu_affinity_set 5902 */ 5903 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1)); 5904 if (cpu_affinity_set == NULL) 5905 err(3, "CPU_ALLOC"); 5906 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 5907 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 5908 5909 for_all_proc_cpus(init_thread_id); 5910 5911 /* 5912 * For online cpus 5913 * find max_core_id, max_package_id 5914 */ 5915 for (i = 0; i <= topo.max_cpu_num; ++i) { 5916 int siblings; 5917 5918 if (cpu_is_not_present(i)) { 5919 if (debug > 1) 5920 fprintf(outf, "cpu%d NOT PRESENT\n", i); 5921 continue; 5922 } 5923 5924 cpus[i].logical_cpu_id = i; 5925 5926 /* get package information */ 5927 cpus[i].physical_package_id = get_physical_package_id(i); 5928 if (cpus[i].physical_package_id > max_package_id) 5929 max_package_id = cpus[i].physical_package_id; 5930 5931 /* get die information */ 5932 cpus[i].die_id = get_die_id(i); 5933 if (cpus[i].die_id > max_die_id) 5934 max_die_id = cpus[i].die_id; 5935 5936 /* get numa node information */ 5937 cpus[i].physical_node_id = get_physical_node_id(&cpus[i]); 5938 if (cpus[i].physical_node_id > topo.max_node_num) 5939 topo.max_node_num = cpus[i].physical_node_id; 5940 5941 /* get core information */ 5942 cpus[i].physical_core_id = get_core_id(i); 5943 if (cpus[i].physical_core_id > max_core_id) 5944 max_core_id = cpus[i].physical_core_id; 5945 5946 /* get thread information */ 5947 siblings = get_thread_siblings(&cpus[i]); 5948 if (siblings > max_siblings) 5949 max_siblings = siblings; 5950 if (cpus[i].thread_id == 0) 5951 topo.num_cores++; 5952 } 5953 5954 topo.cores_per_node = max_core_id + 1; 5955 if (debug > 1) 5956 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n", max_core_id, topo.cores_per_node); 5957 if (!summary_only && topo.cores_per_node > 1) 5958 BIC_PRESENT(BIC_Core); 5959 5960 topo.num_die = max_die_id + 1; 5961 if (debug > 1) 5962 fprintf(outf, "max_die_id %d, sizing for %d die\n", max_die_id, topo.num_die); 5963 if (!summary_only && topo.num_die > 1) 5964 BIC_PRESENT(BIC_Die); 5965 5966 topo.num_packages = max_package_id + 1; 5967 if (debug > 1) 5968 fprintf(outf, "max_package_id %d, sizing for %d packages\n", max_package_id, topo.num_packages); 5969 if (!summary_only && topo.num_packages > 1) 5970 BIC_PRESENT(BIC_Package); 5971 5972 set_node_data(); 5973 if (debug > 1) 5974 fprintf(outf, "nodes_per_pkg %d\n", topo.nodes_per_pkg); 5975 if (!summary_only && topo.nodes_per_pkg > 1) 5976 BIC_PRESENT(BIC_Node); 5977 5978 topo.threads_per_core = max_siblings; 5979 if (debug > 1) 5980 fprintf(outf, "max_siblings %d\n", max_siblings); 5981 5982 if (debug < 1) 5983 return; 5984 5985 for (i = 0; i <= topo.max_cpu_num; ++i) { 5986 if (cpu_is_not_present(i)) 5987 continue; 5988 fprintf(outf, 5989 "cpu %d pkg %d die %d node %d lnode %d core %d thread %d\n", 5990 i, cpus[i].physical_package_id, cpus[i].die_id, 5991 cpus[i].physical_node_id, cpus[i].logical_node_id, cpus[i].physical_core_id, cpus[i].thread_id); 5992 } 5993 5994} 5995 5996void allocate_counters(struct thread_data **t, struct core_data **c, struct pkg_data **p) 5997{ 5998 int i; 5999 int num_cores = topo.cores_per_node * topo.nodes_per_pkg * topo.num_packages; 6000 int num_threads = topo.threads_per_core * num_cores; 6001 6002 *t = calloc(num_threads, sizeof(struct thread_data)); 6003 if (*t == NULL) 6004 goto error; 6005 6006 for (i = 0; i < num_threads; i++) 6007 (*t)[i].cpu_id = -1; 6008 6009 *c = calloc(num_cores, sizeof(struct core_data)); 6010 if (*c == NULL) 6011 goto error; 6012 6013 for (i = 0; i < num_cores; i++) 6014 (*c)[i].core_id = -1; 6015 6016 *p = calloc(topo.num_packages, sizeof(struct pkg_data)); 6017 if (*p == NULL) 6018 goto error; 6019 6020 for (i = 0; i < topo.num_packages; i++) 6021 (*p)[i].package_id = i; 6022 6023 return; 6024error: 6025 err(1, "calloc counters"); 6026} 6027 6028/* 6029 * init_counter() 6030 * 6031 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE 6032 */ 6033void init_counter(struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base, int cpu_id) 6034{ 6035 int pkg_id = cpus[cpu_id].physical_package_id; 6036 int node_id = cpus[cpu_id].logical_node_id; 6037 int core_id = cpus[cpu_id].physical_core_id; 6038 int thread_id = cpus[cpu_id].thread_id; 6039 struct thread_data *t; 6040 struct core_data *c; 6041 struct pkg_data *p; 6042 6043 /* Workaround for systems where physical_node_id==-1 6044 * and logical_node_id==(-1 - topo.num_cpus) 6045 */ 6046 if (node_id < 0) 6047 node_id = 0; 6048 6049 t = GET_THREAD(thread_base, thread_id, core_id, node_id, pkg_id); 6050 c = GET_CORE(core_base, core_id, node_id, pkg_id); 6051 p = GET_PKG(pkg_base, pkg_id); 6052 6053 t->cpu_id = cpu_id; 6054 if (thread_id == 0) { 6055 t->flags |= CPU_IS_FIRST_THREAD_IN_CORE; 6056 if (cpu_is_first_core_in_package(cpu_id)) 6057 t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE; 6058 } 6059 6060 c->core_id = core_id; 6061 p->package_id = pkg_id; 6062} 6063 6064int initialize_counters(int cpu_id) 6065{ 6066 init_counter(EVEN_COUNTERS, cpu_id); 6067 init_counter(ODD_COUNTERS, cpu_id); 6068 return 0; 6069} 6070 6071void allocate_output_buffer() 6072{ 6073 output_buffer = calloc(1, (1 + topo.num_cpus) * 2048); 6074 outp = output_buffer; 6075 if (outp == NULL) 6076 err(-1, "calloc output buffer"); 6077} 6078 6079void allocate_fd_percpu(void) 6080{ 6081 fd_percpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 6082 if (fd_percpu == NULL) 6083 err(-1, "calloc fd_percpu"); 6084} 6085 6086void allocate_irq_buffers(void) 6087{ 6088 irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int)); 6089 if (irq_column_2_cpu == NULL) 6090 err(-1, "calloc %d", topo.num_cpus); 6091 6092 irqs_per_cpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 6093 if (irqs_per_cpu == NULL) 6094 err(-1, "calloc %d", topo.max_cpu_num + 1); 6095} 6096 6097void setup_all_buffers(void) 6098{ 6099 topology_probe(); 6100 allocate_irq_buffers(); 6101 allocate_fd_percpu(); 6102 allocate_counters(&thread_even, &core_even, &package_even); 6103 allocate_counters(&thread_odd, &core_odd, &package_odd); 6104 allocate_output_buffer(); 6105 for_all_proc_cpus(initialize_counters); 6106} 6107 6108void set_base_cpu(void) 6109{ 6110 base_cpu = sched_getcpu(); 6111 if (base_cpu < 0) 6112 err(-ENODEV, "No valid cpus found"); 6113 6114 if (debug > 1) 6115 fprintf(outf, "base_cpu = %d\n", base_cpu); 6116} 6117 6118void turbostat_init() 6119{ 6120 setup_all_buffers(); 6121 set_base_cpu(); 6122 check_dev_msr(); 6123 check_permissions(); 6124 process_cpuid(); 6125 linux_perf_init(); 6126 6127 if (!quiet) 6128 for_all_cpus(print_hwp, ODD_COUNTERS); 6129 6130 if (!quiet) 6131 for_all_cpus(print_epb, ODD_COUNTERS); 6132 6133 if (!quiet) 6134 for_all_cpus(print_perf_limit, ODD_COUNTERS); 6135 6136 if (!quiet) 6137 for_all_cpus(print_rapl, ODD_COUNTERS); 6138 6139 for_all_cpus(set_temperature_target, ODD_COUNTERS); 6140 6141 for_all_cpus(get_cpu_type, ODD_COUNTERS); 6142 for_all_cpus(get_cpu_type, EVEN_COUNTERS); 6143 6144 if (!quiet) 6145 for_all_cpus(print_thermal, ODD_COUNTERS); 6146 6147 if (!quiet && do_irtl_snb) 6148 print_irtl(); 6149 6150 if (DO_BIC(BIC_IPC)) 6151 (void)get_instr_count_fd(base_cpu); 6152} 6153 6154int fork_it(char **argv) 6155{ 6156 pid_t child_pid; 6157 int status; 6158 6159 snapshot_proc_sysfs_files(); 6160 status = for_all_cpus(get_counters, EVEN_COUNTERS); 6161 first_counter_read = 0; 6162 if (status) 6163 exit(status); 6164 /* clear affinity side-effect of get_counters() */ 6165 sched_setaffinity(0, cpu_present_setsize, cpu_present_set); 6166 gettimeofday(&tv_even, (struct timezone *)NULL); 6167 6168 child_pid = fork(); 6169 if (!child_pid) { 6170 /* child */ 6171 execvp(argv[0], argv); 6172 err(errno, "exec %s", argv[0]); 6173 } else { 6174 6175 /* parent */ 6176 if (child_pid == -1) 6177 err(1, "fork"); 6178 6179 signal(SIGINT, SIG_IGN); 6180 signal(SIGQUIT, SIG_IGN); 6181 if (waitpid(child_pid, &status, 0) == -1) 6182 err(status, "waitpid"); 6183 6184 if (WIFEXITED(status)) 6185 status = WEXITSTATUS(status); 6186 } 6187 /* 6188 * n.b. fork_it() does not check for errors from for_all_cpus() 6189 * because re-starting is problematic when forking 6190 */ 6191 snapshot_proc_sysfs_files(); 6192 for_all_cpus(get_counters, ODD_COUNTERS); 6193 gettimeofday(&tv_odd, (struct timezone *)NULL); 6194 timersub(&tv_odd, &tv_even, &tv_delta); 6195 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) 6196 fprintf(outf, "%s: Counter reset detected\n", progname); 6197 else { 6198 compute_average(EVEN_COUNTERS); 6199 format_all_counters(EVEN_COUNTERS); 6200 } 6201 6202 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec / 1000000.0); 6203 6204 flush_output_stderr(); 6205 6206 return status; 6207} 6208 6209int get_and_dump_counters(void) 6210{ 6211 int status; 6212 6213 snapshot_proc_sysfs_files(); 6214 status = for_all_cpus(get_counters, ODD_COUNTERS); 6215 if (status) 6216 return status; 6217 6218 status = for_all_cpus(dump_counters, ODD_COUNTERS); 6219 if (status) 6220 return status; 6221 6222 flush_output_stdout(); 6223 6224 return status; 6225} 6226 6227void print_version() 6228{ 6229 fprintf(outf, "turbostat version 2023.03.17 - Len Brown <lenb@kernel.org>\n"); 6230} 6231 6232#define COMMAND_LINE_SIZE 2048 6233 6234void print_bootcmd(void) 6235{ 6236 char bootcmd[COMMAND_LINE_SIZE]; 6237 FILE *fp; 6238 int ret; 6239 6240 memset(bootcmd, 0, COMMAND_LINE_SIZE); 6241 fp = fopen("/proc/cmdline", "r"); 6242 if (!fp) 6243 return; 6244 6245 ret = fread(bootcmd, sizeof(char), COMMAND_LINE_SIZE - 1, fp); 6246 if (ret) { 6247 bootcmd[ret] = '\0'; 6248 /* the last character is already '\n' */ 6249 fprintf(outf, "Kernel command line: %s", bootcmd); 6250 } 6251 6252 fclose(fp); 6253} 6254 6255int add_counter(unsigned int msr_num, char *path, char *name, 6256 unsigned int width, enum counter_scope scope, 6257 enum counter_type type, enum counter_format format, int flags) 6258{ 6259 struct msr_counter *msrp; 6260 6261 msrp = calloc(1, sizeof(struct msr_counter)); 6262 if (msrp == NULL) { 6263 perror("calloc"); 6264 exit(1); 6265 } 6266 6267 msrp->msr_num = msr_num; 6268 strncpy(msrp->name, name, NAME_BYTES - 1); 6269 if (path) 6270 strncpy(msrp->path, path, PATH_BYTES - 1); 6271 msrp->width = width; 6272 msrp->type = type; 6273 msrp->format = format; 6274 msrp->flags = flags; 6275 6276 switch (scope) { 6277 6278 case SCOPE_CPU: 6279 msrp->next = sys.tp; 6280 sys.tp = msrp; 6281 sys.added_thread_counters++; 6282 if (sys.added_thread_counters > MAX_ADDED_THREAD_COUNTERS) { 6283 fprintf(stderr, "exceeded max %d added thread counters\n", MAX_ADDED_COUNTERS); 6284 exit(-1); 6285 } 6286 break; 6287 6288 case SCOPE_CORE: 6289 msrp->next = sys.cp; 6290 sys.cp = msrp; 6291 sys.added_core_counters++; 6292 if (sys.added_core_counters > MAX_ADDED_COUNTERS) { 6293 fprintf(stderr, "exceeded max %d added core counters\n", MAX_ADDED_COUNTERS); 6294 exit(-1); 6295 } 6296 break; 6297 6298 case SCOPE_PACKAGE: 6299 msrp->next = sys.pp; 6300 sys.pp = msrp; 6301 sys.added_package_counters++; 6302 if (sys.added_package_counters > MAX_ADDED_COUNTERS) { 6303 fprintf(stderr, "exceeded max %d added package counters\n", MAX_ADDED_COUNTERS); 6304 exit(-1); 6305 } 6306 break; 6307 } 6308 6309 return 0; 6310} 6311 6312void parse_add_command(char *add_command) 6313{ 6314 int msr_num = 0; 6315 char *path = NULL; 6316 char name_buffer[NAME_BYTES] = ""; 6317 int width = 64; 6318 int fail = 0; 6319 enum counter_scope scope = SCOPE_CPU; 6320 enum counter_type type = COUNTER_CYCLES; 6321 enum counter_format format = FORMAT_DELTA; 6322 6323 while (add_command) { 6324 6325 if (sscanf(add_command, "msr0x%x", &msr_num) == 1) 6326 goto next; 6327 6328 if (sscanf(add_command, "msr%d", &msr_num) == 1) 6329 goto next; 6330 6331 if (*add_command == '/') { 6332 path = add_command; 6333 goto next; 6334 } 6335 6336 if (sscanf(add_command, "u%d", &width) == 1) { 6337 if ((width == 32) || (width == 64)) 6338 goto next; 6339 width = 64; 6340 } 6341 if (!strncmp(add_command, "cpu", strlen("cpu"))) { 6342 scope = SCOPE_CPU; 6343 goto next; 6344 } 6345 if (!strncmp(add_command, "core", strlen("core"))) { 6346 scope = SCOPE_CORE; 6347 goto next; 6348 } 6349 if (!strncmp(add_command, "package", strlen("package"))) { 6350 scope = SCOPE_PACKAGE; 6351 goto next; 6352 } 6353 if (!strncmp(add_command, "cycles", strlen("cycles"))) { 6354 type = COUNTER_CYCLES; 6355 goto next; 6356 } 6357 if (!strncmp(add_command, "seconds", strlen("seconds"))) { 6358 type = COUNTER_SECONDS; 6359 goto next; 6360 } 6361 if (!strncmp(add_command, "usec", strlen("usec"))) { 6362 type = COUNTER_USEC; 6363 goto next; 6364 } 6365 if (!strncmp(add_command, "raw", strlen("raw"))) { 6366 format = FORMAT_RAW; 6367 goto next; 6368 } 6369 if (!strncmp(add_command, "delta", strlen("delta"))) { 6370 format = FORMAT_DELTA; 6371 goto next; 6372 } 6373 if (!strncmp(add_command, "percent", strlen("percent"))) { 6374 format = FORMAT_PERCENT; 6375 goto next; 6376 } 6377 6378 if (sscanf(add_command, "%18s,%*s", name_buffer) == 1) { /* 18 < NAME_BYTES */ 6379 char *eos; 6380 6381 eos = strchr(name_buffer, ','); 6382 if (eos) 6383 *eos = '\0'; 6384 goto next; 6385 } 6386 6387next: 6388 add_command = strchr(add_command, ','); 6389 if (add_command) { 6390 *add_command = '\0'; 6391 add_command++; 6392 } 6393 6394 } 6395 if ((msr_num == 0) && (path == NULL)) { 6396 fprintf(stderr, "--add: (msrDDD | msr0xXXX | /path_to_counter ) required\n"); 6397 fail++; 6398 } 6399 6400 /* generate default column header */ 6401 if (*name_buffer == '\0') { 6402 if (width == 32) 6403 sprintf(name_buffer, "M0x%x%s", msr_num, format == FORMAT_PERCENT ? "%" : ""); 6404 else 6405 sprintf(name_buffer, "M0X%x%s", msr_num, format == FORMAT_PERCENT ? "%" : ""); 6406 } 6407 6408 if (add_counter(msr_num, path, name_buffer, width, scope, type, format, 0)) 6409 fail++; 6410 6411 if (fail) { 6412 help(); 6413 exit(1); 6414 } 6415} 6416 6417int is_deferred_add(char *name) 6418{ 6419 int i; 6420 6421 for (i = 0; i < deferred_add_index; ++i) 6422 if (!strcmp(name, deferred_add_names[i])) 6423 return 1; 6424 return 0; 6425} 6426 6427int is_deferred_skip(char *name) 6428{ 6429 int i; 6430 6431 for (i = 0; i < deferred_skip_index; ++i) 6432 if (!strcmp(name, deferred_skip_names[i])) 6433 return 1; 6434 return 0; 6435} 6436 6437void probe_sysfs(void) 6438{ 6439 char path[64]; 6440 char name_buf[16]; 6441 FILE *input; 6442 int state; 6443 char *sp; 6444 6445 for (state = 10; state >= 0; --state) { 6446 6447 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state); 6448 input = fopen(path, "r"); 6449 if (input == NULL) 6450 continue; 6451 if (!fgets(name_buf, sizeof(name_buf), input)) 6452 err(1, "%s: failed to read file", path); 6453 6454 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 6455 sp = strchr(name_buf, '-'); 6456 if (!sp) 6457 sp = strchrnul(name_buf, '\n'); 6458 *sp = '%'; 6459 *(sp + 1) = '\0'; 6460 6461 remove_underbar(name_buf); 6462 6463 fclose(input); 6464 6465 sprintf(path, "cpuidle/state%d/time", state); 6466 6467 if (!DO_BIC(BIC_sysfs) && !is_deferred_add(name_buf)) 6468 continue; 6469 6470 if (is_deferred_skip(name_buf)) 6471 continue; 6472 6473 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_USEC, FORMAT_PERCENT, SYSFS_PERCPU); 6474 } 6475 6476 for (state = 10; state >= 0; --state) { 6477 6478 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state); 6479 input = fopen(path, "r"); 6480 if (input == NULL) 6481 continue; 6482 if (!fgets(name_buf, sizeof(name_buf), input)) 6483 err(1, "%s: failed to read file", path); 6484 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 6485 sp = strchr(name_buf, '-'); 6486 if (!sp) 6487 sp = strchrnul(name_buf, '\n'); 6488 *sp = '\0'; 6489 fclose(input); 6490 6491 remove_underbar(name_buf); 6492 6493 sprintf(path, "cpuidle/state%d/usage", state); 6494 6495 if (!DO_BIC(BIC_sysfs) && !is_deferred_add(name_buf)) 6496 continue; 6497 6498 if (is_deferred_skip(name_buf)) 6499 continue; 6500 6501 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_ITEMS, FORMAT_DELTA, SYSFS_PERCPU); 6502 } 6503 6504} 6505 6506/* 6507 * parse cpuset with following syntax 6508 * 1,2,4..6,8-10 and set bits in cpu_subset 6509 */ 6510void parse_cpu_command(char *optarg) 6511{ 6512 unsigned int start, end; 6513 char *next; 6514 6515 if (!strcmp(optarg, "core")) { 6516 if (cpu_subset) 6517 goto error; 6518 show_core_only++; 6519 return; 6520 } 6521 if (!strcmp(optarg, "package")) { 6522 if (cpu_subset) 6523 goto error; 6524 show_pkg_only++; 6525 return; 6526 } 6527 if (show_core_only || show_pkg_only) 6528 goto error; 6529 6530 cpu_subset = CPU_ALLOC(CPU_SUBSET_MAXCPUS); 6531 if (cpu_subset == NULL) 6532 err(3, "CPU_ALLOC"); 6533 cpu_subset_size = CPU_ALLOC_SIZE(CPU_SUBSET_MAXCPUS); 6534 6535 CPU_ZERO_S(cpu_subset_size, cpu_subset); 6536 6537 next = optarg; 6538 6539 while (next && *next) { 6540 6541 if (*next == '-') /* no negative cpu numbers */ 6542 goto error; 6543 6544 start = strtoul(next, &next, 10); 6545 6546 if (start >= CPU_SUBSET_MAXCPUS) 6547 goto error; 6548 CPU_SET_S(start, cpu_subset_size, cpu_subset); 6549 6550 if (*next == '\0') 6551 break; 6552 6553 if (*next == ',') { 6554 next += 1; 6555 continue; 6556 } 6557 6558 if (*next == '-') { 6559 next += 1; /* start range */ 6560 } else if (*next == '.') { 6561 next += 1; 6562 if (*next == '.') 6563 next += 1; /* start range */ 6564 else 6565 goto error; 6566 } 6567 6568 end = strtoul(next, &next, 10); 6569 if (end <= start) 6570 goto error; 6571 6572 while (++start <= end) { 6573 if (start >= CPU_SUBSET_MAXCPUS) 6574 goto error; 6575 CPU_SET_S(start, cpu_subset_size, cpu_subset); 6576 } 6577 6578 if (*next == ',') 6579 next += 1; 6580 else if (*next != '\0') 6581 goto error; 6582 } 6583 6584 return; 6585 6586error: 6587 fprintf(stderr, "\"--cpu %s\" malformed\n", optarg); 6588 help(); 6589 exit(-1); 6590} 6591 6592void cmdline(int argc, char **argv) 6593{ 6594 int opt; 6595 int option_index = 0; 6596 static struct option long_options[] = { 6597 { "add", required_argument, 0, 'a' }, 6598 { "cpu", required_argument, 0, 'c' }, 6599 { "Dump", no_argument, 0, 'D' }, 6600 { "debug", no_argument, 0, 'd' }, /* internal, not documented */ 6601 { "enable", required_argument, 0, 'e' }, 6602 { "interval", required_argument, 0, 'i' }, 6603 { "IPC", no_argument, 0, 'I' }, 6604 { "num_iterations", required_argument, 0, 'n' }, 6605 { "header_iterations", required_argument, 0, 'N' }, 6606 { "help", no_argument, 0, 'h' }, 6607 { "hide", required_argument, 0, 'H' }, // meh, -h taken by --help 6608 { "Joules", no_argument, 0, 'J' }, 6609 { "list", no_argument, 0, 'l' }, 6610 { "out", required_argument, 0, 'o' }, 6611 { "quiet", no_argument, 0, 'q' }, 6612 { "show", required_argument, 0, 's' }, 6613 { "Summary", no_argument, 0, 'S' }, 6614 { "TCC", required_argument, 0, 'T' }, 6615 { "version", no_argument, 0, 'v' }, 6616 { 0, 0, 0, 0 } 6617 }; 6618 6619 progname = argv[0]; 6620 6621 while ((opt = getopt_long_only(argc, argv, "+C:c:Dde:hi:Jn:o:qST:v", long_options, &option_index)) != -1) { 6622 switch (opt) { 6623 case 'a': 6624 parse_add_command(optarg); 6625 break; 6626 case 'c': 6627 parse_cpu_command(optarg); 6628 break; 6629 case 'D': 6630 dump_only++; 6631 break; 6632 case 'e': 6633 /* --enable specified counter */ 6634 bic_enabled = bic_enabled | bic_lookup(optarg, SHOW_LIST); 6635 break; 6636 case 'd': 6637 debug++; 6638 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT); 6639 break; 6640 case 'H': 6641 /* 6642 * --hide: do not show those specified 6643 * multiple invocations simply clear more bits in enabled mask 6644 */ 6645 bic_enabled &= ~bic_lookup(optarg, HIDE_LIST); 6646 break; 6647 case 'h': 6648 default: 6649 help(); 6650 exit(1); 6651 case 'i': 6652 { 6653 double interval = strtod(optarg, NULL); 6654 6655 if (interval < 0.001) { 6656 fprintf(outf, "interval %f seconds is too small\n", interval); 6657 exit(2); 6658 } 6659 6660 interval_tv.tv_sec = interval_ts.tv_sec = interval; 6661 interval_tv.tv_usec = (interval - interval_tv.tv_sec) * 1000000; 6662 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000; 6663 } 6664 break; 6665 case 'J': 6666 rapl_joules++; 6667 break; 6668 case 'l': 6669 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT); 6670 list_header_only++; 6671 quiet++; 6672 break; 6673 case 'o': 6674 outf = fopen_or_die(optarg, "w"); 6675 break; 6676 case 'q': 6677 quiet = 1; 6678 break; 6679 case 'n': 6680 num_iterations = strtod(optarg, NULL); 6681 6682 if (num_iterations <= 0) { 6683 fprintf(outf, "iterations %d should be positive number\n", num_iterations); 6684 exit(2); 6685 } 6686 break; 6687 case 'N': 6688 header_iterations = strtod(optarg, NULL); 6689 6690 if (header_iterations <= 0) { 6691 fprintf(outf, "iterations %d should be positive number\n", header_iterations); 6692 exit(2); 6693 } 6694 break; 6695 case 's': 6696 /* 6697 * --show: show only those specified 6698 * The 1st invocation will clear and replace the enabled mask 6699 * subsequent invocations can add to it. 6700 */ 6701 if (shown == 0) 6702 bic_enabled = bic_lookup(optarg, SHOW_LIST); 6703 else 6704 bic_enabled |= bic_lookup(optarg, SHOW_LIST); 6705 shown = 1; 6706 break; 6707 case 'S': 6708 summary_only++; 6709 break; 6710 case 'T': 6711 tj_max_override = atoi(optarg); 6712 break; 6713 case 'v': 6714 print_version(); 6715 exit(0); 6716 break; 6717 } 6718 } 6719} 6720 6721int main(int argc, char **argv) 6722{ 6723 outf = stderr; 6724 cmdline(argc, argv); 6725 6726 if (!quiet) { 6727 print_version(); 6728 print_bootcmd(); 6729 } 6730 6731 probe_sysfs(); 6732 6733 turbostat_init(); 6734 6735 msr_sum_record(); 6736 6737 /* dump counters and exit */ 6738 if (dump_only) 6739 return get_and_dump_counters(); 6740 6741 /* list header and exit */ 6742 if (list_header_only) { 6743 print_header(","); 6744 flush_output_stdout(); 6745 return 0; 6746 } 6747 6748 /* 6749 * if any params left, it must be a command to fork 6750 */ 6751 if (argc - optind) 6752 return fork_it(argv + optind); 6753 else 6754 turbostat_loop(); 6755 6756 return 0; 6757} 6758